AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Files Variables
Public Member Functions | Public Attributes
Behavioral Architecture Reference

List of all members.

Processes

PROCESS_1323  ( CDRclk )
PROCESS_1324  ( sysclk ,reset )
PROCESS_1325  ( ipb_clk )
PROCESS_1326  ( ipb_master_out.ipb_addr )
PROCESS_1327  ( sysClk ,rst_cntr ,reset )
PROCESS_1328  ( sysClk ,reset )
PROCESS_1329  ( sysClk ,reset )
PROCESS_1330  ( TTC_clk )
PROCESS_1331  ( DRPclk ,sys_lock )
PROCESS_1332  ( ipb_clk )
PROCESS_1333  ( sysClk )
PROCESS_1334  ( ipb_clk )
PROCESS_1335  ( ipb_clk )
PROCESS_1336  ( CDRclk )
PROCESS_1337  ( sysclk ,reset )
PROCESS_1338  ( ipb_clk )
PROCESS_1339  ( ipb_master_out.ipb_addr )
PROCESS_1340  ( sysClk ,reset )
PROCESS_1341  ( sysClk ,reset )
PROCESS_1342  ( TTC_clk )
PROCESS_1343  ( DRPclk ,sys_lock )
PROCESS_1344  ( ipb_clk )
PROCESS_1345  ( ipb_clk )
PROCESS_1346  ( ipb_clk )
PROCESS_1347  ( CDRclk )
PROCESS_1348  ( sysclk ,reset )
PROCESS_1349  ( ipb_clk )
PROCESS_1350  ( ipb_master_out.ipb_addr )
PROCESS_1351  ( sysClk ,reset )
PROCESS_1352  ( sysClk ,reset )
PROCESS_1353  ( TTC_clk )
PROCESS_1354  ( DRPclk ,sys_lock )
PROCESS_1355  ( ipb_clk )
PROCESS_1356  ( ipb_clk )
PROCESS_1357  ( ipb_clk )
PROCESS_1358  ( CDRclk )
PROCESS_1359  ( sysclk ,reset )
PROCESS_1360  ( ipb_clk )
PROCESS_1361  ( ipb_master_out.ipb_addr )
PROCESS_1362  ( sysClk ,reset )
PROCESS_1363  ( sysClk ,reset )
PROCESS_1364  ( TTC_clk )
PROCESS_1365  ( DRPclk ,sys_lock )
PROCESS_1366  ( ipb_clk )
PROCESS_1367  ( ipb_clk )
PROCESS_1368  ( ipb_clk )
PROCESS_1369  ( CDRclk )
PROCESS_1370  ( sysclk ,reset )
PROCESS_1371  ( ipb_clk )
PROCESS_1372  ( ipb_master_out.ipb_addr )
PROCESS_1373  ( sysClk ,reset )
PROCESS_1374  ( sysClk ,reset )
PROCESS_1375  ( TTC_clk )
PROCESS_1376  ( DRPclk ,sys_lock )
PROCESS_1377  ( ipb_clk )
PROCESS_1378  ( ipb_clk )
PROCESS_1379  ( ipb_clk )

Components

HCAL_trig  <Entity HCAL_trig>
TTS_if  <Entity TTS_if>
ttc_if  <Entity ttc_if>
AMC_if  <Entity AMC_if>
I2C  <Entity I2C>
SPI_if  <Entity SPI_if>
ddr_if  <Entity ddr_if>
ipbus_if  <Entity ipbus_if>
sysmon_if  <Entity sysmon_if>
DAQLSCXG_2x_if  <Entity DAQLSCXG_2x_if>
icon2 
ila16x32k 
DAQLSCXG_3x_if  <Entity DAQLSCXG_3x_if>
TTC_cntr  <Entity TTC_cntr>

Constants

ipbus_ver_addr  std_logic_vector ( 15 downto 0 ) := x " 0000 "
ipbus_sfp_addr  std_logic_vector ( 15 downto 0 ) := x " 0002 "
CDRclk_pol  std_logic := ' 0 '
CDRdata_pol  std_logic := ' 1 '
TTCclk_pol  std_logic := ' 1 '
TTCdata_pol  std_logic := ' 1 '
Coarse_Delay  std_logic_vector ( 3 downto 0 ) := x " 0 "

Signals

rst_ipbus  std_logic := ' 0 '
LDC_UsrClk  std_logic := ' 0 '
wr_AMC_en  std_logic := ' 0 '
wr_EnSFP  std_logic := ' 0 '
fake_length  std_logic_vector ( 19 downto 0 ) := x " 00400 "
AMC_en  std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
TTS_disable  std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
AMC_Ready  std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
TTC_lock  std_logic := ' 0 '
BC0_lock  std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
AMC_status  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
AMC_DATA  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
AMC_ack  std_logic := ' 0 '
L1Aovfl_warning  std_logic := ' 0 '
HCAL_trigger  std_logic := ' 0 '
TRIGDATA  array12x8 := ( others = > ( others = > ' 0 ' ) )
TTS_coded  std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
pattern  std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
SPI_SCK_buf  std_logic := ' 0 '
CLK_rdy  std_logic := ' 0 '
I2C_data  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
TTCclk_in  std_logic := ' 0 '
TTC_Clk  std_logic := ' 0 '
TTC_strobe  std_logic := ' 0 '
BcntErr_cnt  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
SinErr_cnt  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
DbErr_cnt  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
L1_reg  std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
Bcnt_reg  std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
OC_reg  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
V2S  std_logic := ' 0 '
S2V  std_logic := ' 0 '
S2V_cntr  std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
S2V_sr  std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
ddr_rdata  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ipb_clk_dcm  std_logic := ' 0 '
ipb_clk  std_logic := ' 0 '
clk125_dcm  std_logic := ' 0 '
clk125  std_logic := ' 0 '
DRPclk_dcm  std_logic := ' 0 '
DRPclk  std_logic := ' 0 '
sysclk_dcm  std_logic := ' 0 '
sysclk  std_logic := ' 0 '
clkfb  std_logic := ' 0 '
refclk_dcm  std_logic := ' 0 '
refclk  std_logic := ' 0 '
mem_clk_dcm  std_logic := ' 0 '
mem_clk  std_logic := ' 0 '
sysclk_inp  std_logic := ' 0 '
sysclk_in  std_logic := ' 0 '
sys_lock  std_logic := ' 0 '
sys_lock_n  std_logic := ' 0 '
ldc_reset  std_logic := ' 0 '
ldc_GTXreset  std_logic := ' 0 '
lsc_start  std_logic := ' 0 '
lsc_reset  std_logic := ' 0 '
lsc_GTXreset  std_logic := ' 0 '
amc_reset  std_logic := ' 0 '
amc_GTXreset  std_logic := ' 0 '
conf7_q  std_logic := ' 0 '
conf7_fall  std_logic := ' 0 '
run  std_logic := ' 0 '
LSC_LinkDown  std_logic := ' 0 '
mem_rst  std_logic := ' 0 '
mem_test  std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
mem_stat  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
mem_ack  std_logic := ' 0 '
mem_data  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
EventData  array3X67 := ( others = > ( others = > ' 0 ' ) )
wport_rdy  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
EventBufAddr  array3x14 := ( others = > ( others = > ' 0 ' ) )
EventBufAddr_we  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
evt_buf_full  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
wport_FIFO_full  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
MonBufOvfl  std_logic := ' 0 '
MonBuf_empty  std_logic := ' 0 '
mon_evt_wc  std_logic_vector ( 47 downto 0 ) := ( others = > ' 0 ' )
mon_evt_cnt  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
mon_ctrl  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
mon_buf_avl  std_logic := ' 0 '
EventBufAddrAvl  std_logic := ' 0 '
EventBufAddrRe  std_logic := ' 0 '
mon_wp  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
EventBuf_rqst  std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
rst_cntr  std_logic := ' 0 '
rst_ddr_pa  std_logic := ' 0 '
inc_ddr_pa  std_logic := ' 0 '
Source_ID  array3X12 := ( others = > ( others = > ' 0 ' ) )
ddr_pa  std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
CDRclk  std_logic := ' 0 '
TTS_clk  std_logic := ' 0 '
chk_lock  std_logic := ' 0 '
chk_lock_q  std_logic := ' 0 '
BC0  std_logic := ' 0 '
BC0_dl  std_logic := ' 0 '
BC0_locked  std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
BC0_cntr  std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
T3_trigger  std_logic := ' 0 '
inc_BX_offset  std_logic := ' 0 '
en_HCAL_trig  std_logic := ' 0 '
ec_BX_offset  std_logic := ' 0 '
add_two  std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
BX_offset  std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
BX_offset2SC  std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
bcnt  std_logic_vector ( 11 downto 0 ) := x " 000 "
LocalL1A_cfg  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
BCN_off  std_logic_vector ( 12 downto 0 ) := ( others = > ' 0 ' )
OC_off  std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
en_cal_win  std_logic := ' 0 '
CalibCtrl  std_logic_vector ( 31 downto 0 ) := x " 0d800d80 "
cal_win_high  std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
cal_win_low  std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
CalType  std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TTC_Brcst  std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
local_TTCcmd  std_logic := ' 0 '
en_brcst  std_logic := ' 0 '
ttc_start  std_logic := ' 0 '
ttc_stop  std_logic := ' 0 '
ttc_soft_reset  std_logic := ' 0 '
ttc_soft_resetp  std_logic := ' 0 '
ttc_ready  std_logic := ' 0 '
ttc_serr  std_logic := ' 0 '
ttc_derr  std_logic := ' 0 '
ttc_bcnt_err  std_logic := ' 0 '
ttc_evcnt_reset  std_logic := ' 0 '
inc_rate_ofw  std_logic := ' 0 '
rate_ofw  std_logic := ' 0 '
rate_ofwp  std_logic := ' 0 '
rate_ofw_q  std_logic := ' 0 '
sync_lost  std_logic := ' 0 '
oc_cntr  std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
ttc_resync  std_logic := ' 0 '
AllEventBuilt  std_logic := ' 0 '
dcc_quiet  std_logic := ' 0 '
inc_oc  std_logic := ' 0 '
inc_L1ac  std_logic := ' 0 '
inc_bcnterr  std_logic := ' 0 '
inc_serr  std_logic := ' 0 '
inc_derr  std_logic := ' 0 '
evn_fifo_full  std_logic := ' 0 '
event_number_avl  std_logic := ' 0 '
state  std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TTS_wait  std_logic_vector ( 20 downto 0 ) := ( others = > ' 0 ' )
event_number  std_logic_vector ( 59 downto 0 ) := ( others = > ' 0 ' )
TTC_serr_cntr  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
TTC_derr_cntr  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
TTC_BcntErr_cntr  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
L1A_cntr  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
L1A_OFW_cntr  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
L1A_BUSY_cntr  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
L1A_LOS_cntr  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
run_cntr  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ready_cntr  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
busy_cntr  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
sync_cntr  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ovfl_cntr  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ReSync_cntr  std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
counter_we  std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
counter_wa  std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
counter_ra_l  std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
counter_ra_h  std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
CounterDi  std_logic_vector ( 47 downto 0 ) := ( others = > ' 0 ' )
CounterDoA  std_logic_vector ( 47 downto 0 ) := ( others = > ' 0 ' )
CounterDoB  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
div  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
CntrRst  std_logic := ' 0 '
CntrRstCycle  std_logic := ' 0 '
CounterDoB_h  std_logic := ' 0 '
got_SN  std_logic := ' 0 '
ipb_strobe_q  std_logic := ' 0 '
SFP_clk  std_logic := ' 0 '
AMC_clk  std_logic := ' 0 '
AMC_clk_in  std_logic := ' 0 '
SV_Cntr  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
sysclk_div  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
SFP_UsrClk  std_logic := ' 0 '
SFP_TxOutClk  std_logic := ' 0 '
I2C_debug_out  std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
SFPOSC_rdy  std_logic := ' 0 '
reset  std_logic := ' 0 '
DAQ_reset  std_logic := ' 0 '
AMCOSC_rdy  std_logic := ' 0 '
TTC_debug  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
TxDisable_i  std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
DAQfifo_re  std_logic := ' 0 '
DAQfifoAlmostEmpty  std_logic := ' 0 '
DAQfifoEmpty  std_logic := ' 0 '
DAQfifo_do  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
DAQ_debug_in  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
LDC_debug_out  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
LSC_debug_out  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
ddr_debug_in  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ddr_debug_out  std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
GbE_REFCLK  std_logic := ' 0 '
S6Link_debug_in  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
S6Link_debug_out  std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
GbE_debug_in  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
GbE_debug_out  std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
AMC_debug_in  std_logic_vector ( 255 downto 0 ) := ( others = > ' 0 ' )
AMC_debug_out  std_logic_vector ( 255 downto 0 ) := ( others = > ' 0 ' )
SFP0_debug_in  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SFP0_debug_out  std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
SFP1_debug_in  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SFP1_debug_out  std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
ipb_master_out  ipb_wbus
ipb_master_in  ipb_rbus
SN  std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
MACADDR  std_logic_vector ( 47 downto 0 ) := ( others = > ' 0 ' )
ipaddr  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
en_RARP  std_logic := ' 0 '
status  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
cmd  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
cmd0_dl  std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
cmd2_dl  std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
conf  std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
LSC_ID  std_logic_vector ( 15 downto 0 ) := x " 1234 "
OT  std_logic := ' 0 '
inc_HTRCRC_err  std_logic := ' 0 '
ttc_data  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
sysmon_data  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
HCAL_trig_data  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
device_temp  std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
ALM  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
evt_data_rdy  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
evt_data_re  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
evt_data_we  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_data  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SFP_ack  std_logic := ' 0 '
S2V_SyncRegs  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
resetSyncRegs  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
sysclk_div7SyncRegs  std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
resetCntr_SyncRegs  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
newIPADDR  std_logic := ' 0 '
newIPADDRSyncRegs  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
DNA_out  std_logic := ' 0 '
load_DNA  std_logic := ' 0 '
shift_DNA  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
DNA_cntr  std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
DNA  std_logic_vector ( 56 downto 0 ) := ( others = > ' 0 ' )
Dis_pd  std_logic := ' 0 '
enSFP  std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
SFP_down  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
WrtMonBlkDone  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
WrtMonEvtDone  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
CONTROL0  std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )
CONTROL1  std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )
TRIG0  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
TRIG1  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
DATA0  std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
DATA1  std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
DB_cmd  std_logic := ' 0 '
status_l  std_logic_vector ( 22 downto 0 ) := ( others = > ' 0 ' )
SFP_down_l  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_status_l  std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
AMC_status_l  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
TTC_cntr_data  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Instantiations

i_TTS_if  TTS_if <Entity TTS_if>
i_HCAL_trig  HCAL_trig <Entity HCAL_trig>
i_I2C  I2C <Entity I2C>
i_SPI_if  SPI_if <Entity SPI_if>
i_ttc_if  ttc_if <Entity ttc_if>
i_ddr_if  ddr_if <Entity ddr_if>
i_ipbus_if  ipbus_if <Entity ipbus_if>
i_AMC_if  AMC_if <Entity AMC_if>
i_DAQLSC_if  DAQLSCXG_2x_if <Entity DAQLSCXG_2x_if>
i_sysmon_if  sysmon_if <Entity sysmon_if>
i_TTS_if  TTS_if <Entity TTS_if>
i_HCAL_trig  HCAL_trig <Entity HCAL_trig>
i_I2C  I2C <Entity I2C>
i_SPI_if  SPI_if <Entity SPI_if>
i_ttc_if  ttc_if <Entity ttc_if>
i_ddr_if  ddr_if <Entity ddr_if>
i_ipbus_if  ipbus_if <Entity ipbus_if>
i_AMC_if  AMC_if <Entity AMC_if>
i_DAQLSC_if  DAQLSCXG_3x_if <Entity DAQLSCXG_3x_if>
i_sysmon_if  sysmon_if <Entity sysmon_if>
i_TTC_cntr  TTC_cntr <Entity TTC_cntr>
i_TTS_if  TTS_if <Entity TTS_if>
i_HCAL_trig  HCAL_trig <Entity HCAL_trig>
i_I2C  I2C <Entity I2C>
i_SPI_if  SPI_if <Entity SPI_if>
i_ttc_if  ttc_if <Entity ttc_if>
i_ddr_if  ddr_if <Entity ddr_if>
i_ipbus_if  ipbus_if <Entity ipbus_if>
i_AMC_if  AMC_if <Entity AMC_if>
i_DAQLSC_if  DAQLSCXG_3x_if <Entity DAQLSCXG_3x_if>
i_sysmon_if  sysmon_if <Entity sysmon_if>
i_TTC_cntr  TTC_cntr <Entity TTC_cntr>
i_TTS_if  TTS_if <Entity TTS_if>
i_HCAL_trig  HCAL_trig <Entity HCAL_trig>
i_I2C  I2C <Entity I2C>
i_SPI_if  SPI_if <Entity SPI_if>
i_ttc_if  ttc_if <Entity ttc_if>
i_ddr_if  ddr_if <Entity ddr_if>
i_ipbus_if  ipbus_if <Entity ipbus_if>
i_AMC_if  AMC_if <Entity AMC_if>
i_DAQLSC_if  DAQLSCXG_3x_if <Entity DAQLSCXG_3x_if>
i_sysmon_if  sysmon_if <Entity sysmon_if>
i_TTC_cntr  TTC_cntr <Entity TTC_cntr>
i_TTS_if  TTS_if <Entity TTS_if>
i_HCAL_trig  HCAL_trig <Entity HCAL_trig>
i_I2C  I2C <Entity I2C>
i_SPI_if  SPI_if <Entity SPI_if>
i_ttc_if  ttc_if <Entity ttc_if>
i_ddr_if  ddr_if <Entity ddr_if>
i_ipbus_if  ipbus_if <Entity ipbus_if>
i_AMC_if  AMC_if <Entity AMC_if>
i_DAQLSC_if  DAQLSCXG_3x_if <Entity DAQLSCXG_3x_if>
i_sysmon_if  sysmon_if <Entity sysmon_if>
i_TTC_cntr  TTC_cntr <Entity TTC_cntr>

Detailed Description

Definition at line 126 of file AMC13_T1_HCA10G.vhd.

The documentation for this class was generated from the following files:
Generated on Sun Mar 6 2016 12:24:22 for AMC13 by   doxygen 1.8.1