AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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AMC13_T1_HCA10G.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 14:49:29 05/12/2010
6 -- Design Name:
7 -- Module Name: DTC_T2 - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 use work.ipbus.ALL;
26 use work.amc13_pack.all;
27 
28 -- Uncomment the following library declaration if using
29 -- arithmetic functions with Signed or Unsigned values
30 -- use IEEE.NUMERIC_STD.ALL;
31 
32 -- Uncomment the following library declaration if instantiating
33 -- any Xilinx primitives in this code.
34 library UNISIM;
35 use UNISIM.VComponents.all;
36 Library UNIMACRO;
37 use UNIMACRO.vcomponents.all;
38 
39 entity AMC13_T1_HCAL is
40  Port (
41  VAUXP : in STD_LOGIC_VECTOR(12 downto 0);
42  VAUXN : in STD_LOGIC_VECTOR(12 downto 0);
43 -- I2C interface
44  CLK_SCL : out STD_LOGIC;
45  CLK_SDA : inout STD_LOGIC;
46  SFP_SCL : out STD_LOGIC_VECTOR(3 downto 0);
47  SFP_SDA : inout STD_LOGIC_VECTOR(3 downto 0);
48 -- SFP slow control
49  SFP_LOS : in STD_LOGIC_VECTOR(2 downto 0);
50  SFP_ABS : in STD_LOGIC_VECTOR(3 downto 0);
51  TxFault : in STD_LOGIC_VECTOR(3 downto 0);
52  TxDisable : out STD_LOGIC_VECTOR(3 downto 0);
53 -- RATE : out STD_LOGIC_VECTOR(3 downto 0);
54 -- CDR signals
55  DIV4 : out STD_LOGIC;
56  DIV_nRST : out STD_LOGIC;
57  CDRclk_p : in STD_LOGIC;
58  CDRclk_n : in STD_LOGIC;
59  CDRdata_p : in STD_LOGIC;
60  CDRdata_n : in STD_LOGIC;
61  TTCdata_p : out STD_LOGIC;
62  TTCdata_n : out STD_LOGIC;
63  TTCclk_p : in STD_LOGIC;
64  TTCclk_n : in STD_LOGIC;
65  TTC_LOS : in STD_LOGIC;
66  TTC_LOL : in STD_LOGIC;
67  TTS_out_p : out STD_LOGIC;
68  TTS_out_n : out STD_LOGIC;
69 -- SPI interface
70  SPI_SCK : in STD_LOGIC;
71  SPI_CS_b : in STD_LOGIC;
72  SPI_MOSI : in STD_LOGIC;
73  SPI_MISO : out STD_LOGIC;
74 -- DDR3 pins
75  sys_clk_p : in STD_LOGIC;
76  sys_clk_n : in STD_LOGIC;
77  ddr3_dq : inout STD_LOGIC_VECTOR(31 downto 0);
78  ddr3_addr : out STD_LOGIC_VECTOR(13 downto 0);
79  ddr3_ba : out STD_LOGIC_VECTOR (2 downto 0);
80  ddr3_dm : out STD_LOGIC_VECTOR (3 downto 0);
81  ddr3_dqs_p : inout STD_LOGIC_VECTOR(3 downto 0);
82  ddr3_dqs_n : inout STD_LOGIC_VECTOR(3 downto 0);
83  ddr3_ras_n : out STD_LOGIC;
84  ddr3_cas_n : out STD_LOGIC;
85  ddr3_we_n : out STD_LOGIC;
86  ddr3_reset_n : out STD_LOGIC;
87  ddr3_cke : out STD_LOGIC_vector(0 to 0);
88  ddr3_odt : out STD_LOGIC_vector(0 to 0);
89  ddr3_ck_p : out STD_LOGIC_vector(0 to 0);
90  ddr3_ck_n : out STD_LOGIC_vector(0 to 0);
91  SFP0_RXN : in STD_LOGIC;
92  SFP0_RXP : in STD_LOGIC;
93  SFP1_RXN : in STD_LOGIC;
94  SFP1_RXP : in STD_LOGIC;
95  SFP2_RXN : in STD_LOGIC;
96  SFP2_RXP : in STD_LOGIC;
97  SFP0_TXN : out STD_LOGIC;
98  SFP0_TXP : out STD_LOGIC;
99  SFP1_TXN : out STD_LOGIC;
100  SFP1_TXP : out STD_LOGIC;
101  SFP2_TXN : out STD_LOGIC;
102  SFP2_TXP : out STD_LOGIC;
103  SFP_REFCLK_N : in STD_LOGIC;
104  SFP_REFCLK_P : in STD_LOGIC;
105  CDR_REFCLK_N : in STD_LOGIC;
106  CDR_REFCLK_P : in STD_LOGIC;
107  AMC_REFCLK_N : in STD_LOGIC;
108  AMC_REFCLK_P : in STD_LOGIC;
109  AMC_RXN : in STD_LOGIC_VECTOR(12 downto 1);
110  AMC_RXP : in STD_LOGIC_VECTOR(12 downto 1);
111  AMC_TXN : out STD_LOGIC_VECTOR(12 downto 1);
112  AMC_TXP : out STD_LOGIC_VECTOR(12 downto 1);
113 -- signal to/from DTC_T2
114  S6LINK_RXN : in STD_LOGIC;
115  S6LINK_RXP : in STD_LOGIC;
116  S6LINK_TXN : out STD_LOGIC;
117  S6LINK_TXP : out STD_LOGIC;
118  S2V_p : in STD_LOGIC;
119  S2V_n : in STD_LOGIC;
120 -- V2S_p : out STD_LOGIC;
121 -- V2S_n : out STD_LOGIC;
122  GbE_REFCLK_N : in STD_LOGIC;
123  GbE_REFCLK_P : in STD_LOGIC);
124 end AMC13_T1_HCAL;
125 
126 architecture Behavioral of AMC13_T1_HCAL is
127 COMPONENT HCAL_trig
128 PORT(
129  TTC_clk : IN std_logic;
130  DRPCLK : IN std_logic;
131  reset : IN std_logic;
132  BC0 : IN std_logic;
133  en_HCAL_trig : IN std_logic;
134  Trigdata : IN array12x8;
135  triggerOut : OUT std_logic;
136  ipb_clk : IN std_logic;
137  ipb_write : IN std_logic;
138  ipb_strobe : IN std_logic;
139  ipb_addr : IN std_logic_vector(31 downto 0);
140  ipb_wdata : IN std_logic_vector(31 downto 0);
141  GTX_REFCLKp : IN std_logic;
142  GTX_REFCLKn : IN std_logic;
143  GTX_RXp : IN std_logic;
144  GTX_RXn : IN std_logic;
145  ipb_rdata : OUT std_logic_vector(31 downto 0);
146  GTX_TXp : OUT std_logic;
147  GTX_TXn : OUT std_logic
148  );
149 END COMPONENT;
150 COMPONENT TTS_if
151  PORT(
152  sysclk : IN std_logic;
153  TTS_clk : IN std_logic;
154  reset : IN std_logic;
155  local_TTC : in STD_LOGIC;
156  TTS : IN std_logic_vector(3 downto 0);
157  TTS_out_p : OUT std_logic;
158  TTS_out_n : OUT std_logic
159  );
160 END COMPONENT;
161 COMPONENT ttc_if
162  PORT(
163  clk : IN std_logic;
164  refclk : IN std_logic;
165  reset : IN std_logic;
166  run : IN std_logic;
167  IsG2 : IN std_logic;
168  sys_lock : IN std_logic;
169  local_TTC : IN std_logic;
170  local_TTCcmd : IN std_logic;
171  single_TTCcmd : in STD_LOGIC;
172  CDRclk_p : IN std_logic;
173  CDRclk_n : IN std_logic;
174  CDRdata_p : IN std_logic;
175  CDRdata_n : IN std_logic;
176  TTC_LOS : IN std_logic;
177  TTC_LOL : IN std_logic;
178  BCN_off : IN std_logic_vector(12 downto 0);
179  OC_off : IN std_logic_vector(3 downto 0);
180  en_cal_win : IN std_logic;
181  cal_win_high : IN std_logic_vector(11 downto 0);
182  cal_win_low : IN std_logic_vector(11 downto 0);
183  en_localL1A : IN std_logic;
184  LocalL1A_cfg : IN std_logic_vector(31 downto 0);
185  localL1A_s : IN std_logic;
186  localL1A_r : IN std_logic;
187  T3_trigger : IN std_logic;
188  HCAL_trigger : IN std_logic;
189  EvnRSt_l : IN std_logic;
190  OcnRSt_l : IN std_logic;
191  ovfl_warning : IN std_logic;
192  ipb_clk : IN std_logic;
193  ipb_write : IN std_logic;
194  ipb_strobe : IN std_logic;
195  ipb_addr : IN std_logic_vector(31 downto 0);
196  ipb_wdata : IN std_logic_vector(31 downto 0);
197  en_brcst : IN std_logic;
198  state : IN std_logic_vector(3 downto 0);
199  evn_fifo_full : IN std_logic;
200  BC0 : OUT std_logic;
201  TTC_strobe : OUT std_logic;
202  TTS_clk : OUT std_logic;
203  DIV4 : OUT std_logic;
204  DIV_nRST : OUT std_logic;
205  CDRclk_out : OUT std_logic;
206  TTCdata_p : OUT std_logic;
207  TTCdata_n : OUT std_logic;
208  CalType : OUT std_logic_vector(3 downto 0);
209  TTC_Brcst : OUT std_logic_vector(3 downto 0);
210  localL1A_periodic : OUT std_logic;
211  ipb_rdata : OUT std_logic_vector(31 downto 0);
212  ttc_start : OUT std_logic;
213  ttc_stop : OUT std_logic;
214  ttc_soft_reset : OUT std_logic;
215  ttc_ready : OUT std_logic;
216  ttc_serr : OUT std_logic;
217  ttc_derr : OUT std_logic;
218  ttc_bcnt_err : OUT std_logic;
219  rate_OFW : OUT std_logic;
220  sync_lost : OUT std_logic;
221  inc_oc : OUT std_logic;
222  inc_l1ac : OUT std_logic;
223  inc_bcnterr : OUT std_logic;
224  inc_serr : OUT std_logic;
225  inc_derr : OUT std_logic;
226  ttc_evcnt_reset : OUT std_logic;
227  event_number_avl : OUT std_logic;
228  event_number : OUT std_logic_vector(59 downto 0)
229  );
230 END COMPONENT;
231 COMPONENT AMC_if
232  Generic (useTCPIP : boolean := false; AMC_useTRIG : boolean := true; simulation : boolean := false);
233  PORT(
234  sysclk : IN std_logic;
235  ipb_clk : IN std_logic;
236  clk125 : IN std_logic;
237  DRPclk : IN std_logic;
238  GTXreset : IN std_logic;
239  reset : IN std_logic;
240  resetCntr : IN std_logic;
241  ReSync : IN std_logic;
242  AllEventBuilt : OUT std_logic;
243  run : IN std_logic;
244  Dis_pd : in STD_LOGIC;
245  enSFP : IN std_logic_vector(3 downto 0);
246  en_localL1A : IN std_logic;
247  test : IN std_logic;
248  NoReSyncFake : IN std_logic;
249  WaitMonBuf : IN std_logic;
250  fake_length : IN std_logic_vector(19 downto 0);
251  T1_version : IN std_logic_vector(7 downto 0);
252  Source_ID : IN array3x12;
253  AMC_en : IN std_logic_vector(11 downto 0);
254  TTS_disable : IN std_logic_vector(11 downto 0);
255  AMC_REFCLK_P : IN std_logic;
256  AMC_REFCLK_N : IN std_logic;
257  AMC_RXN : IN std_logic_vector(12 downto 1);
258  AMC_RXP : IN std_logic_vector(12 downto 1);
259  evt_data_re : IN std_logic_vector(2 downto 0);
260  evt_buf_full : IN std_logic_vector(2 downto 0);
261  ddr_pa : IN std_logic_vector(9 downto 0);
262  MonBuf_empty : IN std_logic;
263  mon_buf_avl : IN std_logic;
264  TCPbuf_avl : IN std_logic;
265  ipb_write : IN std_logic;
266  ipb_strobe : IN std_logic;
267  ipb_addr : IN std_logic_vector(31 downto 0);
268  ipb_wdata : IN std_logic_vector(31 downto 0);
269  TTC_clk : IN std_logic;
270  TTC_LOS : IN std_logic;
271  BC0 : IN std_logic;
272  ttc_evcnt_reset : IN std_logic;
273  event_number_avl : IN std_logic;
274  event_number : IN std_logic_vector(59 downto 0);
275  AMC_Ready : OUT std_logic_vector(11 downto 0);
276  TTC_lock : OUT std_logic;
277  BC0_lock : OUT std_logic_vector(11 downto 0);
278  AMC_TXN : OUT std_logic_vector(12 downto 1);
279  AMC_TXP : OUT std_logic_vector(12 downto 1);
280  AMC_status : OUT std_logic_vector(31 downto 0);
281  evt_data : OUT array3x67;
282  evt_data_we : OUT std_logic_vector(2 downto 0);
283  evt_data_rdy : OUT std_logic_vector(2 downto 0);
284  mon_evt_wc : OUT std_logic_vector(47 downto 0);
285  mon_ctrl : OUT std_logic_vector(31 downto 0);
286  buf_rqst : OUT std_logic_vector(3 downto 0);
287  ipb_rdata : OUT std_logic_vector(31 downto 0);
288  ipb_ack : OUT std_logic;
289  evn_buf_full : OUT std_logic;
290  ovfl_warning : OUT std_logic;
291  TrigData : OUT array12x8;
292  TTS_coded : OUT std_logic_vector(4 downto 0)
293  );
294 END COMPONENT;
295 COMPONENT I2C
296  PORT(
297  clk : IN std_logic;
298  ipb_clk : IN std_logic;
299  reset : IN std_logic;
300  addr : IN std_logic_vector(31 downto 0);
301  SFP_ABS : IN std_logic_vector(3 downto 0);
302  SFP_LOS : IN std_logic_vector(2 downto 0);
303  CLK_SDA : INOUT std_logic;
304  SFP_SDA : INOUT std_logic_vector(3 downto 0);
305  rdata : OUT std_logic_vector(31 downto 0);
306  CLK_rdy : OUT std_logic;
307  CLK_SCL : OUT std_logic;
308  SFP_SCL : OUT std_logic_vector(3 downto 0)
309  );
310 END COMPONENT;
311 COMPONENT SPI_if
312  PORT(
313  SCK : IN std_logic;
314  CSn : IN std_logic;
315  MOSI : IN std_logic;
316  SN : IN std_logic_vector(8 downto 0);
317  OT : IN std_logic;
318  IsT1 : IN std_logic;
319  SPI_rdata : IN std_logic_vector(7 downto 0);
320  MISO : OUT std_logic;
321  SPI_we : OUT std_logic;
322  en_RARP : out STD_LOGIC;
323  newIPADDR : OUT std_logic;
324  IPADDR : OUT std_logic_vector(31 downto 0);
325  SPI_wdata : OUT std_logic_vector(7 downto 0);
326  SPI_addr : OUT std_logic_vector(7 downto 0)
327  );
328 END COMPONENT;
329 COMPONENT ddr_if
330  port(
331  clk_ref : in std_logic;
332  mem_clk_p : in std_logic;
333  mem_clk_n : in std_logic;
334  mem_rst : in std_logic;
335  sysclk : in std_logic;
336  TCPclk : in std_logic;
337  reset : in std_logic;
338  resetsys : in std_logic;
339  run : in std_logic;
340  mem_test : in std_logic_VECTOR(1 downto 0);
341  EventData : in array3X67;
342  EventData_we : in std_logic_VECTOR(2 downto 0);
343  wport_rdy : out std_logic_VECTOR(2 downto 0);
344  WrtMonBlkDone : OUT std_logic_VECTOR(2 downto 0);
345  WrtMonEvtDone : OUT std_logic_VECTOR(2 downto 0);
346  KiloByte_toggle : OUT std_logic_VECTOR(2 downto 0);
347  EoB_toggle : OUT std_logic_VECTOR(2 downto 0);
348  EventBufAddr : in array3x14;
349  EventBufAddr_we : in std_logic_VECTOR(2 downto 0);
350  EventFIFOfull : out std_logic_VECTOR(2 downto 0);
351  TCP_din : in std_logic_vector(31 downto 0);
352  TCP_channel : in STD_LOGIC_VECTOR (1 downto 0);
353  TCP_we : in STD_LOGIC;
354  TCP_wcount : out STD_LOGIC_VECTOR (2 downto 0);
355  TCP_dout : out STD_LOGIC_VECTOR(31 downto 0); -- TCP data are written in unit of 32-bit words
356  TCP_raddr : in std_logic_vector(28 downto 0); -- 28-26 encoded request source 25-0 address in 64 bit word
357  TCP_length : in std_logic_vector(10 downto 0); -- in 64 bit word, actual length - 1
358  TCP_dout_valid : out STD_LOGIC;
359  TCP_rrqst : in STD_LOGIC;
360  TCP_rack : out STD_LOGIC;
361  TCP_lastword : out STD_LOGIC;
362 -- ipbus signals
363  ipb_clk : in STD_LOGIC;
364  ipb_write : in STD_LOGIC;
365  ipb_strobe : in STD_LOGIC;
366  page_addr : in STD_LOGIC_VECTOR(9 downto 0);
367  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
368  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
369  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
370  ipb_ack : out STD_LOGIC;
371  mem_stat : out STD_LOGIC_VECTOR (63 downto 0);
372  device_temp : in STD_LOGIC_VECTOR(11 downto 0);
373 -- ddr3 memory pins
374  ddr3_dq : inout STD_LOGIC_VECTOR (31 downto 0);
375  ddr3_dm : out STD_LOGIC_VECTOR (3 downto 0);
376  ddr3_addr : out STD_LOGIC_VECTOR (13 downto 0);
377  ddr3_ba : out STD_LOGIC_VECTOR (2 downto 0);
378  ddr3_dqs_p : inout STD_LOGIC_VECTOR (3 downto 0);
379  ddr3_dqs_n : inout STD_LOGIC_VECTOR (3 downto 0);
380  ddr3_ras_n : out STD_LOGIC;
381  ddr3_cas_n : out STD_LOGIC;
382  ddr3_we_n : out STD_LOGIC;
383  ddr3_reset_n : out STD_LOGIC;
384  ddr3_cke : out STD_LOGIC_vector(0 to 0);
385  ddr3_odt : out STD_LOGIC_vector(0 to 0);
386  ddr3_ck_p : out STD_LOGIC_vector(0 to 0);
387  ddr3_ck_n : out STD_LOGIC_vector(0 to 0)
388  );
389 END COMPONENT;
390 COMPONENT ipbus_if
391  generic(RXPOLARITY : std_logic := '0'; TXPOLARITY : std_logic := '0');
392  port(
393  ipb_clk : IN std_logic;
394  UsRclk : IN std_logic;
395  DRPclk : IN std_logic;
396  got_SN : out std_logic;
397  reset : IN std_logic;
398  GTX_RESET : IN std_logic;
399  GbE_REFCLK : in std_logic;
400  S6LINK_RXN : in std_logic;
401  S6LINK_RXP : in std_logic;
402  S6LINK_TXN : out std_logic;
403  S6LINK_TXP : out std_logic;
404  wr_amc_en : in std_logic;
405  amc_en : in STD_LOGIC_VECTOR(11 downto 0);
406  en_RARP : in std_logic;
407  IPADDR : in STD_LOGIC_VECTOR(31 downto 0);
408  MACADDR : in STD_LOGIC_VECTOR(47 downto 0);
409  ipb_out : out ipb_wbus;
410  ipb_in : in ipb_rbus;
411  SN : out STD_LOGIC_VECTOR(8 downto 0);
412  debug_in : IN std_logic_vector(31 downto 0);
413  debug_out : OUT std_logic_vector(127 downto 0)
414  );
415 end COMPONENT;
416 COMPONENT sysmon_if
417  PORT(
418  DRPclk : IN std_logic;
419  SN : IN std_logic_vector(8 downto 0);
420  VAUXN_IN : IN std_logic_vector(12 downto 0);
421  VAUXP_IN : IN std_logic_vector(12 downto 0);
422  addr : IN std_logic_vector(15 downto 0);
423  data : OUT std_logic_vector(31 downto 0);
424  device_temp : OUT std_logic_vector(11 downto 0);
425  ALM : OUT std_logic_vector(7 downto 0);
426  OT : OUT std_logic
427  );
428 END COMPONENT;
429 COMPONENT DAQLSCXG_2x_if
430  PORT(
431  sysclk : IN std_logic;
432  clk125 : IN std_logic;
433  DRPclk : IN std_logic;
434  reset : IN std_logic;
435  daq_reset : IN std_logic;
436  gtx_reset : IN std_logic;
437  rstCntr : IN std_logic;
438  Dis_pd : in STD_LOGIC;
439  test : IN std_logic;
440  enSFP : IN std_logic_vector(3 downto 0);
441  SFP_ABS : IN std_logic_vector(1 downto 0);
442  LSC_ID : IN std_logic_vector(15 downto 0);
443  inc_ddr_pa : IN std_logic;
444  evt_data_rdy : IN std_logic_vector(2 downto 0);
445  EventData_in : IN array3x67;
446  EventData_we : IN std_logic_vector(2 downto 0);
447  buf_rqst : IN std_logic_vector(3 downto 0);
448  WrtMonBlkDone : IN std_logic_vector(2 downto 0);
449  WrtMonEvtDone : IN std_logic_vector(2 downto 0);
450  wport_rdy : IN std_logic_vector(2 downto 0);
451  wport_FIFO_full : IN std_logic_vector(2 downto 0);
452  SFP0_RXN : IN std_logic;
453  SFP0_RXP : IN std_logic;
454  SFP1_RXN : IN std_logic;
455  SFP1_RXP : IN std_logic;
456  SFP_REFCLK_P : IN std_logic;
457  SFP_REFCLK_N : IN std_logic;
458  ipb_clk : IN std_logic;
459  ipb_write : IN std_logic;
460  ipb_strobe : IN std_logic;
461  ipb_addr : IN std_logic_vector(31 downto 0);
462  ipb_wdata : IN std_logic_vector(31 downto 0);
463  SFP_down : OUT std_logic_vector(2 downto 0);
464  EventData_re : OUT std_logic_vector(2 downto 0);
465  evt_buf_full : OUT std_logic_vector(2 downto 0);
466  WaitMonBuf : IN std_logic;
467  MonBufOverWrite : IN std_logic;
468  MonBuf_avl : OUT std_logic;
469  MonBuf_empty : OUT std_logic;
470  MonBufOvfl : OUT std_logic;
471  mon_evt_cnt : OUT std_logic_vector(31 downto 0);
472  EventBufAddr_we : OUT std_logic_vector(2 downto 0);
473  EventBufAddr : OUT array3x14;
474  SFP0_TXN : OUT std_logic;
475  SFP0_TXP : OUT std_logic;
476  SFP1_TXN : OUT std_logic;
477  SFP1_TXP : OUT std_logic;
478  ipb_rdata : OUT std_logic_vector(31 downto 0);
479  ipb_ack : OUT std_logic
480  );
481 END COMPONENT;
482 constant ipbus_ver_addr : std_logic_vector(15 downto 0) := x"0000";
483 constant ipbus_sfp_addr: std_logic_vector(15 downto 0) := x"0002";
484 constant CDRclk_pol : std_logic := '0';
485 constant CDRdata_pol : std_logic := '1';
486 constant TTCclk_pol : std_logic := '1';
487 constant TTCdata_pol : std_logic := '1';
488 constant Coarse_Delay: std_logic_vector(3 downto 0) := x"0";
489 signal rst_ipbus : std_logic := '0';
490 signal LDC_UsrClk : std_logic := '0';
491 signal wr_AMC_en : std_logic := '0';
492 signal wr_EnSFP : std_logic := '0';
493 signal fake_length : std_logic_vector(19 downto 0) := x"00400";
494 signal AMC_en : std_logic_vector(11 downto 0) := (others =>'0');
495 signal TTS_disable : std_logic_vector(11 downto 0) := (others =>'0');
496 signal AMC_Ready : std_logic_vector(11 downto 0) := (others =>'0');
497 signal TTC_lock : std_logic := '0';
498 signal BC0_lock : std_logic_vector(11 downto 0) := (others =>'0');
499 signal AMC_status : std_logic_vector(31 downto 0) := (others =>'0');
500 signal AMC_DATA : std_logic_vector(31 downto 0) := (others =>'0');
501 signal AMC_ack : std_logic := '0';
502 signal L1Aovfl_warning : std_logic := '0';
503 signal HCAL_trigger : std_logic := '0';
504 signal TRIGDATA : array12x8 := (others => (others => '0'));
505 signal TTS_coded : std_logic_vector(4 downto 0) := (others =>'0');
506 signal pattern : std_logic_vector(3 downto 0) := (others =>'0');
507 --signal Trig_mask : std_logic_vector(7 downto 0) := (others =>'0');
508 signal SPI_SCK_buf : std_logic := '0';
509 signal CLK_rdy : std_logic := '0';
510 signal I2C_data : std_logic_vector(31 downto 0) := (others =>'0');
511 signal TTCclk_in : std_logic := '0';
512 signal TTC_Clk : std_logic := '0';
513 signal TTC_strobe : std_logic := '0';
514 signal BcntErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
515 signal SinErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
516 signal DbErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
517 signal L1_reg : std_logic_vector(15 downto 0) := (others =>'0');
518 signal Bcnt_reg : std_logic_vector(11 downto 0) := (others =>'0');
519 signal OC_reg : std_logic_vector(31 downto 0) := (others =>'0');
520 signal V2S : std_logic := '0';
521 signal S2V : std_logic := '0';
522 signal S2V_cntr : std_logic_vector(5 downto 0) := (others => '0');
523 signal S2V_sr : std_logic_vector(3 downto 0) := (others => '0');
524 signal ddr_rdata : std_logic_vector(7 downto 0) := (others =>'0');
525 signal ipb_clk_dcm : std_logic := '0';
526 signal ipb_clk : std_logic := '0';
527 signal clk125_dcm : std_logic := '0';
528 signal clk125 : std_logic := '0';
529 signal DRPclk_dcm : std_logic := '0';
530 signal DRPclk : std_logic := '0';
531 signal sysclk_dcm : std_logic := '0';
532 signal sysclk : std_logic := '0';
533 signal clkfb : std_logic := '0';
534 signal refclk_dcm : std_logic := '0';
535 signal refclk : std_logic := '0';
536 signal mem_clk_dcm : std_logic := '0';
537 signal mem_clk : std_logic := '0';
538 signal sysclk_inp : std_logic := '0';
539 signal sysclk_in : std_logic := '0';
540 --signal clk125 : std_logic := '0';
541 signal sys_lock : std_logic := '0';
542 signal sys_lock_n : std_logic := '0';
543 signal ldc_reset : std_logic := '0';
544 signal ldc_GTXreset : std_logic := '0';
545 signal lsc_start : std_logic := '0';
546 signal lsc_reset : std_logic := '0';
547 signal lsc_GTXreset : std_logic := '0';
548 signal amc_reset : std_logic := '0';
549 signal amc_GTXreset : std_logic := '0';
550 signal conf7_q : std_logic := '0';
551 signal conf7_fall : std_logic := '0';
552 signal run : std_logic := '0';
553 signal LSC_LinkDown : std_logic := '0';
554 signal mem_rst : std_logic := '0';
555 signal mem_test : std_logic_vector(1 downto 0) := (others =>'0');
556 signal mem_stat : std_logic_vector(63 downto 0) := (others =>'0');
557 signal mem_ack : std_logic := '0';
558 signal mem_data : std_logic_vector(31 downto 0) := (others =>'0');
559 signal EventData : array3X67 := (others => (others => '0'));
560 signal wport_rdy : std_logic_vector(2 downto 0) := (others =>'0');
561 signal EventBufAddr : array3x14 := (others => (others => '0'));
562 signal EventBufAddr_we : std_logic_vector(2 downto 0) := (others =>'0');
563 signal evt_buf_full : std_logic_vector(2 downto 0) := (others =>'0');
564 signal wport_FIFO_full : std_logic_vector(2 downto 0) := (others =>'0');
565 --signal TCP_din : std_logic_vector(31 downto 0) := (others =>'0');
566 --signal TCP_channel : std_logic_vector(1 downto 0) := (others =>'0');
567 --signal TCP_wrqst : std_logic := '0';
568 --signal TCP_re : std_logic := '0';
569 --signal TCP_dout : std_logic_vector(31 downto 0) := (others =>'0');
570 --signal TCP_raddr : std_logic_vector(23 downto 0) := (others =>'0');
571 --signal TCP_length : std_logic_vector(11 downto 0) := (others =>'0');
572 --signal TCP_dout_valid : std_logic := '0';
573 --signal TCP_rrqst : std_logic := '0';
574 --signal TCP_rack : std_logic := '0';
575 --signal TCP_lastword : std_logic := '0';
576 signal MonBufOvfl : std_logic := '0';
577 signal MonBuf_empty : std_logic := '0';
578 --signal inc_mon_cntr : std_logic := '0';
579 signal mon_evt_wc : std_logic_vector(47 downto 0) := (others =>'0');
580 signal mon_evt_cnt : std_logic_vector(31 downto 0) := (others =>'0');
581 signal mon_ctrl : std_logic_vector(31 downto 0) := (others =>'0');
582 --signal TCPbuf_avl : std_logic := '0';
583 signal mon_buf_avl : std_logic := '0';
584 signal EventBufAddrAvl : std_logic := '0';
585 signal EventBufAddrRe : std_logic := '0';
586 signal mon_wp : std_logic_vector(31 downto 0) := (others =>'0');
587 --signal TCP_releaseAck : std_logic_vector(2 downto 0) := (others =>'0');
588 --signal TCP_releaseRqst : std_logic_vector(2 downto 0) := (others =>'0');
589 --signal TCP_releaseAddr : array3X13 := (others => (others => '0'));
590 signal EventBuf_rqst : std_logic_vector(3 downto 0) := (others =>'0');
591 signal rst_cntr : std_logic := '0';
592 signal rst_ddr_pa : std_logic := '0';
593 signal inc_ddr_pa : std_logic := '0';
594 signal Source_ID : array3X12 := (others => (others => '0'));
595 signal ddr_pa : std_logic_vector(9 downto 0) := (others =>'0');
596 signal CDRclk : std_logic := '0';
597 signal TTS_clk : std_logic := '0';
598 signal chk_lock : std_logic := '0';
599 signal chk_lock_q : std_logic := '0';
600 signal BC0 : std_logic := '0';
601 signal BC0_dl : std_logic := '0';
602 signal BC0_locked : std_logic_vector(1 downto 0) := (others =>'0');
603 signal BC0_cntr : std_logic_vector(4 downto 0) := (others =>'0');
604 signal T3_trigger : std_logic := '0';
605 signal inc_BX_offset : std_logic := '0';
606 signal en_HCAL_trig : std_logic := '0';
607 signal ec_BX_offset : std_logic := '0';
608 signal add_two : std_logic_vector(1 downto 0) := (others =>'0');
609 signal BX_offset : std_logic_vector(11 downto 0) := (others =>'0');
610 signal BX_offset2SC : std_logic_vector(11 downto 0) := (others =>'0');
611 signal bcnt : std_logic_vector(11 downto 0) := x"000";
612 signal LocalL1A_cfg : std_logic_vector(31 downto 0) := (others =>'0');
613 signal BCN_off : std_logic_vector(12 downto 0) := (others =>'0');
614 signal OC_off : std_logic_vector(3 downto 0) := (others =>'0');
615 signal en_cal_win : std_logic := '0';
616 signal CalibCtrl : std_logic_vector(31 downto 0) := x"0d800d80";
617 signal cal_win_high : std_logic_vector(11 downto 0) := (others =>'0');
618 signal cal_win_low : std_logic_vector(11 downto 0) := (others =>'0');
619 signal CalType : std_logic_vector(3 downto 0) := (others =>'0');
620 signal TTC_Brcst : std_logic_vector(3 downto 0) := (others =>'0');
621 signal local_TTCcmd : std_logic := '0';
622 signal en_brcst : std_logic := '0';
623 signal ttc_start : std_logic := '0';
624 signal ttc_stop : std_logic := '0';
625 signal ttc_soft_reset : std_logic := '0';
626 signal ttc_soft_resetp : std_logic := '0';
627 signal ttc_ready : std_logic := '0';
628 signal ttc_serr : std_logic := '0';
629 signal ttc_derr : std_logic := '0';
630 signal ttc_bcnt_err : std_logic := '0';
631 signal ttc_evcnt_reset : std_logic := '0';
632 signal inc_rate_ofw : std_logic := '0';
633 signal rate_ofw : std_logic := '0';
634 signal rate_ofwp : std_logic := '0';
635 signal rate_ofw_q : std_logic := '0';
636 signal sync_lost : std_logic := '0';
637 signal oc_cntr : std_logic_vector(3 downto 0) := (others =>'0');
638 signal ttc_resync : std_logic := '0';
639 signal AllEventBuilt : std_logic := '0';
640 signal dcc_quiet : std_logic := '0';
641 signal inc_oc : std_logic := '0';
642 signal inc_L1ac : std_logic := '0';
643 signal inc_bcnterr : std_logic := '0';
644 signal inc_serr : std_logic := '0';
645 signal inc_derr : std_logic := '0';
646 signal evn_fifo_full : std_logic := '0';
647 signal event_number_avl : std_logic := '0';
648 signal state : std_logic_vector(3 downto 0) := (others =>'0');
649 signal TTS_wait : std_logic_vector(20 downto 0) := (others =>'0');
650 signal event_number : std_logic_vector(59 downto 0) := (others =>'0');
651 signal TTC_serr_cntr : std_logic_vector(7 downto 0) := (others =>'0');
652 signal TTC_derr_cntr : std_logic_vector(7 downto 0) := (others =>'0');
653 signal TTC_BcntErr_cntr : std_logic_vector(7 downto 0) := (others =>'0');
654 signal L1A_cntr : std_logic_vector(7 downto 0) := (others =>'0');
655 signal L1A_OFW_cntr : std_logic_vector(7 downto 0) := (others =>'0');
656 signal L1A_BUSY_cntr : std_logic_vector(7 downto 0) := (others =>'0');
657 signal L1A_LOS_cntr : std_logic_vector(7 downto 0) := (others =>'0');
658 signal run_cntr : std_logic_vector(7 downto 0) := (others =>'0');
659 signal ready_cntr : std_logic_vector(7 downto 0) := (others =>'0');
660 signal busy_cntr : std_logic_vector(7 downto 0) := (others =>'0');
661 signal sync_cntr : std_logic_vector(7 downto 0) := (others =>'0');
662 signal ovfl_cntr : std_logic_vector(7 downto 0) := (others =>'0');
663 signal ReSync_cntr : std_logic_vector(15 downto 0) := (others =>'0');
664 signal counter_we : std_logic_vector(3 downto 0) := (others => '0');
665 signal counter_wa : std_logic_vector(9 downto 0) := (others => '0');
666 signal counter_ra_l : std_logic_vector(9 downto 0) := (others => '0');
667 signal counter_ra_h : std_logic_vector(9 downto 0) := (others => '0');
668 signal CounterDi : std_logic_vector(47 downto 0) := (others => '0');
669 signal CounterDoA : std_logic_vector(47 downto 0) := (others => '0');
670 signal CounterDoB : std_logic_vector(63 downto 0) := (others => '0');
671 signal div : std_logic_vector(7 downto 0) := (others =>'0');
672 signal CntrRst : std_logic := '0';
673 signal CntrRstCycle : std_logic := '0';
674 signal CounterDoB_h : std_logic := '0';
675 signal got_SN : std_logic := '0';
676 signal ipb_strobe_q : std_logic := '0';
677 signal SFP_clk : std_logic := '0';
678 signal AMC_clk : std_logic := '0';
679 signal AMC_clk_in : std_logic := '0';
680 signal SV_Cntr : std_logic_vector(7 downto 0) := (others => '0');
681 signal sysclk_div : std_logic_vector(7 downto 0) := (others => '0');
682 signal SFP_UsrClk : std_logic := '0';
683 signal SFP_TxOutClk : std_logic := '0';
684 signal I2C_debug_out : std_logic_vector(15 downto 0) := (others =>'0');
685 signal SFPOSC_rdy : std_logic := '0';
686 signal reset : std_logic := '0';
687 signal DAQ_reset : std_logic := '0';
688 signal AMCOSC_rdy : std_logic := '0';
689 --signal cs_clk_in : std_logic := '0';
690 --signal cs_clk : std_logic := '0';
691 signal TTC_debug : std_logic_vector(63 downto 0) := (others =>'0');
692 signal TxDisable_i : std_logic_vector(3 downto 0) := (others => '0');
693 signal DAQfifo_re : std_logic := '0';
694 signal DAQfifoAlmostEmpty : std_logic := '0';
695 signal DAQfifoEmpty : std_logic := '0';
696 signal DAQfifo_do : std_logic_vector(63 downto 0) := (others =>'0');
697 signal DAQ_debug_in : std_logic_vector(63 downto 0) := (others =>'0');
698 signal LDC_debug_out : std_logic_vector(63 downto 0) := (others =>'0');
699 signal LSC_debug_out : std_logic_vector(63 downto 0) := (others =>'0');
700 signal ddr_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
701 signal ddr_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
702 signal GbE_REFCLK : std_logic := '0';
703 signal S6Link_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
704 signal S6Link_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
705 signal GbE_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
706 signal GbE_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
707 signal AMC_debug_in : std_logic_vector(255 downto 0) := (others =>'0');
708 signal AMC_debug_out : std_logic_vector(255 downto 0) := (others =>'0');
709 signal SFP0_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
710 signal SFP0_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
711 signal SFP1_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
712 signal SFP1_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
713 signal ipb_master_out : ipb_wbus;
714 signal ipb_master_in : ipb_rbus;
715 signal SN : std_logic_vector(8 downto 0) := (others =>'0');
716 signal MACADDR : std_logic_vector(47 downto 0) := (others =>'0');
717 signal ipaddr : std_logic_vector(31 downto 0) := (others =>'0');
718 signal en_RARP : std_logic := '0';
719 --signal SPI_IP : std_logic_vector(31 downto 0) := (others =>'0');
720 signal status : std_logic_vector(31 downto 0) := (others =>'0');
721 signal cmd : std_logic_vector(31 downto 0) := (others =>'0');
722 signal cmd0_dl : std_logic_vector(1 downto 0) := (others =>'0');
723 signal cmd2_dl : std_logic_vector(1 downto 0) := (others =>'0');
724 signal conf : std_logic_vector(15 downto 0) := (others =>'0');
725 signal LSC_ID : std_logic_vector(15 downto 0) := x"1234";
726 signal OT : std_logic := '0';
727 signal inc_HTRCRC_err : std_logic := '0';
728 signal ttc_data : std_logic_vector(31 downto 0) := (others => '0');
729 signal sysmon_data : std_logic_vector(31 downto 0) := (others => '0');
730 signal HCAL_trig_data : std_logic_vector(31 downto 0) := (others => '0');
731 signal device_temp : std_logic_vector(11 downto 0) := (others =>'0');
732 signal ALM : std_logic_vector(7 downto 0) := (others =>'0');
733 signal evt_data_rdy : std_logic_vector(2 downto 0) := (others => '0');
734 signal evt_data_re : std_logic_vector(2 downto 0) := (others => '0');
735 signal evt_data_we : std_logic_vector(2 downto 0) := (others => '0');
736 --signal event_size : array3x13;
737 signal SFP_data : std_logic_vector(31 downto 0) := (others =>'0');
738 signal SFP_ack : std_logic := '0';
739 --signal TCP_data : std_logic_vector(31 downto 0) := (others =>'0');
740 --signal TCP_ack : std_logic := '0';
741 signal S2V_SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
742 signal resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
743 signal sysclk_div7SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
744 signal resetCntr_SyncRegs : std_logic_vector(2 downto 0) := (others =>'0');
745 signal newIPADDR : std_logic := '0';
746 signal newIPADDRSyncRegs : std_logic_vector(2 downto 0) := (others =>'0');
747 signal DNA_out : std_logic := '0';
748 signal load_DNA : std_logic := '0';
749 signal shift_DNA : std_logic_vector(2 downto 0) := (others =>'0');
750 signal DNA_cntr : std_logic_vector(5 downto 0) := (others =>'0');
751 signal DNA : std_logic_vector(56 downto 0) := (others =>'0');
752 signal Dis_pd : std_logic := '0';
753 signal enSFP : std_logic_vector(3 downto 0) := (others =>'0');
754 signal SFP_down : std_logic_vector(2 downto 0) := (others =>'0');
755 signal WrtMonBlkDone : std_logic_vector(2 downto 0) := (others =>'0');
756 signal WrtMonEvtDone : std_logic_vector(2 downto 0) := (others =>'0');
757 component icon2
758  PORT (
759  CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
760  CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
761 
762 end component;
763 component ila16x32k
764  PORT (
765  CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
766  CLK : IN STD_LOGIC;
767  DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
768  TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
769 
770 end component;
771 signal CONTROL0 : std_logic_vector(35 downto 0) := (others => '0');
772 signal CONTROL1 : std_logic_vector(35 downto 0) := (others => '0');
773 signal TRIG0 : std_logic_vector(7 downto 0) := (others => '0');
774 signal TRIG1 : std_logic_vector(7 downto 0) := (others => '0');
775 signal DATA0 : std_logic_vector(15 downto 0) := (others => '0');
776 signal DATA1 : std_logic_vector(15 downto 0) := (others => '0');
777 begin
778 --i_icon : icon2
779 -- port map (
780 -- CONTROL0 => CONTROL0,
781 -- CONTROL1 => CONTROL1);
782 --i_ila : ila16x32k
783 -- port map (
784 -- CONTROL => CONTROL0,
785 -- CLK => sysclk,
786 -- DATA => DATA0,
787 -- TRIG0 => TRIG0);
788 --DATA0(14) <= evt_buf_full(0);
789 --DATA0(13) <= evt_data_re(0);
790 --DATA0(12) <= evt_data_rdy(0);
791 --DATA0(11 downto 10) <= EventBufAddr(0)(5 downto 4);
792 --DATA0(9 downto 8) <= EventData(0)(65 downto 64);
793 --DATA0(7) <= wport_rdy(0);
794 --DATA0(6) <= wport_FIFO_full(0);
795 --DATA0(5) <= evt_data_we(0);
796 --DATA0(4) <= EventBufAddr_we(0);
797 --DATA0(3 downto 0) <= mem_stat(3 downto 0);
798 --TRIG0(7 downto 4) <= (others => '0');
799 --TRIG0(3) <= wport_rdy(0);
800 --TRIG0(2) <= EventBufAddr_we(0);
801 --TRIG0(1) <= evt_data_re(0);
802 --TRIG0(0) <= evt_data_rdy(0);
803 --
804 --i_il2 : ila16x32k
805 -- port map (
806 -- CONTROL => CONTROL1,
807 -- CLK => mem_stat(19),
808 -- DATA => DATA1,
809 -- TRIG0 => TRIG1);
810 --DATA1(14 downto 0) <= mem_stat(18 downto 4);
811 --TRIG1(7 downto 2) <= (others => '0');
812 --TRIG1(1 downto 0) <= mem_stat(18 downto 17);
813 i_TTS_if: TTS_if PORT MAP(
814  sysclk => sysclk,
815  TTS_clk => TTS_clk,
816  reset => sys_lock_n,
817  local_TTC => conf(8),
818  TTS => state,
819  TTS_out_p => TTS_out_p,
820  TTS_out_n => TTS_out_n
821  );
822 i_HCAL_trig: HCAL_trig PORT MAP(
823  TTC_clk => TTC_clk,
824  DRPCLK => DRPclk,
825  reset => reset,
826  BC0 => BC0_dl ,
827  en_HCAL_trig => en_HCAL_trig ,
828  Trigdata => Trigdata,
829  triggerOut => HCAL_trigger,
830  ipb_clk => ipb_clk,
831  ipb_write => ipb_master_out.ipb_write ,
832  ipb_strobe => ipb_master_out.ipb_strobe ,
833  ipb_addr => ipb_master_out.ipb_addr ,
834  ipb_wdata => ipb_master_out.ipb_wdata ,
835  ipb_rdata => HCAL_trig_data,
836  GTX_REFCLKp => CDR_REFCLK_P,
837  GTX_REFCLKn => CDR_REFCLK_N,
838  GTX_RXp => SFP2_RXP,
839  GTX_RXn => SFP2_RXN,
840  GTX_TXp => SFP2_TXP,
841  GTX_TXn => SFP2_TXN
842  );
843 TxDisable <= TxDisable_i;
844 i_I2C: I2C PORT MAP(
845  clk => DRPclk ,
846  ipb_clk => clk125,
847  reset => sys_lock_n,
848  addr => ipb_master_out.ipb_addr,
849  rdata => I2C_data,
850  CLK_rdy => CLK_rdy,
851  CLK_SCL => CLK_SCL,
852  CLK_SDA => CLK_SDA,
853  SFP_ABS => SFP_ABS,
854  SFP_LOS => SFP_LOS,
855  SFP_SCL => SFP_SCL,
856  SFP_SDA => SFP_SDA
857  );
858 i_SPI_SCK_buf: bufh port map(i => SPI_SCK, o => SPI_SCK_buf);
859 i_SPI_if: SPI_if PORT MAP(
860  SCK => SPI_SCK ,
861  CSn => SPI_CS_b ,
862  MOSI => SPI_MOSI ,
863  MISO => SPI_MISO ,
864  SN => SN,
865  OT => ALM(0),
866  IsT1 => '1',
867  SPI_we => open,
868  en_RARP => en_RARP,
869  newIPADDR => newIPADDR,
870  IPADDR => IPADDR,
871  SPI_rdata => (others => '0'),
872  SPI_wdata => open,
873  SPI_addr => open
874  );
875 i_ttc_if: ttc_if PORT MAP(
876  clk => sysclk ,
877  refclk => sysclk,
878  reset => reset,
879  run => run,
880  IsG2 => '0',
881  TTC_strobe => TTC_strobe,
882  sys_lock => sys_lock,
883  local_TTC => conf(8),
884  local_TTCcmd => local_TTCcmd ,
885  single_TTCcmd => cmd(8),
886  TTS_clk => TTS_clk,
887  BC0 => BC0,
888  DIV4 => DIV4,
889  DIV_nRST => DIV_nRST,
890  CDRclk_p => CDRclk_p,
891  CDRclk_n => CDRclk_n,
892  CDRclk_out => CDRclk,
893  CDRdata_p => CDRdata_p,
894  CDRdata_n => CDRdata_n,
895  TTCdata_p => TTCdata_p,
896  TTCdata_n => TTCdata_n,
897  TTC_LOS => TTC_LOS,
898  TTC_LOL => TTC_LOL,
899  BCN_off => BCN_off,
900  OC_off => OC_off,
901  en_cal_win => en_cal_win,
902  cal_win_high => cal_win_high ,
903  cal_win_low => cal_win_low ,
904  CalType => CalType,
905  TTC_Brcst => TTC_Brcst,
906  ovfl_warning => L1Aovfl_warning ,
907  ipb_clk => ipb_clk,
908  ipb_write => ipb_master_out.ipb_write ,
909  ipb_strobe => ipb_master_out.ipb_strobe ,
910  ipb_addr => ipb_master_out.ipb_addr ,
911  ipb_wdata => ipb_master_out.ipb_wdata ,
912  ipb_rdata => ttc_data,
913  en_localL1A => conf(2),
914  LocalL1A_cfg => LocalL1A_cfg ,
915  localL1A_s => cmd(26),
916  localL1A_r => cmd(10),
917  localL1A_periodic => status(10),
918  T3_trigger => T3_trigger,
919  HCAL_trigger => HCAL_trigger ,
920  EvnRSt_l => cmd(11),
921  OcnRSt_l => cmd(12),
922  en_brcst => en_brcst,
923  ttc_start => ttc_start,
924  ttc_stop => ttc_stop,
925  ttc_soft_reset => ttc_soft_reset ,
926  ttc_ready => ttc_ready,
927  ttc_serr => ttc_serr,
928  ttc_derr => ttc_derr,
929  ttc_bcnt_err => ttc_bcnt_err ,
930  rate_OFW => rate_OFW,
931  sync_lost => sync_lost,
932  inc_oc => inc_oc,
933  inc_l1ac => inc_l1ac,
934  inc_bcnterr => inc_bcnterr ,
935  inc_serr => inc_serr,
936  inc_derr => inc_derr,
937  state => state,
938  evn_fifo_full => evn_fifo_full ,
939  ttc_evcnt_reset => ttc_evcnt_reset ,
940  event_number_avl => event_number_avl ,
941  event_number => event_number
942  );
943 local_TTCcmd <= conf(5) or conf(8);
944 CalibCtrl(31) <= en_cal_win;
945 CalibCtrl(30 downto 28) <= "000";
946 CalibCtrl(27 downto 16) <= cal_win_high;
947 CalibCtrl(15 downto 12) <= CalType;
948 CalibCtrl(11 downto 0) <= cal_win_low;
949 cal_win_high(11 downto 6) <= "110110";
950 cal_win_low(11 downto 6) <= "110110";
951 i_S2V: IBUFDS generic map(DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25") port map(i => S2V_p, ib => S2V_n, o => S2V);
952 process(CDRclk)
953 begin
954  if(CDRclk'event and CDRclk = '1')then
955  if(conf(15) = '0')then
956  T3_trigger <= '0';
957  else
958  T3_trigger <= S2V;
959  end if;
960  end if;
961 end process;
962 i_GbE_REFCLK: IBUFDS_GTE2
963  port map
964  (
965  O => GbE_REFCLK,
966  ODIV2 => open,
967  CEB => '0',
968  I => GbE_REFCLK_P, -- Connect to package pin AB6
969  IB => GbE_REFCLK_N -- Connect to package pin AB5
970  );
971 i_TTCclk_in : IBUFGDS generic map (DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25")
972  port map (
973  O => TTCclk_in, -- Clock buffer output
974  I => TTCclk_p, -- Diff_p clock buffer input
975  IB => TTCclk_n -- Diff_n clock buffer input
976  );
977 i_TTC_CLK_buf: bufg port map(i => TTCclk_in, o => TTC_Clk);
978 i_sysclk_in_buf: bufh port map(i => GbE_REFCLK, o => sysclk_in);
979 i_PLL_sysclk : PLLE2_BASE
980  generic map (
981  BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
982  CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
983  CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
984  CLKIN1_PERIOD => 8.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
985  -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
986  CLKOUT0_DIVIDE => 5,
987  CLKOUT1_DIVIDE => 32,
988  CLKOUT2_DIVIDE => 20,
989  DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
990  REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
991  STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
992  )
993  port map (
994  -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
995  CLKOUT0 => sysclk_dcm,
996  CLKOUT1 => ipb_clk_dcm ,
997  CLKOUT2 => DRPclk_dcm,
998  -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
999  CLKFBOUT => clk125_dcm, -- 1-bit output: Feedback clock
1000  -- Status Port: 1-bit (each) output: PLL status ports
1001  LOCKED => sys_lock, -- 1-bit output: LOCK
1002  -- Clock Input: 1-bit (each) input: Clock input
1003  CLKIN1 => sysclk_in, -- 1-bit input: Input clock
1004  -- Control Ports: 1-bit (each) input: PLL control ports
1005  PWRDWN => '0', -- 1-bit input: Power-down
1006  RST => '0', -- 1-bit input: Reset
1007  -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
1008  CLKFBIN => clk125 -- 1-bit input: Feedback clock
1009  );
1010 i_clk125_buf: bufg port map(i => clk125_dcm, o => clk125 );
1011 i_ipb_clk_buf: bufg port map(i => ipb_clk_dcm, o => ipb_clk);
1012 i_DRPclk_buf: bufg port map(i => DRPclk_dcm, o => DRPclk );
1013 i_sysclk_buf: bufg port map(i => sysclk_dcm, o => sysclk );
1014 --i_refclk_buf: bufg port map(i => refclk_dcm, o => refclk);
1015 reset <= not sys_lock or cmd(0);
1016 --sysclk <= refclk;
1017 process(sysclk,reset)
1018 begin
1019  if(reset = '1')then
1020  resetSyncRegs <= (others => '1');
1021  elsif(sysclk'event and sysclk = '1')then
1022  resetSyncRegs <= resetSyncRegs(1 downto 0) & '0';
1023  end if;
1024 end process;
1025 i_ddr_if: ddr_if PORT MAP(
1026  mem_clk_p => sys_clk_p,
1027  mem_clk_n => sys_clk_n,
1028  mem_rst => mem_rst,
1029  clk_ref => sysclk,
1030  sysclk => sysclk,
1031  TCPclk => sysclk,
1032  reset => reset,
1033  resetsys => resetSyncRegs(2),
1034  run => run,
1035  mem_test => mem_test,
1036  EventData => EventData,
1037  EventData_we => evt_data_we,
1038  wport_rdy => wport_rdy,
1039  WrtMonBlkDone => WrtMonBlkDone ,
1040  WrtMonEvtDone => WrtMonEvtDone ,
1041  KiloByte_toggle => open,
1042  EoB_toggle => open,
1043  EventBufAddr => EventBufAddr ,
1044  EventBufAddr_we => EventBufAddr_we ,
1045  EventFIFOfull => wport_FIFO_full ,
1046  TCP_din => (others => '0'),
1047  TCP_channel => (others => '0'),
1048  TCP_we => '0',
1049  TCP_wcount => open,
1050  TCP_dout => open,
1051  TCP_raddr => (others => '0'),
1052  TCP_length => (others => '0'),
1053  TCP_dout_valid => open,
1054  TCP_rrqst => '0',
1055  TCP_rack => open,
1056  TCP_lastword => open,
1057  page_addr => ddr_pa,
1058  ipb_clk => ipb_clk,
1059  ipb_write => ipb_master_out.ipb_write ,
1060  ipb_strobe => ipb_master_out.ipb_strobe ,
1061  ipb_addr => ipb_master_out.ipb_addr ,
1062  ipb_wdata => ipb_master_out.ipb_wdata ,
1063  ipb_rdata => mem_data,
1064  ipb_ack => mem_ack,
1065  mem_stat => mem_stat,
1066  device_temp => device_temp ,
1067  ddr3_dq => ddr3_dq,
1068  ddr3_dm => ddr3_dm,
1069  ddr3_addr => ddr3_addr,
1070  ddr3_ba => ddr3_ba,
1071  ddr3_dqs_p => ddr3_dqs_p,
1072  ddr3_dqs_n => ddr3_dqs_n,
1073  ddr3_ras_n => ddr3_ras_n,
1074  ddr3_cas_n => ddr3_cas_n,
1075  ddr3_we_n => ddr3_we_n,
1076  ddr3_reset_n => ddr3_reset_n ,
1077  ddr3_cke => ddr3_cke,
1078  ddr3_odt => ddr3_odt,
1079  ddr3_ck_p => ddr3_ck_p,
1080  ddr3_ck_n => ddr3_ck_n
1081  );
1082 --mem_rst <= not sys_lock or not CLK_rdy or cmd(5) or cmd(0);
1083 mem_rst <= not sys_lock or not CLK_rdy or cmd(5);
1084 MACADDR <= x"080030f30" & '0' & not SN(8) & '0' & not SN(7 downto 6) & '1' & SN(5 downto 0);
1085 i_ipbus_if: ipbus_if PORT MAP(
1086  ipb_clk => ipb_clk,
1087  UsRclk => clk125,
1088  DRPclk => DRPclk,
1089  reset => rst_ipbus,
1090  GTX_RESET => sys_lock_n,
1091  MACADDR => MACADDR, -- new mac range 08-00-30-F3-00-00 to 08-00-30-F3-00-7F
1092  en_RARP => en_RARP,
1093  IPADDR => IPADDR,
1094  GbE_REFCLK => GbE_REFCLK,
1095  S6LINK_RXN => S6LINK_RXN,
1096  S6LINK_RXP => S6LINK_RXP,
1097  S6LINK_TXN => S6LINK_TXN,
1098  S6LINK_TXP => S6LINK_TXP,
1099  wr_AMC_en => wr_AMC_en,
1100  amc_en => AMC_en,
1101  ipb_out => ipb_master_out,
1102  ipb_in => ipb_master_in,
1103  got_SN => got_SN,
1104  SN => SN,
1105  debug_in => (others => '0'),
1106  debug_out => open
1107  );
1108 --LSC_LinkDown <= '1' when conf(1) = '0' or or_reduce(EnSFP(2 downto 0) and SFP_down) = '1' else '0';
1109 --status(0) <= LSC_LinkDown;
1110 status(0) <= or_reduce(SFP_down);
1111 status(1) <= MonBufOvfl;
1112 status(2) <= mon_evt_cnt(10);
1113 status(3) <= MonBuf_empty;
1114 status(4) <= mem_stat(0); -- monitor input FIFO overflow
1115 status(5) <= not ttc_ready;
1116 status(6) <= ttc_bcnt_err;
1117 status(7) <= ttc_serr;
1118 status(8) <= ttc_derr;
1119 status(9) <= sync_lost;
1120 status(13) <= L1Aovfl_warning;
1121 status(15) <= mem_stat(63);
1122 status(23) <= '0';
1123 run <= conf(0);
1124 EnSFP(3) <= not conf(1);
1125 mem_test <= conf(6) & conf(4);
1126 --en_brcst <= conf(5);
1127 en_brcst <= '0';
1128 i_cmd0_dl0 : SRL16E
1129  port map (
1130  Q => cmd0_dl(0), -- SRL data output
1131  A0 => '1', -- Select[0] input
1132  A1 => '1', -- Select[1] input
1133  A2 => '1', -- Select[2] input
1134  A3 => '0', -- Select[3] input
1135  CE => '1', -- Clock enable input
1136  CLK => ipb_clk, -- Clock input
1137  D => cmd(0) -- SRL data input
1138  );
1139 i_cmd0_dl1 : SRL16E
1140  port map (
1141  Q => cmd0_dl(1), -- SRL data output
1142  A0 => '1', -- Select[0] input
1143  A1 => '1', -- Select[1] input
1144  A2 => '1', -- Select[2] input
1145  A3 => '0', -- Select[3] input
1146  CE => '1', -- Clock enable input
1147  CLK => ipb_clk, -- Clock input
1148  D => cmd0_dl(0) -- SRL data input
1149  );
1150 i_cmd2_dl0 : SRL16E
1151  port map (
1152  Q => cmd2_dl(0), -- SRL data output
1153  A0 => '1', -- Select[0] input
1154  A1 => '1', -- Select[1] input
1155  A2 => '1', -- Select[2] input
1156  A3 => '0', -- Select[3] input
1157  CE => '1', -- Clock enable input
1158  CLK => ipb_clk, -- Clock input
1159  D => cmd(2) -- SRL data input
1160  );
1161 i_cmd2_dl1 : SRL16E
1162  port map (
1163  Q => cmd2_dl(1), -- SRL data output
1164  A0 => '1', -- Select[0] input
1165  A1 => '1', -- Select[1] input
1166  A2 => '1', -- Select[2] input
1167  A3 => '0', -- Select[3] input
1168  CE => '1', -- Clock enable input
1169  CLK => ipb_clk, -- Clock input
1170  D => cmd2_dl(0) -- SRL data input
1171  );
1172 process(ipb_clk)
1173 begin
1174  if(ipb_clk'event and ipb_clk = '1')then
1175  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = CSR_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1176  cmd <= ipb_master_out.ipb_wdata;
1177  else
1178  cmd <= (others => '0');
1179  end if;
1180  conf7_q <= conf(7);
1181  conf7_fall <= conf7_q and not conf(7);
1182  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = CFG_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1183  conf <= ipb_master_out.ipb_wdata(15 downto 0);
1184  end if;
1185  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = HTR_EN_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1186  Dis_pd <= ipb_master_out.ipb_wdata(15);
1187  EnSFP(1 downto 0) <= ipb_master_out.ipb_wdata(13 downto 12);
1188  AMC_en <= ipb_master_out.ipb_wdata(11 downto 0);
1189  if(AMC_en = ipb_master_out.ipb_wdata(11 downto 0))then
1190  wr_AMC_en <= '0';
1191  else
1192  wr_AMC_en <= '1';
1193  end if;
1194  if(EnSFP(1 downto 0) = ipb_master_out.ipb_wdata(13 downto 12))then
1195  wr_EnSFP <= '0';
1196  else
1197  wr_EnSFP <= '1';
1198  end if;
1199  else
1200  wr_AMC_en <= '0';
1201  wr_EnSFP <= '0';
1202  end if;
1203  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"001a" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1204  TTS_disable <= ipb_master_out.ipb_wdata(11 downto 0);
1205  end if;
1206  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = TTC_cal_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1207  en_cal_win <= ipb_master_out.ipb_wdata(31);
1208  cal_win_high(5 downto 0) <= ipb_master_out.ipb_wdata(21 downto 16);
1209  cal_win_low(5 downto 0) <= ipb_master_out.ipb_wdata(5 downto 0);
1210  end if;
1211  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1212  Source_ID(0)(11 downto 0) <= ipb_master_out.ipb_wdata(11 downto 0);
1213  end if;
1214  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id1_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1215  Source_ID(1)(11 downto 0) <= ipb_master_out.ipb_wdata(11 downto 0);
1216  end if;
1217  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"001c" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1218  LocalL1A_cfg <= ipb_master_out.ipb_wdata;
1219  end if;
1220  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SFP_CSR_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1221  LSC_ID(15 downto 2) <= ipb_master_out.ipb_wdata(31 downto 18);
1222  TxDisable_i <= ipb_master_out.ipb_wdata(15 downto 12);
1223  end if;
1224  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = TTC_bcnt_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1225  OC_OFF <= ipb_master_out.ipb_wdata(19 downto 16);
1226  BCN_OFF <= ipb_master_out.ipb_wdata(12 downto 0);
1227  end if;
1228  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = fake_length_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1229  fake_length <= ipb_master_out.ipb_wdata(19 downto 0);
1230  end if;
1231  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"0019" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1232  pattern <= ipb_master_out.ipb_wdata(11 downto 8);
1233 -- Trig_mask <= ipb_master_out.ipb_wdata(7 downto 0);
1234  end if;
1235  if(reset = '1' or (ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = MON_ctrl_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1'))then
1236  ddr_pa <= (others => '0');
1237  elsif(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = PAGE_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1238  if(run = '1')then
1239  if(MonBuf_empty = '0')then
1240  ddr_pa <= ddr_pa + 1;
1241  end if;
1242  else
1243  ddr_pa <= ipb_master_out.ipb_wdata(9 downto 0);
1244  end if;
1245  end if;
1246  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = PAGE_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1' and run = '1' and MonBuf_empty = '0')then
1247  inc_ddr_pa <= '1';
1248  else
1249  inc_ddr_pa <= '0';
1250  end if;
1251  end if;
1252 end process;
1253 ipb_master_in.ipb_ack <= ipb_master_out.ipb_strobe when ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(17) = '0' else mem_ack;
1254 process(ipb_master_out.ipb_addr)
1255 begin
1256  if(ipb_master_out.ipb_addr(27) = '1' or ipb_master_out.ipb_addr(17) = '1')then
1257  ipb_master_in.ipb_rdata <= mem_data;
1258 -- elsif(ipb_master_out.ipb_addr(20 downto 18) /= "000")then
1259 -- if(ipb_master_out.ipb_addr(0) = '0')then
1260 -- ipb_master_in.ipb_rdata <= mem_stat(31 downto 0);
1261 -- else
1262 -- ipb_master_in.ipb_rdata <= mem_stat(63 downto 32);
1263 -- end if;
1264  elsif(ipb_master_out.ipb_addr(15 downto 5) = CSR_addr(15 downto 5))then
1265  case ipb_master_out.ipb_addr(4 downto 0) is
1266  when "00000" => ipb_master_in.ipb_rdata <= not SN(7 downto 0) & not SN(8) & status(22 downto 0);
1267  when "00001" => ipb_master_in.ipb_rdata <= K7version & conf;
1268  when "00010" => ipb_master_in.ipb_rdata <= mon_ctrl;
1269  when "00011" => ipb_master_in.ipb_rdata <= '0' & SFP_down & AMC_Ready & Dis_pd & EnSFP(2 downto 0) & AMC_en;
1270  when "00100" => ipb_master_in.ipb_rdata <= LSC_ID & TxDisable_i & TxFault & (TTC_LOL or TTC_LOL) & SFP_LOS & SFP_ABS;
1271  when "00101" => ipb_master_in.ipb_rdata <= AMC_status;
1272  when "00110" => ipb_master_in.ipb_rdata <= x"0" & BC0_lock & x"0" & BX_offset2SC;
1273  when "00111" => ipb_master_in.ipb_rdata <= x"00000" & Source_ID(0);
1274  when "01000" => ipb_master_in.ipb_rdata <= x"000" & OC_OFF & "000" & BCN_OFF;
1275  when "01001" => ipb_master_in.ipb_rdata <= CalibCtrl;
1276  when "01010" => ipb_master_in.ipb_rdata <= mem_stat(31 downto 0);
1277  when "01011" => ipb_master_in.ipb_rdata <= mem_stat(63 downto 32);
1278  when "01100" => ipb_master_in.ipb_rdata <= x"00000" & "00" & ddr_pa;
1279  when "01101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(15 downto 0) & '0';
1280  when "01110" => ipb_master_in.ipb_rdata <= mon_evt_cnt;
1281  when "01111" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(31 downto 16) & '0';
1282  when "10000" => ipb_master_in.ipb_rdata <= x"000" & "00" & mon_buf_avl & '1' & '0' & wport_FIFO_full & '0' & wport_rdy & x"0" & '0' & evt_data_rdy;
1283  when "10001" => ipb_master_in.ipb_rdata <= x"00000" & Source_ID(1);
1284  when "11000" => ipb_master_in.ipb_rdata <= x"000" & fake_length;
1285  when "11001" => ipb_master_in.ipb_rdata <= x"00" & "000" & TTS_coded & state & pattern & x"00";
1286  when "11010" => ipb_master_in.ipb_rdata <= ReSync_cntr & x"0" & TTS_disable;
1287  when "11100" => ipb_master_in.ipb_rdata <= LocalL1A_cfg;
1288  when "11101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(47 downto 32) & '0';
1289  when "11110" => ipb_master_in.ipb_rdata <= DNA(31 downto 0);
1290  when "11111" => ipb_master_in.ipb_rdata <= "0000000" & DNA(56 downto 32);
1291  when others => ipb_master_in.ipb_rdata <= (others => '0');
1292  end case;
1293  else
1294  ipb_master_in.ipb_rdata <= AMC_data or CounterDoB(63 downto 32) or CounterDoB(31 downto 0) or I2C_data or sysmon_data or HCAL_trig_data or SFP_data or ttc_data;
1295  end if;
1296 end process;
1297 rst_cntr <= cmd(1) or cmd(0);
1298 process(sysClk, rst_cntr,reset)
1299 begin
1300  if(reset = '1' or rst_cntr = '1')then
1301  TTC_serr_cntr <= (others =>'0');
1302  TTC_derr_cntr <= (others =>'0');
1303  TTC_BcntErr_cntr <= (others =>'0');
1304  L1A_cntr <= (others =>'0');
1305  L1A_OFW_cntr <= (others =>'0');
1306  L1A_BUSY_cntr <= (others =>'0');
1307  L1A_LOS_cntr <= (others =>'0');
1308  run_cntr <= (others =>'0');
1309  ready_cntr <= (others =>'0');
1310  busy_cntr <= (others =>'0');
1311  sync_cntr <= (others =>'0');
1312  ovfl_cntr <= (others =>'0');
1313  ReSync_cntr <= (others =>'0');
1314  elsif(sysClk'event and sysClk = '1')then
1315  if(inc_serr = '1')then
1316  TTC_serr_cntr <= TTC_serr_cntr + 1;
1317  end if;
1318  if(inc_derr = '1')then
1319  TTC_derr_cntr <= TTC_derr_cntr + 1;
1320  end if;
1321  if(inc_bcnterr = '1')then
1322  TTC_BcntErr_cntr <= TTC_BcntErr_cntr + 1;
1323  end if;
1324  if(inc_l1ac = '1')then
1325  L1A_cntr <= L1A_cntr + 1;
1326  if(state = x"1")then
1327  L1A_OFW_cntr <= L1A_OFW_cntr + 1;
1328  end if;
1329  if(state = x"4")then
1330  L1A_BUSY_cntr <= L1A_BUSY_cntr + 1;
1331  end if;
1332  if(state = x"2")then
1333  L1A_LOS_cntr <= L1A_LOS_cntr + 1;
1334  end if;
1335  end if;
1336  if(run = '1')then
1337  run_cntr <= run_cntr + 1;
1338  if(state(3 downto 2) = "10")then
1339  ready_cntr <= ready_cntr + 1;
1340  end if;
1341  if(state(3 downto 2) = "01")then
1342  busy_cntr <= busy_cntr + 1;
1343  end if;
1344  if(state(3) = '0' and state(1) = '1')then
1345  sync_cntr <= sync_cntr + 1;
1346  end if;
1347  if(state(3) = '0' and state(0) = '1')then
1348  ovfl_cntr <= ovfl_cntr + 1;
1349  end if;
1350  end if;
1351  if(ttc_resync = '1')then
1352  ReSync_cntr <= ReSync_cntr + 1;
1353  end if;
1354  end if;
1355 end process;
1356 ttc_resync <= ttc_soft_reset;
1357 process(sysClk,reset)
1358 begin
1359  if(reset = '1')then
1360  TTS_wait <= (others => '0');
1361  elsif(sysClk'event and sysClk = '1')then
1362  if(ttc_resync = '1')then
1363  TTS_wait <= (others => '0');
1364  elsif(TTS_wait(20) = '0' and sync_lost = '0' and AllEventBuilt = '1')then
1365  TTS_wait <= TTS_wait + 1;
1366  end if;
1367  end if;
1368 end process;
1369 process(sysClk,reset)
1370 begin
1371  if(reset = '1')then
1372  state <= "0100";
1373  elsif(sysClk'event and sysClk = '1')then
1374  if(run = '0' and conf(12) = '1')then
1375  state <= pattern;
1376  elsif(run = '0')then
1377  state <= "0100"; -- changed upon request starting version 0x3023
1378  elsif(ttc_resync = '1')then
1379  state <= "0100";
1380  else
1381  case state is
1382  when "1000" => -- Ready
1383  if(TTS_coded(4) = '1')then
1384  state <= "1111";
1385  elsif(TTS_coded(3) = '1')then
1386  state <= "1100";
1387  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1388  state <= "0010";
1389  elsif(L1Aovfl_warning = '1' or evn_fifo_full = '1' or rate_OFWp = '1' or TTS_coded(1) = '1' or TTS_coded(0) = '1')then
1390  state <= "0001";
1391  end if;
1392  when "0001" => -- OFW
1393  if(TTS_coded(4) = '1')then
1394  state <= "1111";
1395  elsif(TTS_coded(3) = '1')then
1396  state <= "1100";
1397  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1398  state <= "0010";
1399  elsif(evn_fifo_full = '1' or rate_OFWp = '1' or TTS_coded(1) = '1')then
1400  state <= "0100";
1401  elsif(L1Aovfl_warning = '0' and rate_OFWp = '0' and TTS_coded(0) = '0')then
1402  state <= "1000";
1403  end if;
1404  when "0100" => -- Busy
1405  if(TTS_wait(20) = '0')then
1406  elsif(TTS_coded(4) = '1')then
1407  state <= "1111";
1408  elsif(TTS_coded(3) = '1')then
1409  state <= "1100";
1410  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1411  state <= "0010";
1412  elsif(evn_fifo_full = '0' and rate_OFWp = '0' and TTS_coded(1) = '0')then
1413  state <= "0001";
1414  end if;
1415  when others => null; -- x"0" or x"f" disconnected, x"2" OOS, x"c" error
1416  end case;
1417  end if;
1418  end if;
1419 end process;
1420 ipb_master_in.ipb_err <= '0';
1421 process(TTC_clk)
1422 begin
1423  if(TTC_clk'event and TTC_clk = '1')then
1424  if(BC0 = '1')then
1425  bcnt <= x"de8"; -- this compensates 5 TTC clock delay in HCAL_trig(2) and ttc_if(3)
1426  elsif(bcnt = x"deb")then
1427  bcnt <= (others => '0');
1428  else
1429  bcnt <= bcnt + 1;
1430  end if;
1431  if(bcnt = BX_offset)then
1432  BC0_dl <= '1';
1433  else
1434  BC0_dl <= '0';
1435  end if;
1436  chk_lock <= BC0_dl;
1437  chk_lock_q <= chk_lock;
1438  if(TTC_lock = '0')then
1439  BC0_locked <= "00";
1440  elsif(chk_lock = '1')then
1441  BC0_locked <= BC0_locked(0) & and_reduce(BC0_lock or (not AMC_en));
1442  end if;
1443  if(TTC_lock = '0')then
1444  inc_BX_offset <= '0';
1445  add_two <= "00";
1446  elsif(chk_lock_q = '1' and BC0_locked = "10")then
1447  inc_BX_offset <= '1';
1448  add_two <= "10";
1449  elsif(add_two /= "00")then
1450  add_two <= add_two - 1;
1451  end if;
1452  if(TTC_lock = '0')then
1453  en_HCAL_trig <= '0';
1454  elsif(chk_lock = '1')then
1455  if(inc_BX_offset = '1' and add_two = "00")then
1456  en_HCAL_trig <= '1';
1457  else
1458  en_HCAL_trig <= '0';
1459  end if;
1460  end if;
1461  if(TTC_lock = '0')then
1462  ec_BX_offset <= '0';
1463  elsif(chk_lock = '1' and inc_BX_offset = '0')then
1464  ec_BX_offset <= '1';
1465  elsif(add_two /= "00")then
1466  ec_BX_offset <= '1';
1467  else
1468  ec_BX_offset <= '0';
1469  end if;
1470  if(TTC_lock = '0')then
1471  BX_offset <= x"100";
1472  elsif(ec_BX_offset = '1')then
1473  if(inc_BX_offset = '1')then
1474  if(BX_offset = x"deb")then
1475  BX_offset <= x"000";
1476  else
1477  BX_offset <= BX_offset + 1;
1478  end if;
1479  elsif(BX_offset = x"000")then
1480  BX_offset <= x"deb";
1481  else
1482  BX_offset <= BX_offset - 1;
1483  end if;
1484  end if;
1485  if(BX_offset(11) = '1')then
1486  BX_offset2SC <= BX_offset - x"dec";
1487  else
1488  BX_offset2SC <= BX_offset;
1489  end if;
1490  end if;
1491 end process;
1492 i_AMC_if: AMC_if PORT MAP(
1493  sysclk => sysclk,
1494  ipb_clk => ipb_clk,
1495  clk125 => clk125,
1496  DRPclk => DRPclk ,
1497  reset => AMC_reset,
1498  ReSync => ttc_resync,
1499  GTXreset => amc_GTXreset,
1500  resetCntr => rst_cntr,
1501  AllEventBuilt => AllEventBuilt ,
1502  run => run,
1503  Dis_pd => Dis_pd,
1504  enSFP => enSFP,
1505  test => conf(7),
1506  NoReSyncFake => conf(11),
1507  WaitMonBuf => conf(14),
1508  fake_length => fake_length ,
1509  en_localL1A => conf(2),
1510  T1_version => K7version(7 downto 0),
1511  Source_ID => Source_ID,
1512  AMC_en => AMC_en,
1513  TTS_disable => TTS_disable ,
1514  AMC_Ready => AMC_Ready,
1515  TTC_lock => TTC_lock,
1516  BC0_lock => BC0_lock,
1517  AMC_REFCLK_P => AMC_REFCLK_P ,
1518  AMC_REFCLK_N => AMC_REFCLK_N ,
1519  AMC_RXN => AMC_RXN,
1520  AMC_RXP => AMC_RXP,
1521  AMC_TXN => AMC_TXN,
1522  AMC_TXP => AMC_TXP,
1523  AMC_status => AMC_status,
1524  evt_data => EventData,
1525  evt_data_we => evt_data_we ,
1526  evt_buf_full => evt_buf_full ,
1527  evt_data_re => evt_data_re ,
1528  evt_data_rdy => evt_data_rdy ,
1529  ddr_pa => ddr_pa,
1530  MonBuf_empty => MonBuf_empty ,
1531  mon_evt_wc => mon_evt_wc,
1532  mon_ctrl => mon_ctrl,
1533  mon_buf_avl => mon_buf_avl ,
1534  TCPbuf_avl => '1',
1535  buf_rqst => EventBuf_rqst,
1536  ipb_write => ipb_master_out.ipb_write ,
1537  ipb_strobe => ipb_master_out.ipb_strobe ,
1538  ipb_addr => ipb_master_out.ipb_addr ,
1539  ipb_wdata => ipb_master_out.ipb_wdata ,
1540  ipb_rdata => AMC_data,
1541  ipb_ack => AMC_ack,
1542  TTC_clk => TTC_clk,
1543  TTC_LOS => TTC_LOS,
1544  BC0 => BC0_dl ,
1545  ttc_evcnt_reset => ttc_evcnt_reset ,
1546  event_number_avl => event_number_avl ,
1547  event_number => event_number ,
1548  evn_buf_full => evn_fifo_full,
1549  ovfl_warning => L1Aovfl_warning ,
1550  TrigData => TrigData,
1551  TTS_coded => TTS_coded
1552  );
1553 AMC_reset <= not sys_lock or cmd(0) or cmd0_dl(1);
1554 amc_GTXreset <= wr_AMC_en or conf7_fall or not sys_lock;
1555 sys_lock_n <= not sys_lock;
1556 i_DAQLSC_if: DAQLSCXG_2x_if PORT MAP(
1557  sysclk => sysclk,
1558  clk125 => clk125,
1559  DRPclk => DRPclk,
1560  reset => AMC_reset,
1561  daq_reset => lsc_reset,
1562  gtx_reset => lsc_GTXreset,
1563  rstCntr => rst_cntr,
1564  test => '0',
1565  Dis_pd => Dis_pd,
1566  enSFP => enSFP,
1567  SFP_ABS => SFP_ABS(1 downto 0),
1568  LSC_ID => LSC_ID,
1569  SFP_down => SFP_down,
1570  inc_ddr_pa => inc_ddr_pa,
1571  evt_data_rdy => evt_data_rdy ,
1572  EventData_in => EventData,
1573  EventData_we => evt_data_we,
1574  EventData_re => evt_data_re,
1575  evt_buf_full => evt_buf_full ,
1576  buf_rqst => EventBuf_rqst,
1577  WaitMonBuf => conf(14),
1578  MonBufOverWrite => conf(13),
1579  MonBuf_avl => mon_buf_avl,
1580  MonBuf_empty => MonBuf_empty ,
1581  MonBufOvfl => MonBufOvfl,
1582  mon_evt_cnt => mon_evt_cnt ,
1583  WrtMonBlkDone => WrtMonBlkDone ,
1584  WrtMonEvtDone => WrtMonEvtDone ,
1585  wport_rdy => wport_rdy,
1586  wport_FIFO_full => wport_FIFO_full ,
1587  EventBufAddr_we => EventBufAddr_we ,
1588  EventBufAddr => EventBufAddr ,
1589  SFP0_RXN => SFP0_RXN,
1590  SFP0_RXP => SFP0_RXP,
1591  SFP1_RXN => SFP1_RXN,
1592  SFP1_RXP => SFP1_RXP,
1593  SFP0_TXN => SFP0_TXN,
1594  SFP0_TXP => SFP0_TXP,
1595  SFP1_TXN => SFP1_TXN,
1596  SFP1_TXP => SFP1_TXP,
1597  SFP_REFCLK_P => SFP_REFCLK_P ,
1598  SFP_REFCLK_N => SFP_REFCLK_N ,
1599  ipb_clk => ipb_clk,
1600  ipb_write => ipb_master_out.ipb_write ,
1601  ipb_strobe => ipb_master_out.ipb_strobe ,
1602  ipb_addr => ipb_master_out.ipb_addr ,
1603  ipb_wdata => ipb_master_out.ipb_wdata ,
1604  ipb_rdata => SFP_data,
1605  ipb_ack => SFP_ack
1606  );
1607 lsc_reset <= lsc_start or cmd(2) or cmd2_dl(1);
1608 --lsc_GTXreset <= wr_EnSFP or not sys_lock or cmd2_dl(0);
1609 lsc_GTXreset <= lsc_start or cmd2_dl(0);
1610 process(DRPclk, sys_lock)
1611 begin
1612  if(sys_lock = '0')then
1613  lsc_start <= '1';
1614  elsif(DRPclk'event and DRPclk = '1')then
1615  if(CLK_rdy = '1')then
1616  lsc_start <= '0';
1617  end if;
1618  end if;
1619 end process;
1620 i_sysmon_if: sysmon_if PORT MAP(
1621  DRPclk => DRPclk,
1622  SN => SN,
1623  VAUXN_IN => VAUXN,
1624  VAUXP_IN => VAUXP,
1625  addr => ipb_master_out.ipb_addr(15 downto 0),
1626  data => sysmon_data ,
1627  device_temp => device_temp ,
1628  ALM => ALM,
1629  OT => OT
1630  );
1631 i_counter_L : BRAM_TDP_MACRO
1632  generic map (
1633  BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
1634  DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1635  DOA_REG => 0, -- Optional port A output register (0 or 1)
1636  DOB_REG => 0, -- Optional port B output register (0 or 1)
1637  INIT_A => X"000000000", -- Initial values on A output port
1638  INIT_B => X"000000000", -- Initial values on B output port
1639  INIT_FILE => "NONE",
1640  READ_WIDTH_A => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1641  READ_WIDTH_B => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1642  SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY",
1643  -- "GENERATE_X_ONLY" or "NONE"
1644  SRVAL_A => X"000000000", -- Set/Reset value for A port output
1645  SRVAL_B => X"000000000", -- Set/Reset value for B port output
1646  WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
1647  WRITE_MODE_B => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
1648  WRITE_WIDTH_A => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1649  WRITE_WIDTH_B => 32) -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1650  port map (
1651  DOA => CounterDoA(31 downto 0), -- Output port-A data, width defined by READ_WIDTH_A parameter
1652  DOB => CounterDoB(31 downto 0), -- Output port-B data, width defined by READ_WIDTH_B parameter
1653  ADDRA => counter_wa, -- Input port-A address, width defined by Port A depth
1654  ADDRB => counter_ra_l, -- Input port-B address, width defined by Port B depth
1655  CLKA => sysclk, -- 1-bit input port-A clock
1656  CLKB => clk125, -- 1-bit input port-B clock
1657  DIA => CounterDi(31 downto 0), -- Input port-A data, width defined by WRITE_WIDTH_A parameter
1658  DIB => (others => '0'), -- Input port-B data, width defined by WRITE_WIDTH_B parameter
1659  ENA => '1', -- 1-bit input port-A enable
1660  ENB => '1', -- 1-bit input port-B enable
1661  REGCEA => '1', -- 1-bit input port-A output register enable
1662  REGCEB => '1', -- 1-bit input port-B output register enable
1663  RSTA => '0', -- 1-bit input port-A reset
1664  RSTB => '0', -- 1-bit input port-B reset
1665  WEA => counter_we, -- Input port-A write enable, width defined by Port A depth
1666  WEB => x"0" -- Input port-B write enable, width defined by Port B depth
1667  );
1668 i_counter_H : BRAM_TDP_MACRO
1669  generic map (
1670  BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
1671  DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1672  DOA_REG => 0, -- Optional port A output register (0 or 1)
1673  DOB_REG => 0, -- Optional port B output register (0 or 1)
1674  INIT_A => X"000000000", -- Initial values on A output port
1675  INIT_B => X"000000000", -- Initial values on B output port
1676  INIT_FILE => "NONE",
1677  READ_WIDTH_A => 16, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1678  READ_WIDTH_B => 16, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1679  SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY",
1680  -- "GENERATE_X_ONLY" or "NONE"
1681  SRVAL_A => X"000000000", -- Set/Reset value for A port output
1682  SRVAL_B => X"000000000", -- Set/Reset value for B port output
1683  WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
1684  WRITE_MODE_B => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
1685  WRITE_WIDTH_A => 16, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1686  WRITE_WIDTH_B => 16) -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1687  port map (
1688  DOA => CounterDoA(47 downto 32), -- Output port-A data, width defined by READ_WIDTH_A parameter
1689  DOB => CounterDoB(47 downto 32), -- Output port-B data, width defined by READ_WIDTH_B parameter
1690  ADDRA => counter_wa, -- Input port-A address, width defined by Port A depth
1691  ADDRB => counter_ra_h, -- Input port-B address, width defined by Port B depth
1692  CLKA => sysclk, -- 1-bit input port-A clock
1693  CLKB => clk125, -- 1-bit input port-B clock
1694  DIA => CounterDi(47 downto 32), -- Input port-A data, width defined by WRITE_WIDTH_A parameter
1695  DIB => (others => '0'), -- Input port-B data, width defined by WRITE_WIDTH_B parameter
1696  ENA => '1', -- 1-bit input port-A enable
1697  ENB => '1', -- 1-bit input port-B enable
1698  REGCEA => '1', -- 1-bit input port-A output register enable
1699  REGCEB => '1', -- 1-bit input port-B output register enable
1700  RSTA => '0', -- 1-bit input port-A reset
1701  RSTB => '0', -- 1-bit input port-B reset
1702  WEA => counter_we(1 downto 0), -- Input port-A write enable, width defined by Port A depth
1703  WEB => "00" -- Input port-B write enable, width defined by Port B depth
1704  );
1705 counter_we <= x"f" when div(1 downto 0) = "11" else x"0";
1706 process(ipb_clk)
1707 begin
1708  if(ipb_clk'event and ipb_clk = '1')then
1709  newIPADDRSyncRegs <= newIPADDRSyncRegs(1 downto 0) & newIPADDR;
1710  rst_ipbus <= not newIPADDRSyncRegs(2) and newIPADDR;
1711  end if;
1712 end process;
1713 CounterDi(47 downto 8) <= (others => '0') when CntrRstCycle = '1' else
1714 CounterDoA(47 downto 8) + 1 when CounterDi(7 downto 0) < CounterDoA(7 downto 0) else CounterDoA(47 downto 8);
1715 counter_wa <= "00000" & div(6 downto 2);
1716 counter_ra_l(4 downto 0) <= ipb_master_out.ipb_addr(5 downto 1);
1717 counter_ra_h(4 downto 0) <= ipb_master_out.ipb_addr(5 downto 1);
1718 counter_ra_l(5) <= ipb_master_out.ipb_addr(0);
1719 counter_ra_h(5) <= not ipb_master_out.ipb_addr(0);
1720 counter_ra_l(9 downto 6) <= x"0" when ipb_master_out.ipb_addr(15 downto 6) = misc_cntr_addr(15 downto 6) else x"1";
1721 counter_ra_h(9 downto 6) <= x"0" when ipb_master_out.ipb_addr(15 downto 6) = misc_cntr_addr(15 downto 6) else x"1";
1722 process(sysClk)
1723 begin
1724  if(sysclk'event and sysclk = '1')then
1725  if(CntrRst = '1')then
1726  div <= (others => '0');
1727  else
1728  div <= div + 1;
1729  end if;
1730  resetCntr_SyncRegs <= resetCntr_SyncRegs(1 downto 0) & rst_cntr;
1731  CntrRst <= not resetCntr_SyncRegs(2) and resetCntr_SyncRegs(1);
1732  if(CntrRst = '1')then
1733  CntrRstCycle <= '1';
1734  elsif(and_reduce(div) = '1')then
1735  CntrRstCycle <= '0';
1736  end if;
1737  if(CntrRstCycle = '1')then
1738  CounterDi(7 downto 0) <= (others => '0');
1739  else
1740  case div(6 downto 2) is
1741  when "00000" => CounterDi(7 downto 0) <= TTC_serr_cntr;
1742  when "00001" => CounterDi(7 downto 0) <= TTC_derr_cntr;
1743  when "00010" => CounterDi(7 downto 0) <= TTC_BcntErr_cntr;
1744  when "00011" => CounterDi(7 downto 0) <= L1A_cntr;
1745  when "00100" => CounterDi(7 downto 0) <= run_cntr;
1746  when "00101" => CounterDi(7 downto 0) <= ready_cntr;
1747  when "00110" => CounterDi(7 downto 0) <= busy_cntr;
1748  when "00111" => CounterDi(7 downto 0) <= sync_cntr;
1749  when "01000" => CounterDi(7 downto 0) <= ovfl_cntr;
1750  when "01001" => CounterDi(7 downto 0) <= L1A_OFW_cntr;
1751  when "01010" => CounterDi(7 downto 0) <= L1A_BUSY_cntr;
1752  when "01011" => CounterDi(7 downto 0) <= L1A_LOS_cntr;
1753  when others => CounterDi(7 downto 0) <= (others => '0');
1754  end case;
1755  end if;
1756  end if;
1757 end process;
1758 i_DNA_PORT : DNA_PORT
1759  generic map (
1760  SIM_DNA_VALUE => X"00123456789abcd" -- Specifies a sample 57-bit DNA value for simulation
1761  )
1762  port map (
1763  DOUT => DNA_out, -- 1-bit output: DNA output data.
1764  CLK => ipb_clk, -- 1-bit input: Clock input.
1765  DIN => '0', -- 1-bit input: User data input pin.
1766  READ => load_DNA, -- 1-bit input: Active high load DNA, active low read input.
1767  SHIFT => shift_DNA(1) -- 1-bit input: Active high shift enable input.
1768  );
1769 process(ipb_clk)
1770 begin
1771  if(ipb_clk'event and ipb_clk = '1')then
1772  load_DNA <= not sys_lock;
1773  if(sys_lock = '0')then
1774  shift_DNA(0) <= '0';
1775  elsif(load_DNA = '1')then
1776  shift_DNA(0) <= '1';
1777  elsif(shift_DNA(2) = '1' and or_reduce(DNA_cntr(5 downto 1)) = '0')then
1778  shift_DNA(0) <= '0';
1779  end if;
1780  shift_DNA(2) <= shift_DNA(0);
1781  if(shift_DNA(2) = '1')then
1782  DNA_cntr <= DNA_cntr - 1;
1783  elsif(shift_DNA(0) = '1')then
1784  DNA_cntr <= "110111";
1785  end if;
1786  if(shift_DNA(2) = '1')then
1787  DNA <= DNA(55 downto 0) & DNA_OUT;
1788  end if;
1789  end if;
1790 end process;
1791 process(ipb_clk)
1792 begin
1793  if(ipb_clk'event and ipb_clk = '0')then
1794  shift_DNA(1) <= shift_DNA(0);
1795  end if;
1796 end process;
1797 end Behavioral;
1798 
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