AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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AMC13_T1_HCAL.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 14:49:29 05/12/2010
6 -- Design Name:
7 -- Module Name: DTC_T2 - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 use work.ipbus.ALL;
26 use work.amc13_pack.all;
27 
28 -- Uncomment the following library declaration if using
29 -- arithmetic functions with Signed or Unsigned values
30 -- use IEEE.NUMERIC_STD.ALL;
31 
32 -- Uncomment the following library declaration if instantiating
33 -- any Xilinx primitives in this code.
34 library UNISIM;
35 use UNISIM.VComponents.all;
36 Library UNIMACRO;
37 use UNIMACRO.vcomponents.all;
38 
39 entity AMC13_T1_HCAL is
40  Port (
41  VAUXP : in STD_LOGIC_VECTOR(12 downto 0);
42  VAUXN : in STD_LOGIC_VECTOR(12 downto 0);
43 -- I2C interface
44  CLK_SCL : out STD_LOGIC;
45  CLK_SDA : inout STD_LOGIC;
46  SFP_SCL : out STD_LOGIC_VECTOR(3 downto 0);
47  SFP_SDA : inout STD_LOGIC_VECTOR(3 downto 0);
48 -- SFP slow control
49  SFP_LOS : in STD_LOGIC_VECTOR(2 downto 0);
50  SFP_ABS : in STD_LOGIC_VECTOR(3 downto 0);
51  TxFault : in STD_LOGIC_VECTOR(3 downto 0);
52  TxDisable : out STD_LOGIC_VECTOR(3 downto 0);
53 -- RATE : out STD_LOGIC_VECTOR(3 downto 0);
54 -- CDR signals
55  DIV4 : out STD_LOGIC;
56  DIV_nRST : out STD_LOGIC;
57  CDRclk_p : in STD_LOGIC;
58  CDRclk_n : in STD_LOGIC;
59  CDRdata_p : in STD_LOGIC;
60  CDRdata_n : in STD_LOGIC;
61  TTCdata_p : out STD_LOGIC;
62  TTCdata_n : out STD_LOGIC;
63  TTCclk_p : in STD_LOGIC;
64  TTCclk_n : in STD_LOGIC;
65  TTC_LOS : in STD_LOGIC;
66  TTC_LOL : in STD_LOGIC;
67  TTS_out_p : out STD_LOGIC;
68  TTS_out_n : out STD_LOGIC;
69 -- SPI interface
70  SPI_SCK : in STD_LOGIC;
71  SPI_CS_b : in STD_LOGIC;
72  SPI_MOSI : in STD_LOGIC;
73  SPI_MISO : out STD_LOGIC;
74 -- DDR3 pins
75  sys_clk_p : in STD_LOGIC;
76  sys_clk_n : in STD_LOGIC;
77  ddr3_dq : inout STD_LOGIC_VECTOR(31 downto 0);
78  ddr3_addr : out STD_LOGIC_VECTOR(13 downto 0);
79  ddr3_ba : out STD_LOGIC_VECTOR (2 downto 0);
80  ddr3_dm : out STD_LOGIC_VECTOR (3 downto 0);
81  ddr3_dqs_p : inout STD_LOGIC_VECTOR(3 downto 0);
82  ddr3_dqs_n : inout STD_LOGIC_VECTOR(3 downto 0);
83  ddr3_ras_n : out STD_LOGIC;
84  ddr3_cas_n : out STD_LOGIC;
85  ddr3_we_n : out STD_LOGIC;
86  ddr3_reset_n : out STD_LOGIC;
87  ddr3_cke : out STD_LOGIC_vector(0 to 0);
88  ddr3_odt : out STD_LOGIC_vector(0 to 0);
89  ddr3_ck_p : out STD_LOGIC_vector(0 to 0);
90  ddr3_ck_n : out STD_LOGIC_vector(0 to 0);
91  SFP0_RXN : in STD_LOGIC;
92  SFP0_RXP : in STD_LOGIC;
93  SFP1_RXN : in STD_LOGIC;
94  SFP1_RXP : in STD_LOGIC;
95  SFP2_RXN : in STD_LOGIC;
96  SFP2_RXP : in STD_LOGIC;
97  SFP0_TXN : out STD_LOGIC;
98  SFP0_TXP : out STD_LOGIC;
99  SFP1_TXN : out STD_LOGIC;
100  SFP1_TXP : out STD_LOGIC;
101  SFP2_TXN : out STD_LOGIC;
102  SFP2_TXP : out STD_LOGIC;
103  CDR_REFCLK_N : in STD_LOGIC;
104  CDR_REFCLK_P : in STD_LOGIC;
105  SFP_REFCLK_N : in STD_LOGIC;
106  SFP_REFCLK_P : in STD_LOGIC;
107  AMC_REFCLK_N : in STD_LOGIC;
108  AMC_REFCLK_P : in STD_LOGIC;
109  AMC_RXN : in STD_LOGIC_VECTOR(12 downto 1);
110  AMC_RXP : in STD_LOGIC_VECTOR(12 downto 1);
111  AMC_TXN : out STD_LOGIC_VECTOR(12 downto 1);
112  AMC_TXP : out STD_LOGIC_VECTOR(12 downto 1);
113 -- signal to/from DTC_T2
114  S6LINK_RXN : in STD_LOGIC;
115  S6LINK_RXP : in STD_LOGIC;
116  S6LINK_TXN : out STD_LOGIC;
117  S6LINK_TXP : out STD_LOGIC;
118  S2V_p : in STD_LOGIC;
119  S2V_n : in STD_LOGIC;
120 -- V2S_p : out STD_LOGIC;
121 -- V2S_n : out STD_LOGIC;
122  GbE_REFCLK_N : in STD_LOGIC;
123  GbE_REFCLK_P : in STD_LOGIC);
124 end AMC13_T1_HCAL;
125 
126 architecture Behavioral of AMC13_T1_HCAL is
127 COMPONENT HCAL_trig
128 PORT(
129  TTC_clk : IN std_logic;
130  DRPCLK : IN std_logic;
131  reset : IN std_logic;
132  BC0 : IN std_logic;
133  en_HCAL_trig : IN std_logic;
134  Trigdata : IN array12x8;
135  triggerOut : OUT std_logic;
136  ipb_clk : IN std_logic;
137  ipb_write : IN std_logic;
138  ipb_strobe : IN std_logic;
139  ipb_addr : IN std_logic_vector(31 downto 0);
140  ipb_wdata : IN std_logic_vector(31 downto 0);
141  GTX_REFCLKp : IN std_logic;
142  GTX_REFCLKn : IN std_logic;
143  GTX_RXp : IN std_logic;
144  GTX_RXn : IN std_logic;
145  ipb_rdata : OUT std_logic_vector(31 downto 0);
146  GTX_TXp : OUT std_logic;
147  GTX_TXn : OUT std_logic
148  );
149 END COMPONENT;
150 COMPONENT TTS_if
151  PORT(
152  sysclk : IN std_logic;
153  TTS_clk : IN std_logic;
154  reset : IN std_logic;
155  local_TTC : in STD_LOGIC;
156  TTS : IN std_logic_vector(3 downto 0);
157  TTS_out_p : OUT std_logic;
158  TTS_out_n : OUT std_logic
159  );
160 END COMPONENT;
161 COMPONENT ttc_if
162  PORT(
163  clk : IN std_logic;
164  refclk : IN std_logic;
165  reset : IN std_logic;
166  run : IN std_logic;
167  IsG2 : IN std_logic;
168  DB_cmd_in : IN std_logic;
169  DB_cmd_Out : OUT std_logic;
170  sys_lock : IN std_logic;
171  local_TTC : IN std_logic;
172  local_TTCcmd : IN std_logic;
173  single_TTCcmd : in STD_LOGIC;
174  CDRclk_p : IN std_logic;
175  CDRclk_n : IN std_logic;
176  CDRdata_p : IN std_logic;
177  CDRdata_n : IN std_logic;
178  TTC_LOS : IN std_logic;
179  TTC_LOL : IN std_logic;
180  BCN_off : IN std_logic_vector(12 downto 0);
181  OC_off : IN std_logic_vector(3 downto 0);
182  en_cal_win : IN std_logic;
183  cal_win_high : IN std_logic_vector(11 downto 0);
184  cal_win_low : IN std_logic_vector(11 downto 0);
185  en_localL1A : IN std_logic;
186  LocalL1A_cfg : IN std_logic_vector(31 downto 0);
187  localL1A_s : IN std_logic;
188  localL1A_r : IN std_logic;
189  T3_trigger : IN std_logic;
190  HCAL_trigger : IN std_logic;
191  EvnRSt_l : IN std_logic;
192  OcnRSt_l : IN std_logic;
193  ovfl_warning : IN std_logic;
194  ipb_clk : IN std_logic;
195  ipb_write : IN std_logic;
196  ipb_strobe : IN std_logic;
197  ipb_addr : IN std_logic_vector(31 downto 0);
198  ipb_wdata : IN std_logic_vector(31 downto 0);
199  en_brcst : IN std_logic;
200  state : IN std_logic_vector(3 downto 0);
201  evn_fifo_full : IN std_logic;
202  BC0 : OUT std_logic;
203  TTC_strobe : OUT std_logic;
204  TTS_clk : OUT std_logic;
205  DIV4 : OUT std_logic;
206  DIV_nRST : OUT std_logic;
207  CDRclk_out : OUT std_logic;
208  TTCdata_p : OUT std_logic;
209  TTCdata_n : OUT std_logic;
210  CalType : OUT std_logic_vector(3 downto 0);
211  TTC_Brcst : OUT std_logic_vector(3 downto 0);
212  localL1A_periodic : OUT std_logic;
213  ipb_rdata : OUT std_logic_vector(31 downto 0);
214  ttc_start : OUT std_logic;
215  ttc_stop : OUT std_logic;
216  ttc_soft_reset : OUT std_logic;
217  ttc_ready : OUT std_logic;
218  ttc_serr : OUT std_logic;
219  ttc_derr : OUT std_logic;
220  ttc_bcnt_err : OUT std_logic;
221  rate_OFW : OUT std_logic;
222  sync_lost : OUT std_logic;
223  inc_oc : OUT std_logic;
224  inc_l1ac : OUT std_logic;
225  inc_bcnterr : OUT std_logic;
226  inc_serr : OUT std_logic;
227  inc_derr : OUT std_logic;
228  ttc_evcnt_reset : OUT std_logic;
229  event_number_avl : OUT std_logic;
230  event_number : OUT std_logic_vector(59 downto 0)
231  );
232 END COMPONENT;
233 COMPONENT AMC_if
234  Generic (useTCPIP : boolean := false; AMC_useTRIG : boolean := true; simulation : boolean := false);
235  PORT(
236  sysclk : IN std_logic;
237  ipb_clk : IN std_logic;
238  clk125 : IN std_logic;
239  DRPclk : IN std_logic;
240  GTXreset : IN std_logic;
241  reset : IN std_logic;
242  DB_cmd : IN std_logic;
243  resetCntr : IN std_logic;
244  ReSync : IN std_logic;
245  AllEventBuilt : OUT std_logic;
246  run : IN std_logic;
247  en_inject_err : in STD_LOGIC;
248  Dis_pd : in STD_LOGIC;
249  enSFP : IN std_logic_vector(3 downto 0);
250  en_localL1A : IN std_logic;
251  test : IN std_logic;
252  NoReSyncFake : IN std_logic;
253  WaitMonBuf : IN std_logic;
254  fake_length : IN std_logic_vector(19 downto 0);
255  T1_version : IN std_logic_vector(7 downto 0);
256  Source_ID : IN array3x12;
257  AMC_en : IN std_logic_vector(11 downto 0);
258  TTS_disable : IN std_logic_vector(11 downto 0);
259  AMC_REFCLK_P : IN std_logic;
260  AMC_REFCLK_N : IN std_logic;
261  AMC_RXN : IN std_logic_vector(12 downto 1);
262  AMC_RXP : IN std_logic_vector(12 downto 1);
263  evt_data_re : IN std_logic_vector(2 downto 0);
264  evt_buf_full : IN std_logic_vector(2 downto 0);
265  ddr_pa : IN std_logic_vector(9 downto 0);
266  MonBuf_empty : IN std_logic;
267  mon_buf_avl : IN std_logic;
268  TCPbuf_avl : IN std_logic;
269  ipb_write : IN std_logic;
270  ipb_strobe : IN std_logic;
271  ipb_addr : IN std_logic_vector(31 downto 0);
272  ipb_wdata : IN std_logic_vector(31 downto 0);
273  TTC_clk : IN std_logic;
274  TTC_LOS : IN std_logic;
275  BC0 : IN std_logic;
276  ttc_evcnt_reset : IN std_logic;
277  event_number_avl : IN std_logic;
278  event_number : IN std_logic_vector(59 downto 0);
279  AMC_Ready : OUT std_logic_vector(11 downto 0);
280  TTC_lock : OUT std_logic;
281  BC0_lock : OUT std_logic_vector(11 downto 0);
282  AMC_TXN : OUT std_logic_vector(12 downto 1);
283  AMC_TXP : OUT std_logic_vector(12 downto 1);
284  AMC_status : OUT std_logic_vector(31 downto 0);
285  evt_data : OUT array3x67;
286  evt_data_we : OUT std_logic_vector(2 downto 0);
287  evt_data_rdy : OUT std_logic_vector(2 downto 0);
288  mon_evt_wc : OUT std_logic_vector(47 downto 0);
289  mon_ctrl : OUT std_logic_vector(31 downto 0);
290  buf_rqst : OUT std_logic_vector(3 downto 0);
291  ipb_rdata : OUT std_logic_vector(31 downto 0);
292  ipb_ack : OUT std_logic;
293  evn_buf_full : OUT std_logic;
294  ovfl_warning : OUT std_logic;
295  TrigData : OUT array12x8;
296  TTS_coded : OUT std_logic_vector(4 downto 0)
297  );
298 END COMPONENT;
299 COMPONENT I2C
300  PORT(
301  clk : IN std_logic;
302  ipb_clk : IN std_logic;
303  reset : IN std_logic;
304  addr : IN std_logic_vector(31 downto 0);
305  SFP_ABS : IN std_logic_vector(3 downto 0);
306  SFP_LOS : IN std_logic_vector(2 downto 0);
307  CLK_SDA : INOUT std_logic;
308  SFP_SDA : INOUT std_logic_vector(3 downto 0);
309  rdata : OUT std_logic_vector(31 downto 0);
310  CLK_rdy : OUT std_logic;
311  CLK_SCL : OUT std_logic;
312  SFP_SCL : OUT std_logic_vector(3 downto 0)
313  );
314 END COMPONENT;
315 COMPONENT SPI_if
316  PORT(
317  SCK : IN std_logic;
318  CSn : IN std_logic;
319  MOSI : IN std_logic;
320  SN : IN std_logic_vector(8 downto 0);
321  OT : IN std_logic;
322  IsT1 : IN std_logic;
323  SPI_rdata : IN std_logic_vector(7 downto 0);
324  MISO : OUT std_logic;
325  SPI_we : OUT std_logic;
326  en_RARP : out STD_LOGIC;
327  newIPADDR : OUT std_logic;
328  IPADDR : OUT std_logic_vector(31 downto 0);
329  SPI_wdata : OUT std_logic_vector(7 downto 0);
330  SPI_addr : OUT std_logic_vector(7 downto 0)
331  );
332 END COMPONENT;
333 COMPONENT ddr_if
334  port(
335  clk_ref : in std_logic;
336  mem_clk_p : in std_logic;
337  mem_clk_n : in std_logic;
338  mem_rst : in std_logic;
339  sysclk : in std_logic;
340  TCPclk : in std_logic;
341  reset : in std_logic;
342  resetsys : in std_logic;
343  run : in std_logic;
344  mem_test : in std_logic_VECTOR(1 downto 0);
345  EventData : in array3X67;
346  EventData_we : in std_logic_VECTOR(2 downto 0);
347  wport_rdy : out std_logic_VECTOR(2 downto 0);
348  WrtMonBlkDone : OUT std_logic_VECTOR(2 downto 0);
349  WrtMonEvtDone : OUT std_logic_VECTOR(2 downto 0);
350  KiloByte_toggle : OUT std_logic_VECTOR(2 downto 0);
351  EoB_toggle : OUT std_logic_VECTOR(2 downto 0);
352  EventBufAddr : in array3x14;
353  EventBufAddr_we : in std_logic_VECTOR(2 downto 0);
354  EventFIFOfull : out std_logic_VECTOR(2 downto 0);
355  TCP_din : in std_logic_vector(31 downto 0);
356  TCP_channel : in STD_LOGIC_VECTOR (1 downto 0);
357  TCP_we : in STD_LOGIC;
358  TCP_wcount : out STD_LOGIC_VECTOR (2 downto 0);
359  TCP_dout : out STD_LOGIC_VECTOR(31 downto 0); -- TCP data are written in unit of 32-bit words
360  TCP_raddr : in std_logic_vector(28 downto 0); -- 28-26 encoded request source 25-0 address in 64 bit word
361  TCP_length : in std_logic_vector(10 downto 0); -- in 64 bit word, actual length - 1
362  TCP_dout_valid : out STD_LOGIC;
363  TCP_rrqst : in STD_LOGIC;
364  TCP_rack : out STD_LOGIC;
365  TCP_lastword : out STD_LOGIC;
366 -- ipbus signals
367  ipb_clk : in STD_LOGIC;
368  ipb_write : in STD_LOGIC;
369  ipb_strobe : in STD_LOGIC;
370  page_addr : in STD_LOGIC_VECTOR(9 downto 0);
371  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
372  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
373  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
374  ipb_ack : out STD_LOGIC;
375  mem_stat : out STD_LOGIC_VECTOR (63 downto 0);
376  device_temp : in STD_LOGIC_VECTOR(11 downto 0);
377 -- ddr3 memory pins
378  ddr3_dq : inout STD_LOGIC_VECTOR (31 downto 0);
379  ddr3_dm : out STD_LOGIC_VECTOR (3 downto 0);
380  ddr3_addr : out STD_LOGIC_VECTOR (13 downto 0);
381  ddr3_ba : out STD_LOGIC_VECTOR (2 downto 0);
382  ddr3_dqs_p : inout STD_LOGIC_VECTOR (3 downto 0);
383  ddr3_dqs_n : inout STD_LOGIC_VECTOR (3 downto 0);
384  ddr3_ras_n : out STD_LOGIC;
385  ddr3_cas_n : out STD_LOGIC;
386  ddr3_we_n : out STD_LOGIC;
387  ddr3_reset_n : out STD_LOGIC;
388  ddr3_cke : out STD_LOGIC_vector(0 to 0);
389  ddr3_odt : out STD_LOGIC_vector(0 to 0);
390  ddr3_ck_p : out STD_LOGIC_vector(0 to 0);
391  ddr3_ck_n : out STD_LOGIC_vector(0 to 0)
392  );
393 END COMPONENT;
394 COMPONENT ipbus_if
395  generic(RXPOLARITY : std_logic := '0'; TXPOLARITY : std_logic := '0');
396  port(
397  ipb_clk : IN std_logic;
398  UsRclk : IN std_logic;
399  DRPclk : IN std_logic;
400  got_SN : out std_logic;
401  reset : IN std_logic;
402  GTX_RESET : IN std_logic;
403  GbE_REFCLK : in std_logic;
404  S6LINK_RXN : in std_logic;
405  S6LINK_RXP : in std_logic;
406  S6LINK_TXN : out std_logic;
407  S6LINK_TXP : out std_logic;
408  wr_amc_en : in std_logic;
409  amc_en : in STD_LOGIC_VECTOR(11 downto 0);
410  en_RARP : in std_logic;
411  IPADDR : in STD_LOGIC_VECTOR(31 downto 0);
412  MACADDR : in STD_LOGIC_VECTOR(47 downto 0);
413  ipb_out : out ipb_wbus;
414  ipb_in : in ipb_rbus;
415  SN : out STD_LOGIC_VECTOR(8 downto 0);
416  debug_in : IN std_logic_vector(31 downto 0);
417  debug_out : OUT std_logic_vector(127 downto 0)
418  );
419 end COMPONENT;
420 COMPONENT sysmon_if
421  PORT(
422  DRPclk : IN std_logic;
423  DB_cmd : IN std_logic;
424  SN : IN std_logic_vector(8 downto 0);
425  VAUXN_IN : IN std_logic_vector(12 downto 0);
426  VAUXP_IN : IN std_logic_vector(12 downto 0);
427  addr : IN std_logic_vector(15 downto 0);
428  data : OUT std_logic_vector(31 downto 0);
429  device_temp : OUT std_logic_vector(11 downto 0);
430  ALM : OUT std_logic_vector(7 downto 0);
431  OT : OUT std_logic
432  );
433 END COMPONENT;
434 --COMPONENT DAQLSCXG_2x_if
435 -- PORT(
436 -- sysclk : IN std_logic;
437 -- clk125 : IN std_logic;
438 -- DRPclk : IN std_logic;
439 -- reset : IN std_logic;
440 -- daq_reset : IN std_logic;
441 -- gtx_reset : IN std_logic;
442 -- rstCntr : IN std_logic;
443 -- Dis_pd : in STD_LOGIC;
444 -- DB_cmd : in STD_LOGIC;
445 -- test : IN std_logic;
446 -- enSFP : IN std_logic_vector(3 downto 0);
447 -- SFP_ABS : IN std_logic_vector(1 downto 0);
448 -- LSC_ID : IN std_logic_vector(15 downto 0);
449 -- inc_ddr_pa : IN std_logic;
450 -- evt_data_rdy : IN std_logic_vector(2 downto 0);
451 -- EventData_in : IN array3x67;
452 -- EventData_we : IN std_logic_vector(2 downto 0);
453 -- buf_rqst : IN std_logic_vector(3 downto 0);
454 -- WrtMonBlkDone : IN std_logic_vector(2 downto 0);
455 -- WrtMonEvtDone : IN std_logic_vector(2 downto 0);
456 -- wport_rdy : IN std_logic_vector(2 downto 0);
457 -- wport_FIFO_full : IN std_logic_vector(2 downto 0);
458 -- SFP0_RXN : IN std_logic;
459 -- SFP0_RXP : IN std_logic;
460 -- SFP1_RXN : IN std_logic;
461 -- SFP1_RXP : IN std_logic;
462 -- SFP_REFCLK_P : in std_logic;
463 -- SFP_REFCLK_N : in std_logic;
464 -- ipb_clk : IN std_logic;
465 -- ipb_write : IN std_logic;
466 -- ipb_strobe : IN std_logic;
467 -- ipb_addr : IN std_logic_vector(31 downto 0);
468 -- ipb_wdata : IN std_logic_vector(31 downto 0);
469 -- SFP_down : OUT std_logic_vector(2 downto 0);
470 -- EventData_re : OUT std_logic_vector(2 downto 0);
471 -- evt_buf_full : OUT std_logic_vector(2 downto 0);
472 -- WaitMonBuf : IN std_logic;
473 -- MonBufOverWrite : IN std_logic;
474 -- MonBuf_avl : OUT std_logic;
475 -- MonBuf_empty : OUT std_logic;
476 -- MonBufOvfl : OUT std_logic;
477 -- mon_evt_cnt : OUT std_logic_vector(31 downto 0);
478 -- EventBufAddr_we : OUT std_logic_vector(2 downto 0);
479 -- EventBufAddr : OUT array3x14;
480 -- SFP0_TXN : OUT std_logic;
481 -- SFP0_TXP : OUT std_logic;
482 -- SFP1_TXN : OUT std_logic;
483 -- SFP1_TXP : OUT std_logic;
484 -- ipb_rdata : OUT std_logic_vector(31 downto 0);
485 -- ipb_ack : OUT std_logic
486 -- );
487 --END COMPONENT;
488 COMPONENT DAQLSCXG_3x_if
489  PORT(
490  sysclk : IN std_logic;
491  clk125 : IN std_logic;
492  DRPclk : IN std_logic;
493  reset : IN std_logic;
494  daq_reset : IN std_logic;
495  gtx_reset : IN std_logic;
496  rstCntr : IN std_logic;
497  Dis_pd : in STD_LOGIC;
498  test : IN std_logic;
499  DB_cmd : IN std_logic;
500  enSFP : IN std_logic_vector(3 downto 0);
501  SFP_ABS : IN std_logic_vector(2 downto 0);
502  LSC_ID : IN std_logic_vector(15 downto 0);
503  inc_ddr_pa : IN std_logic;
504  evt_data_rdy : IN std_logic_vector(2 downto 0);
505  EventData_in : IN array3x67;
506  EventData_we : IN std_logic_vector(2 downto 0);
507  buf_rqst : IN std_logic_vector(3 downto 0);
508  WaitMonBuf : IN std_logic;
509  WrtMonBlkDone : IN std_logic_vector(2 downto 0);
510  WrtMonEvtDone : IN std_logic_vector(2 downto 0);
511  wport_rdy : IN std_logic_vector(2 downto 0);
512  wport_FIFO_full : IN std_logic_vector(2 downto 0);
513  SFP0_RXN : IN std_logic;
514  SFP0_RXP : IN std_logic;
515  SFP1_RXN : IN std_logic;
516  SFP1_RXP : IN std_logic;
517  SFP2_RXN : IN std_logic;
518  SFP2_RXP : IN std_logic;
519  SFP_REFCLK_P : in std_logic;
520  SFP_REFCLK_N : in std_logic;
521  ipb_clk : IN std_logic;
522  ipb_write : IN std_logic;
523  ipb_strobe : IN std_logic;
524  ipb_addr : IN std_logic_vector(31 downto 0);
525  ipb_wdata : IN std_logic_vector(31 downto 0);
526  SFP_down : OUT std_logic_vector(2 downto 0);
527  EventData_re : OUT std_logic_vector(2 downto 0);
528  evt_buf_full : OUT std_logic_vector(2 downto 0);
529  MonBufOverWrite : IN std_logic;
530  MonBuf_avl : OUT std_logic;
531  MonBuf_empty : OUT std_logic;
532  MonBufOvfl : OUT std_logic;
533  mon_evt_cnt : OUT std_logic_vector(31 downto 0);
534  EventBufAddr_we : OUT std_logic_vector(2 downto 0);
535  EventBufAddr : OUT array3x14;
536  SFP0_TXN : OUT std_logic;
537  SFP0_TXP : OUT std_logic;
538  SFP1_TXN : OUT std_logic;
539  SFP1_TXP : OUT std_logic;
540  SFP2_TXN : OUT std_logic;
541  SFP2_TXP : OUT std_logic;
542  ipb_rdata : OUT std_logic_vector(31 downto 0);
543  ipb_ack : OUT std_logic
544  );
545 END COMPONENT;
546 COMPONENT TTC_cntr
547  PORT(
548  sysclk : IN std_logic;
549  clk125 : IN std_logic;
550  ipb_clk : IN std_logic;
551  reset : IN std_logic;
552  rst_cntr : IN std_logic;
553  DB_cmd : IN std_logic;
554  inc_serr : IN std_logic;
555  inc_derr : IN std_logic;
556  inc_bcnterr : IN std_logic;
557  inc_l1ac : IN std_logic;
558  run : IN std_logic;
559  state : IN std_logic_vector(3 downto 0);
560  ttc_resync : IN std_logic;
561  ipb_addr : IN std_logic_vector(15 downto 0);
562  ipb_rdata : OUT std_logic_vector(31 downto 0)
563  );
564 END COMPONENT;
565 constant ipbus_ver_addr : std_logic_vector(15 downto 0) := x"0000";
566 constant ipbus_sfp_addr: std_logic_vector(15 downto 0) := x"0002";
567 constant CDRclk_pol : std_logic := '0';
568 constant CDRdata_pol : std_logic := '1';
569 constant TTCclk_pol : std_logic := '1';
570 constant TTCdata_pol : std_logic := '1';
571 constant Coarse_Delay: std_logic_vector(3 downto 0) := x"0";
572 signal rst_ipbus : std_logic := '0';
573 signal LDC_UsrClk : std_logic := '0';
574 signal wr_AMC_en : std_logic := '0';
575 signal wr_EnSFP : std_logic := '0';
576 signal fake_length : std_logic_vector(19 downto 0) := x"00400";
577 signal AMC_en : std_logic_vector(11 downto 0) := (others =>'0');
578 signal TTS_disable : std_logic_vector(11 downto 0) := (others =>'0');
579 signal AMC_Ready : std_logic_vector(11 downto 0) := (others =>'0');
580 signal TTC_lock : std_logic := '0';
581 signal BC0_lock : std_logic_vector(11 downto 0) := (others =>'0');
582 signal AMC_status : std_logic_vector(31 downto 0) := (others =>'0');
583 signal AMC_DATA : std_logic_vector(31 downto 0) := (others =>'0');
584 signal AMC_ack : std_logic := '0';
585 signal L1Aovfl_warning : std_logic := '0';
586 signal HCAL_trigger : std_logic := '0';
587 signal TRIGDATA : array12x8 := (others => (others => '0'));
588 signal TTS_coded : std_logic_vector(4 downto 0) := (others =>'0');
589 signal pattern : std_logic_vector(3 downto 0) := (others =>'0');
590 --signal Trig_mask : std_logic_vector(7 downto 0) := (others =>'0');
591 signal SPI_SCK_buf : std_logic := '0';
592 signal CLK_rdy : std_logic := '0';
593 signal I2C_data : std_logic_vector(31 downto 0) := (others =>'0');
594 signal TTCclk_in : std_logic := '0';
595 signal TTC_Clk : std_logic := '0';
596 signal TTC_strobe : std_logic := '0';
597 signal BcntErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
598 signal SinErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
599 signal DbErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
600 signal L1_reg : std_logic_vector(15 downto 0) := (others =>'0');
601 signal Bcnt_reg : std_logic_vector(11 downto 0) := (others =>'0');
602 signal OC_reg : std_logic_vector(31 downto 0) := (others =>'0');
603 signal DB_cmd : std_logic := '0';
604 signal V2S : std_logic := '0';
605 signal S2V : std_logic := '0';
606 signal S2V_cntr : std_logic_vector(5 downto 0) := (others => '0');
607 signal S2V_sr : std_logic_vector(3 downto 0) := (others => '0');
608 signal ddr_rdata : std_logic_vector(7 downto 0) := (others =>'0');
609 signal ipb_clk_dcm : std_logic := '0';
610 signal ipb_clk : std_logic := '0';
611 signal clk125_dcm : std_logic := '0';
612 signal clk125 : std_logic := '0';
613 signal DRPclk_dcm : std_logic := '0';
614 signal DRPclk : std_logic := '0';
615 signal sysclk_dcm : std_logic := '0';
616 signal sysclk : std_logic := '0';
617 signal clkfb : std_logic := '0';
618 signal refclk_dcm : std_logic := '0';
619 signal refclk : std_logic := '0';
620 signal mem_clk_dcm : std_logic := '0';
621 signal mem_clk : std_logic := '0';
622 signal sysclk_inp : std_logic := '0';
623 signal sysclk_in : std_logic := '0';
624 --signal clk125 : std_logic := '0';
625 signal sys_lock : std_logic := '0';
626 signal sys_lock_n : std_logic := '0';
627 signal ldc_reset : std_logic := '0';
628 signal ldc_GTXreset : std_logic := '0';
629 signal lsc_start : std_logic := '0';
630 signal lsc_reset : std_logic := '0';
631 signal lsc_GTXreset : std_logic := '0';
632 signal amc_reset : std_logic := '0';
633 signal amc_GTXreset : std_logic := '0';
634 signal conf7_q : std_logic := '0';
635 signal conf7_fall : std_logic := '0';
636 signal run : std_logic := '0';
637 signal LSC_LinkDown : std_logic := '0';
638 signal mem_rst : std_logic := '0';
639 signal mem_test : std_logic_vector(1 downto 0) := (others =>'0');
640 signal mem_stat : std_logic_vector(63 downto 0) := (others =>'0');
641 signal mem_ack : std_logic := '0';
642 signal mem_data : std_logic_vector(31 downto 0) := (others =>'0');
643 signal EventData : array3X67 := (others => (others => '0'));
644 signal wport_rdy : std_logic_vector(2 downto 0) := (others =>'0');
645 signal EventBufAddr : array3x14 := (others => (others => '0'));
646 signal EventBufAddr_we : std_logic_vector(2 downto 0) := (others =>'0');
647 signal evt_buf_full : std_logic_vector(2 downto 0) := (others =>'0');
648 signal wport_FIFO_full : std_logic_vector(2 downto 0) := (others =>'0');
649 --signal TCP_din : std_logic_vector(31 downto 0) := (others =>'0');
650 --signal TCP_channel : std_logic_vector(1 downto 0) := (others =>'0');
651 --signal TCP_wrqst : std_logic := '0';
652 --signal TCP_re : std_logic := '0';
653 --signal TCP_dout : std_logic_vector(31 downto 0) := (others =>'0');
654 --signal TCP_raddr : std_logic_vector(23 downto 0) := (others =>'0');
655 --signal TCP_length : std_logic_vector(11 downto 0) := (others =>'0');
656 --signal TCP_dout_valid : std_logic := '0';
657 --signal TCP_rrqst : std_logic := '0';
658 --signal TCP_rack : std_logic := '0';
659 --signal TCP_lastword : std_logic := '0';
660 signal MonBufOvfl : std_logic := '0';
661 signal MonBuf_empty : std_logic := '0';
662 --signal inc_mon_cntr : std_logic := '0';
663 signal mon_evt_wc : std_logic_vector(47 downto 0) := (others =>'0');
664 signal mon_evt_cnt : std_logic_vector(31 downto 0) := (others =>'0');
665 signal mon_ctrl : std_logic_vector(31 downto 0) := (others =>'0');
666 --signal TCPbuf_avl : std_logic := '0';
667 signal mon_buf_avl : std_logic := '0';
668 signal EventBufAddrAvl : std_logic := '0';
669 signal EventBufAddrRe : std_logic := '0';
670 signal mon_wp : std_logic_vector(31 downto 0) := (others =>'0');
671 --signal TCP_releaseAck : std_logic_vector(2 downto 0) := (others =>'0');
672 --signal TCP_releaseRqst : std_logic_vector(2 downto 0) := (others =>'0');
673 --signal TCP_releaseAddr : array3X13 := (others => (others => '0'));
674 signal EventBuf_rqst : std_logic_vector(3 downto 0) := (others =>'0');
675 signal rst_cntr : std_logic := '0';
676 signal rst_ddr_pa : std_logic := '0';
677 signal inc_ddr_pa : std_logic := '0';
678 signal Source_ID : array3X12 := (others => (others => '0'));
679 signal ddr_pa : std_logic_vector(9 downto 0) := (others =>'0');
680 signal CDRclk : std_logic := '0';
681 signal TTS_clk : std_logic := '0';
682 signal chk_lock : std_logic := '0';
683 signal chk_lock_q : std_logic := '0';
684 signal BC0 : std_logic := '0';
685 signal BC0_dl : std_logic := '0';
686 signal BC0_locked : std_logic_vector(1 downto 0) := (others =>'0');
687 signal BC0_cntr : std_logic_vector(4 downto 0) := (others =>'0');
688 signal T3_trigger : std_logic := '0';
689 signal inc_BX_offset : std_logic := '0';
690 signal en_HCAL_trig : std_logic := '0';
691 signal ec_BX_offset : std_logic := '0';
692 signal add_two : std_logic_vector(1 downto 0) := (others =>'0');
693 signal BX_offset : std_logic_vector(11 downto 0) := (others =>'0');
694 signal BX_offset2SC : std_logic_vector(11 downto 0) := (others =>'0');
695 signal bcnt : std_logic_vector(11 downto 0) := x"000";
696 signal LocalL1A_cfg : std_logic_vector(31 downto 0) := (others =>'0');
697 signal BCN_off : std_logic_vector(12 downto 0) := (others =>'0');
698 signal OC_off : std_logic_vector(3 downto 0) := (others =>'0');
699 signal en_cal_win : std_logic := '0';
700 signal CalibCtrl : std_logic_vector(31 downto 0) := x"0d800d80";
701 signal cal_win_high : std_logic_vector(11 downto 0) := (others =>'0');
702 signal cal_win_low : std_logic_vector(11 downto 0) := (others =>'0');
703 signal CalType : std_logic_vector(3 downto 0) := (others =>'0');
704 signal TTC_Brcst : std_logic_vector(3 downto 0) := (others =>'0');
705 signal local_TTCcmd : std_logic := '0';
706 signal en_brcst : std_logic := '0';
707 signal ttc_start : std_logic := '0';
708 signal ttc_stop : std_logic := '0';
709 signal ttc_soft_reset : std_logic := '0';
710 signal ttc_soft_resetp : std_logic := '0';
711 signal ttc_ready : std_logic := '0';
712 signal ttc_serr : std_logic := '0';
713 signal ttc_derr : std_logic := '0';
714 signal ttc_bcnt_err : std_logic := '0';
715 signal ttc_evcnt_reset : std_logic := '0';
716 signal inc_rate_ofw : std_logic := '0';
717 signal rate_ofw : std_logic := '0';
718 signal rate_ofwp : std_logic := '0';
719 signal rate_ofw_q : std_logic := '0';
720 signal sync_lost : std_logic := '0';
721 signal oc_cntr : std_logic_vector(3 downto 0) := (others =>'0');
722 signal ttc_resync : std_logic := '0';
723 signal AllEventBuilt : std_logic := '0';
724 signal dcc_quiet : std_logic := '0';
725 signal inc_oc : std_logic := '0';
726 signal inc_L1ac : std_logic := '0';
727 signal inc_bcnterr : std_logic := '0';
728 signal inc_serr : std_logic := '0';
729 signal inc_derr : std_logic := '0';
730 signal evn_fifo_full : std_logic := '0';
731 signal event_number_avl : std_logic := '0';
732 signal state : std_logic_vector(3 downto 0) := (others =>'0');
733 signal TTS_wait : std_logic_vector(20 downto 0) := (others =>'0');
734 signal event_number : std_logic_vector(59 downto 0) := (others =>'0');
735 signal status_l : std_logic_vector(22 downto 0) := (others =>'0');
736 signal SFP_down_l : std_logic_vector(2 downto 0) := (others =>'0');
737 signal SFP_status_l : std_logic_vector(11 downto 0) := (others =>'0');
738 signal AMC_status_l : std_logic_vector(31 downto 0) := (others =>'0');
739 signal TTC_cntr_data : std_logic_vector(31 downto 0) := (others => '0');
740 signal got_SN : std_logic := '0';
741 signal ipb_strobe_q : std_logic := '0';
742 signal SFP_clk : std_logic := '0';
743 signal AMC_clk : std_logic := '0';
744 signal AMC_clk_in : std_logic := '0';
745 signal SV_Cntr : std_logic_vector(7 downto 0) := (others => '0');
746 signal sysclk_div : std_logic_vector(7 downto 0) := (others => '0');
747 signal SFP_UsrClk : std_logic := '0';
748 signal SFP_TxOutClk : std_logic := '0';
749 signal I2C_debug_out : std_logic_vector(15 downto 0) := (others =>'0');
750 signal SFPOSC_rdy : std_logic := '0';
751 signal reset : std_logic := '0';
752 signal DAQ_reset : std_logic := '0';
753 signal AMCOSC_rdy : std_logic := '0';
754 --signal cs_clk_in : std_logic := '0';
755 --signal cs_clk : std_logic := '0';
756 signal TTC_debug : std_logic_vector(63 downto 0) := (others =>'0');
757 signal TxDisable_i : std_logic_vector(3 downto 0) := (others => '0');
758 signal DAQfifo_re : std_logic := '0';
759 signal DAQfifoAlmostEmpty : std_logic := '0';
760 signal DAQfifoEmpty : std_logic := '0';
761 signal DAQfifo_do : std_logic_vector(63 downto 0) := (others =>'0');
762 signal DAQ_debug_in : std_logic_vector(63 downto 0) := (others =>'0');
763 signal LDC_debug_out : std_logic_vector(63 downto 0) := (others =>'0');
764 signal LSC_debug_out : std_logic_vector(63 downto 0) := (others =>'0');
765 signal ddr_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
766 signal ddr_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
767 signal GbE_REFCLK : std_logic := '0';
768 signal S6Link_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
769 signal S6Link_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
770 signal GbE_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
771 signal GbE_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
772 signal AMC_debug_in : std_logic_vector(255 downto 0) := (others =>'0');
773 signal AMC_debug_out : std_logic_vector(255 downto 0) := (others =>'0');
774 signal SFP0_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
775 signal SFP0_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
776 signal SFP1_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
777 signal SFP1_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
778 signal ipb_master_out : ipb_wbus;
779 signal ipb_master_in : ipb_rbus;
780 signal SN : std_logic_vector(8 downto 0) := (others =>'0');
781 signal MACADDR : std_logic_vector(47 downto 0) := (others =>'0');
782 signal ipaddr : std_logic_vector(31 downto 0) := (others =>'0');
783 signal en_RARP : std_logic := '0';
784 --signal SPI_IP : std_logic_vector(31 downto 0) := (others =>'0');
785 signal status : std_logic_vector(31 downto 0) := (others =>'0');
786 signal cmd : std_logic_vector(31 downto 0) := (others =>'0');
787 signal cmd0_dl : std_logic_vector(1 downto 0) := (others =>'0');
788 signal cmd2_dl : std_logic_vector(1 downto 0) := (others =>'0');
789 signal conf : std_logic_vector(15 downto 0) := (others =>'0');
790 signal LSC_ID : std_logic_vector(15 downto 0) := x"1234";
791 signal OT : std_logic := '0';
792 signal inc_HTRCRC_err : std_logic := '0';
793 signal ttc_data : std_logic_vector(31 downto 0) := (others => '0');
794 signal sysmon_data : std_logic_vector(31 downto 0) := (others => '0');
795 signal HCAL_trig_data : std_logic_vector(31 downto 0) := (others => '0');
796 signal device_temp : std_logic_vector(11 downto 0) := (others =>'0');
797 signal ALM : std_logic_vector(7 downto 0) := (others =>'0');
798 signal evt_data_rdy : std_logic_vector(2 downto 0) := (others => '0');
799 signal evt_data_re : std_logic_vector(2 downto 0) := (others => '0');
800 signal evt_data_we : std_logic_vector(2 downto 0) := (others => '0');
801 --signal event_size : array3x13;
802 signal SFP_data : std_logic_vector(31 downto 0) := (others =>'0');
803 signal SFP_ack : std_logic := '0';
804 --signal TCP_data : std_logic_vector(31 downto 0) := (others =>'0');
805 --signal TCP_ack : std_logic := '0';
806 signal S2V_SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
807 signal resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
808 signal sysclk_div7SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
809 signal resetCntr_SyncRegs : std_logic_vector(2 downto 0) := (others =>'0');
810 signal newIPADDR : std_logic := '0';
811 signal newIPADDRSyncRegs : std_logic_vector(2 downto 0) := (others =>'0');
812 signal DNA_out : std_logic := '0';
813 signal load_DNA : std_logic := '0';
814 signal shift_DNA : std_logic_vector(2 downto 0) := (others =>'0');
815 signal DNA_cntr : std_logic_vector(5 downto 0) := (others =>'0');
816 signal DNA : std_logic_vector(56 downto 0) := (others =>'0');
817 signal Dis_pd : std_logic := '0';
818 signal enSFP : std_logic_vector(3 downto 0) := (others =>'0');
819 signal SFP_down : std_logic_vector(2 downto 0) := (others =>'0');
820 signal WrtMonBlkDone : std_logic_vector(2 downto 0) := (others =>'0');
821 signal WrtMonEvtDone : std_logic_vector(2 downto 0) := (others =>'0');
822 component icon2
823  PORT (
824  CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
825  CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
826 
827 end component;
828 component ila16x32k
829  PORT (
830  CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
831  CLK : IN STD_LOGIC;
832  DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
833  TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
834 
835 end component;
836 signal CONTROL0 : std_logic_vector(35 downto 0) := (others => '0');
837 signal CONTROL1 : std_logic_vector(35 downto 0) := (others => '0');
838 signal TRIG0 : std_logic_vector(7 downto 0) := (others => '0');
839 signal TRIG1 : std_logic_vector(7 downto 0) := (others => '0');
840 signal DATA0 : std_logic_vector(15 downto 0) := (others => '0');
841 signal DATA1 : std_logic_vector(15 downto 0) := (others => '0');
842 begin
843 --i_icon : icon2
844 -- port map (
845 -- CONTROL0 => CONTROL0,
846 -- CONTROL1 => CONTROL1);
847 --i_ila : ila16x32k
848 -- port map (
849 -- CONTROL => CONTROL0,
850 -- CLK => sysclk,
851 -- DATA => DATA0,
852 -- TRIG0 => TRIG0);
853 --DATA0(14) <= evt_buf_full(0);
854 --DATA0(13) <= evt_data_re(0);
855 --DATA0(12) <= evt_data_rdy(0);
856 --DATA0(11 downto 10) <= EventBufAddr(0)(5 downto 4);
857 --DATA0(9 downto 8) <= EventData(0)(65 downto 64);
858 --DATA0(7) <= wport_rdy(0);
859 --DATA0(6) <= wport_FIFO_full(0);
860 --DATA0(5) <= evt_data_we(0);
861 --DATA0(4) <= EventBufAddr_we(0);
862 --DATA0(3 downto 0) <= mem_stat(3 downto 0);
863 --TRIG0(7 downto 4) <= (others => '0');
864 --TRIG0(3) <= wport_rdy(0);
865 --TRIG0(2) <= EventBufAddr_we(0);
866 --TRIG0(1) <= evt_data_re(0);
867 --TRIG0(0) <= evt_data_rdy(0);
868 --
869 --i_il2 : ila16x32k
870 -- port map (
871 -- CONTROL => CONTROL1,
872 -- CLK => mem_stat(19),
873 -- DATA => DATA1,
874 -- TRIG0 => TRIG1);
875 --DATA1(14 downto 0) <= mem_stat(18 downto 4);
876 --TRIG1(7 downto 2) <= (others => '0');
877 --TRIG1(1 downto 0) <= mem_stat(18 downto 17);
878 i_TTS_if: TTS_if PORT MAP(
879  sysclk => sysclk,
880  TTS_clk => TTS_clk,
881  reset => sys_lock_n,
882  local_TTC => conf(8),
883  TTS => state,
884  TTS_out_p => TTS_out_p,
885  TTS_out_n => TTS_out_n
886  );
887 i_HCAL_trig: HCAL_trig PORT MAP(
888  TTC_clk => TTC_clk,
889  DRPCLK => DRPclk,
890  reset => reset,
891  BC0 => BC0_dl ,
892  en_HCAL_trig => en_HCAL_trig ,
893  Trigdata => Trigdata,
894  triggerOut => HCAL_trigger,
895  ipb_clk => ipb_clk,
896  ipb_write => ipb_master_out.ipb_write ,
897  ipb_strobe => ipb_master_out.ipb_strobe ,
898  ipb_addr => ipb_master_out.ipb_addr ,
899  ipb_wdata => ipb_master_out.ipb_wdata ,
900  ipb_rdata => HCAL_trig_data,
901  GTX_REFCLKp => CDR_REFCLK_P,
902  GTX_REFCLKn => CDR_REFCLK_N,
903  GTX_RXp => SFP2_RXP,
904  GTX_RXn => SFP2_RXN,
905  GTX_TXp => SFP2_TXP,
906  GTX_TXn => SFP2_TXN
907  );
908 TxDisable <= TxDisable_i;
909 i_I2C: I2C PORT MAP(
910  clk => DRPclk ,
911  ipb_clk => clk125,
912  reset => sys_lock_n,
913  addr => ipb_master_out.ipb_addr,
914  rdata => I2C_data,
915  CLK_rdy => CLK_rdy,
916  CLK_SCL => CLK_SCL,
917  CLK_SDA => CLK_SDA,
918  SFP_ABS => SFP_ABS,
919  SFP_LOS => SFP_LOS,
920  SFP_SCL => SFP_SCL,
921  SFP_SDA => SFP_SDA
922  );
923 i_SPI_SCK_buf: bufh port map(i => SPI_SCK, o => SPI_SCK_buf);
924 i_SPI_if: SPI_if PORT MAP(
925  SCK => SPI_SCK ,
926  CSn => SPI_CS_b ,
927  MOSI => SPI_MOSI ,
928  MISO => SPI_MISO ,
929  SN => SN,
930  OT => ALM(0),
931  IsT1 => '1',
932  SPI_we => open,
933  en_RARP => en_RARP,
934  newIPADDR => newIPADDR,
935  IPADDR => IPADDR,
936  SPI_rdata => (others => '0'),
937  SPI_wdata => open,
938  SPI_addr => open
939  );
940 i_ttc_if: ttc_if PORT MAP(
941  clk => sysclk ,
942  refclk => sysclk ,
943  reset => reset,
944  run => run,
945  DB_cmd_in => cmd(9),
946  DB_cmd_out => DB_cmd,
947  IsG2 => '0',
948  TTC_strobe => TTC_strobe,
949  sys_lock => sys_lock,
950  local_TTC => conf(8),
951  local_TTCcmd => local_TTCcmd ,
952  single_TTCcmd => cmd(8),
953  TTS_clk => TTS_clk,
954  BC0 => BC0,
955  DIV4 => DIV4,
956  DIV_nRST => DIV_nRST,
957  CDRclk_p => CDRclk_p,
958  CDRclk_n => CDRclk_n,
959  CDRclk_out => CDRclk,
960  CDRdata_p => CDRdata_p,
961  CDRdata_n => CDRdata_n,
962  TTCdata_p => TTCdata_p,
963  TTCdata_n => TTCdata_n,
964  TTC_LOS => TTC_LOS,
965  TTC_LOL => TTC_LOL,
966  BCN_off => BCN_off,
967  OC_off => OC_off,
968  en_cal_win => en_cal_win,
969  cal_win_high => cal_win_high ,
970  cal_win_low => cal_win_low ,
971  CalType => CalType,
972  TTC_Brcst => TTC_Brcst,
973  ovfl_warning => L1Aovfl_warning ,
974  ipb_clk => ipb_clk,
975  ipb_write => ipb_master_out.ipb_write ,
976  ipb_strobe => ipb_master_out.ipb_strobe ,
977  ipb_addr => ipb_master_out.ipb_addr ,
978  ipb_wdata => ipb_master_out.ipb_wdata ,
979  ipb_rdata => ttc_data,
980  en_localL1A => conf(2),
981  LocalL1A_cfg => LocalL1A_cfg ,
982  localL1A_s => cmd(26),
983  localL1A_r => cmd(10),
984  localL1A_periodic => status(10),
985  T3_trigger => T3_trigger,
986  HCAL_trigger => HCAL_trigger ,
987  EvnRSt_l => cmd(11),
988  OcnRSt_l => cmd(12),
989  en_brcst => en_brcst,
990  ttc_start => ttc_start,
991  ttc_stop => ttc_stop,
992  ttc_soft_reset => ttc_soft_reset ,
993  ttc_ready => ttc_ready,
994  ttc_serr => ttc_serr,
995  ttc_derr => ttc_derr,
996  ttc_bcnt_err => ttc_bcnt_err ,
997  rate_OFW => rate_OFW,
998  sync_lost => sync_lost,
999  inc_oc => inc_oc,
1000  inc_l1ac => inc_l1ac,
1001  inc_bcnterr => inc_bcnterr ,
1002  inc_serr => inc_serr,
1003  inc_derr => inc_derr,
1004  state => state,
1005  evn_fifo_full => evn_fifo_full ,
1006  ttc_evcnt_reset => ttc_evcnt_reset ,
1007  event_number_avl => event_number_avl ,
1008  event_number => event_number
1009  );
1010 local_TTCcmd <= conf(5) or conf(8);
1011 CalibCtrl(31) <= en_cal_win;
1012 CalibCtrl(30 downto 28) <= "000";
1013 CalibCtrl(27 downto 16) <= cal_win_high;
1014 CalibCtrl(15 downto 12) <= CalType;
1015 CalibCtrl(11 downto 0) <= cal_win_low;
1016 cal_win_high(11 downto 6) <= "110110";
1017 cal_win_low(11 downto 6) <= "110110";
1018 i_S2V: IBUFDS generic map(DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25") port map(i => S2V_p, ib => S2V_n, o => S2V);
1019 process(CDRclk)
1020 begin
1021  if(CDRclk'event and CDRclk = '1')then
1022  if(conf(15) = '0')then
1023  T3_trigger <= '0';
1024  else
1025  T3_trigger <= S2V;
1026  end if;
1027  end if;
1028 end process;
1029 i_GbE_REFCLK: IBUFDS_GTE2
1030  port map
1031  (
1032  O => GbE_REFCLK,
1033  ODIV2 => open,
1034  CEB => '0',
1035  I => GbE_REFCLK_P, -- Connect to package pin AB6
1036  IB => GbE_REFCLK_N -- Connect to package pin AB5
1037  );
1038 i_TTCclk_in : IBUFGDS generic map (DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25")
1039  port map (
1040  O => TTCclk_in, -- Clock buffer output
1041  I => TTCclk_p, -- Diff_p clock buffer input
1042  IB => TTCclk_n -- Diff_n clock buffer input
1043  );
1044 i_TTC_CLK_buf: bufg port map(i => TTCclk_in, o => TTC_Clk);
1045 i_sysclk_in_buf: bufh port map(i => GbE_REFCLK, o => sysclk_in);
1046 i_PLL_sysclk : PLLE2_BASE
1047  generic map (
1048  BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
1049  CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
1050  CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
1051  CLKIN1_PERIOD => 8.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
1052  -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
1053  CLKOUT0_DIVIDE => 5,
1054  CLKOUT1_DIVIDE => 32,
1055  CLKOUT2_DIVIDE => 20,
1056  DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
1057  REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
1058  STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
1059  )
1060  port map (
1061  -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
1062  CLKOUT0 => sysclk_dcm,
1063  CLKOUT1 => ipb_clk_dcm ,
1064  CLKOUT2 => DRPclk_dcm,
1065  -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
1066  CLKFBOUT => clk125_dcm, -- 1-bit output: Feedback clock
1067  -- Status Port: 1-bit (each) output: PLL status ports
1068  LOCKED => sys_lock, -- 1-bit output: LOCK
1069  -- Clock Input: 1-bit (each) input: Clock input
1070  CLKIN1 => sysclk_in, -- 1-bit input: Input clock
1071  -- Control Ports: 1-bit (each) input: PLL control ports
1072  PWRDWN => '0', -- 1-bit input: Power-down
1073  RST => '0', -- 1-bit input: Reset
1074  -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
1075  CLKFBIN => clk125 -- 1-bit input: Feedback clock
1076  );
1077 i_clk125_buf: bufg port map(i => clk125_dcm, o => clk125 );
1078 i_ipb_clk_buf: bufg port map(i => ipb_clk_dcm, o => ipb_clk);
1079 i_DRPclk_buf: bufg port map(i => DRPclk_dcm, o => DRPclk );
1080 i_sysclk_buf: bufg port map(i => sysclk_dcm, o => sysclk );
1081 --i_refclk_buf: bufg port map(i => refclk_dcm, o => refclk);
1082 reset <= not sys_lock or cmd(0);
1083 --sysclk <= refclk;
1084 process(sysclk,reset)
1085 begin
1086  if(reset = '1')then
1087  resetSyncRegs <= (others => '1');
1088  elsif(sysclk'event and sysclk = '1')then
1089  resetSyncRegs <= resetSyncRegs(1 downto 0) & '0';
1090  end if;
1091 end process;
1092 i_ddr_if: ddr_if PORT MAP(
1093  mem_clk_p => sys_clk_p,
1094  mem_clk_n => sys_clk_n,
1095  mem_rst => mem_rst,
1096  clk_ref => sysclk,
1097  sysclk => sysclk,
1098  TCPclk => sysclk,
1099  reset => reset,
1100  resetsys => resetSyncRegs(2),
1101  run => run,
1102  mem_test => mem_test,
1103  EventData => EventData,
1104  EventData_we => evt_data_we,
1105  wport_rdy => wport_rdy,
1106  WrtMonBlkDone => WrtMonBlkDone ,
1107  WrtMonEvtDone => WrtMonEvtDone ,
1108  KiloByte_toggle => open,
1109  EoB_toggle => open,
1110  EventBufAddr => EventBufAddr ,
1111  EventBufAddr_we => EventBufAddr_we ,
1112  EventFIFOfull => wport_FIFO_full ,
1113  TCP_din => (others => '0'),
1114  TCP_channel => (others => '0'),
1115  TCP_we => '0',
1116  TCP_wcount => open,
1117  TCP_dout => open,
1118  TCP_raddr => (others => '0'),
1119  TCP_length => (others => '0'),
1120  TCP_dout_valid => open,
1121  TCP_rrqst => '0',
1122  TCP_rack => open,
1123  TCP_lastword => open,
1124  page_addr => ddr_pa,
1125  ipb_clk => ipb_clk,
1126  ipb_write => ipb_master_out.ipb_write ,
1127  ipb_strobe => ipb_master_out.ipb_strobe ,
1128  ipb_addr => ipb_master_out.ipb_addr ,
1129  ipb_wdata => ipb_master_out.ipb_wdata ,
1130  ipb_rdata => mem_data,
1131  ipb_ack => mem_ack,
1132  mem_stat => mem_stat,
1133  device_temp => device_temp ,
1134  ddr3_dq => ddr3_dq,
1135  ddr3_dm => ddr3_dm,
1136  ddr3_addr => ddr3_addr,
1137  ddr3_ba => ddr3_ba,
1138  ddr3_dqs_p => ddr3_dqs_p,
1139  ddr3_dqs_n => ddr3_dqs_n,
1140  ddr3_ras_n => ddr3_ras_n,
1141  ddr3_cas_n => ddr3_cas_n,
1142  ddr3_we_n => ddr3_we_n,
1143  ddr3_reset_n => ddr3_reset_n ,
1144  ddr3_cke => ddr3_cke,
1145  ddr3_odt => ddr3_odt,
1146  ddr3_ck_p => ddr3_ck_p,
1147  ddr3_ck_n => ddr3_ck_n
1148  );
1149 --mem_rst <= not sys_lock or not CLK_rdy or cmd(5) or cmd(0);
1150 mem_rst <= not sys_lock or not CLK_rdy or cmd(5);
1151 MACADDR <= x"080030f30" & '0' & not SN(8) & '0' & not SN(7 downto 6) & '1' & SN(5 downto 0);
1152 i_ipbus_if: ipbus_if PORT MAP(
1153  ipb_clk => ipb_clk,
1154  UsRclk => clk125,
1155  DRPclk => DRPclk,
1156  reset => rst_ipbus,
1157  GTX_RESET => sys_lock_n,
1158  MACADDR => MACADDR, -- new mac range 08-00-30-F3-00-00 to 08-00-30-F3-00-7F
1159  en_RARP => en_RARP,
1160  IPADDR => IPADDR,
1161  GbE_REFCLK => GbE_REFCLK,
1162  S6LINK_RXN => S6LINK_RXN,
1163  S6LINK_RXP => S6LINK_RXP,
1164  S6LINK_TXN => S6LINK_TXN,
1165  S6LINK_TXP => S6LINK_TXP,
1166  wr_AMC_en => wr_AMC_en,
1167  amc_en => AMC_en,
1168  ipb_out => ipb_master_out,
1169  ipb_in => ipb_master_in,
1170  got_SN => got_SN,
1171  SN => SN,
1172  debug_in => (others => '0'),
1173  debug_out => open
1174  );
1175 --LSC_LinkDown <= '1' when conf(1) = '0' or or_reduce(EnSFP(2 downto 0) and SFP_down) = '1' else '0';
1176 --status(0) <= LSC_LinkDown;
1177 status(0) <= or_reduce(SFP_down);
1178 status(1) <= MonBufOvfl;
1179 status(2) <= mon_evt_cnt(10);
1180 status(3) <= MonBuf_empty;
1181 status(4) <= mem_stat(0); -- monitor input FIFO overflow
1182 status(5) <= not ttc_ready;
1183 status(6) <= ttc_bcnt_err;
1184 status(7) <= ttc_serr;
1185 status(8) <= ttc_derr;
1186 status(9) <= sync_lost;
1187 status(13) <= L1Aovfl_warning;
1188 status(15) <= mem_stat(63);
1189 status(23) <= '0';
1190 run <= conf(0);
1191 EnSFP(3) <= not conf(1);
1192 mem_test <= conf(6) & conf(4);
1193 --en_brcst <= conf(5);
1194 en_brcst <= '0';
1195 i_cmd0_dl0 : SRL16E
1196  port map (
1197  Q => cmd0_dl(0), -- SRL data output
1198  A0 => '1', -- Select[0] input
1199  A1 => '1', -- Select[1] input
1200  A2 => '1', -- Select[2] input
1201  A3 => '0', -- Select[3] input
1202  CE => '1', -- Clock enable input
1203  CLK => ipb_clk, -- Clock input
1204  D => cmd(0) -- SRL data input
1205  );
1206 i_cmd0_dl1 : SRL16E
1207  port map (
1208  Q => cmd0_dl(1), -- SRL data output
1209  A0 => '1', -- Select[0] input
1210  A1 => '1', -- Select[1] input
1211  A2 => '1', -- Select[2] input
1212  A3 => '0', -- Select[3] input
1213  CE => '1', -- Clock enable input
1214  CLK => ipb_clk, -- Clock input
1215  D => cmd0_dl(0) -- SRL data input
1216  );
1217 i_cmd2_dl0 : SRL16E
1218  port map (
1219  Q => cmd2_dl(0), -- SRL data output
1220  A0 => '1', -- Select[0] input
1221  A1 => '1', -- Select[1] input
1222  A2 => '1', -- Select[2] input
1223  A3 => '0', -- Select[3] input
1224  CE => '1', -- Clock enable input
1225  CLK => ipb_clk, -- Clock input
1226  D => cmd(2) -- SRL data input
1227  );
1228 i_cmd2_dl1 : SRL16E
1229  port map (
1230  Q => cmd2_dl(1), -- SRL data output
1231  A0 => '1', -- Select[0] input
1232  A1 => '1', -- Select[1] input
1233  A2 => '1', -- Select[2] input
1234  A3 => '0', -- Select[3] input
1235  CE => '1', -- Clock enable input
1236  CLK => ipb_clk, -- Clock input
1237  D => cmd2_dl(0) -- SRL data input
1238  );
1239 process(ipb_clk)
1240 begin
1241  if(ipb_clk'event and ipb_clk = '1')then
1242  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = CSR_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1243  cmd <= ipb_master_out.ipb_wdata;
1244  else
1245  cmd <= (others => '0');
1246  end if;
1247  conf7_q <= conf(7);
1248  conf7_fall <= conf7_q and not conf(7);
1249  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = CFG_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1250  conf <= ipb_master_out.ipb_wdata(15 downto 0);
1251  end if;
1252  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = HTR_EN_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1253  Dis_pd <= ipb_master_out.ipb_wdata(15);
1254  EnSFP(1 downto 0) <= ipb_master_out.ipb_wdata(13 downto 12);
1255  AMC_en <= ipb_master_out.ipb_wdata(11 downto 0);
1256  if(AMC_en = ipb_master_out.ipb_wdata(11 downto 0))then
1257  wr_AMC_en <= '0';
1258  else
1259  wr_AMC_en <= '1';
1260  end if;
1261  if(EnSFP(1 downto 0) = ipb_master_out.ipb_wdata(13 downto 12))then
1262  wr_EnSFP <= '0';
1263  else
1264  wr_EnSFP <= '1';
1265  end if;
1266  else
1267  wr_AMC_en <= '0';
1268  wr_EnSFP <= '0';
1269  end if;
1270  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"001a" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1271  TTS_disable <= ipb_master_out.ipb_wdata(11 downto 0);
1272  end if;
1273  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = TTC_cal_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1274  en_cal_win <= ipb_master_out.ipb_wdata(31);
1275  cal_win_high(5 downto 0) <= ipb_master_out.ipb_wdata(21 downto 16);
1276  cal_win_low(5 downto 0) <= ipb_master_out.ipb_wdata(5 downto 0);
1277  end if;
1278  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1279  Source_ID(0)(11 downto 0) <= ipb_master_out.ipb_wdata(11 downto 0);
1280  end if;
1281  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id1_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1282  Source_ID(1)(11 downto 0) <= ipb_master_out.ipb_wdata(11 downto 0);
1283  end if;
1284  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"001c" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1285  LocalL1A_cfg <= ipb_master_out.ipb_wdata;
1286  end if;
1287  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SFP_CSR_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1288  LSC_ID(15 downto 2) <= ipb_master_out.ipb_wdata(31 downto 18);
1289  TxDisable_i <= ipb_master_out.ipb_wdata(15 downto 12);
1290  end if;
1291  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = TTC_bcnt_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1292  OC_OFF <= ipb_master_out.ipb_wdata(19 downto 16);
1293  BCN_OFF <= ipb_master_out.ipb_wdata(12 downto 0);
1294  end if;
1295  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = fake_length_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1296  fake_length <= ipb_master_out.ipb_wdata(19 downto 0);
1297  end if;
1298  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"0019" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1299  pattern <= ipb_master_out.ipb_wdata(11 downto 8);
1300 -- Trig_mask <= ipb_master_out.ipb_wdata(7 downto 0);
1301  end if;
1302  if(reset = '1' or (ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = MON_ctrl_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1'))then
1303  ddr_pa <= (others => '0');
1304  elsif(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = PAGE_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1305  if(run = '1')then
1306  if(MonBuf_empty = '0')then
1307  ddr_pa <= ddr_pa + 1;
1308  end if;
1309  else
1310  ddr_pa <= ipb_master_out.ipb_wdata(9 downto 0);
1311  end if;
1312  end if;
1313  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = PAGE_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1' and run = '1' and MonBuf_empty = '0')then
1314  inc_ddr_pa <= '1';
1315  else
1316  inc_ddr_pa <= '0';
1317  end if;
1318  if(DB_cmd = '1')then
1319  status_l <= status(22 downto 0);
1320  SFP_down_l <= SFP_down;
1321  SFP_status_l <= TxFault & (TTC_LOL or TTC_LOL) & SFP_LOS & SFP_ABS;
1322  AMC_status_l <= AMC_status;
1323  end if;
1324  end if;
1325 end process;
1326 ipb_master_in.ipb_ack <= ipb_master_out.ipb_strobe when ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(17) = '0' else mem_ack;
1327 process(ipb_master_out.ipb_addr)
1328 begin
1329  if(ipb_master_out.ipb_addr(27) = '1' or ipb_master_out.ipb_addr(17) = '1')then
1330  ipb_master_in.ipb_rdata <= mem_data;
1331  elsif(ipb_master_out.ipb_addr(14 downto 5) = CSR_addr(14 downto 5))then
1332  if(ipb_master_out.ipb_addr(15) = '0')then
1333  case ipb_master_out.ipb_addr(4 downto 0) is
1334  when "00000" => ipb_master_in.ipb_rdata <= not SN(7 downto 0) & not SN(8) & status(22 downto 0);
1335  when "00001" => ipb_master_in.ipb_rdata <= K7version & conf;
1336  when "00010" => ipb_master_in.ipb_rdata <= mon_ctrl;
1337  when "00011" => ipb_master_in.ipb_rdata <= '0' & SFP_down & AMC_Ready & Dis_pd & EnSFP(2 downto 0) & AMC_en;
1338  when "00100" => ipb_master_in.ipb_rdata <= LSC_ID & TxDisable_i & TxFault & (TTC_LOL or TTC_LOL) & SFP_LOS & SFP_ABS;
1339  when "00101" => ipb_master_in.ipb_rdata <= AMC_status;
1340  when "00111" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(0);
1341  when "01000" => ipb_master_in.ipb_rdata <= x"000" & OC_OFF & "000" & BCN_OFF;
1342  when "01001" => ipb_master_in.ipb_rdata <= CalibCtrl;
1343  when "01010" => ipb_master_in.ipb_rdata <= mem_stat(31 downto 0);
1344  when "01011" => ipb_master_in.ipb_rdata <= mem_stat(63 downto 32);
1345  when "01100" => ipb_master_in.ipb_rdata <= x"00000" & "00" & ddr_pa;
1346  when "01101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(15 downto 0) & '0';
1347  when "01110" => ipb_master_in.ipb_rdata <= mon_evt_cnt;
1348  when "01111" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(31 downto 16) & '0';
1349  when "10000" => ipb_master_in.ipb_rdata <= x"000" & "00" & mon_buf_avl & '1' & '0' & wport_FIFO_full & '0' & wport_rdy & x"0" & '0' & evt_data_rdy;
1350  when "10001" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(1);
1351  when "10010" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(2);
1352  when "11000" => ipb_master_in.ipb_rdata <= x"000" & fake_length;
1353  when "11001" => ipb_master_in.ipb_rdata <= x"00" & "000" & TTS_coded & state & pattern & x"00";
1354  when "11010" => ipb_master_in.ipb_rdata <= x"00000" & TTS_disable;
1355  when "11100" => ipb_master_in.ipb_rdata <= LocalL1A_cfg;
1356  when "11101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(47 downto 32) & '0';
1357  when "11110" => ipb_master_in.ipb_rdata <= DNA(31 downto 0);
1358  when "11111" => ipb_master_in.ipb_rdata <= "0000000" & DNA(56 downto 32);
1359  when others => ipb_master_in.ipb_rdata <= (others => '0');
1360  end case;
1361  else
1362  case ipb_master_out.ipb_addr(4 downto 0) is
1363  when "00000" => ipb_master_in.ipb_rdata <= not SN(7 downto 0) & not SN(8) & status_l;
1364  when "00001" => ipb_master_in.ipb_rdata <= K7version & conf;
1365  when "00010" => ipb_master_in.ipb_rdata <= mon_ctrl;
1366  when "00011" => ipb_master_in.ipb_rdata <= '0' & SFP_down_l & AMC_Ready & Dis_pd & EnSFP(2 downto 0) & AMC_en;
1367  when "00100" => ipb_master_in.ipb_rdata <= LSC_ID & TxDisable_i & SFP_status_l;
1368  when "00101" => ipb_master_in.ipb_rdata <= AMC_status_l;
1369  when "00111" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(0);
1370  when "01000" => ipb_master_in.ipb_rdata <= x"000" & OC_OFF & "000" & BCN_OFF;
1371  when "01001" => ipb_master_in.ipb_rdata <= CalibCtrl;
1372  when "01010" => ipb_master_in.ipb_rdata <= mem_stat(31 downto 0);
1373  when "01011" => ipb_master_in.ipb_rdata <= mem_stat(63 downto 32);
1374  when "01100" => ipb_master_in.ipb_rdata <= x"00000" & "00" & ddr_pa;
1375  when "01101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(15 downto 0) & '0';
1376  when "01110" => ipb_master_in.ipb_rdata <= mon_evt_cnt;
1377  when "01111" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(31 downto 16) & '0';
1378  when "10000" => ipb_master_in.ipb_rdata <= x"000" & "00" & mon_buf_avl & '1' & '0' & wport_FIFO_full & '0' & wport_rdy & x"0" & '0' & evt_data_rdy;
1379  when "10001" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(1);
1380  when "10010" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(2);
1381  when "11000" => ipb_master_in.ipb_rdata <= x"000" & fake_length;
1382  when "11001" => ipb_master_in.ipb_rdata <= x"00" & "000" & TTS_coded & state & pattern & x"00";
1383  when "11010" => ipb_master_in.ipb_rdata <= x"00000" & TTS_disable;
1384  when "11100" => ipb_master_in.ipb_rdata <= LocalL1A_cfg;
1385  when "11101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(47 downto 32) & '0';
1386  when "11110" => ipb_master_in.ipb_rdata <= DNA(31 downto 0);
1387  when "11111" => ipb_master_in.ipb_rdata <= "0000000" & DNA(56 downto 32);
1388  when others => ipb_master_in.ipb_rdata <= (others => '0');
1389  end case;
1390  end if;
1391  else
1392  ipb_master_in.ipb_rdata <= AMC_data or TTC_cntr_data or I2C_data or sysmon_data or SFP_data or ttc_data;
1393  end if;
1394 end process;
1395 rst_cntr <= cmd(1) or cmd(0);
1396 ttc_resync <= ttc_soft_reset;
1397 process(sysClk,reset)
1398 begin
1399  if(reset = '1')then
1400  TTS_wait <= (others => '0');
1401  elsif(sysClk'event and sysClk = '1')then
1402  if(ttc_resync = '1')then
1403  TTS_wait <= (others => '0');
1404  elsif(TTS_wait(20) = '0' and sync_lost = '0' and AllEventBuilt = '1')then
1405  TTS_wait <= TTS_wait + 1;
1406  end if;
1407  end if;
1408 end process;
1409 process(sysClk,reset)
1410 begin
1411  if(reset = '1')then
1412  state <= "0100";
1413  elsif(sysClk'event and sysClk = '1')then
1414  if(run = '0' and conf(12) = '1')then
1415  state <= pattern;
1416  elsif(run = '0')then
1417  state <= "0100"; -- changed upon request starting version 0x3023
1418  elsif(ttc_resync = '1')then
1419  state <= "0100";
1420  else
1421  case state is
1422  when "1000" => -- Ready
1423  if(TTS_coded(4) = '1')then
1424  state <= "1111";
1425  elsif(TTS_coded(3) = '1')then
1426  state <= "1100";
1427  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1428  state <= "0010";
1429  elsif(L1Aovfl_warning = '1' or evn_fifo_full = '1' or rate_OFWp = '1' or TTS_coded(1) = '1' or TTS_coded(0) = '1')then
1430  state <= "0001";
1431  end if;
1432  when "0001" => -- OFW
1433  if(TTS_coded(4) = '1')then
1434  state <= "1111";
1435  elsif(TTS_coded(3) = '1')then
1436  state <= "1100";
1437  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1438  state <= "0010";
1439  elsif(evn_fifo_full = '1' or rate_OFWp = '1' or TTS_coded(1) = '1')then
1440  state <= "0100";
1441  elsif(L1Aovfl_warning = '0' and rate_OFWp = '0' and TTS_coded(0) = '0')then
1442  state <= "1000";
1443  end if;
1444  when "0100" => -- Busy
1445  if(TTS_wait(20) = '0')then
1446  elsif(TTS_coded(4) = '1')then
1447  state <= "1111";
1448  elsif(TTS_coded(3) = '1')then
1449  state <= "1100";
1450  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1451  state <= "0010";
1452  elsif(evn_fifo_full = '0' and rate_OFWp = '0' and TTS_coded(1) = '0')then
1453  state <= "0001";
1454  end if;
1455  when others => null; -- x"0" or x"f" disconnected, x"2" OOS, x"c" error
1456  end case;
1457  end if;
1458  end if;
1459 end process;
1460 ipb_master_in.ipb_err <= '0';
1461 process(TTC_clk)
1462 begin
1463  if(TTC_clk'event and TTC_clk = '1')then
1464  if(BC0 = '1')then
1465  bcnt <= x"de8"; -- this compensates 5 TTC clock delay in HCAL_trig(2) and ttc_if(3)
1466  elsif(bcnt = x"deb")then
1467  bcnt <= (others => '0');
1468  else
1469  bcnt <= bcnt + 1;
1470  end if;
1471  if(bcnt = BX_offset)then
1472  BC0_dl <= '1';
1473  else
1474  BC0_dl <= '0';
1475  end if;
1476  chk_lock <= BC0_dl;
1477  chk_lock_q <= chk_lock;
1478  if(TTC_lock = '0')then
1479  BC0_locked <= "00";
1480  elsif(chk_lock = '1')then
1481  BC0_locked <= BC0_locked(0) & and_reduce(BC0_lock or (not AMC_en));
1482  end if;
1483  if(TTC_lock = '0')then
1484  inc_BX_offset <= '0';
1485  add_two <= "00";
1486  elsif(chk_lock_q = '1' and BC0_locked = "10")then
1487  inc_BX_offset <= '1';
1488  add_two <= "10";
1489  elsif(add_two /= "00")then
1490  add_two <= add_two - 1;
1491  end if;
1492  if(TTC_lock = '0')then
1493  en_HCAL_trig <= '0';
1494  elsif(chk_lock = '1')then
1495  if(inc_BX_offset = '1' and add_two = "00")then
1496  en_HCAL_trig <= '1';
1497  else
1498  en_HCAL_trig <= '0';
1499  end if;
1500  end if;
1501  if(TTC_lock = '0')then
1502  ec_BX_offset <= '0';
1503  elsif(chk_lock = '1' and inc_BX_offset = '0')then
1504  ec_BX_offset <= '1';
1505  elsif(add_two /= "00")then
1506  ec_BX_offset <= '1';
1507  else
1508  ec_BX_offset <= '0';
1509  end if;
1510  if(TTC_lock = '0')then
1511  BX_offset <= x"100";
1512  elsif(ec_BX_offset = '1')then
1513  if(inc_BX_offset = '1')then
1514  if(BX_offset = x"deb")then
1515  BX_offset <= x"000";
1516  else
1517  BX_offset <= BX_offset + 1;
1518  end if;
1519  elsif(BX_offset = x"000")then
1520  BX_offset <= x"deb";
1521  else
1522  BX_offset <= BX_offset - 1;
1523  end if;
1524  end if;
1525  if(BX_offset(11) = '1')then
1526  BX_offset2SC <= BX_offset - x"dec";
1527  else
1528  BX_offset2SC <= BX_offset;
1529  end if;
1530  end if;
1531 end process;
1532 i_AMC_if: AMC_if PORT MAP(
1533  sysclk => sysclk,
1534  ipb_clk => ipb_clk,
1535  clk125 => clk125,
1536  DRPclk => DRPclk,
1537  reset => AMC_reset,
1538  DB_cmd => DB_cmd,
1539  ReSync => ttc_resync,
1540  GTXreset => amc_GTXreset,
1541  resetCntr => rst_cntr,
1542  AllEventBuilt => AllEventBuilt ,
1543  run => run,
1544  en_inject_err => conf(10),
1545  Dis_pd => Dis_pd,
1546  enSFP => enSFP,
1547  test => conf(7),
1548  NoReSyncFake => conf(11),
1549  WaitMonBuf => conf(14),
1550  fake_length => fake_length ,
1551  en_localL1A => conf(2),
1552  T1_version => K7version(7 downto 0),
1553  Source_ID => Source_ID,
1554  AMC_en => AMC_en,
1555  TTS_disable => TTS_disable ,
1556  AMC_Ready => AMC_Ready,
1557  TTC_lock => TTC_lock,
1558  BC0_lock => BC0_lock,
1559  AMC_REFCLK_P => AMC_REFCLK_P ,
1560  AMC_REFCLK_N => AMC_REFCLK_N ,
1561  AMC_RXN => AMC_RXN,
1562  AMC_RXP => AMC_RXP,
1563  AMC_TXN => AMC_TXN,
1564  AMC_TXP => AMC_TXP,
1565  AMC_status => AMC_status,
1566  evt_data => EventData,
1567  evt_data_we => evt_data_we ,
1568  evt_buf_full => evt_buf_full ,
1569  evt_data_re => evt_data_re ,
1570  evt_data_rdy => evt_data_rdy ,
1571  ddr_pa => ddr_pa,
1572  MonBuf_empty => MonBuf_empty ,
1573  mon_evt_wc => mon_evt_wc,
1574  mon_ctrl => mon_ctrl,
1575  mon_buf_avl => mon_buf_avl ,
1576  TCPbuf_avl => '1',
1577  buf_rqst => EventBuf_rqst,
1578  ipb_write => ipb_master_out.ipb_write ,
1579  ipb_strobe => ipb_master_out.ipb_strobe ,
1580  ipb_addr => ipb_master_out.ipb_addr ,
1581  ipb_wdata => ipb_master_out.ipb_wdata ,
1582  ipb_rdata => AMC_data,
1583  ipb_ack => AMC_ack,
1584  TTC_clk => TTC_clk,
1585  TTC_LOS => TTC_LOS,
1586  BC0 => BC0_dl ,
1587  ttc_evcnt_reset => ttc_evcnt_reset ,
1588  event_number_avl => event_number_avl ,
1589  event_number => event_number ,
1590  evn_buf_full => evn_fifo_full,
1591  ovfl_warning => L1Aovfl_warning ,
1592  TrigData => TrigData,
1593  TTS_coded => TTS_coded
1594  );
1595 AMC_reset <= not sys_lock or cmd(0) or cmd0_dl(1);
1596 amc_GTXreset <= wr_AMC_en or conf7_fall or not sys_lock;
1597 sys_lock_n <= not sys_lock;
1598 --i_DAQLSC_if: DAQLSCXG_2x_if PORT MAP(
1599 -- sysclk => sysclk,
1600 -- clk125 => clk125,
1601 -- DRPclk => DRPclk,
1602 -- reset => AMC_reset,
1603 -- daq_reset => lsc_reset,
1604 -- gtx_reset => lsc_GTXreset,
1605 -- rstCntr => rst_cntr,
1606 -- test => '0',
1607 -- DB_cmd => DB_cmd,
1608 -- Dis_pd => Dis_pd,
1609 -- enSFP => enSFP,
1610 -- SFP_ABS => SFP_ABS(1 downto 0),
1611 -- LSC_ID => LSC_ID,
1612 -- SFP_down => SFP_down,
1613 -- inc_ddr_pa => inc_ddr_pa,
1614 -- evt_data_rdy => evt_data_rdy,
1615 -- EventData_in => EventData,
1616 -- EventData_we => evt_data_we,
1617 -- EventData_re => evt_data_re,
1618 -- evt_buf_full => evt_buf_full,
1619 -- buf_rqst => EventBuf_rqst,
1620 -- WaitMonBuf => conf(14),
1621 -- MonBufOverWrite => conf(13),
1622 -- MonBuf_avl => mon_buf_avl,
1623 -- MonBuf_empty => MonBuf_empty,
1624 -- MonBufOvfl => MonBufOvfl,
1625 -- mon_evt_cnt => mon_evt_cnt,
1626 -- WrtMonBlkDone => WrtMonBlkDone,
1627 -- WrtMonEvtDone => WrtMonEvtDone,
1628 -- wport_rdy => wport_rdy,
1629 -- wport_FIFO_full => wport_FIFO_full,
1630 -- EventBufAddr_we => EventBufAddr_we,
1631 -- EventBufAddr => EventBufAddr,
1632 -- SFP0_RXN => SFP0_RXN,
1633 -- SFP0_RXP => SFP0_RXP,
1634 -- SFP1_RXN => SFP1_RXN,
1635 -- SFP1_RXP => SFP1_RXP,
1636 -- SFP0_TXN => SFP0_TXN,
1637 -- SFP0_TXP => SFP0_TXP,
1638 -- SFP1_TXN => SFP1_TXN,
1639 -- SFP1_TXP => SFP1_TXP,
1640 -- SFP_REFCLK_p => GbE_REFCLK,
1641 -- SFP_REFCLK_n => '0',
1642 -- ipb_clk => ipb_clk,
1643 -- ipb_write => ipb_master_out.ipb_write,
1644 -- ipb_strobe => ipb_master_out.ipb_strobe,
1645 -- ipb_addr => ipb_master_out.ipb_addr,
1646 -- ipb_wdata => ipb_master_out.ipb_wdata,
1647 -- ipb_rdata => SFP_data,
1648 -- ipb_ack => SFP_ack
1649 -- );
1650 i_DAQLSC_if: DAQLSCXG_3x_if PORT MAP(
1651  sysclk => sysclk,
1652  clk125 => clk125,
1653  DRPclk => DRPclk,
1654  reset => AMC_reset,
1655  daq_reset => lsc_reset,
1656  gtx_reset => lsc_GTXreset,
1657  rstCntr => rst_cntr,
1658  test => '0',
1659  DB_cmd => DB_cmd,
1660  Dis_pd => Dis_pd,
1661  enSFP => enSFP,
1662  SFP_ABS => SFP_ABS(2 downto 0),
1663  LSC_ID => LSC_ID,
1664  SFP_down => SFP_down,
1665  inc_ddr_pa => inc_ddr_pa,
1666  evt_data_rdy => evt_data_rdy ,
1667  EventData_in => EventData,
1668  EventData_we => evt_data_we,
1669  EventData_re => evt_data_re,
1670  evt_buf_full => evt_buf_full ,
1671  buf_rqst => EventBuf_rqst,
1672  WaitMonBuf => conf(14),
1673  MonBufOverWrite => conf(13),
1674  MonBuf_avl => mon_buf_avl,
1675  MonBuf_empty => MonBuf_empty ,
1676  MonBufOvfl => MonBufOvfl,
1677  mon_evt_cnt => mon_evt_cnt ,
1678  WrtMonBlkDone => WrtMonBlkDone ,
1679  WrtMonEvtDone => WrtMonEvtDone ,
1680  wport_rdy => wport_rdy,
1681  wport_FIFO_full => wport_FIFO_full ,
1682  EventBufAddr_we => EventBufAddr_we ,
1683  EventBufAddr => EventBufAddr ,
1684  SFP0_RXN => SFP0_RXN,
1685  SFP0_RXP => SFP0_RXP,
1686  SFP1_RXN => SFP1_RXN,
1687  SFP1_RXP => SFP1_RXP,
1688  SFP2_RXN => '1',
1689  SFP2_RXP => '0',
1690  SFP0_TXN => SFP0_TXN,
1691  SFP0_TXP => SFP0_TXP,
1692  SFP1_TXN => SFP1_TXN,
1693  SFP1_TXP => SFP1_TXP,
1694  SFP2_TXN => open,
1695  SFP2_TXP => open,
1696  SFP_REFCLK_P => GbE_REFCLK,
1697  SFP_REFCLK_N => '0',
1698  ipb_clk => ipb_clk,
1699  ipb_write => ipb_master_out.ipb_write ,
1700  ipb_strobe => ipb_master_out.ipb_strobe ,
1701  ipb_addr => ipb_master_out.ipb_addr ,
1702  ipb_wdata => ipb_master_out.ipb_wdata ,
1703  ipb_rdata => SFP_data,
1704  ipb_ack => SFP_ack
1705  );
1706 lsc_reset <= lsc_start or cmd(2) or cmd2_dl(1);
1707 --lsc_GTXreset <= wr_EnSFP or not sys_lock or cmd2_dl(0);
1708 lsc_GTXreset <= lsc_start or cmd2_dl(0);
1709 process(DRPclk, sys_lock)
1710 begin
1711  if(sys_lock = '0')then
1712  lsc_start <= '1';
1713  elsif(DRPclk'event and DRPclk = '1')then
1714  if(CLK_rdy = '1')then
1715  lsc_start <= '0';
1716  end if;
1717  end if;
1718 end process;
1719 i_sysmon_if: sysmon_if PORT MAP(
1720  DRPclk => ipb_clk,
1721  DB_cmd => DB_cmd,
1722  SN => SN,
1723  VAUXN_IN => VAUXN,
1724  VAUXP_IN => VAUXP,
1725  addr => ipb_master_out.ipb_addr(15 downto 0),
1726  data => sysmon_data ,
1727  device_temp => device_temp ,
1728  ALM => ALM,
1729  OT => OT
1730  );
1731 process(ipb_clk)
1732 begin
1733  if(ipb_clk'event and ipb_clk = '1')then
1734  newIPADDRSyncRegs <= newIPADDRSyncRegs(1 downto 0) & newIPADDR;
1735  rst_ipbus <= not newIPADDRSyncRegs(2) and newIPADDR;
1736  end if;
1737 end process;
1738 i_TTC_cntr: TTC_cntr PORT MAP(
1739  sysclk => sysclk,
1740  clk125 => clk125,
1741  ipb_clk => ipb_clk,
1742  reset => reset,
1743  rst_cntr => rst_cntr,
1744  DB_cmd => DB_cmd,
1745  inc_serr => inc_serr,
1746  inc_derr => inc_derr,
1747  inc_bcnterr => inc_bcnterr ,
1748  inc_l1ac => inc_l1ac,
1749  run => run,
1750  state => state,
1751  ttc_resync => ttc_resync,
1752  ipb_addr => ipb_master_out.ipb_addr (15 downto 0),
1753  ipb_rdata => TTC_cntr_data
1754  );
1755 i_DNA_PORT : DNA_PORT
1756  generic map (
1757  SIM_DNA_VALUE => X"00123456789abcd" -- Specifies a sample 57-bit DNA value for simulation
1758  )
1759  port map (
1760  DOUT => DNA_out, -- 1-bit output: DNA output data.
1761  CLK => ipb_clk, -- 1-bit input: Clock input.
1762  DIN => '0', -- 1-bit input: User data input pin.
1763  READ => load_DNA, -- 1-bit input: Active high load DNA, active low read input.
1764  SHIFT => shift_DNA(1) -- 1-bit input: Active high shift enable input.
1765  );
1766 process(ipb_clk)
1767 begin
1768  if(ipb_clk'event and ipb_clk = '1')then
1769  load_DNA <= not sys_lock;
1770  if(sys_lock = '0')then
1771  shift_DNA(0) <= '0';
1772  elsif(load_DNA = '1')then
1773  shift_DNA(0) <= '1';
1774  elsif(shift_DNA(2) = '1' and or_reduce(DNA_cntr(5 downto 1)) = '0')then
1775  shift_DNA(0) <= '0';
1776  end if;
1777  shift_DNA(2) <= shift_DNA(0);
1778  if(shift_DNA(2) = '1')then
1779  DNA_cntr <= DNA_cntr - 1;
1780  elsif(shift_DNA(0) = '1')then
1781  DNA_cntr <= "110111";
1782  end if;
1783  if(shift_DNA(2) = '1')then
1784  DNA <= DNA(55 downto 0) & DNA_OUT;
1785  end if;
1786  end if;
1787 end process;
1788 process(ipb_clk)
1789 begin
1790  if(ipb_clk'event and ipb_clk = '0')then
1791  shift_DNA(1) <= shift_DNA(0);
1792  end if;
1793 end process;
1794 end Behavioral;
1795 
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