AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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AMC13_T1_HCAL10G1.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 14:49:29 05/12/2010
6 -- Design Name:
7 -- Module Name: DTC_T2 - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 use work.ipbus.ALL;
26 use work.amc13_pack.all;
27 
28 -- Uncomment the following library declaration if using
29 -- arithmetic functions with Signed or Unsigned values
30 -- use IEEE.NUMERIC_STD.ALL;
31 
32 -- Uncomment the following library declaration if instantiating
33 -- any Xilinx primitives in this code.
34 library UNISIM;
35 use UNISIM.VComponents.all;
36 Library UNIMACRO;
37 use UNIMACRO.vcomponents.all;
38 
39 entity AMC13_T1_HCAL is
40  Port (
41  VAUXP : in STD_LOGIC_VECTOR(12 downto 0);
42  VAUXN : in STD_LOGIC_VECTOR(12 downto 0);
43 -- I2C interface
44  CLK_SCL : out STD_LOGIC;
45  CLK_SDA : inout STD_LOGIC;
46  SFP_SCL : out STD_LOGIC_VECTOR(3 downto 0);
47  SFP_SDA : inout STD_LOGIC_VECTOR(3 downto 0);
48 -- SFP slow control
49  SFP_LOS : in STD_LOGIC_VECTOR(2 downto 0);
50  SFP_ABS : in STD_LOGIC_VECTOR(3 downto 0);
51  TxFault : in STD_LOGIC_VECTOR(3 downto 0);
52  TxDisable : out STD_LOGIC_VECTOR(3 downto 0);
53 -- RATE : out STD_LOGIC_VECTOR(3 downto 0);
54 -- CDR signals
55  DIV4 : out STD_LOGIC;
56  DIV_nRST : out STD_LOGIC;
57  CDRclk_p : in STD_LOGIC;
58  CDRclk_n : in STD_LOGIC;
59  CDRdata_p : in STD_LOGIC;
60  CDRdata_n : in STD_LOGIC;
61  TTCdata_p : out STD_LOGIC;
62  TTCdata_n : out STD_LOGIC;
63  TTCclk_p : in STD_LOGIC;
64  TTCclk_n : in STD_LOGIC;
65  TTC_LOS : in STD_LOGIC;
66  TTC_LOL : in STD_LOGIC;
67  TTS_out_p : out STD_LOGIC;
68  TTS_out_n : out STD_LOGIC;
69 -- SPI interface
70  SPI_SCK : in STD_LOGIC;
71  SPI_CS_b : in STD_LOGIC;
72  SPI_MOSI : in STD_LOGIC;
73  SPI_MISO : out STD_LOGIC;
74 -- DDR3 pins
75  sys_clk_p : in STD_LOGIC;
76  sys_clk_n : in STD_LOGIC;
77  ddr3_dq : inout STD_LOGIC_VECTOR(31 downto 0);
78  ddr3_addr : out STD_LOGIC_VECTOR(13 downto 0);
79  ddr3_ba : out STD_LOGIC_VECTOR (2 downto 0);
80  ddr3_dm : out STD_LOGIC_VECTOR (3 downto 0);
81  ddr3_dqs_p : inout STD_LOGIC_VECTOR(3 downto 0);
82  ddr3_dqs_n : inout STD_LOGIC_VECTOR(3 downto 0);
83  ddr3_ras_n : out STD_LOGIC;
84  ddr3_cas_n : out STD_LOGIC;
85  ddr3_we_n : out STD_LOGIC;
86  ddr3_reset_n : out STD_LOGIC;
87  ddr3_cke : out STD_LOGIC_vector(0 to 0);
88  ddr3_odt : out STD_LOGIC_vector(0 to 0);
89  ddr3_ck_p : out STD_LOGIC_vector(0 to 0);
90  ddr3_ck_n : out STD_LOGIC_vector(0 to 0);
91  SFP0_RXN : in STD_LOGIC;
92  SFP0_RXP : in STD_LOGIC;
93 -- SFP1_RXN : in STD_LOGIC;
94 -- SFP1_RXP : in STD_LOGIC;
95  SFP2_RXN : in STD_LOGIC;
96  SFP2_RXP : in STD_LOGIC;
97  SFP0_TXN : out STD_LOGIC;
98  SFP0_TXP : out STD_LOGIC;
99 -- SFP1_TXN : out STD_LOGIC;
100 -- SFP1_TXP : out STD_LOGIC;
101  SFP2_TXN : out STD_LOGIC;
102  SFP2_TXP : out STD_LOGIC;
103  CDR_REFCLK_N : in STD_LOGIC;
104  CDR_REFCLK_P : in STD_LOGIC;
105  SFP_REFCLK_N : in STD_LOGIC;
106  SFP_REFCLK_P : in STD_LOGIC;
107  AMC_REFCLK_N : in STD_LOGIC;
108  AMC_REFCLK_P : in STD_LOGIC;
109  AMC_RXN : in STD_LOGIC_VECTOR(12 downto 1);
110  AMC_RXP : in STD_LOGIC_VECTOR(12 downto 1);
111  AMC_TXN : out STD_LOGIC_VECTOR(12 downto 1);
112  AMC_TXP : out STD_LOGIC_VECTOR(12 downto 1);
113 -- signal to/from DTC_T2
114  S6LINK_RXN : in STD_LOGIC;
115  S6LINK_RXP : in STD_LOGIC;
116  S6LINK_TXN : out STD_LOGIC;
117  S6LINK_TXP : out STD_LOGIC;
118  S2V_p : in STD_LOGIC;
119  S2V_n : in STD_LOGIC;
120 -- V2S_p : out STD_LOGIC;
121 -- V2S_n : out STD_LOGIC;
122  GbE_REFCLK_N : in STD_LOGIC;
123  GbE_REFCLK_P : in STD_LOGIC);
124 end AMC13_T1_HCAL;
125 
126 architecture Behavioral of AMC13_T1_HCAL is
127 COMPONENT HCAL_trig
128 PORT(
129  TTC_clk : IN std_logic;
130  DRPCLK : IN std_logic;
131  reset : IN std_logic;
132  BC0 : IN std_logic;
133  en_HCAL_trig : IN std_logic;
134  Trigdata : IN array12x8;
135  triggerOut : OUT std_logic;
136  ipb_clk : IN std_logic;
137  ipb_write : IN std_logic;
138  ipb_strobe : IN std_logic;
139  ipb_addr : IN std_logic_vector(31 downto 0);
140  ipb_wdata : IN std_logic_vector(31 downto 0);
141  GTX_REFCLKp : IN std_logic;
142  GTX_REFCLKn : IN std_logic;
143  GTX_RXp : IN std_logic;
144  GTX_RXn : IN std_logic;
145  ipb_rdata : OUT std_logic_vector(31 downto 0);
146  GTX_TXp : OUT std_logic;
147  GTX_TXn : OUT std_logic
148  );
149 END COMPONENT;
150 COMPONENT TTS_if
151  PORT(
152  sysclk : IN std_logic;
153  TTS_clk : IN std_logic;
154  reset : IN std_logic;
155  local_TTC : in STD_LOGIC;
156  TTS : IN std_logic_vector(3 downto 0);
157  TTS_out_p : OUT std_logic;
158  TTS_out_n : OUT std_logic
159  );
160 END COMPONENT;
161 COMPONENT ttc_if
162  PORT(
163  clk : IN std_logic;
164  refclk : IN std_logic;
165  reset : IN std_logic;
166  run : IN std_logic;
167  IsG2 : IN std_logic;
168  DB_cmd_in : IN std_logic;
169  DB_cmd_Out : OUT std_logic;
170  sys_lock : IN std_logic;
171  local_TTC : IN std_logic;
172  local_TTCcmd : IN std_logic;
173  single_TTCcmd : in STD_LOGIC;
174  CDRclk_p : IN std_logic;
175  CDRclk_n : IN std_logic;
176  CDRdata_p : IN std_logic;
177  CDRdata_n : IN std_logic;
178  TTC_LOS : IN std_logic;
179  TTC_LOL : IN std_logic;
180  BCN_off : IN std_logic_vector(12 downto 0);
181  OC_off : IN std_logic_vector(3 downto 0);
182  en_cal_win : IN std_logic;
183  cal_win_high : IN std_logic_vector(11 downto 0);
184  cal_win_low : IN std_logic_vector(11 downto 0);
185  en_localL1A : IN std_logic;
186  LocalL1A_cfg : IN std_logic_vector(31 downto 0);
187  localL1A_s : IN std_logic;
188  localL1A_r : IN std_logic;
189  T3_trigger : IN std_logic;
190  HCAL_trigger : IN std_logic;
191  EvnRSt_l : IN std_logic;
192  OcnRSt_l : IN std_logic;
193  ovfl_warning : IN std_logic;
194  ipb_clk : IN std_logic;
195  ipb_write : IN std_logic;
196  ipb_strobe : IN std_logic;
197  ipb_addr : IN std_logic_vector(31 downto 0);
198  ipb_wdata : IN std_logic_vector(31 downto 0);
199  en_brcst : IN std_logic;
200  state : IN std_logic_vector(3 downto 0);
201  evn_fifo_full : IN std_logic;
202  BC0 : OUT std_logic;
203  TTC_strobe : OUT std_logic;
204  TTS_clk : OUT std_logic;
205  DIV4 : OUT std_logic;
206  DIV_nRST : OUT std_logic;
207  CDRclk_out : OUT std_logic;
208  TTCdata_p : OUT std_logic;
209  TTCdata_n : OUT std_logic;
210  CalType : OUT std_logic_vector(3 downto 0);
211  TTC_Brcst : OUT std_logic_vector(3 downto 0);
212  localL1A_periodic : OUT std_logic;
213  ipb_rdata : OUT std_logic_vector(31 downto 0);
214  ttc_start : OUT std_logic;
215  ttc_stop : OUT std_logic;
216  ttc_soft_reset : OUT std_logic;
217  ttc_ready : OUT std_logic;
218  ttc_serr : OUT std_logic;
219  ttc_derr : OUT std_logic;
220  ttc_bcnt_err : OUT std_logic;
221  rate_OFW : OUT std_logic;
222  sync_lost : OUT std_logic;
223  inc_oc : OUT std_logic;
224  inc_l1ac : OUT std_logic;
225  inc_bcnterr : OUT std_logic;
226  inc_serr : OUT std_logic;
227  inc_derr : OUT std_logic;
228  ttc_evcnt_reset : OUT std_logic;
229  event_number_avl : OUT std_logic;
230  event_number : OUT std_logic_vector(59 downto 0)
231  );
232 END COMPONENT;
233 COMPONENT AMC_if
234  Generic (useTCPIP : boolean := false; AMC_useTRIG : boolean := true; simulation : boolean := false);
235  PORT(
236  sysclk : IN std_logic;
237  ipb_clk : IN std_logic;
238  clk125 : IN std_logic;
239  DRPclk : IN std_logic;
240  GTXreset : IN std_logic;
241  reset : IN std_logic;
242  DB_cmd : IN std_logic;
243  resetCntr : IN std_logic;
244  ReSync : IN std_logic;
245  AllEventBuilt : OUT std_logic;
246  run : IN std_logic;
247  en_inject_err : in STD_LOGIC;
248  Dis_pd : in STD_LOGIC;
249  enSFP : IN std_logic_vector(3 downto 0);
250  en_localL1A : IN std_logic;
251  test : IN std_logic;
252  NoReSyncFake : IN std_logic;
253  WaitMonBuf : IN std_logic;
254  fake_length : IN std_logic_vector(19 downto 0);
255  T1_version : IN std_logic_vector(7 downto 0);
256  Source_ID : IN array3x12;
257  AMC_en : IN std_logic_vector(11 downto 0);
258  TTS_disable : IN std_logic_vector(11 downto 0);
259  AMC_REFCLK_P : IN std_logic;
260  AMC_REFCLK_N : IN std_logic;
261  AMC_RXN : IN std_logic_vector(12 downto 1);
262  AMC_RXP : IN std_logic_vector(12 downto 1);
263  evt_data_re : IN std_logic_vector(2 downto 0);
264  evt_buf_full : IN std_logic_vector(2 downto 0);
265  ddr_pa : IN std_logic_vector(9 downto 0);
266  MonBuf_empty : IN std_logic;
267  mon_buf_avl : IN std_logic;
268  TCPbuf_avl : IN std_logic;
269  ipb_write : IN std_logic;
270  ipb_strobe : IN std_logic;
271  ipb_addr : IN std_logic_vector(31 downto 0);
272  ipb_wdata : IN std_logic_vector(31 downto 0);
273  TTC_clk : IN std_logic;
274  TTC_LOS : IN std_logic;
275  BC0 : IN std_logic;
276  ttc_evcnt_reset : IN std_logic;
277  event_number_avl : IN std_logic;
278  event_number : IN std_logic_vector(59 downto 0);
279  AMC_Ready : OUT std_logic_vector(11 downto 0);
280  TTC_lock : OUT std_logic;
281  BC0_lock : OUT std_logic_vector(11 downto 0);
282  AMC_TXN : OUT std_logic_vector(12 downto 1);
283  AMC_TXP : OUT std_logic_vector(12 downto 1);
284  AMC_status : OUT std_logic_vector(31 downto 0);
285  evt_data : OUT array3x67;
286  evt_data_we : OUT std_logic_vector(2 downto 0);
287  evt_data_rdy : OUT std_logic_vector(2 downto 0);
288  mon_evt_wc : OUT std_logic_vector(47 downto 0);
289  mon_ctrl : OUT std_logic_vector(31 downto 0);
290  buf_rqst : OUT std_logic_vector(3 downto 0);
291  ipb_rdata : OUT std_logic_vector(31 downto 0);
292  ipb_ack : OUT std_logic;
293  evn_buf_full : OUT std_logic;
294  ovfl_warning : OUT std_logic;
295  TrigData : OUT array12x8;
296  TTS_coded : OUT std_logic_vector(4 downto 0)
297  );
298 END COMPONENT;
299 COMPONENT I2C
300  PORT(
301  clk : IN std_logic;
302  ipb_clk : IN std_logic;
303  reset : IN std_logic;
304  addr : IN std_logic_vector(31 downto 0);
305  SFP_ABS : IN std_logic_vector(3 downto 0);
306  SFP_LOS : IN std_logic_vector(2 downto 0);
307  CLK_SDA : INOUT std_logic;
308  SFP_SDA : INOUT std_logic_vector(3 downto 0);
309  rdata : OUT std_logic_vector(31 downto 0);
310  CLK_rdy : OUT std_logic;
311  CLK_SCL : OUT std_logic;
312  SFP_SCL : OUT std_logic_vector(3 downto 0)
313  );
314 END COMPONENT;
315 COMPONENT SPI_if
316  PORT(
317  SCK : IN std_logic;
318  CSn : IN std_logic;
319  MOSI : IN std_logic;
320  SN : IN std_logic_vector(8 downto 0);
321  OT : IN std_logic;
322  IsT1 : IN std_logic;
323  SPI_rdata : IN std_logic_vector(7 downto 0);
324  MISO : OUT std_logic;
325  SPI_we : OUT std_logic;
326  en_RARP : out STD_LOGIC;
327  newIPADDR : OUT std_logic;
328  IPADDR : OUT std_logic_vector(31 downto 0);
329  SPI_wdata : OUT std_logic_vector(7 downto 0);
330  SPI_addr : OUT std_logic_vector(7 downto 0)
331  );
332 END COMPONENT;
333 COMPONENT ddr_if
334  port(
335  clk_ref : in std_logic;
336  mem_clk_p : in std_logic;
337  mem_clk_n : in std_logic;
338  mem_rst : in std_logic;
339  sysclk : in std_logic;
340  TCPclk : in std_logic;
341  reset : in std_logic;
342  resetsys : in std_logic;
343  run : in std_logic;
344  mem_test : in std_logic_VECTOR(1 downto 0);
345  EventData : in array3X67;
346  EventData_we : in std_logic_VECTOR(2 downto 0);
347  wport_rdy : out std_logic_VECTOR(2 downto 0);
348  WrtMonBlkDone : OUT std_logic_VECTOR(2 downto 0);
349  WrtMonEvtDone : OUT std_logic_VECTOR(2 downto 0);
350  KiloByte_toggle : OUT std_logic_VECTOR(2 downto 0);
351  EoB_toggle : OUT std_logic_VECTOR(2 downto 0);
352  EventBufAddr : in array3x14;
353  EventBufAddr_we : in std_logic_VECTOR(2 downto 0);
354  EventFIFOfull : out std_logic_VECTOR(2 downto 0);
355  TCP_din : in std_logic_vector(31 downto 0);
356  TCP_channel : in STD_LOGIC_VECTOR (1 downto 0);
357  TCP_we : in STD_LOGIC;
358  TCP_wcount : out STD_LOGIC_VECTOR (2 downto 0);
359  TCP_dout : out STD_LOGIC_VECTOR(31 downto 0); -- TCP data are written in unit of 32-bit words
360  TCP_raddr : in std_logic_vector(28 downto 0); -- 28-26 encoded request source 25-0 address in 64 bit word
361  TCP_length : in std_logic_vector(10 downto 0); -- in 64 bit word, actual length - 1
362  TCP_dout_valid : out STD_LOGIC;
363  TCP_rrqst : in STD_LOGIC;
364  TCP_rack : out STD_LOGIC;
365  TCP_lastword : out STD_LOGIC;
366 -- ipbus signals
367  ipb_clk : in STD_LOGIC;
368  ipb_write : in STD_LOGIC;
369  ipb_strobe : in STD_LOGIC;
370  page_addr : in STD_LOGIC_VECTOR(9 downto 0);
371  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
372  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
373  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
374  ipb_ack : out STD_LOGIC;
375  mem_stat : out STD_LOGIC_VECTOR (63 downto 0);
376  device_temp : in STD_LOGIC_VECTOR(11 downto 0);
377 -- ddr3 memory pins
378  ddr3_dq : inout STD_LOGIC_VECTOR (31 downto 0);
379  ddr3_dm : out STD_LOGIC_VECTOR (3 downto 0);
380  ddr3_addr : out STD_LOGIC_VECTOR (13 downto 0);
381  ddr3_ba : out STD_LOGIC_VECTOR (2 downto 0);
382  ddr3_dqs_p : inout STD_LOGIC_VECTOR (3 downto 0);
383  ddr3_dqs_n : inout STD_LOGIC_VECTOR (3 downto 0);
384  ddr3_ras_n : out STD_LOGIC;
385  ddr3_cas_n : out STD_LOGIC;
386  ddr3_we_n : out STD_LOGIC;
387  ddr3_reset_n : out STD_LOGIC;
388  ddr3_cke : out STD_LOGIC_vector(0 to 0);
389  ddr3_odt : out STD_LOGIC_vector(0 to 0);
390  ddr3_ck_p : out STD_LOGIC_vector(0 to 0);
391  ddr3_ck_n : out STD_LOGIC_vector(0 to 0)
392  );
393 END COMPONENT;
394 COMPONENT ipbus_if
395  generic(RXPOLARITY : std_logic := '0'; TXPOLARITY : std_logic := '0');
396  port(
397  ipb_clk : IN std_logic;
398  UsRclk : IN std_logic;
399  DRPclk : IN std_logic;
400  got_SN : out std_logic;
401  reset : IN std_logic;
402  GTX_RESET : IN std_logic;
403  GbE_REFCLK : in std_logic;
404  S6LINK_RXN : in std_logic;
405  S6LINK_RXP : in std_logic;
406  S6LINK_TXN : out std_logic;
407  S6LINK_TXP : out std_logic;
408  wr_amc_en : in std_logic;
409  amc_en : in STD_LOGIC_VECTOR(11 downto 0);
410  en_RARP : in std_logic;
411  IPADDR : in STD_LOGIC_VECTOR(31 downto 0);
412  MACADDR : in STD_LOGIC_VECTOR(47 downto 0);
413  ipb_out : out ipb_wbus;
414  ipb_in : in ipb_rbus;
415  SN : out STD_LOGIC_VECTOR(8 downto 0);
416  debug_in : IN std_logic_vector(31 downto 0);
417  debug_out : OUT std_logic_vector(127 downto 0)
418  );
419 end COMPONENT;
420 COMPONENT sysmon_if
421  PORT(
422  DRPclk : IN std_logic;
423  DB_cmd : IN std_logic;
424  SN : IN std_logic_vector(8 downto 0);
425  VAUXN_IN : IN std_logic_vector(12 downto 0);
426  VAUXP_IN : IN std_logic_vector(12 downto 0);
427  addr : IN std_logic_vector(15 downto 0);
428  data : OUT std_logic_vector(31 downto 0);
429  device_temp : OUT std_logic_vector(11 downto 0);
430  ALM : OUT std_logic_vector(7 downto 0);
431  OT : OUT std_logic
432  );
433 END COMPONENT;
434 COMPONENT DAQLSCXG_3x_if
435  generic(N_SFP : integer := 1);
436  PORT(
437  sysclk : IN std_logic;
438  clk125 : IN std_logic;
439  DRPclk : IN std_logic;
440  reset : IN std_logic;
441  daq_reset : IN std_logic;
442  gtx_reset : IN std_logic;
443  rstCntr : IN std_logic;
444  Dis_pd : in STD_LOGIC;
445  test : IN std_logic;
446  DB_cmd : IN std_logic;
447  enSFP : IN std_logic_vector(3 downto 0);
448  SFP_ABS : IN std_logic_vector(2 downto 0);
449  LSC_ID : IN std_logic_vector(15 downto 0);
450  inc_ddr_pa : IN std_logic;
451  evt_data_rdy : IN std_logic_vector(2 downto 0);
452  EventData_in : IN array3x67;
453  EventData_we : IN std_logic_vector(2 downto 0);
454  buf_rqst : IN std_logic_vector(3 downto 0);
455  WaitMonBuf : IN std_logic;
456  WrtMonBlkDone : IN std_logic_vector(2 downto 0);
457  WrtMonEvtDone : IN std_logic_vector(2 downto 0);
458  wport_rdy : IN std_logic_vector(2 downto 0);
459  wport_FIFO_full : IN std_logic_vector(2 downto 0);
460  SFP0_RXN : IN std_logic;
461  SFP0_RXP : IN std_logic;
462  SFP1_RXN : IN std_logic;
463  SFP1_RXP : IN std_logic;
464  SFP2_RXN : IN std_logic;
465  SFP2_RXP : IN std_logic;
466  SFP_REFCLK_P : in std_logic;
467  SFP_REFCLK_N : in std_logic;
468  ipb_clk : IN std_logic;
469  ipb_write : IN std_logic;
470  ipb_strobe : IN std_logic;
471  ipb_addr : IN std_logic_vector(31 downto 0);
472  ipb_wdata : IN std_logic_vector(31 downto 0);
473  SFP_down : OUT std_logic_vector(2 downto 0);
474  EventData_re : OUT std_logic_vector(2 downto 0);
475  evt_buf_full : OUT std_logic_vector(2 downto 0);
476  MonBufOverWrite : IN std_logic;
477  MonBuf_avl : OUT std_logic;
478  MonBuf_empty : OUT std_logic;
479  MonBufOvfl : OUT std_logic;
480  mon_evt_cnt : OUT std_logic_vector(31 downto 0);
481  EventBufAddr_we : OUT std_logic_vector(2 downto 0);
482  EventBufAddr : OUT array3x14;
483  SFP0_TXN : OUT std_logic;
484  SFP0_TXP : OUT std_logic;
485  SFP1_TXN : OUT std_logic;
486  SFP1_TXP : OUT std_logic;
487  SFP2_TXN : OUT std_logic;
488  SFP2_TXP : OUT std_logic;
489  ipb_rdata : OUT std_logic_vector(31 downto 0);
490  ipb_ack : OUT std_logic
491  );
492 END COMPONENT;
493 COMPONENT TTC_cntr
494  PORT(
495  sysclk : IN std_logic;
496  clk125 : IN std_logic;
497  ipb_clk : IN std_logic;
498  reset : IN std_logic;
499  rst_cntr : IN std_logic;
500  DB_cmd : IN std_logic;
501  inc_serr : IN std_logic;
502  inc_derr : IN std_logic;
503  inc_bcnterr : IN std_logic;
504  inc_l1ac : IN std_logic;
505  run : IN std_logic;
506  state : IN std_logic_vector(3 downto 0);
507  ttc_resync : IN std_logic;
508  ipb_addr : IN std_logic_vector(15 downto 0);
509  ipb_rdata : OUT std_logic_vector(31 downto 0)
510  );
511 END COMPONENT;
512 constant ipbus_ver_addr : std_logic_vector(15 downto 0) := x"0000";
513 constant ipbus_sfp_addr: std_logic_vector(15 downto 0) := x"0002";
514 constant CDRclk_pol : std_logic := '0';
515 constant CDRdata_pol : std_logic := '1';
516 constant TTCclk_pol : std_logic := '1';
517 constant TTCdata_pol : std_logic := '1';
518 constant Coarse_Delay: std_logic_vector(3 downto 0) := x"0";
519 signal rst_ipbus : std_logic := '0';
520 signal LDC_UsrClk : std_logic := '0';
521 signal wr_AMC_en : std_logic := '0';
522 signal wr_EnSFP : std_logic := '0';
523 signal fake_length : std_logic_vector(19 downto 0) := x"00400";
524 signal AMC_en : std_logic_vector(11 downto 0) := (others =>'0');
525 signal TTS_disable : std_logic_vector(11 downto 0) := (others =>'0');
526 signal AMC_Ready : std_logic_vector(11 downto 0) := (others =>'0');
527 signal TTC_lock : std_logic := '0';
528 signal BC0_lock : std_logic_vector(11 downto 0) := (others =>'0');
529 signal AMC_status : std_logic_vector(31 downto 0) := (others =>'0');
530 signal AMC_DATA : std_logic_vector(31 downto 0) := (others =>'0');
531 signal AMC_ack : std_logic := '0';
532 signal L1Aovfl_warning : std_logic := '0';
533 signal HCAL_trigger : std_logic := '0';
534 signal TRIGDATA : array12x8 := (others => (others => '0'));
535 signal TTS_coded : std_logic_vector(4 downto 0) := (others =>'0');
536 signal pattern : std_logic_vector(3 downto 0) := (others =>'0');
537 --signal Trig_mask : std_logic_vector(7 downto 0) := (others =>'0');
538 signal SPI_SCK_buf : std_logic := '0';
539 signal CLK_rdy : std_logic := '0';
540 signal I2C_data : std_logic_vector(31 downto 0) := (others =>'0');
541 signal TTCclk_in : std_logic := '0';
542 signal TTC_Clk : std_logic := '0';
543 signal TTC_strobe : std_logic := '0';
544 signal BcntErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
545 signal SinErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
546 signal DbErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
547 signal L1_reg : std_logic_vector(15 downto 0) := (others =>'0');
548 signal Bcnt_reg : std_logic_vector(11 downto 0) := (others =>'0');
549 signal OC_reg : std_logic_vector(31 downto 0) := (others =>'0');
550 signal DB_cmd : std_logic := '0';
551 signal V2S : std_logic := '0';
552 signal S2V : std_logic := '0';
553 signal S2V_cntr : std_logic_vector(5 downto 0) := (others => '0');
554 signal S2V_sr : std_logic_vector(3 downto 0) := (others => '0');
555 signal ddr_rdata : std_logic_vector(7 downto 0) := (others =>'0');
556 signal ipb_clk_dcm : std_logic := '0';
557 signal ipb_clk : std_logic := '0';
558 signal clk125_dcm : std_logic := '0';
559 signal clk125 : std_logic := '0';
560 signal DRPclk_dcm : std_logic := '0';
561 signal DRPclk : std_logic := '0';
562 signal sysclk_dcm : std_logic := '0';
563 signal sysclk : std_logic := '0';
564 signal clkfb : std_logic := '0';
565 signal refclk_dcm : std_logic := '0';
566 signal refclk : std_logic := '0';
567 signal mem_clk_dcm : std_logic := '0';
568 signal mem_clk : std_logic := '0';
569 signal sysclk_inp : std_logic := '0';
570 signal sysclk_in : std_logic := '0';
571 --signal clk125 : std_logic := '0';
572 signal sys_lock : std_logic := '0';
573 signal sys_lock_n : std_logic := '0';
574 signal ldc_reset : std_logic := '0';
575 signal ldc_GTXreset : std_logic := '0';
576 signal lsc_start : std_logic := '0';
577 signal lsc_reset : std_logic := '0';
578 signal lsc_GTXreset : std_logic := '0';
579 signal amc_reset : std_logic := '0';
580 signal amc_GTXreset : std_logic := '0';
581 signal conf7_q : std_logic := '0';
582 signal conf7_fall : std_logic := '0';
583 signal run : std_logic := '0';
584 signal LSC_LinkDown : std_logic := '0';
585 signal mem_rst : std_logic := '0';
586 signal mem_test : std_logic_vector(1 downto 0) := (others =>'0');
587 signal mem_stat : std_logic_vector(63 downto 0) := (others =>'0');
588 signal mem_ack : std_logic := '0';
589 signal mem_data : std_logic_vector(31 downto 0) := (others =>'0');
590 signal EventData : array3X67 := (others => (others => '0'));
591 signal wport_rdy : std_logic_vector(2 downto 0) := (others =>'0');
592 signal EventBufAddr : array3x14 := (others => (others => '0'));
593 signal EventBufAddr_we : std_logic_vector(2 downto 0) := (others =>'0');
594 signal evt_buf_full : std_logic_vector(2 downto 0) := (others =>'0');
595 signal wport_FIFO_full : std_logic_vector(2 downto 0) := (others =>'0');
596 --signal TCP_din : std_logic_vector(31 downto 0) := (others =>'0');
597 --signal TCP_channel : std_logic_vector(1 downto 0) := (others =>'0');
598 --signal TCP_wrqst : std_logic := '0';
599 --signal TCP_re : std_logic := '0';
600 --signal TCP_dout : std_logic_vector(31 downto 0) := (others =>'0');
601 --signal TCP_raddr : std_logic_vector(23 downto 0) := (others =>'0');
602 --signal TCP_length : std_logic_vector(11 downto 0) := (others =>'0');
603 --signal TCP_dout_valid : std_logic := '0';
604 --signal TCP_rrqst : std_logic := '0';
605 --signal TCP_rack : std_logic := '0';
606 --signal TCP_lastword : std_logic := '0';
607 signal MonBufOvfl : std_logic := '0';
608 signal MonBuf_empty : std_logic := '0';
609 --signal inc_mon_cntr : std_logic := '0';
610 signal mon_evt_wc : std_logic_vector(47 downto 0) := (others =>'0');
611 signal mon_evt_cnt : std_logic_vector(31 downto 0) := (others =>'0');
612 signal mon_ctrl : std_logic_vector(31 downto 0) := (others =>'0');
613 --signal TCPbuf_avl : std_logic := '0';
614 signal mon_buf_avl : std_logic := '0';
615 signal EventBufAddrAvl : std_logic := '0';
616 signal EventBufAddrRe : std_logic := '0';
617 signal mon_wp : std_logic_vector(31 downto 0) := (others =>'0');
618 --signal TCP_releaseAck : std_logic_vector(2 downto 0) := (others =>'0');
619 --signal TCP_releaseRqst : std_logic_vector(2 downto 0) := (others =>'0');
620 --signal TCP_releaseAddr : array3X13 := (others => (others => '0'));
621 signal EventBuf_rqst : std_logic_vector(3 downto 0) := (others =>'0');
622 signal rst_cntr : std_logic := '0';
623 signal rst_ddr_pa : std_logic := '0';
624 signal inc_ddr_pa : std_logic := '0';
625 signal Source_ID : array3X12 := (others => (others => '0'));
626 signal ddr_pa : std_logic_vector(9 downto 0) := (others =>'0');
627 signal CDRclk : std_logic := '0';
628 signal TTS_clk : std_logic := '0';
629 signal chk_lock : std_logic := '0';
630 signal chk_lock_q : std_logic := '0';
631 signal BC0 : std_logic := '0';
632 signal BC0_dl : std_logic := '0';
633 signal BC0_locked : std_logic_vector(1 downto 0) := (others =>'0');
634 signal BC0_cntr : std_logic_vector(4 downto 0) := (others =>'0');
635 signal T3_trigger : std_logic := '0';
636 signal inc_BX_offset : std_logic := '0';
637 signal en_HCAL_trig : std_logic := '0';
638 signal ec_BX_offset : std_logic := '0';
639 signal add_two : std_logic_vector(1 downto 0) := (others =>'0');
640 signal BX_offset : std_logic_vector(11 downto 0) := (others =>'0');
641 signal BX_offset2SC : std_logic_vector(11 downto 0) := (others =>'0');
642 signal bcnt : std_logic_vector(11 downto 0) := x"000";
643 signal LocalL1A_cfg : std_logic_vector(31 downto 0) := (others =>'0');
644 signal BCN_off : std_logic_vector(12 downto 0) := (others =>'0');
645 signal OC_off : std_logic_vector(3 downto 0) := (others =>'0');
646 signal en_cal_win : std_logic := '0';
647 signal CalibCtrl : std_logic_vector(31 downto 0) := x"0d800d80";
648 signal cal_win_high : std_logic_vector(11 downto 0) := (others =>'0');
649 signal cal_win_low : std_logic_vector(11 downto 0) := (others =>'0');
650 signal CalType : std_logic_vector(3 downto 0) := (others =>'0');
651 signal TTC_Brcst : std_logic_vector(3 downto 0) := (others =>'0');
652 signal local_TTCcmd : std_logic := '0';
653 signal en_brcst : std_logic := '0';
654 signal ttc_start : std_logic := '0';
655 signal ttc_stop : std_logic := '0';
656 signal ttc_soft_reset : std_logic := '0';
657 signal ttc_soft_resetp : std_logic := '0';
658 signal ttc_ready : std_logic := '0';
659 signal ttc_serr : std_logic := '0';
660 signal ttc_derr : std_logic := '0';
661 signal ttc_bcnt_err : std_logic := '0';
662 signal ttc_evcnt_reset : std_logic := '0';
663 signal inc_rate_ofw : std_logic := '0';
664 signal rate_ofw : std_logic := '0';
665 signal rate_ofwp : std_logic := '0';
666 signal rate_ofw_q : std_logic := '0';
667 signal sync_lost : std_logic := '0';
668 signal oc_cntr : std_logic_vector(3 downto 0) := (others =>'0');
669 signal ttc_resync : std_logic := '0';
670 signal AllEventBuilt : std_logic := '0';
671 signal dcc_quiet : std_logic := '0';
672 signal inc_oc : std_logic := '0';
673 signal inc_L1ac : std_logic := '0';
674 signal inc_bcnterr : std_logic := '0';
675 signal inc_serr : std_logic := '0';
676 signal inc_derr : std_logic := '0';
677 signal evn_fifo_full : std_logic := '0';
678 signal event_number_avl : std_logic := '0';
679 signal state : std_logic_vector(3 downto 0) := (others =>'0');
680 signal TTS_wait : std_logic_vector(20 downto 0) := (others =>'0');
681 signal event_number : std_logic_vector(59 downto 0) := (others =>'0');
682 signal status_l : std_logic_vector(22 downto 0) := (others =>'0');
683 signal SFP_down_l : std_logic_vector(2 downto 0) := (others =>'0');
684 signal SFP_status_l : std_logic_vector(11 downto 0) := (others =>'0');
685 signal AMC_status_l : std_logic_vector(31 downto 0) := (others =>'0');
686 signal TTC_cntr_data : std_logic_vector(31 downto 0) := (others => '0');
687 signal got_SN : std_logic := '0';
688 signal ipb_strobe_q : std_logic := '0';
689 signal SFP_clk : std_logic := '0';
690 signal AMC_clk : std_logic := '0';
691 signal AMC_clk_in : std_logic := '0';
692 signal SV_Cntr : std_logic_vector(7 downto 0) := (others => '0');
693 signal sysclk_div : std_logic_vector(7 downto 0) := (others => '0');
694 signal SFP_UsrClk : std_logic := '0';
695 signal SFP_TxOutClk : std_logic := '0';
696 signal I2C_debug_out : std_logic_vector(15 downto 0) := (others =>'0');
697 signal SFPOSC_rdy : std_logic := '0';
698 signal reset : std_logic := '0';
699 signal DAQ_reset : std_logic := '0';
700 signal AMCOSC_rdy : std_logic := '0';
701 --signal cs_clk_in : std_logic := '0';
702 --signal cs_clk : std_logic := '0';
703 signal TTC_debug : std_logic_vector(63 downto 0) := (others =>'0');
704 signal TxDisable_i : std_logic_vector(3 downto 0) := (others => '0');
705 signal DAQfifo_re : std_logic := '0';
706 signal DAQfifoAlmostEmpty : std_logic := '0';
707 signal DAQfifoEmpty : std_logic := '0';
708 signal DAQfifo_do : std_logic_vector(63 downto 0) := (others =>'0');
709 signal DAQ_debug_in : std_logic_vector(63 downto 0) := (others =>'0');
710 signal LDC_debug_out : std_logic_vector(63 downto 0) := (others =>'0');
711 signal LSC_debug_out : std_logic_vector(63 downto 0) := (others =>'0');
712 signal ddr_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
713 signal ddr_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
714 signal GbE_REFCLK : std_logic := '0';
715 signal S6Link_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
716 signal S6Link_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
717 signal GbE_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
718 signal GbE_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
719 signal AMC_debug_in : std_logic_vector(255 downto 0) := (others =>'0');
720 signal AMC_debug_out : std_logic_vector(255 downto 0) := (others =>'0');
721 signal SFP0_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
722 signal SFP0_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
723 signal SFP1_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
724 signal SFP1_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
725 signal ipb_master_out : ipb_wbus;
726 signal ipb_master_in : ipb_rbus;
727 signal SN : std_logic_vector(8 downto 0) := (others =>'0');
728 signal MACADDR : std_logic_vector(47 downto 0) := (others =>'0');
729 signal ipaddr : std_logic_vector(31 downto 0) := (others =>'0');
730 signal en_RARP : std_logic := '0';
731 --signal SPI_IP : std_logic_vector(31 downto 0) := (others =>'0');
732 signal status : std_logic_vector(31 downto 0) := (others =>'0');
733 signal cmd : std_logic_vector(31 downto 0) := (others =>'0');
734 signal cmd0_dl : std_logic_vector(1 downto 0) := (others =>'0');
735 signal cmd2_dl : std_logic_vector(1 downto 0) := (others =>'0');
736 signal conf : std_logic_vector(15 downto 0) := (others =>'0');
737 signal LSC_ID : std_logic_vector(15 downto 0) := x"1234";
738 signal OT : std_logic := '0';
739 signal inc_HTRCRC_err : std_logic := '0';
740 signal ttc_data : std_logic_vector(31 downto 0) := (others => '0');
741 signal sysmon_data : std_logic_vector(31 downto 0) := (others => '0');
742 signal HCAL_trig_data : std_logic_vector(31 downto 0) := (others => '0');
743 signal device_temp : std_logic_vector(11 downto 0) := (others =>'0');
744 signal ALM : std_logic_vector(7 downto 0) := (others =>'0');
745 signal evt_data_rdy : std_logic_vector(2 downto 0) := (others => '0');
746 signal evt_data_re : std_logic_vector(2 downto 0) := (others => '0');
747 signal evt_data_we : std_logic_vector(2 downto 0) := (others => '0');
748 --signal event_size : array3x13;
749 signal SFP_data : std_logic_vector(31 downto 0) := (others =>'0');
750 signal SFP_ack : std_logic := '0';
751 --signal TCP_data : std_logic_vector(31 downto 0) := (others =>'0');
752 --signal TCP_ack : std_logic := '0';
753 signal S2V_SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
754 signal resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
755 signal sysclk_div7SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
756 signal resetCntr_SyncRegs : std_logic_vector(2 downto 0) := (others =>'0');
757 signal newIPADDR : std_logic := '0';
758 signal newIPADDRSyncRegs : std_logic_vector(2 downto 0) := (others =>'0');
759 signal DNA_out : std_logic := '0';
760 signal load_DNA : std_logic := '0';
761 signal shift_DNA : std_logic_vector(2 downto 0) := (others =>'0');
762 signal DNA_cntr : std_logic_vector(5 downto 0) := (others =>'0');
763 signal DNA : std_logic_vector(56 downto 0) := (others =>'0');
764 signal Dis_pd : std_logic := '0';
765 signal enSFP : std_logic_vector(3 downto 0) := (others =>'0');
766 signal SFP_down : std_logic_vector(2 downto 0) := (others =>'0');
767 signal WrtMonBlkDone : std_logic_vector(2 downto 0) := (others =>'0');
768 signal WrtMonEvtDone : std_logic_vector(2 downto 0) := (others =>'0');
769 component icon2
770  PORT (
771  CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
772  CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
773 
774 end component;
775 component ila16x32k
776  PORT (
777  CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
778  CLK : IN STD_LOGIC;
779  DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
780  TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
781 
782 end component;
783 signal CONTROL0 : std_logic_vector(35 downto 0) := (others => '0');
784 signal CONTROL1 : std_logic_vector(35 downto 0) := (others => '0');
785 signal TRIG0 : std_logic_vector(7 downto 0) := (others => '0');
786 signal TRIG1 : std_logic_vector(7 downto 0) := (others => '0');
787 signal DATA0 : std_logic_vector(15 downto 0) := (others => '0');
788 signal DATA1 : std_logic_vector(15 downto 0) := (others => '0');
789 begin
790 --i_icon : icon2
791 -- port map (
792 -- CONTROL0 => CONTROL0,
793 -- CONTROL1 => CONTROL1);
794 --i_ila : ila16x32k
795 -- port map (
796 -- CONTROL => CONTROL0,
797 -- CLK => sysclk,
798 -- DATA => DATA0,
799 -- TRIG0 => TRIG0);
800 --DATA0(14) <= evt_buf_full(0);
801 --DATA0(13) <= evt_data_re(0);
802 --DATA0(12) <= evt_data_rdy(0);
803 --DATA0(11 downto 10) <= EventBufAddr(0)(5 downto 4);
804 --DATA0(9 downto 8) <= EventData(0)(65 downto 64);
805 --DATA0(7) <= wport_rdy(0);
806 --DATA0(6) <= wport_FIFO_full(0);
807 --DATA0(5) <= evt_data_we(0);
808 --DATA0(4) <= EventBufAddr_we(0);
809 --DATA0(3 downto 0) <= mem_stat(3 downto 0);
810 --TRIG0(7 downto 4) <= (others => '0');
811 --TRIG0(3) <= wport_rdy(0);
812 --TRIG0(2) <= EventBufAddr_we(0);
813 --TRIG0(1) <= evt_data_re(0);
814 --TRIG0(0) <= evt_data_rdy(0);
815 --
816 --i_il2 : ila16x32k
817 -- port map (
818 -- CONTROL => CONTROL1,
819 -- CLK => mem_stat(19),
820 -- DATA => DATA1,
821 -- TRIG0 => TRIG1);
822 --DATA1(14 downto 0) <= mem_stat(18 downto 4);
823 --TRIG1(7 downto 2) <= (others => '0');
824 --TRIG1(1 downto 0) <= mem_stat(18 downto 17);
825 i_TTS_if: TTS_if PORT MAP(
826  sysclk => sysclk,
827  TTS_clk => TTS_clk,
828  reset => sys_lock_n,
829  local_TTC => conf(8),
830  TTS => state,
831  TTS_out_p => TTS_out_p,
832  TTS_out_n => TTS_out_n
833  );
834 i_HCAL_trig: HCAL_trig PORT MAP(
835  TTC_clk => TTC_clk,
836  DRPCLK => DRPclk,
837  reset => reset,
838  BC0 => BC0_dl ,
839  en_HCAL_trig => en_HCAL_trig ,
840  Trigdata => Trigdata,
841  triggerOut => HCAL_trigger,
842  ipb_clk => ipb_clk,
843  ipb_write => ipb_master_out.ipb_write ,
844  ipb_strobe => ipb_master_out.ipb_strobe ,
845  ipb_addr => ipb_master_out.ipb_addr ,
846  ipb_wdata => ipb_master_out.ipb_wdata ,
847  ipb_rdata => HCAL_trig_data,
848  GTX_REFCLKp => CDR_REFCLK_P,
849  GTX_REFCLKn => CDR_REFCLK_N,
850  GTX_RXp => SFP2_RXP,
851  GTX_RXn => SFP2_RXN,
852  GTX_TXp => SFP2_TXP,
853  GTX_TXn => SFP2_TXN
854  );
855 TxDisable <= TxDisable_i;
856 i_I2C: I2C PORT MAP(
857  clk => DRPclk ,
858  ipb_clk => clk125,
859  reset => sys_lock_n,
860  addr => ipb_master_out.ipb_addr,
861  rdata => I2C_data,
862  CLK_rdy => CLK_rdy,
863  CLK_SCL => CLK_SCL,
864  CLK_SDA => CLK_SDA,
865  SFP_ABS => SFP_ABS,
866  SFP_LOS => SFP_LOS,
867  SFP_SCL => SFP_SCL,
868  SFP_SDA => SFP_SDA
869  );
870 i_SPI_SCK_buf: bufh port map(i => SPI_SCK, o => SPI_SCK_buf);
871 i_SPI_if: SPI_if PORT MAP(
872  SCK => SPI_SCK ,
873  CSn => SPI_CS_b ,
874  MOSI => SPI_MOSI ,
875  MISO => SPI_MISO ,
876  SN => SN,
877  OT => ALM(0),
878  IsT1 => '1',
879  SPI_we => open,
880  en_RARP => en_RARP,
881  newIPADDR => newIPADDR,
882  IPADDR => IPADDR,
883  SPI_rdata => (others => '0'),
884  SPI_wdata => open,
885  SPI_addr => open
886  );
887 i_ttc_if: ttc_if PORT MAP(
888  clk => sysclk ,
889  refclk => sysclk,
890  reset => reset,
891  run => run,
892  DB_cmd_in => cmd(9),
893  DB_cmd_out => DB_cmd,
894  IsG2 => '0',
895  TTC_strobe => TTC_strobe,
896  sys_lock => sys_lock,
897  local_TTC => conf(8),
898  local_TTCcmd => local_TTCcmd ,
899  single_TTCcmd => cmd(8),
900  TTS_clk => TTS_clk,
901  BC0 => BC0,
902  DIV4 => DIV4,
903  DIV_nRST => DIV_nRST,
904  CDRclk_p => CDRclk_p,
905  CDRclk_n => CDRclk_n,
906  CDRclk_out => CDRclk,
907  CDRdata_p => CDRdata_p,
908  CDRdata_n => CDRdata_n,
909  TTCdata_p => TTCdata_p,
910  TTCdata_n => TTCdata_n,
911  TTC_LOS => TTC_LOS,
912  TTC_LOL => TTC_LOL,
913  BCN_off => BCN_off,
914  OC_off => OC_off,
915  en_cal_win => en_cal_win,
916  cal_win_high => cal_win_high ,
917  cal_win_low => cal_win_low ,
918  CalType => CalType,
919  TTC_Brcst => TTC_Brcst,
920  ovfl_warning => L1Aovfl_warning ,
921  ipb_clk => ipb_clk,
922  ipb_write => ipb_master_out.ipb_write ,
923  ipb_strobe => ipb_master_out.ipb_strobe ,
924  ipb_addr => ipb_master_out.ipb_addr ,
925  ipb_wdata => ipb_master_out.ipb_wdata ,
926  ipb_rdata => ttc_data,
927  en_localL1A => conf(2),
928  LocalL1A_cfg => LocalL1A_cfg ,
929  localL1A_s => cmd(26),
930  localL1A_r => cmd(10),
931  localL1A_periodic => status(10),
932  T3_trigger => T3_trigger,
933  HCAL_trigger => HCAL_trigger ,
934  EvnRSt_l => cmd(11),
935  OcnRSt_l => cmd(12),
936  en_brcst => en_brcst,
937  ttc_start => ttc_start,
938  ttc_stop => ttc_stop,
939  ttc_soft_reset => ttc_soft_reset ,
940  ttc_ready => ttc_ready,
941  ttc_serr => ttc_serr,
942  ttc_derr => ttc_derr,
943  ttc_bcnt_err => ttc_bcnt_err ,
944  rate_OFW => rate_OFW,
945  sync_lost => sync_lost,
946  inc_oc => inc_oc,
947  inc_l1ac => inc_l1ac,
948  inc_bcnterr => inc_bcnterr ,
949  inc_serr => inc_serr,
950  inc_derr => inc_derr,
951  state => state,
952  evn_fifo_full => evn_fifo_full ,
953  ttc_evcnt_reset => ttc_evcnt_reset ,
954  event_number_avl => event_number_avl ,
955  event_number => event_number
956  );
957 local_TTCcmd <= conf(5) or conf(8);
958 CalibCtrl(31) <= en_cal_win;
959 CalibCtrl(30 downto 28) <= "000";
960 CalibCtrl(27 downto 16) <= cal_win_high;
961 CalibCtrl(15 downto 12) <= CalType;
962 CalibCtrl(11 downto 0) <= cal_win_low;
963 cal_win_high(11 downto 6) <= "110110";
964 cal_win_low(11 downto 6) <= "110110";
965 i_S2V: IBUFDS generic map(DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25") port map(i => S2V_p, ib => S2V_n, o => S2V);
966 process(CDRclk)
967 begin
968  if(CDRclk'event and CDRclk = '1')then
969  if(conf(15) = '0')then
970  T3_trigger <= '0';
971  else
972  T3_trigger <= S2V;
973  end if;
974  end if;
975 end process;
976 i_GbE_REFCLK: IBUFDS_GTE2
977  port map
978  (
979  O => GbE_REFCLK,
980  ODIV2 => open,
981  CEB => '0',
982  I => GbE_REFCLK_P, -- Connect to package pin AB6
983  IB => GbE_REFCLK_N -- Connect to package pin AB5
984  );
985 i_TTCclk_in : IBUFGDS generic map (DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25")
986  port map (
987  O => TTCclk_in, -- Clock buffer output
988  I => TTCclk_p, -- Diff_p clock buffer input
989  IB => TTCclk_n -- Diff_n clock buffer input
990  );
991 i_TTC_CLK_buf: bufg port map(i => TTCclk_in, o => TTC_Clk);
992 i_sysclk_in_buf: bufh port map(i => GbE_REFCLK, o => sysclk_in);
993 i_PLL_sysclk : PLLE2_BASE
994  generic map (
995  BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
996  CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
997  CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
998  CLKIN1_PERIOD => 8.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
999  -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
1000  CLKOUT0_DIVIDE => 5,
1001  CLKOUT1_DIVIDE => 32,
1002  CLKOUT2_DIVIDE => 20,
1003  DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
1004  REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
1005  STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
1006  )
1007  port map (
1008  -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
1009  CLKOUT0 => sysclk_dcm,
1010  CLKOUT1 => ipb_clk_dcm ,
1011  CLKOUT2 => DRPclk_dcm,
1012  -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
1013  CLKFBOUT => clk125_dcm, -- 1-bit output: Feedback clock
1014  -- Status Port: 1-bit (each) output: PLL status ports
1015  LOCKED => sys_lock, -- 1-bit output: LOCK
1016  -- Clock Input: 1-bit (each) input: Clock input
1017  CLKIN1 => sysclk_in, -- 1-bit input: Input clock
1018  -- Control Ports: 1-bit (each) input: PLL control ports
1019  PWRDWN => '0', -- 1-bit input: Power-down
1020  RST => '0', -- 1-bit input: Reset
1021  -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
1022  CLKFBIN => clk125 -- 1-bit input: Feedback clock
1023  );
1024 i_clk125_buf: bufg port map(i => clk125_dcm, o => clk125 );
1025 i_ipb_clk_buf: bufg port map(i => ipb_clk_dcm, o => ipb_clk);
1026 i_DRPclk_buf: bufg port map(i => DRPclk_dcm, o => DRPclk );
1027 i_sysclk_buf: bufg port map(i => sysclk_dcm, o => sysclk );
1028 --i_refclk_buf: bufg port map(i => refclk_dcm, o => refclk);
1029 reset <= not sys_lock or cmd(0);
1030 --sysclk <= refclk;
1031 process(sysclk,reset)
1032 begin
1033  if(reset = '1')then
1034  resetSyncRegs <= (others => '1');
1035  elsif(sysclk'event and sysclk = '1')then
1036  resetSyncRegs <= resetSyncRegs(1 downto 0) & '0';
1037  end if;
1038 end process;
1039 i_ddr_if: ddr_if PORT MAP(
1040  mem_clk_p => sys_clk_p,
1041  mem_clk_n => sys_clk_n,
1042  mem_rst => mem_rst,
1043  clk_ref => sysclk,
1044  sysclk => sysclk,
1045  TCPclk => sysclk,
1046  reset => reset,
1047  resetsys => resetSyncRegs(2),
1048  run => run,
1049  mem_test => mem_test,
1050  EventData => EventData,
1051  EventData_we => evt_data_we,
1052  wport_rdy => wport_rdy,
1053  WrtMonBlkDone => WrtMonBlkDone ,
1054  WrtMonEvtDone => WrtMonEvtDone ,
1055  KiloByte_toggle => open,
1056  EoB_toggle => open,
1057  EventBufAddr => EventBufAddr ,
1058  EventBufAddr_we => EventBufAddr_we ,
1059  EventFIFOfull => wport_FIFO_full ,
1060  TCP_din => (others => '0'),
1061  TCP_channel => (others => '0'),
1062  TCP_we => '0',
1063  TCP_wcount => open,
1064  TCP_dout => open,
1065  TCP_raddr => (others => '0'),
1066  TCP_length => (others => '0'),
1067  TCP_dout_valid => open,
1068  TCP_rrqst => '0',
1069  TCP_rack => open,
1070  TCP_lastword => open,
1071  page_addr => ddr_pa,
1072  ipb_clk => ipb_clk,
1073  ipb_write => ipb_master_out.ipb_write ,
1074  ipb_strobe => ipb_master_out.ipb_strobe ,
1075  ipb_addr => ipb_master_out.ipb_addr ,
1076  ipb_wdata => ipb_master_out.ipb_wdata ,
1077  ipb_rdata => mem_data,
1078  ipb_ack => mem_ack,
1079  mem_stat => mem_stat,
1080  device_temp => device_temp ,
1081  ddr3_dq => ddr3_dq,
1082  ddr3_dm => ddr3_dm,
1083  ddr3_addr => ddr3_addr,
1084  ddr3_ba => ddr3_ba,
1085  ddr3_dqs_p => ddr3_dqs_p,
1086  ddr3_dqs_n => ddr3_dqs_n,
1087  ddr3_ras_n => ddr3_ras_n,
1088  ddr3_cas_n => ddr3_cas_n,
1089  ddr3_we_n => ddr3_we_n,
1090  ddr3_reset_n => ddr3_reset_n ,
1091  ddr3_cke => ddr3_cke,
1092  ddr3_odt => ddr3_odt,
1093  ddr3_ck_p => ddr3_ck_p,
1094  ddr3_ck_n => ddr3_ck_n
1095  );
1096 --mem_rst <= not sys_lock or not CLK_rdy or cmd(5) or cmd(0);
1097 mem_rst <= not sys_lock or not CLK_rdy or cmd(5);
1098 MACADDR <= x"080030f30" & '0' & not SN(8) & '0' & not SN(7 downto 6) & '1' & SN(5 downto 0);
1099 i_ipbus_if: ipbus_if PORT MAP(
1100  ipb_clk => ipb_clk,
1101  UsRclk => clk125,
1102  DRPclk => DRPclk,
1103  reset => rst_ipbus,
1104  GTX_RESET => sys_lock_n,
1105  MACADDR => MACADDR, -- new mac range 08-00-30-F3-00-00 to 08-00-30-F3-00-7F
1106  en_RARP => en_RARP,
1107  IPADDR => IPADDR,
1108  GbE_REFCLK => GbE_REFCLK,
1109  S6LINK_RXN => S6LINK_RXN,
1110  S6LINK_RXP => S6LINK_RXP,
1111  S6LINK_TXN => S6LINK_TXN,
1112  S6LINK_TXP => S6LINK_TXP,
1113  wr_AMC_en => wr_AMC_en,
1114  amc_en => AMC_en,
1115  ipb_out => ipb_master_out,
1116  ipb_in => ipb_master_in,
1117  got_SN => got_SN,
1118  SN => SN,
1119  debug_in => (others => '0'),
1120  debug_out => open
1121  );
1122 --LSC_LinkDown <= '1' when conf(1) = '0' or or_reduce(EnSFP(2 downto 0) and SFP_down) = '1' else '0';
1123 --status(0) <= LSC_LinkDown;
1124 status(0) <= or_reduce(SFP_down);
1125 status(1) <= MonBufOvfl;
1126 status(2) <= mon_evt_cnt(10);
1127 status(3) <= MonBuf_empty;
1128 status(4) <= mem_stat(0); -- monitor input FIFO overflow
1129 status(5) <= not ttc_ready;
1130 status(6) <= ttc_bcnt_err;
1131 status(7) <= ttc_serr;
1132 status(8) <= ttc_derr;
1133 status(9) <= sync_lost;
1134 status(13) <= L1Aovfl_warning;
1135 status(15) <= mem_stat(63);
1136 status(23) <= '0';
1137 run <= conf(0);
1138 EnSFP(3) <= not conf(1);
1139 mem_test <= conf(6) & conf(4);
1140 --en_brcst <= conf(5);
1141 en_brcst <= '0';
1142 i_cmd0_dl0 : SRL16E
1143  port map (
1144  Q => cmd0_dl(0), -- SRL data output
1145  A0 => '1', -- Select[0] input
1146  A1 => '1', -- Select[1] input
1147  A2 => '1', -- Select[2] input
1148  A3 => '0', -- Select[3] input
1149  CE => '1', -- Clock enable input
1150  CLK => ipb_clk, -- Clock input
1151  D => cmd(0) -- SRL data input
1152  );
1153 i_cmd0_dl1 : SRL16E
1154  port map (
1155  Q => cmd0_dl(1), -- SRL data output
1156  A0 => '1', -- Select[0] input
1157  A1 => '1', -- Select[1] input
1158  A2 => '1', -- Select[2] input
1159  A3 => '0', -- Select[3] input
1160  CE => '1', -- Clock enable input
1161  CLK => ipb_clk, -- Clock input
1162  D => cmd0_dl(0) -- SRL data input
1163  );
1164 i_cmd2_dl0 : SRL16E
1165  port map (
1166  Q => cmd2_dl(0), -- SRL data output
1167  A0 => '1', -- Select[0] input
1168  A1 => '1', -- Select[1] input
1169  A2 => '1', -- Select[2] input
1170  A3 => '0', -- Select[3] input
1171  CE => '1', -- Clock enable input
1172  CLK => ipb_clk, -- Clock input
1173  D => cmd(2) -- SRL data input
1174  );
1175 i_cmd2_dl1 : SRL16E
1176  port map (
1177  Q => cmd2_dl(1), -- SRL data output
1178  A0 => '1', -- Select[0] input
1179  A1 => '1', -- Select[1] input
1180  A2 => '1', -- Select[2] input
1181  A3 => '0', -- Select[3] input
1182  CE => '1', -- Clock enable input
1183  CLK => ipb_clk, -- Clock input
1184  D => cmd2_dl(0) -- SRL data input
1185  );
1186 process(ipb_clk)
1187 begin
1188  if(ipb_clk'event and ipb_clk = '1')then
1189  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = CSR_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1190  cmd <= ipb_master_out.ipb_wdata;
1191  else
1192  cmd <= (others => '0');
1193  end if;
1194  conf7_q <= conf(7);
1195  conf7_fall <= conf7_q and not conf(7);
1196  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = CFG_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1197  conf <= ipb_master_out.ipb_wdata(15 downto 0);
1198  end if;
1199  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = HTR_EN_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1200  Dis_pd <= ipb_master_out.ipb_wdata(15);
1201  EnSFP(0) <= ipb_master_out.ipb_wdata(12);
1202  AMC_en <= ipb_master_out.ipb_wdata(11 downto 0);
1203  if(AMC_en = ipb_master_out.ipb_wdata(11 downto 0))then
1204  wr_AMC_en <= '0';
1205  else
1206  wr_AMC_en <= '1';
1207  end if;
1208  if(EnSFP(0) = ipb_master_out.ipb_wdata(12))then
1209  wr_EnSFP <= '0';
1210  else
1211  wr_EnSFP <= '1';
1212  end if;
1213  else
1214  wr_AMC_en <= '0';
1215  wr_EnSFP <= '0';
1216  end if;
1217  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"001a" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1218  TTS_disable <= ipb_master_out.ipb_wdata(11 downto 0);
1219  end if;
1220  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = TTC_cal_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1221  en_cal_win <= ipb_master_out.ipb_wdata(31);
1222  cal_win_high(5 downto 0) <= ipb_master_out.ipb_wdata(21 downto 16);
1223  cal_win_low(5 downto 0) <= ipb_master_out.ipb_wdata(5 downto 0);
1224  end if;
1225  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1226  Source_ID(0)(11 downto 0) <= ipb_master_out.ipb_wdata(11 downto 0);
1227  end if;
1228  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id1_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1229  Source_ID(1)(11 downto 0) <= ipb_master_out.ipb_wdata(11 downto 0);
1230  end if;
1231  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"001c" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1232  LocalL1A_cfg <= ipb_master_out.ipb_wdata;
1233  end if;
1234  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SFP_CSR_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1235  LSC_ID(15 downto 2) <= ipb_master_out.ipb_wdata(31 downto 18);
1236  TxDisable_i <= ipb_master_out.ipb_wdata(15 downto 12);
1237  end if;
1238  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = TTC_bcnt_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1239  OC_OFF <= ipb_master_out.ipb_wdata(19 downto 16);
1240  BCN_OFF <= ipb_master_out.ipb_wdata(12 downto 0);
1241  end if;
1242  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = fake_length_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1243  fake_length <= ipb_master_out.ipb_wdata(19 downto 0);
1244  end if;
1245  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"0019" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1246  pattern <= ipb_master_out.ipb_wdata(11 downto 8);
1247 -- Trig_mask <= ipb_master_out.ipb_wdata(7 downto 0);
1248  end if;
1249  if(reset = '1' or (ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = MON_ctrl_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1'))then
1250  ddr_pa <= (others => '0');
1251  elsif(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = PAGE_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1252  if(run = '1')then
1253  if(MonBuf_empty = '0')then
1254  ddr_pa <= ddr_pa + 1;
1255  end if;
1256  else
1257  ddr_pa <= ipb_master_out.ipb_wdata(9 downto 0);
1258  end if;
1259  end if;
1260  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = PAGE_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1' and run = '1' and MonBuf_empty = '0')then
1261  inc_ddr_pa <= '1';
1262  else
1263  inc_ddr_pa <= '0';
1264  end if;
1265  if(DB_cmd = '1')then
1266  status_l <= status(22 downto 0);
1267  SFP_down_l <= SFP_down;
1268  SFP_status_l <= TxFault & (TTC_LOL or TTC_LOL) & SFP_LOS & SFP_ABS;
1269  AMC_status_l <= AMC_status;
1270  end if;
1271  end if;
1272 end process;
1273 ipb_master_in.ipb_ack <= ipb_master_out.ipb_strobe when ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(17) = '0' else mem_ack;
1274 process(ipb_master_out.ipb_addr)
1275 begin
1276  if(ipb_master_out.ipb_addr(27) = '1' or ipb_master_out.ipb_addr(17) = '1')then
1277  ipb_master_in.ipb_rdata <= mem_data;
1278  elsif(ipb_master_out.ipb_addr(14 downto 5) = CSR_addr(14 downto 5))then
1279  if(ipb_master_out.ipb_addr(15) = '0')then
1280  case ipb_master_out.ipb_addr(4 downto 0) is
1281  when "00000" => ipb_master_in.ipb_rdata <= not SN(7 downto 0) & not SN(8) & status(22 downto 0);
1282  when "00001" => ipb_master_in.ipb_rdata <= K7version & conf;
1283  when "00010" => ipb_master_in.ipb_rdata <= mon_ctrl;
1284  when "00011" => ipb_master_in.ipb_rdata <= '0' & SFP_down & AMC_Ready & Dis_pd & EnSFP(2 downto 0) & AMC_en;
1285  when "00100" => ipb_master_in.ipb_rdata <= LSC_ID & TxDisable_i & TxFault & (TTC_LOL or TTC_LOL) & SFP_LOS & SFP_ABS;
1286  when "00101" => ipb_master_in.ipb_rdata <= AMC_status;
1287  when "00111" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(0);
1288  when "01000" => ipb_master_in.ipb_rdata <= x"000" & OC_OFF & "000" & BCN_OFF;
1289  when "01001" => ipb_master_in.ipb_rdata <= CalibCtrl;
1290  when "01010" => ipb_master_in.ipb_rdata <= mem_stat(31 downto 0);
1291  when "01011" => ipb_master_in.ipb_rdata <= mem_stat(63 downto 32);
1292  when "01100" => ipb_master_in.ipb_rdata <= x"00000" & "00" & ddr_pa;
1293  when "01101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(15 downto 0) & '0';
1294  when "01110" => ipb_master_in.ipb_rdata <= mon_evt_cnt;
1295  when "01111" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(31 downto 16) & '0';
1296  when "10000" => ipb_master_in.ipb_rdata <= x"000" & "00" & mon_buf_avl & '1' & '0' & wport_FIFO_full & '0' & wport_rdy & x"0" & '0' & evt_data_rdy;
1297  when "10001" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(1);
1298  when "10010" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(2);
1299  when "11000" => ipb_master_in.ipb_rdata <= x"000" & fake_length;
1300  when "11001" => ipb_master_in.ipb_rdata <= x"00" & "000" & TTS_coded & state & pattern & x"00";
1301  when "11010" => ipb_master_in.ipb_rdata <= x"00000" & TTS_disable;
1302  when "11100" => ipb_master_in.ipb_rdata <= LocalL1A_cfg;
1303  when "11101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(47 downto 32) & '0';
1304  when "11110" => ipb_master_in.ipb_rdata <= DNA(31 downto 0);
1305  when "11111" => ipb_master_in.ipb_rdata <= "0000000" & DNA(56 downto 32);
1306  when others => ipb_master_in.ipb_rdata <= (others => '0');
1307  end case;
1308  else
1309  case ipb_master_out.ipb_addr(4 downto 0) is
1310  when "00000" => ipb_master_in.ipb_rdata <= not SN(7 downto 0) & not SN(8) & status_l;
1311  when "00001" => ipb_master_in.ipb_rdata <= K7version & conf;
1312  when "00010" => ipb_master_in.ipb_rdata <= mon_ctrl;
1313  when "00011" => ipb_master_in.ipb_rdata <= '0' & SFP_down_l & AMC_Ready & Dis_pd & EnSFP(2 downto 0) & AMC_en;
1314  when "00100" => ipb_master_in.ipb_rdata <= LSC_ID & TxDisable_i & SFP_status_l;
1315  when "00101" => ipb_master_in.ipb_rdata <= AMC_status_l;
1316  when "00111" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(0);
1317  when "01000" => ipb_master_in.ipb_rdata <= x"000" & OC_OFF & "000" & BCN_OFF;
1318  when "01001" => ipb_master_in.ipb_rdata <= CalibCtrl;
1319  when "01010" => ipb_master_in.ipb_rdata <= mem_stat(31 downto 0);
1320  when "01011" => ipb_master_in.ipb_rdata <= mem_stat(63 downto 32);
1321  when "01100" => ipb_master_in.ipb_rdata <= x"00000" & "00" & ddr_pa;
1322  when "01101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(15 downto 0) & '0';
1323  when "01110" => ipb_master_in.ipb_rdata <= mon_evt_cnt;
1324  when "01111" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(31 downto 16) & '0';
1325  when "10000" => ipb_master_in.ipb_rdata <= x"000" & "00" & mon_buf_avl & '1' & '0' & wport_FIFO_full & '0' & wport_rdy & x"0" & '0' & evt_data_rdy;
1326  when "10001" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(1);
1327  when "10010" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(2);
1328  when "11000" => ipb_master_in.ipb_rdata <= x"000" & fake_length;
1329  when "11001" => ipb_master_in.ipb_rdata <= x"00" & "000" & TTS_coded & state & pattern & x"00";
1330  when "11010" => ipb_master_in.ipb_rdata <= x"00000" & TTS_disable;
1331  when "11100" => ipb_master_in.ipb_rdata <= LocalL1A_cfg;
1332  when "11101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(47 downto 32) & '0';
1333  when "11110" => ipb_master_in.ipb_rdata <= DNA(31 downto 0);
1334  when "11111" => ipb_master_in.ipb_rdata <= "0000000" & DNA(56 downto 32);
1335  when others => ipb_master_in.ipb_rdata <= (others => '0');
1336  end case;
1337  end if;
1338  else
1339  ipb_master_in.ipb_rdata <= AMC_data or TTC_cntr_data or I2C_data or sysmon_data or SFP_data or ttc_data;
1340  end if;
1341 end process;
1342 rst_cntr <= cmd(1) or cmd(0);
1343 ttc_resync <= ttc_soft_reset;
1344 process(sysClk,reset)
1345 begin
1346  if(reset = '1')then
1347  TTS_wait <= (others => '0');
1348  elsif(sysClk'event and sysClk = '1')then
1349  if(ttc_resync = '1')then
1350  TTS_wait <= (others => '0');
1351  elsif(TTS_wait(20) = '0' and sync_lost = '0' and AllEventBuilt = '1')then
1352  TTS_wait <= TTS_wait + 1;
1353  end if;
1354  end if;
1355 end process;
1356 process(sysClk,reset)
1357 begin
1358  if(reset = '1')then
1359  state <= "0100";
1360  elsif(sysClk'event and sysClk = '1')then
1361  if(run = '0' and conf(12) = '1')then
1362  state <= pattern;
1363  elsif(run = '0')then
1364  state <= "0100"; -- changed upon request starting version 0x3023
1365  elsif(ttc_resync = '1')then
1366  state <= "0100";
1367  else
1368  case state is
1369  when "1000" => -- Ready
1370  if(TTS_coded(4) = '1')then
1371  state <= "1111";
1372  elsif(TTS_coded(3) = '1')then
1373  state <= "1100";
1374  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1375  state <= "0010";
1376  elsif(L1Aovfl_warning = '1' or evn_fifo_full = '1' or rate_OFWp = '1' or TTS_coded(1) = '1' or TTS_coded(0) = '1')then
1377  state <= "0001";
1378  end if;
1379  when "0001" => -- OFW
1380  if(TTS_coded(4) = '1')then
1381  state <= "1111";
1382  elsif(TTS_coded(3) = '1')then
1383  state <= "1100";
1384  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1385  state <= "0010";
1386  elsif(evn_fifo_full = '1' or rate_OFWp = '1' or TTS_coded(1) = '1')then
1387  state <= "0100";
1388  elsif(L1Aovfl_warning = '0' and rate_OFWp = '0' and TTS_coded(0) = '0')then
1389  state <= "1000";
1390  end if;
1391  when "0100" => -- Busy
1392  if(TTS_wait(20) = '0')then
1393  elsif(TTS_coded(4) = '1')then
1394  state <= "1111";
1395  elsif(TTS_coded(3) = '1')then
1396  state <= "1100";
1397  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1398  state <= "0010";
1399  elsif(evn_fifo_full = '0' and rate_OFWp = '0' and TTS_coded(1) = '0')then
1400  state <= "0001";
1401  end if;
1402  when others => null; -- x"0" or x"f" disconnected, x"2" OOS, x"c" error
1403  end case;
1404  end if;
1405  end if;
1406 end process;
1407 ipb_master_in.ipb_err <= '0';
1408 process(TTC_clk)
1409 begin
1410  if(TTC_clk'event and TTC_clk = '1')then
1411  if(BC0 = '1')then
1412  bcnt <= x"de8"; -- this compensates 5 TTC clock delay in HCAL_trig(2) and ttc_if(3)
1413  elsif(bcnt = x"deb")then
1414  bcnt <= (others => '0');
1415  else
1416  bcnt <= bcnt + 1;
1417  end if;
1418  if(bcnt = BX_offset)then
1419  BC0_dl <= '1';
1420  else
1421  BC0_dl <= '0';
1422  end if;
1423  chk_lock <= BC0_dl;
1424  chk_lock_q <= chk_lock;
1425  if(TTC_lock = '0')then
1426  BC0_locked <= "00";
1427  elsif(chk_lock = '1')then
1428  BC0_locked <= BC0_locked(0) & and_reduce(BC0_lock or (not AMC_en));
1429  end if;
1430  if(TTC_lock = '0')then
1431  inc_BX_offset <= '0';
1432  add_two <= "00";
1433  elsif(chk_lock_q = '1' and BC0_locked = "10")then
1434  inc_BX_offset <= '1';
1435  add_two <= "10";
1436  elsif(add_two /= "00")then
1437  add_two <= add_two - 1;
1438  end if;
1439  if(TTC_lock = '0')then
1440  en_HCAL_trig <= '0';
1441  elsif(chk_lock = '1')then
1442  if(inc_BX_offset = '1' and add_two = "00")then
1443  en_HCAL_trig <= '1';
1444  else
1445  en_HCAL_trig <= '0';
1446  end if;
1447  end if;
1448  if(TTC_lock = '0')then
1449  ec_BX_offset <= '0';
1450  elsif(chk_lock = '1' and inc_BX_offset = '0')then
1451  ec_BX_offset <= '1';
1452  elsif(add_two /= "00")then
1453  ec_BX_offset <= '1';
1454  else
1455  ec_BX_offset <= '0';
1456  end if;
1457  if(TTC_lock = '0')then
1458  BX_offset <= x"100";
1459  elsif(ec_BX_offset = '1')then
1460  if(inc_BX_offset = '1')then
1461  if(BX_offset = x"deb")then
1462  BX_offset <= x"000";
1463  else
1464  BX_offset <= BX_offset + 1;
1465  end if;
1466  elsif(BX_offset = x"000")then
1467  BX_offset <= x"deb";
1468  else
1469  BX_offset <= BX_offset - 1;
1470  end if;
1471  end if;
1472  if(BX_offset(11) = '1')then
1473  BX_offset2SC <= BX_offset - x"dec";
1474  else
1475  BX_offset2SC <= BX_offset;
1476  end if;
1477  end if;
1478 end process;
1479 i_AMC_if: AMC_if PORT MAP(
1480  sysclk => sysclk,
1481  ipb_clk => ipb_clk,
1482  clk125 => clk125,
1483  DRPclk => DRPclk,
1484  reset => AMC_reset,
1485  DB_cmd => DB_cmd,
1486  ReSync => ttc_resync,
1487  GTXreset => amc_GTXreset,
1488  resetCntr => rst_cntr,
1489  AllEventBuilt => AllEventBuilt ,
1490  run => run,
1491  en_inject_err => conf(10),
1492  Dis_pd => Dis_pd,
1493  enSFP => enSFP,
1494  test => conf(7),
1495  NoReSyncFake => conf(11),
1496  WaitMonBuf => conf(14),
1497  fake_length => fake_length ,
1498  en_localL1A => conf(2),
1499  T1_version => K7version(7 downto 0),
1500  Source_ID => Source_ID,
1501  AMC_en => AMC_en,
1502  TTS_disable => TTS_disable ,
1503  AMC_Ready => AMC_Ready,
1504  TTC_lock => TTC_lock,
1505  BC0_lock => BC0_lock,
1506  AMC_REFCLK_P => AMC_REFCLK_P ,
1507  AMC_REFCLK_N => AMC_REFCLK_N ,
1508  AMC_RXN => AMC_RXN,
1509  AMC_RXP => AMC_RXP,
1510  AMC_TXN => AMC_TXN,
1511  AMC_TXP => AMC_TXP,
1512  AMC_status => AMC_status,
1513  evt_data => EventData,
1514  evt_data_we => evt_data_we ,
1515  evt_buf_full => evt_buf_full ,
1516  evt_data_re => evt_data_re ,
1517  evt_data_rdy => evt_data_rdy ,
1518  ddr_pa => ddr_pa,
1519  MonBuf_empty => MonBuf_empty ,
1520  mon_evt_wc => mon_evt_wc,
1521  mon_ctrl => mon_ctrl,
1522  mon_buf_avl => mon_buf_avl ,
1523  TCPbuf_avl => '1',
1524  buf_rqst => EventBuf_rqst,
1525  ipb_write => ipb_master_out.ipb_write ,
1526  ipb_strobe => ipb_master_out.ipb_strobe ,
1527  ipb_addr => ipb_master_out.ipb_addr ,
1528  ipb_wdata => ipb_master_out.ipb_wdata ,
1529  ipb_rdata => AMC_data,
1530  ipb_ack => AMC_ack,
1531  TTC_clk => TTC_clk,
1532  TTC_LOS => TTC_LOS,
1533  BC0 => BC0_dl ,
1534  ttc_evcnt_reset => ttc_evcnt_reset ,
1535  event_number_avl => event_number_avl ,
1536  event_number => event_number ,
1537  evn_buf_full => evn_fifo_full,
1538  ovfl_warning => L1Aovfl_warning ,
1539  TrigData => TrigData,
1540  TTS_coded => TTS_coded
1541  );
1542 AMC_reset <= not sys_lock or cmd(0) or cmd0_dl(1);
1543 amc_GTXreset <= wr_AMC_en or conf7_fall or not sys_lock;
1544 sys_lock_n <= not sys_lock;
1545 --i_DAQLSC_if: DAQLSCXG_2x_if PORT MAP(
1546 -- sysclk => sysclk,
1547 -- clk125 => clk125,
1548 -- DRPclk => DRPclk,
1549 -- reset => AMC_reset,
1550 -- daq_reset => lsc_reset,
1551 -- gtx_reset => lsc_GTXreset,
1552 -- rstCntr => rst_cntr,
1553 -- test => '0',
1554 -- DB_cmd => DB_cmd,
1555 -- Dis_pd => Dis_pd,
1556 -- enSFP => enSFP,
1557 -- SFP_ABS => SFP_ABS(1 downto 0),
1558 -- LSC_ID => LSC_ID,
1559 -- SFP_down => SFP_down,
1560 -- inc_ddr_pa => inc_ddr_pa,
1561 -- evt_data_rdy => evt_data_rdy,
1562 -- EventData_in => EventData,
1563 -- EventData_we => evt_data_we,
1564 -- EventData_re => evt_data_re,
1565 -- evt_buf_full => evt_buf_full,
1566 -- buf_rqst => EventBuf_rqst,
1567 -- WaitMonBuf => conf(14),
1568 -- MonBufOverWrite => conf(13),
1569 -- MonBuf_avl => mon_buf_avl,
1570 -- MonBuf_empty => MonBuf_empty,
1571 -- MonBufOvfl => MonBufOvfl,
1572 -- mon_evt_cnt => mon_evt_cnt,
1573 -- WrtMonBlkDone => WrtMonBlkDone,
1574 -- WrtMonEvtDone => WrtMonEvtDone,
1575 -- wport_rdy => wport_rdy,
1576 -- wport_FIFO_full => wport_FIFO_full,
1577 -- EventBufAddr_we => EventBufAddr_we,
1578 -- EventBufAddr => EventBufAddr,
1579 -- SFP0_RXN => SFP0_RXN,
1580 -- SFP0_RXP => SFP0_RXP,
1581 -- SFP1_RXN => SFP1_RXN,
1582 -- SFP1_RXP => SFP1_RXP,
1583 -- SFP0_TXN => SFP0_TXN,
1584 -- SFP0_TXP => SFP0_TXP,
1585 -- SFP1_TXN => SFP1_TXN,
1586 -- SFP1_TXP => SFP1_TXP,
1587 -- SFP_REFCLK_p => GbE_REFCLK,
1588 -- SFP_REFCLK_n => '0',
1589 -- ipb_clk => ipb_clk,
1590 -- ipb_write => ipb_master_out.ipb_write,
1591 -- ipb_strobe => ipb_master_out.ipb_strobe,
1592 -- ipb_addr => ipb_master_out.ipb_addr,
1593 -- ipb_wdata => ipb_master_out.ipb_wdata,
1594 -- ipb_rdata => SFP_data,
1595 -- ipb_ack => SFP_ack
1596 -- );
1597 i_DAQLSC_if: DAQLSCXG_3x_if generic map(N_SFP => 1) PORT MAP(
1598  sysclk => sysclk,
1599  clk125 => clk125,
1600  DRPclk => DRPclk,
1601  reset => AMC_reset,
1602  daq_reset => lsc_reset,
1603  gtx_reset => lsc_GTXreset,
1604  rstCntr => rst_cntr,
1605  test => '0',
1606  DB_cmd => DB_cmd,
1607  Dis_pd => Dis_pd,
1608  enSFP => enSFP,
1609  SFP_ABS => SFP_ABS(2 downto 0),
1610  LSC_ID => LSC_ID,
1611  SFP_down => SFP_down,
1612  inc_ddr_pa => inc_ddr_pa,
1613  evt_data_rdy => evt_data_rdy ,
1614  EventData_in => EventData,
1615  EventData_we => evt_data_we,
1616  EventData_re => evt_data_re,
1617  evt_buf_full => evt_buf_full ,
1618  buf_rqst => EventBuf_rqst,
1619  WaitMonBuf => conf(14),
1620  MonBufOverWrite => conf(13),
1621  MonBuf_avl => mon_buf_avl,
1622  MonBuf_empty => MonBuf_empty ,
1623  MonBufOvfl => MonBufOvfl,
1624  mon_evt_cnt => mon_evt_cnt ,
1625  WrtMonBlkDone => WrtMonBlkDone ,
1626  WrtMonEvtDone => WrtMonEvtDone ,
1627  wport_rdy => wport_rdy,
1628  wport_FIFO_full => wport_FIFO_full ,
1629  EventBufAddr_we => EventBufAddr_we ,
1630  EventBufAddr => EventBufAddr ,
1631  SFP0_RXN => SFP0_RXN,
1632  SFP0_RXP => SFP0_RXP,
1633  SFP1_RXN => '1',
1634  SFP1_RXP => '0',
1635  SFP2_RXN => '1',
1636  SFP2_RXP => '0',
1637  SFP0_TXN => SFP0_TXN,
1638  SFP0_TXP => SFP0_TXP,
1639  SFP1_TXN => open,
1640  SFP1_TXP => open,
1641  SFP2_TXN => open,
1642  SFP2_TXP => open,
1643  SFP_REFCLK_P => SFP_REFCLK_P ,
1644  SFP_REFCLK_N => SFP_REFCLK_N,
1645  ipb_clk => ipb_clk,
1646  ipb_write => ipb_master_out.ipb_write ,
1647  ipb_strobe => ipb_master_out.ipb_strobe ,
1648  ipb_addr => ipb_master_out.ipb_addr ,
1649  ipb_wdata => ipb_master_out.ipb_wdata ,
1650  ipb_rdata => SFP_data,
1651  ipb_ack => SFP_ack
1652  );
1653 lsc_reset <= lsc_start or cmd(2) or cmd2_dl(1);
1654 --lsc_GTXreset <= wr_EnSFP or not sys_lock or cmd2_dl(0);
1655 lsc_GTXreset <= lsc_start or cmd2_dl(0);
1656 process(DRPclk, sys_lock)
1657 begin
1658  if(sys_lock = '0')then
1659  lsc_start <= '1';
1660  elsif(DRPclk'event and DRPclk = '1')then
1661  if(CLK_rdy = '1')then
1662  lsc_start <= '0';
1663  end if;
1664  end if;
1665 end process;
1666 i_sysmon_if: sysmon_if PORT MAP(
1667  DRPclk => ipb_clk,
1668  DB_cmd => DB_cmd,
1669  SN => SN,
1670  VAUXN_IN => VAUXN,
1671  VAUXP_IN => VAUXP,
1672  addr => ipb_master_out.ipb_addr(15 downto 0),
1673  data => sysmon_data ,
1674  device_temp => device_temp ,
1675  ALM => ALM,
1676  OT => OT
1677  );
1678 process(ipb_clk)
1679 begin
1680  if(ipb_clk'event and ipb_clk = '1')then
1681  newIPADDRSyncRegs <= newIPADDRSyncRegs(1 downto 0) & newIPADDR;
1682  rst_ipbus <= not newIPADDRSyncRegs(2) and newIPADDR;
1683  end if;
1684 end process;
1685 i_TTC_cntr: TTC_cntr PORT MAP(
1686  sysclk => sysclk,
1687  clk125 => clk125,
1688  ipb_clk => ipb_clk,
1689  reset => reset,
1690  rst_cntr => rst_cntr,
1691  DB_cmd => DB_cmd,
1692  inc_serr => inc_serr,
1693  inc_derr => inc_derr,
1694  inc_bcnterr => inc_bcnterr ,
1695  inc_l1ac => inc_l1ac,
1696  run => run,
1697  state => state,
1698  ttc_resync => ttc_resync,
1699  ipb_addr => ipb_master_out.ipb_addr (15 downto 0),
1700  ipb_rdata => TTC_cntr_data
1701  );
1702 i_DNA_PORT : DNA_PORT
1703  generic map (
1704  SIM_DNA_VALUE => X"00123456789abcd" -- Specifies a sample 57-bit DNA value for simulation
1705  )
1706  port map (
1707  DOUT => DNA_out, -- 1-bit output: DNA output data.
1708  CLK => ipb_clk , -- 1-bit input: Clock input.
1709  DIN => '0', -- 1-bit input: User data input pin.
1710  READ => load_DNA, -- 1-bit input: Active high load DNA, active low read input.
1711  SHIFT => shift_DNA(1) -- 1-bit input: Active high shift enable input.
1712  );
1713 process(ipb_clk)
1714 begin
1715  if(ipb_clk'event and ipb_clk = '1')then
1716  load_DNA <= not sys_lock;
1717  if(sys_lock = '0')then
1718  shift_DNA(0) <= '0';
1719  elsif(load_DNA = '1')then
1720  shift_DNA(0) <= '1';
1721  elsif(shift_DNA(2) = '1' and or_reduce(DNA_cntr(5 downto 1)) = '0')then
1722  shift_DNA(0) <= '0';
1723  end if;
1724  shift_DNA(2) <= shift_DNA(0);
1725  if(shift_DNA(2) = '1')then
1726  DNA_cntr <= DNA_cntr - 1;
1727  elsif(shift_DNA(0) = '1')then
1728  DNA_cntr <= "110111";
1729  end if;
1730  if(shift_DNA(2) = '1')then
1731  DNA <= DNA(55 downto 0) & DNA_OUT;
1732  end if;
1733  end if;
1734 end process;
1735 process(ipb_clk)
1736 begin
1737  if(ipb_clk'event and ipb_clk = '0')then
1738  shift_DNA(1) <= shift_DNA(0);
1739  end if;
1740 end process;
1741 end Behavioral;
1742 
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