Behavioral Architecture Reference

List of all members.

Types
array8X12	array ( 0 to 7 ) of std_logic_vector ( 11 downto 0 )

Signals
fifo_re	std_logic := ' 0 '
fifo_we	std_logic := ' 0 '
wait_time	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
dip	std_logic_vector ( 71 downto 0 ) := ( others = > ' 0 ' )
dop	std_logic_vector ( 71 downto 0 ) := ( others = > ' 0 ' )
fifo_empty	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
fifo_Almostempty	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
fifo_full	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
rdcount	array8X12 := ( others = > ( others = > ' 0 ' ) )
wrcount	array8X12 := ( others = > ( others = > ' 0 ' ) )

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Detailed Description

Definition at line 49 of file FIFO66x2048.vhd.

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The documentation for this class was generated from the following file:

• /home/dan/work/CMS/firmware/trunk/src/TCPIP_if/FIFO66x2048.vhd