DAQLSCXG_2x_if Member List

This is the complete list of members for DAQLSCXG_2x_if, including all inherited members.

ack_pckt (defined in Core_logic)	Core_logic	Port
ack_pckt (defined in build_pckt_s)	build_pckt_s	Port
ack_pckt (defined in Core_logic)	Core_logic	Port
ack_pckt (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
aclr (defined in FIFO_sync)	FIFO_sync	Port
aclr (defined in FIFO_sync)	FIFO_sync	Port
Addr (defined in SLINK_opt)	SLINK_opt	Port
Addr (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
addr (defined in fed_itf)	fed_itf	Port
addr (defined in fed_itf)	fed_itf	Port
addra (defined in Memory)	Memory	Port
addra (defined in Memory)	Memory	Port
addrb (defined in Memory)	Memory	Port
addrb (defined in Memory)	Memory	Port
almost_f (defined in FIFO_sync)	FIFO_sync	Port
almost_f (defined in FIFO_sync)	FIFO_sync	Port
amc13_pack (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	use clause
Back_p (defined in event_generator)	event_generator	Port
Back_p (defined in event_generator)	event_generator	Port
base_clk (defined in freq_measure)	freq_measure	Port
base_clk (defined in freq_measure)	freq_measure	Port
block_free (defined in fed_itf)	fed_itf	Port
block_free (defined in Core_logic)	Core_logic	Port
block_free (defined in fed_itf)	fed_itf	Port
block_free (defined in Core_logic)	Core_logic	Port
block_sz_fed (defined in fed_itf)	fed_itf	Port
block_sz_fed (defined in Core_logic)	Core_logic	Port
block_sz_fed (defined in fed_itf)	fed_itf	Port
block_sz_fed (defined in Core_logic)	Core_logic	Port
BLOCKSYNC_OUT (defined in BLOCK_SYNC_SM)	BLOCK_SYNC_SM	Port
buf_rqst (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
card_ID (defined in Core_logic)	Core_logic	Port
card_ID (defined in build_pckt_s)	build_pckt_s	Port
card_ID (defined in rcv_pckt_s)	rcv_pckt_s	Port
card_ID (defined in Core_logic)	Core_logic	Port
card_ID (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
card_ID (defined in rcv_pckt_s_XGMII)	rcv_pckt_s_XGMII	Port
card_ID_rcv (defined in Core_logic)	Core_logic	Port
card_ID_rcv (defined in Core_logic)	Core_logic	Port
clear (defined in CRC_SLINKx)	CRC_SLINKx	Port
clear (defined in CRC_SLINKx)	CRC_SLINKx	Port
clk (defined in lpm_fifo)	lpm_fifo	Port
clk (defined in CRC_SLINKx)	CRC_SLINKx	Port
clk (defined in lpm_fifo)	lpm_fifo	Port
clk (defined in CRC_SLINKx)	CRC_SLINKx	Port
clk (defined in XGbEPCS32)	XGbEPCS32	Port
clk (defined in check_event)	check_event	Port
clk (defined in cmsCRC64)	cmsCRC64	Port
clk125 (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
clk156 (defined in XGMII_serdes_wapper)	XGMII_serdes_wapper	Port
clk2x (defined in XGbEPCS32)	XGbEPCS32	Port
clk_r (defined in FIFO_sync)	FIFO_sync	Port
clk_r (defined in FIFO_sync)	FIFO_sync	Port
clk_w (defined in FIFO_sync)	FIFO_sync	Port
clk_w (defined in FIFO_sync)	FIFO_sync	Port
clka (defined in Memory)	Memory	Port
clka (defined in Memory)	Memory	Port
clkb (defined in Memory)	Memory	Port
clkb (defined in Memory)	Memory	Port
clock (defined in SLINK_opt)	SLINK_opt	Port
clock (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
clock_r (defined in SLINK_opt)	SLINK_opt	Port
clock_r (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
clock_t (defined in rcv_pckt_s)	rcv_pckt_s	Port
clock_t (defined in rcv_pckt_s_XGMII)	rcv_pckt_s_XGMII	Port
clocki (defined in resync)	resync	Port
clocki (defined in resync)	resync	Port
clocki (defined in resync)	resync	Port
clocki (defined in resync)	resync	Port
clocki (defined in resync)	resync	Port
clocki (defined in resync)	resync	Port
clocki (defined in resync)	resync	Port
clocki (defined in resync)	resync	Port
clocko (defined in resync)	resync	Port
clocko (defined in resync)	resync	Port
clocko (defined in resync)	resync	Port
clocko (defined in resync)	resync	Port
clocko (defined in resync)	resync	Port
clocko (defined in resync)	resync	Port
clocko (defined in resync)	resync	Port
clocko (defined in resync)	resync	Port
cmd (defined in Core_logic)	Core_logic	Port
cmd (defined in build_pckt_s)	build_pckt_s	Port
cmd (defined in rcv_pckt_s)	rcv_pckt_s	Port
cmd (defined in Core_logic)	Core_logic	Port
cmd (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
cmd (defined in rcv_pckt_s_XGMII)	rcv_pckt_s_XGMII	Port
cmd_rcv (defined in Core_logic)	Core_logic	Port
cmd_rcv (defined in Core_logic)	Core_logic	Port
cmsCRC_err (defined in check_event)	check_event	Port
cnt_evt (defined in fed_itf)	fed_itf	Port
cnt_evt (defined in fed_itf)	fed_itf	Port
cnt_pckt_rcv (defined in fed_itf)	fed_itf	Port
cnt_pckt_rcv (defined in rcv_pckt_s)	rcv_pckt_s	Port
cnt_pckt_rcv (defined in fed_itf)	fed_itf	Port
cnt_pckt_rcv (defined in rcv_pckt_s_XGMII)	rcv_pckt_s_XGMII	Port
cnt_pckt_snd (defined in fed_itf)	fed_itf	Port
cnt_pckt_snd (defined in build_pckt_s)	build_pckt_s	Port
cnt_pckt_snd (defined in fed_itf)	fed_itf	Port
cnt_pckt_snd (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
CPLL_RESET (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
CPLL_RESET (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
CPLL_RESET (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
CPLL_RESET (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
CPLL_RESET (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
CPLL_RESET (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
CPLLLOCK (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
CPLLLOCK (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
CPLLLOCK (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
CPLLLOCK (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
CPLLLOCK (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
CPLLLOCK (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
CPLLREFCLKLOST (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
CPLLREFCLKLOST (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
CPLLREFCLKLOST (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
CPLLREFCLKLOST (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
CPLLREFCLKLOST (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
CPLLREFCLKLOST (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
crc (defined in crc_gen_usb_32to16)	crc_gen_usb_32to16	Port
crc (defined in crc_gen_usb_32to16)	crc_gen_usb_32to16	Port
crc (defined in crc_gen_32b)	crc_gen_32b	Port
crc (defined in crc_gen_32b)	crc_gen_32b	Port
crc (defined in cmsCRC64)	cmsCRC64	Port
crc_ce (defined in cmsCRC64)	cmsCRC64	Port
crc_d (defined in cmsCRC64)	cmsCRC64	Port
crc_err (defined in cmsCRC64)	cmsCRC64	Port
crc_init (defined in cmsCRC64)	cmsCRC64	Port
CRC_out (defined in CRC_SLINKx)	CRC_SLINKx	Port
CRC_out (defined in CRC_SLINKx)	CRC_SLINKx	Port
crc_valid (defined in crc_gen_usb_32to16)	crc_gen_usb_32to16	Port
crc_valid (defined in crc_gen_usb_32to16)	crc_gen_usb_32to16	Port
crc_valid (defined in crc_gen_32b)	crc_gen_32b	Port
crc_valid (defined in crc_gen_32b)	crc_gen_32b	Port
ctrl_i (defined in xaui_wd_align)	xaui_wd_align	Port
ctrl_o (defined in xaui_wd_align)	xaui_wd_align	Port
D (defined in CRC_SLINKx)	CRC_SLINKx	Port
D (defined in CRC_SLINKx)	CRC_SLINKx	Port
daq_reset (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
data (defined in event_generator)	event_generator	Port
data (defined in crc_gen_usb_32to16)	crc_gen_usb_32to16	Port
data (defined in rcv_pckt_s)	rcv_pckt_s	Port
data (defined in event_generator)	event_generator	Port
data (defined in crc_gen_32b)	crc_gen_32b	Port
data (defined in rcv_pckt_s_XGMII)	rcv_pckt_s_XGMII	Port
data_evt (defined in Core_logic)	Core_logic	Port
data_evt (defined in build_pckt_s)	build_pckt_s	Port
data_evt (defined in Core_logic)	Core_logic	Port
data_evt (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
data_fed (defined in fed_itf)	fed_itf	Port
data_fed (defined in Core_logic)	Core_logic	Port
data_fed (defined in fed_itf)	fed_itf	Port
data_fed (defined in Core_logic)	Core_logic	Port
data_i (defined in xaui_wd_align)	xaui_wd_align	Port
data_o (defined in xaui_wd_align)	xaui_wd_align	Port
data_pckt (defined in Core_logic)	Core_logic	Port
data_pckt (defined in build_pckt_s)	build_pckt_s	Port
data_pckt (defined in Core_logic)	Core_logic	Port
data_pckt (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
data_rcv (defined in Core_logic)	Core_logic	Port
data_rcv (defined in Core_logic)	Core_logic	Port
data_rd (defined in fed_itf)	fed_itf	Port
data_rd (defined in Core_logic)	Core_logic	Port
data_rd (defined in fed_itf)	fed_itf	Port
data_rd (defined in Core_logic)	Core_logic	Port
data_valid (defined in crc_gen_usb_32to16)	crc_gen_usb_32to16	Port
data_valid (defined in crc_gen_usb_32to16)	crc_gen_usb_32to16	Port
data_valid (defined in serdes5_wrapper)	serdes5_wrapper	Port
data_valid (defined in crc_gen_32b)	crc_gen_32b	Port
data_valid (defined in crc_gen_32b)	crc_gen_32b	Port
DATA_VALID (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
DATA_VALID (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
DATA_VALID (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
DATA_VALID_IN (defined in SCRAMBLER)	SCRAMBLER	Port
DATA_VALID_IN (defined in DESCRAMBLER)	DESCRAMBLER	Port
data_wr (defined in fed_itf)	fed_itf	Port
data_wr (defined in Core_logic)	Core_logic	Port
data_wr (defined in fed_itf)	fed_itf	Port
data_wr (defined in Core_logic)	Core_logic	Port
datai (defined in rcv_pckt_s)	rcv_pckt_s	Port
datai (defined in rcv_pckt_s_XGMII)	rcv_pckt_s_XGMII	Port
datao (defined in build_pckt_s)	build_pckt_s	Port
datao (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
datar (defined in FIFO_sync)	FIFO_sync	Port
datar (defined in FIFO_sync)	FIFO_sync	Port
dataw (defined in FIFO_sync)	FIFO_sync	Port
dataw (defined in FIFO_sync)	FIFO_sync	Port
din (defined in lpm_fifo)	lpm_fifo	Port
din (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
din (defined in lpm_fifo)	lpm_fifo	Port
din (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
dina (defined in Memory)	Memory	Port
dina (defined in Memory)	Memory	Port
Dis_pd (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
DONT_RESET_ON_DATA_ERROR (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
DONT_RESET_ON_DATA_ERROR (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
DONT_RESET_ON_DATA_ERROR (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
DONT_RESET_ON_DATA_ERROR_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
DONT_RESET_ON_DATA_ERROR_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
DONT_RESET_ON_DATA_ERROR_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
dout (defined in lpm_fifo)	lpm_fifo	Port
dout (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
dout (defined in lpm_fifo)	lpm_fifo	Port
dout (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
dout (defined in cmsCRC64)	cmsCRC64	Port
dout_vld (defined in cmsCRC64)	cmsCRC64	Port
doutb (defined in Memory)	Memory	Port
doutb (defined in Memory)	Memory	Port
DRP_clk (defined in DaqLSCXG)	DaqLSCXG	Port
DRPADDR_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
DRPADDR_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
DRPADDR_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
DRPclk (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
DRPCLK_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
DRPCLK_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
DRPCLK_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
DRPDI_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
DRPDI_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
DRPDI_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
DRPDO_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
DRPDO_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
DRPDO_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
DRPEN_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
DRPEN_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
DRPEN_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
DRPRDY_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
DRPRDY_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
DRPRDY_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
DRPWE_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
DRPWE_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
DRPWE_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
EmacPhyTxC (defined in XGbEPCS32)	XGbEPCS32	Port
EmacPhyTxD (defined in XGbEPCS32)	XGbEPCS32	Port
empty (defined in lpm_fifo)	lpm_fifo	Port
empty (defined in FIFO_sync)	FIFO_sync	Port
empty (defined in lpm_fifo)	lpm_fifo	Port
empty (defined in FIFO_sync)	FIFO_sync	Port
en_stop (defined in check_event)	check_event	Port
ena_ack (defined in Core_logic)	Core_logic	Port
ena_ack (defined in rcv_pckt_s)	rcv_pckt_s	Port
ena_ack (defined in Core_logic)	Core_logic	Port
ena_ack (defined in rcv_pckt_s_XGMII)	rcv_pckt_s_XGMII	Port
ena_cmd (defined in Core_logic)	Core_logic	Port
ena_cmd (defined in rcv_pckt_s)	rcv_pckt_s	Port
ena_cmd (defined in Core_logic)	Core_logic	Port
ena_cmd (defined in rcv_pckt_s_XGMII)	rcv_pckt_s_XGMII	Port
ena_PCIe (defined in trigger_gen)	trigger_gen	Port
ena_PCIe (defined in trigger_gen)	trigger_gen	Port
enable (defined in CRC_SLINKx)	CRC_SLINKx	Port
enable (defined in CRC_SLINKx)	CRC_SLINKx	Port
end_blk_fed (defined in fed_itf)	fed_itf	Port
end_blk_fed (defined in Core_logic)	Core_logic	Port
end_blk_fed (defined in fed_itf)	fed_itf	Port
end_blk_fed (defined in Core_logic)	Core_logic	Port
end_evt (defined in trigger_gen)	trigger_gen	Port
end_evt (defined in memory_rnd)	memory_rnd	Port
end_evt (defined in trigger_gen)	trigger_gen	Port
end_evt (defined in memory_rnd)	memory_rnd	Port
end_pckt (defined in build_pckt_s)	build_pckt_s	Port
end_pckt (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
end_snd_pckt (defined in Core_logic)	Core_logic	Port
end_snd_pckt (defined in Core_logic)	Core_logic	Port
enSFP (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
eoc (defined in crc_gen_usb_32to16)	crc_gen_usb_32to16	Port
eoc (defined in crc_gen_usb_32to16)	crc_gen_usb_32to16	Port
eoc (defined in crc_gen_32b)	crc_gen_32b	Port
eoc (defined in crc_gen_32b)	crc_gen_32b	Port
EQ_MODE (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Generic
EQ_MODE (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Generic
EQ_MODE (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Generic
error_gen (defined in build_pckt_s)	build_pckt_s	Port
error_gen (defined in rcv_pckt_s)	rcv_pckt_s	Port
error_gen (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
error_gen (defined in rcv_pckt_s_XGMII)	rcv_pckt_s_XGMII	Port
EventBufAddr (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
EventBufAddr_we (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
EventData_in (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
EventData_re (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
EventData_we (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
evt_buf_full (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
evt_clk (defined in event_generator)	event_generator	Port
evt_clk (defined in event_generator)	event_generator	Port
evt_data_rdy (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
EXAMPLE_SIM_GTRESET_SPEEDUP (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Generic
EXAMPLE_SIM_GTRESET_SPEEDUP (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Generic
EXAMPLE_SIM_GTRESET_SPEEDUP (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Generic
EXAMPLE_SIMULATION (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Generic
EXAMPLE_SIMULATION (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Generic
EXAMPLE_SIMULATION (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Generic
EXAMPLE_USE_CHIPSCOPE (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Generic
EXAMPLE_USE_CHIPSCOPE (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Generic
EXAMPLE_USE_CHIPSCOPE (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Generic
EYESCANDATAERROR_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
EYESCANDATAERROR_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
EYESCANDATAERROR_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
fifo_deep (defined in FIFO_sync)	FIFO_sync	Generic
fifo_deep (defined in FIFO_sync)	FIFO_sync	Generic
Free_clki (defined in resync)	resync	Port
Free_clki (defined in resync)	resync	Port
Free_clki (defined in resync)	resync	Port
Free_clki (defined in resync)	resync	Port
Free_clki (defined in resync)	resync	Port
Free_clki (defined in resync)	resync	Port
Free_clki (defined in resync)	resync	Port
Free_clki (defined in resync)	resync	Port
frequency (defined in freq_measure)	freq_measure	Port
frequency (defined in freq_measure)	freq_measure	Port
full (defined in lpm_fifo)	lpm_fifo	Port
full (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
full (defined in lpm_fifo)	lpm_fifo	Port
full (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
func (defined in fed_itf)	fed_itf	Port
func (defined in Core_logic)	Core_logic	Port
func (defined in fed_itf)	fed_itf	Port
func (defined in Core_logic)	Core_logic	Port
generator (defined in fed_itf)	fed_itf	Generic
generator (defined in fed_itf)	fed_itf	Generic
Greset_clk (defined in Core_logic)	Core_logic	Port
Greset_clk (defined in rcv_pckt_s)	rcv_pckt_s	Port
Greset_clk (defined in Core_logic)	Core_logic	Port
Greset_clk (defined in rcv_pckt_s_XGMII)	rcv_pckt_s_XGMII	Port
Greset_CLK (defined in fed_itf)	fed_itf	Port
Greset_CLK (defined in build_pckt_s)	build_pckt_s	Port
Greset_CLK (defined in fed_itf)	fed_itf	Port
Greset_CLK (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
Greset_clkT (defined in rcv_pckt_s)	rcv_pckt_s	Port
Greset_clkT (defined in rcv_pckt_s_XGMII)	rcv_pckt_s_XGMII	Port
Greset_sysCLK (defined in fed_itf)	fed_itf	Port
Greset_sysCLK (defined in fed_itf)	fed_itf	Port
GT0_DATA_VALID_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_DATA_VALID_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_DATA_VALID_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_DRPADDR_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_DRPADDR_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_DRPADDR_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_DRPCLK_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_DRPCLK_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_DRPCLK_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_DRPDI_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_DRPDI_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_DRPDI_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_DRPDO_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_DRPDO_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_DRPDO_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_DRPEN_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_DRPEN_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_DRPEN_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_DRPRDY_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_DRPRDY_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_DRPRDY_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_DRPWE_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_DRPWE_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_DRPWE_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_EYESCANDATAERROR_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_EYESCANDATAERROR_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_EYESCANDATAERROR_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_GTREFCLK0_COMMON_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_GTREFCLK0_COMMON_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_GTREFCLK0_COMMON_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_GTRXRESET_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_GTRXRESET_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_GTRXRESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_GTTXRESET_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_GTTXRESET_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_GTTXRESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_GTXRXN_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_GTXRXN_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_GTXRXN_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_GTXRXP_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_GTXRXP_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_GTXRXP_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_GTXTXN_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_GTXTXN_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_GTXTXN_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_GTXTXP_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_GTXTXP_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_GTXTXP_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_LOOPBACK_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_LOOPBACK_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_QPLLLOCK_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_QPLLLOCK_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_QPLLLOCK_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_QPLLLOCKDETCLK_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_QPLLLOCKDETCLK_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_QPLLLOCKDETCLK_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_QPLLREFCLKLOST_OUT (defined in serdes5GpdProd)	serdes5GpdProd	Port
GT0_QPLLREFCLKLOST_OUT (defined in SFP2_v2_7)	SFP2_v2_7	Port
GT0_QPLLREFCLKLOST_OUT (defined in SFP3_v2_7)	SFP3_v2_7	Port
GT0_QPLLRESET_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_QPLLRESET_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_QPLLRESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RX_FSM_RESET_DONE_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RX_FSM_RESET_DONE_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RX_FSM_RESET_DONE_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXBUFRESET_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXBUFRESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXBUFSTATUS_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXBUFSTATUS_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXBUFSTATUS_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXBYTEISALIGNED_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXBYTEREALIGN_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXCDRLOCK_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXCDRLOCK_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXCDRLOCK_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXCHARISCOMMA_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXCHARISK_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXCLKCORCNT_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXCOMMADET_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXDATA_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXDATA_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXDATA_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXDATAVALID_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXDATAVALID_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXDFEAGCHOLD_IN (defined in serdes5GpdProd)	serdes5GpdProd	Port
GT0_RXDFEAGCHOLD_IN (defined in SFP2_v2_7)	SFP2_v2_7	Port
GT0_RXDFEAGCHOLD_IN (defined in SFP3_v2_7)	SFP3_v2_7	Port
GT0_RXDFELFHOLD_IN (defined in serdes5GpdProd)	serdes5GpdProd	Port
GT0_RXDFELFHOLD_IN (defined in SFP2_v2_7)	SFP2_v2_7	Port
GT0_RXDFELFHOLD_IN (defined in SFP3_v2_7)	SFP3_v2_7	Port
GT0_RXDISPERR_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXGEARBOXSLIP_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXGEARBOXSLIP_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXHEADER_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXHEADER_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXHEADERVALID_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXHEADERVALID_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXLPMEN_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXLPMEN_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXMCOMMAALIGNEN_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXNOTINTABLE_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXOUTCLK_OUT (defined in serdes5GpdProd)	serdes5GpdProd	Port
GT0_RXOUTCLK_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXOUTCLK_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXPCOMMAALIGNEN_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXPCSRESET_IN (defined in SFP2_v2_7)	SFP2_v2_7	Port
GT0_RXPCSRESET_IN (defined in SFP3_v2_7)	SFP3_v2_7	Port
GT0_RXPD_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXPD_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXPD_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXPMARESET_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXPMARESET_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXPMARESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXPRBSCNTRESET_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXPRBSCNTRESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXPRBSERR_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXPRBSERR_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXPRBSSEL_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXPRBSSEL_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXRESETDONE_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXRESETDONE_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXRESETDONE_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXUSERRDY_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXUSERRDY_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXUSERRDY_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXUSRCLK2_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXUSRCLK2_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXUSRCLK2_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_RXUSRCLK_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_RXUSRCLK_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_RXUSRCLK_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_TX_FSM_RESET_DONE_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_TX_FSM_RESET_DONE_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_TX_FSM_RESET_DONE_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_TXCHARISK_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_TXDATA_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_TXDATA_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_TXDATA_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_TXDIFFCTRL_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_TXDIFFCTRL_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_TXHEADER_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_TXHEADER_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_TXINHIBIT_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_TXINHIBIT_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_TXMAINCURSOR_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_TXMAINCURSOR_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_TXOUTCLK_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_TXOUTCLK_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_TXOUTCLK_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_TXOUTCLKFABRIC_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_TXOUTCLKFABRIC_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_TXOUTCLKFABRIC_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_TXOUTCLKPCS_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_TXOUTCLKPCS_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_TXOUTCLKPCS_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_TXPCSRESET_IN (defined in SFP2_v2_7)	SFP2_v2_7	Port
GT0_TXPCSRESET_IN (defined in SFP3_v2_7)	SFP3_v2_7	Port
GT0_TXPD_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_TXPD_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_TXPD_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_TXPRBSSEL_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_TXPRBSSEL_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_TXRESETDONE_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_TXRESETDONE_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_TXRESETDONE_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_TXSEQUENCE_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_TXSEQUENCE_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_TXUSERRDY_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_TXUSERRDY_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_TXUSERRDY_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_TXUSRCLK2_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_TXUSRCLK2_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_TXUSRCLK2_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT0_TXUSRCLK_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT0_TXUSRCLK_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT0_TXUSRCLK_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_DATA_VALID_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_DATA_VALID_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_DATA_VALID_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_DRPADDR_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_DRPADDR_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_DRPADDR_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_DRPCLK_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_DRPCLK_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_DRPCLK_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_DRPDI_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_DRPDI_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_DRPDI_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_DRPDO_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_DRPDO_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_DRPDO_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_DRPEN_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_DRPEN_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_DRPEN_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_DRPRDY_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_DRPRDY_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_DRPRDY_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_DRPWE_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_DRPWE_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_DRPWE_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_EYESCANDATAERROR_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_EYESCANDATAERROR_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_EYESCANDATAERROR_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_GTRXRESET_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_GTRXRESET_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_GTRXRESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_GTTXRESET_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_GTTXRESET_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_GTTXRESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_GTXRXN_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_GTXRXN_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_GTXRXN_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_GTXRXP_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_GTXRXP_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_GTXRXP_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_GTXTXN_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_GTXTXN_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_GTXTXN_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_GTXTXP_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_GTXTXP_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_GTXTXP_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_LOOPBACK_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_LOOPBACK_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RX_FSM_RESET_DONE_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RX_FSM_RESET_DONE_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RX_FSM_RESET_DONE_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXBUFRESET_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXBUFRESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXBUFSTATUS_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXBUFSTATUS_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXBUFSTATUS_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXBYTEISALIGNED_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXBYTEREALIGN_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXCDRLOCK_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXCDRLOCK_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXCDRLOCK_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXCHARISCOMMA_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXCHARISK_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXCLKCORCNT_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXCOMMADET_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXDATA_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXDATA_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXDATA_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXDATAVALID_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXDATAVALID_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXDFEAGCHOLD_IN (defined in serdes5GpdProd)	serdes5GpdProd	Port
GT1_RXDFEAGCHOLD_IN (defined in SFP2_v2_7)	SFP2_v2_7	Port
GT1_RXDFEAGCHOLD_IN (defined in SFP3_v2_7)	SFP3_v2_7	Port
GT1_RXDFELFHOLD_IN (defined in serdes5GpdProd)	serdes5GpdProd	Port
GT1_RXDFELFHOLD_IN (defined in SFP2_v2_7)	SFP2_v2_7	Port
GT1_RXDFELFHOLD_IN (defined in SFP3_v2_7)	SFP3_v2_7	Port
GT1_RXDISPERR_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXGEARBOXSLIP_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXGEARBOXSLIP_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXHEADER_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXHEADER_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXHEADERVALID_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXHEADERVALID_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXLPMEN_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXLPMEN_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXMCOMMAALIGNEN_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXNOTINTABLE_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXOUTCLK_OUT (defined in serdes5GpdProd)	serdes5GpdProd	Port
GT1_RXOUTCLK_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXOUTCLK_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXPCOMMAALIGNEN_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXPCSRESET_IN (defined in SFP2_v2_7)	SFP2_v2_7	Port
GT1_RXPCSRESET_IN (defined in SFP3_v2_7)	SFP3_v2_7	Port
GT1_RXPD_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXPD_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXPD_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXPMARESET_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXPMARESET_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXPMARESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXPRBSCNTRESET_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXPRBSCNTRESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXPRBSERR_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXPRBSERR_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXPRBSSEL_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXPRBSSEL_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXRESETDONE_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXRESETDONE_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXRESETDONE_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXUSERRDY_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXUSERRDY_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXUSERRDY_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXUSRCLK2_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXUSRCLK2_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXUSRCLK2_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_RXUSRCLK_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_RXUSRCLK_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_RXUSRCLK_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_TX_FSM_RESET_DONE_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_TX_FSM_RESET_DONE_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_TX_FSM_RESET_DONE_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_TXCHARISK_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_TXDATA_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_TXDATA_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_TXDATA_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_TXDIFFCTRL_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_TXDIFFCTRL_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_TXHEADER_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_TXHEADER_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_TXINHIBIT_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_TXINHIBIT_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_TXMAINCURSOR_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_TXMAINCURSOR_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_TXOUTCLK_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_TXOUTCLK_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_TXOUTCLK_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_TXOUTCLKFABRIC_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_TXOUTCLKFABRIC_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_TXOUTCLKFABRIC_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_TXOUTCLKPCS_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_TXOUTCLKPCS_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_TXOUTCLKPCS_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_TXPCSRESET_IN (defined in SFP2_v2_7)	SFP2_v2_7	Port
GT1_TXPCSRESET_IN (defined in SFP3_v2_7)	SFP3_v2_7	Port
GT1_TXPD_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_TXPD_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_TXPD_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_TXPRBSSEL_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_TXPRBSSEL_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_TXRESETDONE_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_TXRESETDONE_OUT (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_TXRESETDONE_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_TXSEQUENCE_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_TXSEQUENCE_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_TXUSERRDY_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_TXUSERRDY_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_TXUSERRDY_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_TXUSRCLK2_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_TXUSRCLK2_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_TXUSRCLK2_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT1_TXUSRCLK_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT1_TXUSRCLK_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
GT1_TXUSRCLK_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_DATA_VALID_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_DATA_VALID_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_DRPADDR_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_DRPADDR_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_DRPCLK_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_DRPCLK_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_DRPDI_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_DRPDI_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_DRPDO_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_DRPDO_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_DRPEN_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_DRPEN_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_DRPRDY_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_DRPRDY_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_DRPWE_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_DRPWE_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_EYESCANDATAERROR_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_EYESCANDATAERROR_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_GTRXRESET_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_GTRXRESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_GTTXRESET_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_GTTXRESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_GTXRXN_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_GTXRXN_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_GTXRXP_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_GTXRXP_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_GTXTXN_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_GTXTXN_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_GTXTXP_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_GTXTXP_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_LOOPBACK_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RX_FSM_RESET_DONE_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RX_FSM_RESET_DONE_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXBUFRESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXBUFSTATUS_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXBUFSTATUS_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXBYTEISALIGNED_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXBYTEREALIGN_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXCDRLOCK_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXCDRLOCK_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXCHARISCOMMA_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXCHARISK_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXCLKCORCNT_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXCOMMADET_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXDATA_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXDATA_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXDATAVALID_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXDFEAGCHOLD_IN (defined in serdes5GpdProd)	serdes5GpdProd	Port
GT2_RXDFEAGCHOLD_IN (defined in SFP3_v2_7)	SFP3_v2_7	Port
GT2_RXDFELFHOLD_IN (defined in serdes5GpdProd)	serdes5GpdProd	Port
GT2_RXDFELFHOLD_IN (defined in SFP3_v2_7)	SFP3_v2_7	Port
GT2_RXDISPERR_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXGEARBOXSLIP_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXHEADER_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXHEADERVALID_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXLPMEN_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXMCOMMAALIGNEN_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXNOTINTABLE_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXOUTCLK_OUT (defined in serdes5GpdProd)	serdes5GpdProd	Port
GT2_RXOUTCLK_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXPCOMMAALIGNEN_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXPCSRESET_IN (defined in SFP3_v2_7)	SFP3_v2_7	Port
GT2_RXPD_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXPD_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXPMARESET_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXPMARESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXPRBSCNTRESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXPRBSERR_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXPRBSSEL_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXRESETDONE_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXRESETDONE_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXUSERRDY_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXUSERRDY_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXUSRCLK2_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXUSRCLK2_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_RXUSRCLK_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_RXUSRCLK_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_TX_FSM_RESET_DONE_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_TX_FSM_RESET_DONE_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_TXCHARISK_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_TXDATA_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_TXDATA_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_TXDIFFCTRL_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_TXHEADER_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_TXINHIBIT_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_TXMAINCURSOR_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_TXOUTCLK_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_TXOUTCLK_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_TXOUTCLKFABRIC_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_TXOUTCLKFABRIC_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_TXOUTCLKPCS_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_TXOUTCLKPCS_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_TXPCSRESET_IN (defined in SFP3_v2_7)	SFP3_v2_7	Port
GT2_TXPD_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_TXPD_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_TXPRBSSEL_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_TXRESETDONE_OUT (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_TXRESETDONE_OUT (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_TXSEQUENCE_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_TXUSERRDY_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_TXUSERRDY_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_TXUSRCLK2_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_TXUSRCLK2_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT2_TXUSRCLK_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
GT2_TXUSRCLK_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
GT_SIM_GTRESET_SPEEDUP (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Generic
GT_SIM_GTRESET_SPEEDUP (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Generic
GT_SIM_GTRESET_SPEEDUP (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Generic
GT_TYPE (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Generic
GT_TYPE (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Generic
GT_TYPE (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Generic
GT_TYPE (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Generic
GT_TYPE (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Generic
GT_TYPE (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Generic
GTRXRESET (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
GTRXRESET (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
GTRXRESET (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
GTRXRESET_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
GTRXRESET_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
GTRXRESET_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
GTTXRESET (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
GTTXRESET (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
GTTXRESET (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
GTTXRESET_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
GTTXRESET_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
GTTXRESET_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
gtx_refclk (defined in DaqLSCXG)	DaqLSCXG	Port
gtx_refclk_n (defined in DaqLSCXG)	DaqLSCXG	Port
gtx_refclk_p (defined in DaqLSCXG)	DaqLSCXG	Port
gtx_reset (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
GTX_RXD (defined in XGbEPCS32)	XGbEPCS32	Port
GTX_RXDVLD (defined in XGbEPCS32)	XGbEPCS32	Port
GTX_RXGEARBOXSLIP_OUT (defined in XGbEPCS32)	XGbEPCS32	Port
GTX_RXGOOD (defined in XGbEPCS32)	XGbEPCS32	Port
GTX_RXHEADER (defined in XGbEPCS32)	XGbEPCS32	Port
GTX_RXHEADERVLD (defined in XGbEPCS32)	XGbEPCS32	Port
gtx_rxresetdone (defined in XGMII_serdes_wapper)	XGMII_serdes_wapper	Port
GTX_TX_PAUSE (defined in XGbEPCS32)	XGbEPCS32	Port
GTX_TXD (defined in XGbEPCS32)	XGbEPCS32	Port
GTX_TXHEADER (defined in XGbEPCS32)	XGbEPCS32	Port
GTXRXN_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
GTXRXN_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
GTXRXN_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
GTXRXP_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
GTXRXP_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
GTXRXP_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
GTXTXN_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
GTXTXN_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
GTXTXN_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
GTXTXP_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
GTXTXP_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
GTXTXP_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
idle_state (defined in Core_logic)	Core_logic	Port
idle_state (defined in build_pckt_s)	build_pckt_s	Port
idle_state (defined in Core_logic)	Core_logic	Port
idle_state (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
inc_ddr_pa (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
inc_err (defined in check_event)	check_event	Port
inh_TX (defined in XGbEPCS32)	XGbEPCS32	Port
init_pckt (defined in Core_logic)	Core_logic	Port
init_pckt (defined in build_pckt_s)	build_pckt_s	Port
init_pckt (defined in Core_logic)	Core_logic	Port
init_pckt (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
inject_err (defined in SLINK_opt)	SLINK_opt	Port
inject_err (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
inject_err (defined in cmsCRC64)	cmsCRC64	Port
input (defined in resync)	resync	Port
input (defined in resync)	resync	Port
input (defined in resync)	resync	Port
input (defined in resync)	resync	Port
input (defined in resync)	resync	Port
input (defined in resync)	resync	Port
input (defined in resync)	resync	Port
input (defined in resync)	resync	Port
interval_retrans (defined in Core_logic)	Core_logic	Generic
interval_retrans (defined in Core_logic)	Core_logic	Generic
ipb_ack (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
ipb_addr (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
ipb_clk (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
ipb_rdata (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
ipb_strobe (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
ipb_wdata (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
ipb_write (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
k_byte (defined in build_pckt_s)	build_pckt_s	Port
k_byte (defined in rcv_pckt_s)	rcv_pckt_s	Port
k_byte (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
k_byte (defined in rcv_pckt_s_XGMII)	rcv_pckt_s_XGMII	Port
len_pckt (defined in Core_logic)	Core_logic	Port
len_pckt (defined in build_pckt_s)	build_pckt_s	Port
len_pckt (defined in Core_logic)	Core_logic	Port
len_pckt (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
LINK_LFF (defined in SLINK_opt)	SLINK_opt	Port
LINK_LFF (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
LinkAlmostFull (defined in fed_itf)	fed_itf	Port
LinkAlmostFull (defined in fed_itf)	fed_itf	Port
LINKCtrl (defined in SLINK_opt)	SLINK_opt	Port
LINKCtrl (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
LinkCtrl (defined in DaqLSCXG)	DaqLSCXG	Port
LINKData (defined in SLINK_opt)	SLINK_opt	Port
LINKData (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
LinkData (defined in DaqLSCXG)	DaqLSCXG	Port
LinkDown (defined in DaqLSCXG)	DaqLSCXG	Port
LINKDown (defined in SLINK_opt)	SLINK_opt	Port
LINKDown (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
LinkFull (defined in DaqLSCXG)	DaqLSCXG	Port
LINKWe (defined in SLINK_opt)	SLINK_opt	Port
LINKWe (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
LinkWe (defined in DaqLSCXG)	DaqLSCXG	Port
LOAD_SEED (defined in generate_3)	generate_3	Port
LOAD_SEED (defined in generate_3)	generate_3	Port
LOOPBACK_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
LOOPBACK_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
low_clk (defined in event_generator)	event_generator	Port
low_clk (defined in event_generator)	event_generator	Port
LSC_ID (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
MMCM_LOCK (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
MMCM_LOCK (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
MMCM_LOCK (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
MMCM_LOCK (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
MMCM_LOCK (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
MMCM_LOCK (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
MMCM_RESET (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
MMCM_RESET (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
MMCM_RESET (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
MMCM_RESET (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
MMCM_RESET (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
MMCM_RESET (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
mon_evt_cnt (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
MonBuf_avl (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
MonBuf_empty (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
MonBufOverWrite (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
MonBufOvfl (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
mydefs (defined in DaqLSCXG)	DaqLSCXG	use clause
N_SFP (defined in DaqLSCXG)	DaqLSCXG	Generic
numeric_std (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	use clause
NUMERIC_STD (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	use clause
NUMERIC_STD (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	use clause
NUMERIC_STD (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	use clause
NUMERIC_STD (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	use clause
NUMERIC_STD (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	use clause
NUMERIC_STD (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	use clause
output (defined in resync)	resync	Port
output (defined in resync)	resync	Port
output (defined in resync)	resync	Port
output (defined in resync)	resync	Port
output (defined in resync)	resync	Port
output (defined in resync)	resync	Port
output (defined in resync)	resync	Port
output (defined in resync)	resync	Port
PCIe_clk (defined in event_generator)	event_generator	Port
PCIe_clk (defined in event_generator)	event_generator	Port
PCIe_cs (defined in event_generator)	event_generator	Port
PCIe_cs (defined in event_generator)	event_generator	Port
PCIe_dt (defined in memory_rnd)	memory_rnd	Port
PCIe_dt (defined in memory_rnd)	memory_rnd	Port
PCIe_dti (defined in event_generator)	event_generator	Port
PCIe_dti (defined in event_generator)	event_generator	Port
PCIe_dto (defined in event_generator)	event_generator	Port
PCIe_dto (defined in event_generator)	event_generator	Port
PCIe_func (defined in event_generator)	event_generator	Port
PCIe_func (defined in event_generator)	event_generator	Port
PCIe_wen (defined in event_generator)	event_generator	Port
PCIe_wen (defined in event_generator)	event_generator	Port
PCS_lock (defined in XGMII_serdes_wapper)	XGMII_serdes_wapper	Port
PCS_RSVD_ATTR_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Generic
PCS_RSVD_ATTR_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Generic
PCS_RSVD_ATTR_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Generic
PHALIGNMENT_DONE (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
PHALIGNMENT_DONE (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
PHALIGNMENT_DONE (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
PHALIGNMENT_DONE (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
PHALIGNMENT_DONE (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
PHALIGNMENT_DONE (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
PHASE_ALIGNMENT_MANUAL (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Generic
PHASE_ALIGNMENT_MANUAL (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Generic
PHASE_ALIGNMENT_MANUAL (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Generic
PHASE_ALIGNMENT_MANUAL (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Generic
PHASE_ALIGNMENT_MANUAL (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Generic
PHASE_ALIGNMENT_MANUAL (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Generic
PhyEmacRxC (defined in XGbEPCS32)	XGbEPCS32	Port
PhyEmacRxD (defined in XGbEPCS32)	XGbEPCS32	Port
PMA_RSV_IN (defined in serdes5GpdProd)	serdes5GpdProd	Generic
PMA_RSV_IN (defined in SFP2_v2_7)	SFP2_v2_7	Generic
PMA_RSV_IN (defined in SFP3_v2_7)	SFP3_v2_7	Generic
QPLL_FBDIV_TOP (defined in serdes5GpdProd)	serdes5GpdProd	Generic
QPLL_FBDIV_TOP (defined in SFP2_v2_7)	SFP2_v2_7	Generic
QPLL_FBDIV_TOP (defined in SFP3_v2_7)	SFP3_v2_7	Generic
QPLL_RESET (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
QPLL_RESET (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
QPLL_RESET (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
QPLL_RESET (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
QPLL_RESET (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
QPLL_RESET (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
QPLLCLK_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
QPLLCLK_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
QPLLCLK_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
QPLLLOCK (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
QPLLLOCK (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
QPLLLOCK (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
QPLLLOCK (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
QPLLLOCK (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
QPLLLOCK (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
qplllock (defined in serdes5_wrapper)	serdes5_wrapper	Port
QPLLREFCLK_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
QPLLREFCLK_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
QPLLREFCLK_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
QPLLREFCLKLOST (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
QPLLREFCLKLOST (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
QPLLREFCLKLOST (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
QPLLREFCLKLOST (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
QPLLREFCLKLOST (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
QPLLREFCLKLOST (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
rd_clk (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
rd_clk (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
rd_dt (defined in Core_logic)	Core_logic	Port
rd_dt (defined in build_pckt_s)	build_pckt_s	Port
rd_dt (defined in Core_logic)	Core_logic	Port
rd_dt (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
rd_en (defined in lpm_fifo)	lpm_fifo	Port
rd_en (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
rd_en (defined in lpm_fifo)	lpm_fifo	Port
rd_en (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
rd_rst (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
rd_rst (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
read_bck (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
read_CE (defined in SLINK_opt)	SLINK_opt	Port
read_CE (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
read_ce (defined in fed_itf)	fed_itf	Port
read_ce (defined in fed_itf)	fed_itf	Port
RECCLK_MONITOR_RESTART (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
RECCLK_MONITOR_RESTART (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
RECCLK_MONITOR_RESTART (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
RECCLK_STABLE (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
RECCLK_STABLE (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
RECCLK_STABLE (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
refclk (defined in serdes5_wrapper)	serdes5_wrapper	Port
ren (defined in FIFO_sync)	FIFO_sync	Port
ren (defined in FIFO_sync)	FIFO_sync	Port
req_reset_resync (defined in Core_logic)	Core_logic	Port
req_reset_resync (defined in Core_logic)	Core_logic	Port
reset (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
reset_clk (defined in Core_logic)	Core_logic	Port
reset_clk (defined in rcv_pckt_s)	rcv_pckt_s	Port
reset_clk (defined in Core_logic)	Core_logic	Port
reset_clk (defined in rcv_pckt_s_XGMII)	rcv_pckt_s_XGMII	Port
reset_CLK (defined in fed_itf)	fed_itf	Port
reset_CLK (defined in build_pckt_s)	build_pckt_s	Port
reset_CLK (defined in fed_itf)	fed_itf	Port
reset_CLK (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
reset_clkT (defined in rcv_pckt_s)	rcv_pckt_s	Port
reset_clkT (defined in rcv_pckt_s_XGMII)	rcv_pckt_s_XGMII	Port
RESET_PHALIGNMENT (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
RESET_PHALIGNMENT (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
RESET_PHALIGNMENT (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
RESET_PHALIGNMENT (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
RESET_PHALIGNMENT (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
RESET_PHALIGNMENT (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
Reset_sync (defined in reset_resync)	reset_resync	Port
Reset_sync (defined in reset_resync)	reset_resync	Port
Reset_sync (defined in reset_resync)	reset_resync	Port
Reset_sync (defined in reset_resync)	reset_resync	Port
Reset_sync (defined in reset_resync)	reset_resync	Port
Reset_sync (defined in reset_resync)	reset_resync	Port
reset_sysCLK (defined in fed_itf)	fed_itf	Port
reset_sysCLK (defined in fed_itf)	fed_itf	Port
RESET_TXSync (defined in XGbEPCS32)	XGbEPCS32	Port
retransmit (defined in Core_logic)	Core_logic	Port
retransmit (defined in Core_logic)	Core_logic	Port
retransmit_ena (defined in fed_itf)	fed_itf	Port
retransmit_ena (defined in fed_itf)	fed_itf	Port
RETRY_COUNTER (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
RETRY_COUNTER (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
RETRY_COUNTER (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
RETRY_COUNTER (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
RETRY_COUNTER (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
RETRY_COUNTER (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
RETRY_COUNTER_BITWIDTH (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Generic
RETRY_COUNTER_BITWIDTH (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Generic
RETRY_COUNTER_BITWIDTH (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Generic
RETRY_COUNTER_BITWIDTH (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Generic
RETRY_COUNTER_BITWIDTH (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Generic
RETRY_COUNTER_BITWIDTH (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Generic
rnd (defined in generate_3)	generate_3	Port
rnd (defined in generate_3)	generate_3	Port
rst (defined in lpm_fifo)	lpm_fifo	Port
rst (defined in lpm_fifo)	lpm_fifo	Port
RST_EvtClk (defined in memory_rnd)	memory_rnd	Port
RST_EvtClk (defined in memory_rnd)	memory_rnd	Port
Rst_Evtclk (defined in trigger_gen)	trigger_gen	Port
Rst_Evtclk (defined in trigger_gen)	trigger_gen	Port
rst_length (defined in Core_logic)	Core_logic	Generic
rst_length (defined in Core_logic)	Core_logic	Generic
RST_lowClk (defined in memory_rnd)	memory_rnd	Port
RST_lowClk (defined in memory_rnd)	memory_rnd	Port
Rst_Pciclk (defined in trigger_gen)	trigger_gen	Port
Rst_Pciclk (defined in trigger_gen)	trigger_gen	Port
RST_PCIClk (defined in memory_rnd)	memory_rnd	Port
RST_PCIClk (defined in memory_rnd)	memory_rnd	Port
rstb (defined in Memory)	Memory	Port
rstb (defined in Memory)	Memory	Port
rstCntr (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
run_mode (defined in trigger_gen)	trigger_gen	Port
run_mode (defined in trigger_gen)	trigger_gen	Port
RUN_PHALIGNMENT (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
RUN_PHALIGNMENT (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
RUN_PHALIGNMENT (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
RUN_PHALIGNMENT (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
RUN_PHALIGNMENT (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
RUN_PHALIGNMENT (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
RX_DATA_WIDTH (defined in DESCRAMBLER)	DESCRAMBLER	Generic
RX_DFE_KL_CFG2_IN (defined in serdes5GpdProd)	serdes5GpdProd	Generic
RX_DFE_KL_CFG2_IN (defined in SFP2_v2_7)	SFP2_v2_7	Generic
RX_DFE_KL_CFG2_IN (defined in SFP3_v2_7)	SFP3_v2_7	Generic
RX_FSM_RESET_DONE (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
RX_FSM_RESET_DONE (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
RX_FSM_RESET_DONE (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
RX_QPLL_USED (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Generic
RX_QPLL_USED (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Generic
RX_QPLL_USED (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Generic
RX_QPLL_USED (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Generic
RX_QPLL_USED (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Generic
RX_QPLL_USED (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Generic
RXBUFRESET_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXBUFRESET_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXBUFSTATUS_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
RXBUFSTATUS_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXBUFSTATUS_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
rxbyteisaligned (defined in serdes5_wrapper)	serdes5_wrapper	Port
RXBYTEISALIGNED_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
rxbyterealign (defined in serdes5_wrapper)	serdes5_wrapper	Port
RXBYTEREALIGN_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
rxcdrlock (defined in serdes5_wrapper)	serdes5_wrapper	Port
RXCDRLOCK_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
RXCDRLOCK_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXCDRLOCK_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
rxchariscomma (defined in serdes5_wrapper)	serdes5_wrapper	Port
RXCHARISCOMMA_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
rxcharisk (defined in serdes5_wrapper)	serdes5_wrapper	Port
RXCHARISK_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
RXCLKCORCNT_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
rxcommadet (defined in serdes5_wrapper)	serdes5_wrapper	Port
RXCOMMADET_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
rxdata (defined in serdes5_wrapper)	serdes5_wrapper	Port
RXDATA_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
RXDATA_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXDATA_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXDATAVALID_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXDATAVALID_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXDFEAGCHOLD (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
RXDFEAGCHOLD (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
RXDFEAGCHOLD (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
RXDFEAGCHOLD_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
RXDFEAGCHOLD_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXDFEAGCHOLD_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXDFELFHOLD (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
RXDFELFHOLD (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
RXDFELFHOLD (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
RXDFELFHOLD_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
RXDFELFHOLD_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXDFELFHOLD_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXDISPERR_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
rxfsmresetdone (defined in serdes5_wrapper)	serdes5_wrapper	Port
RXGEARBOXSLIP_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXGEARBOXSLIP_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXGEARBOXSLIP_OUT (defined in BLOCK_SYNC_SM)	BLOCK_SYNC_SM	Port
RXHEADER_IN (defined in BLOCK_SYNC_SM)	BLOCK_SYNC_SM	Port
RXHEADER_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXHEADER_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXHEADERVALID_IN (defined in BLOCK_SYNC_SM)	BLOCK_SYNC_SM	Port
RXHEADERVALID_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXHEADERVALID_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXLPMEN_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXLPMEN_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXLPMHFHOLD (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
RXLPMHFHOLD (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
RXLPMHFHOLD (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
RXLPMLFHOLD (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
RXLPMLFHOLD (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
RXLPMLFHOLD (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
rxmcommaalignen (defined in serdes5_wrapper)	serdes5_wrapper	Port
RXMCOMMAALIGNEN_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
rxnotintable (defined in serdes5_wrapper)	serdes5_wrapper	Port
RXNOTINTABLE_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
RXOUTCLK_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
RXOUTCLK_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXOUTCLK_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
rxpcommaalignen (defined in serdes5_wrapper)	serdes5_wrapper	Port
RXPCOMMAALIGNEN_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
RXPCSRESET_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXPCSRESET_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXPD_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
RXPD_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXPD_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXPMARESET_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
RXPMARESET_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXPMARESET_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXPRBSCNTRESET_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXPRBSCNTRESET_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXPRBSERR_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXPRBSERR_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXPRBSSEL_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXPRBSSEL_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
rxresetdone (defined in serdes5_wrapper)	serdes5_wrapper	Port
RXRESETDONE (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
RXRESETDONE (defined in XGbEPCS32)	XGbEPCS32	Port
RXRESETDONE (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
RXRESETDONE (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
RXRESETDONE_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
RXRESETDONE_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXRESETDONE_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXUSERCLK (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
RXUSERCLK (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
RXUSERCLK (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
RXUSERRDY (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
RXUSERRDY (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
RXUSERRDY (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
RXUSERRDY_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
RXUSERRDY_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXUSERRDY_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXUSRCLK (defined in XGbEPCS32)	XGbEPCS32	Port
RXUSRCLK2_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
RXUSRCLK2_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXUSRCLK2_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
RXUSRCLK_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
RXUSRCLK_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
RXUSRCLK_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
rxusrclk_o (defined in DaqLSCXG)	DaqLSCXG	Port
SCRAMBLED_DATA_IN (defined in DESCRAMBLER)	DESCRAMBLER	Port
SCRAMBLED_DATA_OUT (defined in SCRAMBLER)	SCRAMBLER	Port
SD_Data_i (defined in SLINK_opt)	SLINK_opt	Port
SD_Data_i (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
SD_Data_o (defined in SLINK_opt)	SLINK_opt	Port
SD_Data_o (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
SD_Kb_i (defined in SLINK_opt)	SLINK_opt	Port
SD_Kb_i (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
SD_Kb_o (defined in SLINK_opt)	SLINK_opt	Port
SD_Kb_o (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
SEED (defined in generate_3)	generate_3	Port
SEED (defined in generate_3)	generate_3	Port
Seq_nb (defined in Core_logic)	Core_logic	Port
Seq_nb (defined in build_pckt_s)	build_pckt_s	Port
Seq_nb (defined in Core_logic)	Core_logic	Port
Seq_nb (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
seqnb (defined in rcv_pckt_s)	rcv_pckt_s	Port
seqnb (defined in rcv_pckt_s_XGMII)	rcv_pckt_s_XGMII	Port
seqnb_rcv (defined in Core_logic)	Core_logic	Port
seqnb_rcv (defined in Core_logic)	Core_logic	Port
serdes_init (defined in SLINK_opt)	SLINK_opt	Port
serdes_init (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
Serdes_status (defined in SLINK_opt)	SLINK_opt	Port
Serdes_status (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
SFP0_RXN (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
SFP0_RXP (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
SFP0_TXN (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
SFP0_TXP (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
SFP1_RXN (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
SFP1_RXP (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
SFP1_TXN (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
SFP1_TXP (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
SFP2_RXN (defined in XGMII_serdes_wapper)	XGMII_serdes_wapper	Port
SFP2_RXP (defined in XGMII_serdes_wapper)	XGMII_serdes_wapper	Port
SFP2_TXN (defined in XGMII_serdes_wapper)	XGMII_serdes_wapper	Port
SFP2_TXP (defined in XGMII_serdes_wapper)	XGMII_serdes_wapper	Port
SFP_ABS (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
SFP_down (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
sfp_pd (defined in DaqLSCXG)	DaqLSCXG	Port
SFP_REFCLK (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
SFP_REFCLK_N (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
SFP_REFCLK_P (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
sfp_rxn (defined in DaqLSCXG)	DaqLSCXG	Port
sfp_rxp (defined in DaqLSCXG)	DaqLSCXG	Port
sfp_txn (defined in DaqLSCXG)	DaqLSCXG	Port
sfp_txp (defined in DaqLSCXG)	DaqLSCXG	Port
SH_CNT_MAX (defined in BLOCK_SYNC_SM)	BLOCK_SYNC_SM	Generic
SH_INVALID_CNT_MAX (defined in BLOCK_SYNC_SM)	BLOCK_SYNC_SM	Generic
SOFT_RESET (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
SOFT_RESET (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
SOFT_RESET (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
SOFT_RESET (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
SOFT_RESET (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
SOFT_RESET (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
SOFT_RESET_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
SOFT_RESET_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
SOFT_RESET_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
src_ID (defined in SLINK_opt)	SLINK_opt	Port
src_ID (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
srcID (defined in DaqLSCXG)	DaqLSCXG	Port
sta_dt (defined in Core_logic)	Core_logic	Port
sta_dt (defined in Core_logic)	Core_logic	Port
STABLE_CLOCK (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
STABLE_CLOCK (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
STABLE_CLOCK (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
STABLE_CLOCK (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
STABLE_CLOCK (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
STABLE_CLOCK (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
STABLE_CLOCK_PERIOD (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Generic
STABLE_CLOCK_PERIOD (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Generic
STABLE_CLOCK_PERIOD (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Generic
START (defined in generate_3)	generate_3	Port
START (defined in generate_3)	generate_3	Port
start (defined in memory_rnd)	memory_rnd	Port
start (defined in memory_rnd)	memory_rnd	Port
start_evt (defined in fed_itf)	fed_itf	Port
start_evt (defined in Core_logic)	Core_logic	Port
start_evt (defined in fed_itf)	fed_itf	Port
start_evt (defined in Core_logic)	Core_logic	Port
start_pckt (defined in Core_logic)	Core_logic	Port
start_pckt (defined in build_pckt_s)	build_pckt_s	Port
start_pckt (defined in Core_logic)	Core_logic	Port
start_pckt (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
status (defined in Core_logic)	Core_logic	Port
status (defined in build_pckt_s)	build_pckt_s	Port
status (defined in rcv_pckt_s)	rcv_pckt_s	Port
status (defined in Core_logic)	Core_logic	Port
status (defined in rcv_pckt_s_XGMII)	rcv_pckt_s_XGMII	Port
status_addr (defined in DaqLSCXG)	DaqLSCXG	Port
status_ce (defined in DaqLSCXG)	DaqLSCXG	Port
status_data (defined in SLINK_opt)	SLINK_opt	Port
status_data (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
status_port (defined in DaqLSCXG)	DaqLSCXG	Port
status_state (defined in Core_logic)	Core_logic	Port
status_state (defined in build_pckt_s)	build_pckt_s	Port
status_state (defined in Core_logic)	Core_logic	Port
status_state (defined in build_pckt_s_XGMII)	build_pckt_s_XGMII	Port
status_state_build_p (defined in fed_itf)	fed_itf	Port
status_state_build_p (defined in fed_itf)	fed_itf	Port
status_state_core (defined in fed_itf)	fed_itf	Port
status_state_core (defined in fed_itf)	fed_itf	Port
stop (defined in check_event)	check_event	Port
stop_evt (defined in fed_itf)	fed_itf	Port
stop_evt (defined in Core_logic)	Core_logic	Port
stop_evt (defined in fed_itf)	fed_itf	Port
stop_evt (defined in Core_logic)	Core_logic	Port
sync_loss (defined in DaqLSCXG)	DaqLSCXG	Port
SYS_CLK (defined in SLINK_opt)	SLINK_opt	Port
SYS_CLK (defined in SLINK_opt_XGMII)	SLINK_opt_XGMII	Port
sys_clk (defined in DaqLSCXG)	DaqLSCXG	Port
sys_reset (defined in DaqLSCXG)	DaqLSCXG	Port
sysclk (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
SYSCLK_IN (defined in serdes5GpdProd_init)	serdes5GpdProd_init	Port
SYSCLK_IN (defined in SFP2_v2_7_init)	SFP2_v2_7_init	Port
SYSCLK_IN (defined in SFP3_v2_7_init)	SFP3_v2_7_init	Port
SYSTEM_RESET (defined in BLOCK_SYNC_SM)	BLOCK_SYNC_SM	Port
SYSTEM_RESET (defined in SCRAMBLER)	SCRAMBLER	Port
SYSTEM_RESET (defined in DESCRAMBLER)	DESCRAMBLER	Port
test (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
time_out_val (defined in Core_logic)	Core_logic	Generic
time_out_val (defined in Core_logic)	Core_logic	Generic
trailer (defined in cmsCRC64)	cmsCRC64	Port
trig_nb (defined in trigger_gen)	trigger_gen	Port
trig_nb (defined in trigger_gen)	trigger_gen	Port
trigger (defined in trigger_gen)	trigger_gen	Port
trigger (defined in memory_rnd)	memory_rnd	Port
trigger (defined in trigger_gen)	trigger_gen	Port
trigger (defined in memory_rnd)	memory_rnd	Port
ttc_trigger (defined in trigger_gen)	trigger_gen	Port
ttc_trigger (defined in trigger_gen)	trigger_gen	Port
TX_DATA_WIDTH (defined in SCRAMBLER)	SCRAMBLER	Generic
TX_FSM_RESET_DONE (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
TX_FSM_RESET_DONE (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
TX_FSM_RESET_DONE (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
TX_high (defined in XGbEPCS32)	XGbEPCS32	Port
TX_QPLL_USED (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Generic
TX_QPLL_USED (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Generic
TX_QPLL_USED (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Generic
TX_QPLL_USED (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Generic
TX_QPLL_USED (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Generic
TX_QPLL_USED (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Generic
txcharisk (defined in serdes5_wrapper)	serdes5_wrapper	Port
TXCHARISK_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
txdata (defined in serdes5_wrapper)	serdes5_wrapper	Port
TXDATA_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
TXDATA_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
TXDATA_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
TXDIFFCTRL_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
TXDIFFCTRL_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
txfsmresetdone (defined in serdes5_wrapper)	serdes5_wrapper	Port
TXHEADER_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
TXHEADER_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
TXINHIBIT_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
TXINHIBIT_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
TXMAINCURSOR_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
TXMAINCURSOR_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
TXOUTCLK_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
TXOUTCLK_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
TXOUTCLK_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
TXOUTCLKFABRIC_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
TXOUTCLKFABRIC_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
TXOUTCLKFABRIC_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
TXOUTCLKPCS_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
TXOUTCLKPCS_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
TXOUTCLKPCS_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
TXPCSRESET_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
TXPCSRESET_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
TXPD_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
TXPD_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
TXPD_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
TXPRBSSEL_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
TXPRBSSEL_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
TXRESETDONE (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
TXRESETDONE (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
TXRESETDONE (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
txresetdone (defined in serdes5_wrapper)	serdes5_wrapper	Port
TXRESETDONE_OUT (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
TXRESETDONE_OUT (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
TXRESETDONE_OUT (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
TXSEQUENCE_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
TXSEQUENCE_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
TXUSERCLK (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
TXUSERCLK (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
TXUSERCLK (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
TXUSERRDY (defined in serdes5GpdProd_TX_STARTUP_FSM)	serdes5GpdProd_TX_STARTUP_FSM	Port
TXUSERRDY (defined in serdes5GpdProd_RX_STARTUP_FSM)	serdes5GpdProd_RX_STARTUP_FSM	Port
TXUSERRDY (defined in SFP2_v2_7_TX_STARTUP_FSM)	SFP2_v2_7_TX_STARTUP_FSM	Port
TXUSERRDY (defined in SFP2_v2_7_RX_STARTUP_FSM)	SFP2_v2_7_RX_STARTUP_FSM	Port
TXUSERRDY (defined in SFP3_v2_7_TX_STARTUP_FSM)	SFP3_v2_7_TX_STARTUP_FSM	Port
TXUSERRDY (defined in SFP3_v2_7_RX_STARTUP_FSM)	SFP3_v2_7_RX_STARTUP_FSM	Port
TXUSERRDY_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
TXUSERRDY_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
TXUSERRDY_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
TXUSRCLK (defined in XGbEPCS32)	XGbEPCS32	Port
TXUSRCLK2_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
TXUSRCLK2_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
TXUSRCLK2_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
TXUSRCLK_IN (defined in serdes5GpdProd_GT)	serdes5GpdProd_GT	Port
TXUSRCLK_IN (defined in SFP2_v2_7_GT)	SFP2_v2_7_GT	Port
TXUSRCLK_IN (defined in SFP3_v2_7_GT)	SFP3_v2_7_GT	Port
txusrclk_o (defined in DaqLSCXG)	DaqLSCXG	Port
txusrclk_out (defined in serdes5_wrapper)	serdes5_wrapper	Port
uctrl (defined in event_generator)	event_generator	Port
uctrl (defined in event_generator)	event_generator	Port
UNIMACRO (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Library
UNISIM (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Library
UNSCRAMBLED_DATA_IN (defined in SCRAMBLER)	SCRAMBLER	Port
UNSCRAMBLED_DATA_OUT (defined in DESCRAMBLER)	DESCRAMBLER	Port
USER_CLK (defined in BLOCK_SYNC_SM)	BLOCK_SYNC_SM	Port
USER_CLK (defined in SCRAMBLER)	SCRAMBLER	Port
USER_CLK (defined in DESCRAMBLER)	DESCRAMBLER	Port
VCOMPONENTS (defined in serdes5GpdProd_init)	serdes5GpdProd_init	use clause
VCOMPONENTS (defined in BLOCK_SYNC_SM)	BLOCK_SYNC_SM	use clause
VCOMPONENTS (defined in SCRAMBLER)	SCRAMBLER	use clause
VCOMPONENTS (defined in DESCRAMBLER)	DESCRAMBLER	use clause
VCOMPONENTS (defined in SFP2_v2_7_init)	SFP2_v2_7_init	use clause
VCOMPONENTS (defined in SFP3_v2_7_init)	SFP3_v2_7_init	use clause
VComponents (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	use clause
vcomponents (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	use clause
WaitMonBuf (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
wc (defined in memory_rnd)	memory_rnd	Port
wc (defined in memory_rnd)	memory_rnd	Port
wea (defined in Memory)	Memory	Port
wea (defined in Memory)	Memory	Port
wen (defined in event_generator)	event_generator	Port
wen (defined in FIFO_sync)	FIFO_sync	Port
wen (defined in Core_logic)	Core_logic	Port
wen (defined in event_generator)	event_generator	Port
wen (defined in FIFO_sync)	FIFO_sync	Port
wen (defined in Core_logic)	Core_logic	Port
work (defined in fed_itf)	fed_itf	Library
work (defined in fed_itf)	fed_itf	Library
wport_FIFO_full (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
wport_rdy (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
wr_clk (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
wr_clk (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
wr_cmd (defined in fed_itf)	fed_itf	Port
wr_cmd (defined in Core_logic)	Core_logic	Port
wr_cmd (defined in fed_itf)	fed_itf	Port
wr_cmd (defined in Core_logic)	Core_logic	Port
wr_data_count (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
wr_data_count (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
wr_en (defined in lpm_fifo)	lpm_fifo	Port
wr_en (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
wr_en (defined in lpm_fifo)	lpm_fifo	Port
wr_en (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
wr_ena (defined in fed_itf)	fed_itf	Port
wr_ena (defined in fed_itf)	fed_itf	Port
wr_rst (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
wr_rst (defined in lpm_fifo_dc)	lpm_fifo_dc	Port
WRAPPER_SIM_GTRESET_SPEEDUP (defined in serdes5GpdProd)	serdes5GpdProd	Generic
WRAPPER_SIM_GTRESET_SPEEDUP (defined in SFP2_v2_7)	SFP2_v2_7	Generic
WRAPPER_SIM_GTRESET_SPEEDUP (defined in SFP3_v2_7)	SFP3_v2_7	Generic
WrtMonBlkDone (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
WrtMonEvtDone (defined in DAQLSCXG_2x_if)	DAQLSCXG_2x_if	Port
xgmii_rxc (defined in XGMII_serdes_wapper)	XGMII_serdes_wapper	Port
xgmii_rxd (defined in XGMII_serdes_wapper)	XGMII_serdes_wapper	Port
xgmii_txc (defined in XGMII_serdes_wapper)	XGMII_serdes_wapper	Port
xgmii_txd (defined in XGMII_serdes_wapper)	XGMII_serdes_wapper	Port
XilinxCoreLib (defined in lpm_fifo)	lpm_fifo	Library
XilinxCoreLib (defined in lpm_fifo_dc)	lpm_fifo_dc	Library
XilinxCoreLib (defined in Memory)	Memory	Library
XilinxCoreLib (defined in lpm_fifo)	lpm_fifo	Library
XilinxCoreLib (defined in lpm_fifo_dc)	lpm_fifo_dc	Library
XilinxCoreLib (defined in Memory)	Memory	Library