RTL Architecture Reference

List of all members.

Processes
PROCESS_37	( USER_CLK )
PROCESS_38	( USER_CLK )
PROCESS_39	( USER_CLK )
PROCESS_40	( USER_CLK )
PROCESS_41	( USER_CLK )
PROCESS_42	( USER_CLK )
PROCESS_1186	( USER_CLK )
PROCESS_1187	( USER_CLK )
PROCESS_1188	( USER_CLK )
PROCESS_1189	( USER_CLK )
PROCESS_1190	( USER_CLK )
PROCESS_1191	( USER_CLK )

Constants
DLY	time := 10 ps

Signals
next_begin_c	std_logic
next_sh_invalid_c	std_logic
next_sh_valid_c	std_logic
next_slip_c	std_logic
next_sync_done_c	std_logic
next_test_sh_c	std_logic
sh_count_equals_max_i	std_logic
sh_invalid_cnt_equals_max_i	std_logic
sh_invalid_cnt_equals_zero_i	std_logic
slip_done_i	std_logic
slip_pulse_i	std_logic
sync_found_i	std_logic
begin_r	std_logic
blocksync_out_i	std_logic
rxgearboxslip_out_i	std_logic
sh_invalid_r	std_logic
sh_valid_r	std_logic
slip_count_i	std_logic_vector ( 31 downto 0 )
slip_r	std_logic
sync_done_r	std_logic
sync_header_count_i	unsigned ( 9 downto 0 )
sync_header_invalid_count_i	unsigned ( 9 downto 0 )
test_sh_r	std_logic

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Detailed Description

Definition at line 92 of file block_sync_sm.vhd.

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The documentation for this class was generated from the following files:

• /home/dan/work/CMS/firmware/trunk/src/CMS_DAQ_2x_if/10Gb_if/block_sync_sm.vhd
• /home/dan/work/CMS/firmware/trunk/src/TCPIP_if/block_sync_sm.vhd