AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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DaqLSCXG10G1.vhd
1 
2 library IEEE;
3 use IEEE.STD_LOGIC_1164.ALL;
4 use ieee.std_logic_unsigned.all;
5 use work.amc13_pack.all;
6 use work.mydefs.all;
7 
8 
9 library UNISIM;
10 use UNISIM.VComponents.all;
11 
12 entity DaqLSCXG is
13  generic(N_SFP : integer := 1);
14  Port ( sys_reset : in STD_LOGIC; -- active high reset of all logic but GTX
15  sys_clk : in STD_LOGIC;
16  sfp_pd : in array3x2;
17  DRP_clk : in STD_LOGIC;
18  LinkWe : in STD_LOGIC_VECTOR (2 downto 0);
19  LinkCtrl : in STD_LOGIC_VECTOR (2 downto 0);
20  LinkData : in array3x64;
21  srcID : in array3x16;
22  LinkDown : out STD_LOGIC_VECTOR (2 downto 0);
23  LinkFull : out STD_LOGIC_VECTOR (2 downto 0);
24  --
25 -- ack_cnt : out STD_LOGIC_VECTOR (2 downto 0); -- 1 ck pulse (txusrclk) indicating a received acknowledge
26 -- pckt_cnt : out STD_LOGIC_VECTOR (2 downto 0); -- 1 ck pulse (txusrclk) indicating a transmit packet
27 -- retransmit_cnt : out STD_LOGIC_VECTOR (2 downto 0); -- 1 ck pulse (txusrclk) indicating a retransmit packet
28 -- event_cnt : out STD_LOGIC_VECTOR (2 downto 0); -- 1 ck pulse (sys_clk) indicating a sent event
29  sync_loss : out STD_LOGIC_VECTOR (2 downto 0); -- goes to '1' (rxusrclk) when SERDES is out of synch
30  status_ce : in std_logic_VECTOR (2 downto 0); -- not implemented yet
31  status_addr : in STD_LOGIC_VECTOR (15 downto 0); -- not implemented yet
32  status_port : out array3x64; -- first 32 bits are hard-wired
33  --
34  txusrclk_o : out STD_LOGIC; -- reconstructed tx clock, to be used to clock sending circuitry
35  rxusrclk_o : out STD_LOGIC; -- reconstructed rx clock, to be used to clock receiving circuitry
36  --
37  gtx_reset : in std_logic; -- full reset of GTX only
38  gtx_refclk_p : in std_logic; -- iob for refclk neg
39  gtx_refclk_n : in std_logic; -- iob for refclk neg
40  sfp_rxn : in std_logic_VECTOR (2 downto 0); -- sfp iobs
41  sfp_rxp : in std_logic_VECTOR (2 downto 0);
42  sfp_txn : out std_logic_VECTOR (2 downto 0);
43  sfp_txp : out std_logic_VECTOR (2 downto 0)
44  );
45 end DaqLSCXG;
46 
47 architecture Behavioral of DaqLSCXG is
48 COMPONENT SLINK_opt_XGMII
49 port (
50  reset : in std_logic;
51  -- FED interface
52  SYS_CLK : in std_logic;
53  LINKWe : in std_logic;
54  LINKCtrl : in std_logic;
55  LINKData : in std_logic_vector(63 downto 0);
56  src_ID : in std_logic_vector(15 downto 0);
57  inject_err : in std_logic_vector(17 downto 0);
58  read_CE : in std_logic;
59  Addr : in std_logic_vector(15 downto 0);
60  status_data : out std_logic_vector(63 downto 0);
61  LINKDown : out std_logic;
62  LINK_LFF : out std_logic;
63 
64  -- interface SERDES
65  clock : in std_logic;
66  serdes_init : in std_logic;
67  SD_Data_o : out std_logic_vector(63 downto 0);
68  SD_Kb_o : out std_logic_vector(7 downto 0);
69  clock_r : in std_logic;
70  SD_Data_i : in std_logic_vector(63 downto 0);
71  SD_Kb_i : in std_logic_vector(7 downto 0);
72 
73  Serdes_status : in std_logic_vector(31 downto 0)
74 
75  );
76 END COMPONENT;
77 COMPONENT ten_gig_eth_pcs_pma_0_example_design
78 PORT (
79  refclk_p : in std_logic;
80  refclk_n : in std_logic;
81  dclk : in std_logic;
82  core_clk156_out : out std_logic;
83  reset : in std_logic;
84  sim_speedup_control: in std_logic := '0';
85  xgmii_txd : in std_logic_vector(63 downto 0);
86  xgmii_txc : in std_logic_vector(7 downto 0);
87  xgmii_rxd : out std_logic_vector(63 downto 0);
88  xgmii_rxc : out std_logic_vector(7 downto 0);
89  xgmii_rx_clk : out std_logic;
90  txp : out std_logic;
91  txn : out std_logic;
92  rxp : in std_logic;
93  rxn : in std_logic;
94  pma_loopback : in std_logic;
95  pma_reset : in std_logic;
96  global_tx_disable: in std_logic;
97  pcs_loopback : in std_logic;
98  pcs_reset : in std_logic;
99  test_patt_a_b : in std_logic_vector(57 downto 0);
100  data_patt_sel : in std_logic;
101  test_patt_sel : in std_logic;
102  rx_test_patt_en : in std_logic;
103  tx_test_patt_en : in std_logic;
104  prbs31_tx_en : in std_logic;
105  prbs31_rx_en : in std_logic;
106  set_pma_link_status : in std_logic;
107  set_pcs_link_status : in std_logic;
108  clear_pcs_status2 : in std_logic;
109  clear_test_patt_err_count: in std_logic;
110 
111  pma_link_status : out std_logic;
112  rx_sig_det : out std_logic;
113  pcs_rx_link_status : out std_logic;
114  pcs_rx_locked : out std_logic;
115  pcs_hiber : out std_logic;
116  teng_pcs_rx_link_status : out std_logic;
117  pcs_err_block_count : out std_logic_vector(7 downto 0);
118  pcs_ber_count : out std_logic_vector(5 downto 0);
119  pcs_rx_hiber_lh : out std_logic;
120  pcs_rx_locked_ll : out std_logic;
121  pcs_test_patt_err_count : out std_logic_vector(15 downto 0);
122  core_status : out std_logic_vector(7 downto 0);
123  resetdone : out std_logic;
124  signal_detect : in std_logic;
125  tx_fault : in std_logic;
126  tx_disable : out std_logic);
127 END COMPONENT;
128 
129 -- Local signals
130 
131 signal sys_reset_bar : std_logic;
132 signal serdes_core_clk156_out : std_logic;
133 signal txdata, rxdata : array3x64;
134 signal rxcharisk, txcharisk, rxchariscomma, gtx_rxnotintable : array3x8;
135 signal gtx_rxresetdone : std_logic_vector(2 downto 0);
136 signal PCS_lock : std_logic_vector(2 downto 0);
137 signal serdes_status : array3x32 := (others => (others => '0'));
138 begin
139 txusrclk_o <= serdes_core_clk156_out;
140 rxusrclk_o <= serdes_core_clk156_out;
141 sync_loss <= not PCS_lock;
142 g_SLINK_opt : for i in 0 to 2 generate
143  Inst_SLINK_opt: SLINK_opt_XGMII
144 PORT MAP(
145 -- FROM FED logic
146  reset => sys_reset_bar, -- needs an active low reset
147  SYS_CLK => sys_clk,
148 -- DATA interface from FED
149  LINKWe => not LinkWe (i),
150  LINKCtrl => LinkCtrl(i),
151  LINKData => LinkData(i),
152  src_ID => srcID(i),
153  inject_err => (others =>'0'),
154  read_CE => '0',
155  Addr => status_addr,
156  status_data => status_port(i),
157  serdes_status => serdes_status(i),
158  LINKDown => LinkDown(i),
159  LINK_LFF => LinkFull(i),
160 -- SERDES interface
161  clock => serdes_core_clk156_out, --clk_156_service, -- clk tx from SERDES
162  serdes_init => serdes_status(i)(0), -- status that comes back from GTX
163  SD_Data_o => TXDATA(i), -- data sent to serdes (64 bit)
164  SD_Kb_o => TXCHARISK(i), -- control K associated to SD_Data_o (8 bits)
165  clock_r => serdes_core_clk156_out, -- reconstructed clock from SERDES
166  SD_Data_i => RXDATA(i), -- return data from SERDES 64 bit
167  SD_Kb_i => RXCHARISK(i) -- return control K associated to SD_Data_i (8 bits)
168  );
169  serdes_status(i)(0) <= PCS_lock(i);
170  serdes_status(i)(1) <= gtx_rxresetdone(i);
171 end generate;
172 sys_reset_bar <= not(sys_reset);
173 g_XGMII_serdes: if (N_SFP = 1) generate
174  XGMII_serdes: ten_gig_eth_pcs_pma_0_example_design
175  PORT MAP (
176  refclk_p => gtx_refclk_p,
177  refclk_n => gtx_refclk_n,
178  dclk => serdes_core_clk156_out,--clk_156_service,
179  core_clk156_out => serdes_core_clk156_out,
180  reset => gtx_reset,
181  sim_speedup_control => '0',
182  xgmii_txd => TXDATA(0),
183  xgmii_txc => TXCHARISK(0),
184  xgmii_rxd => RXDATA(0),
185  xgmii_rxc => RXCHARISK(0),
186  xgmii_rx_clk => rxusrclk_o,
187  txp => sfp_txp(0),
188  txn => sfp_txn(0),
189  rxp => sfp_rxp(0),
190  rxn => sfp_rxn(0),
191  pma_loopback => '0',
192  pma_reset => '0',
193  global_tx_disable => '0',
194  pcs_loopback => '0',
195  pcs_reset => '0',
196  test_patt_a_b => (others => '0'),
197  data_patt_sel => '0',
198  test_patt_sel => '0',
199  rx_test_patt_en => '0',
200  tx_test_patt_en => '0',
201  prbs31_tx_en => '0',
202  prbs31_rx_en => '0',
203  set_pma_link_status => '0',
204  set_pcs_link_status => '0',
205  clear_pcs_status2 => '0',
206  clear_test_patt_err_count => '0',
207 
208  pma_link_status => open,
209  rx_sig_det => open,
210  pcs_rx_link_status => open,
211  pcs_rx_locked => open,
212  pcs_hiber => open,
213  teng_pcs_rx_link_status => open,
214  pcs_err_block_count => open,
215  pcs_ber_count => open,
216  pcs_rx_hiber_lh => open,
217  pcs_rx_locked_ll => open,
218  pcs_test_patt_err_count => open,
219  core_status(0) => PCS_lock(0), -- goes to 1 when PCS block lock aquired
220  core_status(7 downto 1) => open,
221  resetdone => gtx_rxresetdone(0),
222  signal_detect => '1',
223  tx_fault => '0',
224  tx_disable => open
225  );
226 end generate;
227 end Behavioral;
228 
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