AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Files Variables
DaqLSCXG10G.vhd
1 
2 library IEEE;
3 use IEEE.STD_LOGIC_1164.ALL;
4 use ieee.std_logic_unsigned.all;
5 use work.amc13_pack.all;
6 use work.mydefs.all;
7 
8 
9 library UNISIM;
10 use UNISIM.VComponents.all;
11 
12 entity DaqLSCXG is
13  generic(N_SFP : integer := 1);
14  Port ( sys_reset : in STD_LOGIC; -- active high reset of all logic but GTX
15  sys_clk : in STD_LOGIC;
16  sfp_pd : in array3x2;
17  DRP_clk : in STD_LOGIC;
18  LinkWe : in STD_LOGIC_VECTOR (2 downto 0);
19  LinkCtrl : in STD_LOGIC_VECTOR (2 downto 0);
20  LinkData : in array3x64;
21  srcID : in array3x16;
22  LinkDown : out STD_LOGIC_VECTOR (2 downto 0);
23  LinkFull : out STD_LOGIC_VECTOR (2 downto 0);
24  --
25 -- ack_cnt : out STD_LOGIC_VECTOR (2 downto 0); -- 1 ck pulse (txusrclk) indicating a received acknowledge
26 -- pckt_cnt : out STD_LOGIC_VECTOR (2 downto 0); -- 1 ck pulse (txusrclk) indicating a transmit packet
27 -- retransmit_cnt : out STD_LOGIC_VECTOR (2 downto 0); -- 1 ck pulse (txusrclk) indicating a retransmit packet
28 -- event_cnt : out STD_LOGIC_VECTOR (2 downto 0); -- 1 ck pulse (sys_clk) indicating a sent event
29  sync_loss : out STD_LOGIC_VECTOR (2 downto 0); -- goes to '1' (rxusrclk) when SERDES is out of synch
30  status_ce : in std_logic_VECTOR (2 downto 0); -- not implemented yet
31  status_addr : in STD_LOGIC_VECTOR (15 downto 0); -- not implemented yet
32  status_port : out array3x64; -- first 32 bits are hard-wired
33  --
34  txusrclk_o : out STD_LOGIC; -- reconstructed tx clock, to be used to clock sending circuitry
35  rxusrclk_o : out STD_LOGIC; -- reconstructed rx clock, to be used to clock receiving circuitry
36  --
37  gtx_reset : in std_logic; -- full reset of GTX only
38  gtx_refclk_p : in std_logic; -- iob for refclk neg
39  gtx_refclk_n : in std_logic; -- iob for refclk neg
40  sfp_rxn : in std_logic_VECTOR (2 downto 0); -- sfp iobs
41  sfp_rxp : in std_logic_VECTOR (2 downto 0);
42  sfp_txn : out std_logic_VECTOR (2 downto 0);
43  sfp_txp : out std_logic_VECTOR (2 downto 0)
44  );
45 end DaqLSCXG;
46 
47 architecture Behavioral of DaqLSCXG is
48 COMPONENT SLINK_opt_XGMII
49 port (
50  reset : in std_logic;
51  -- FED interface
52  SYS_CLK : in std_logic;
53  LINKWe : in std_logic;
54  LINKCtrl : in std_logic;
55  LINKData : in std_logic_vector(63 downto 0);
56  src_ID : in std_logic_vector(15 downto 0);
57  inject_err : in std_logic_vector(17 downto 0);
58  read_CE : in std_logic;
59  Addr : in std_logic_vector(15 downto 0);
60  status_data : out std_logic_vector(63 downto 0);
61  LINKDown : out std_logic;
62  LINK_LFF : out std_logic;
63 
64  -- interface SERDES
65  clock : in std_logic;
66  serdes_init : in std_logic;
67  SD_Data_o : out std_logic_vector(63 downto 0);
68  SD_Kb_o : out std_logic_vector(7 downto 0);
69  clock_r : in std_logic;
70  SD_Data_i : in std_logic_vector(63 downto 0);
71  SD_Kb_i : in std_logic_vector(7 downto 0);
72 
73  Serdes_status : in std_logic_vector(31 downto 0)
74 
75  );
76 END COMPONENT;
77 COMPONENT XGMII_serdes_wapper
78  PORT(
79  DRPclk : IN std_logic;
80  reset : IN std_logic;
81  gtx_reset : IN std_logic;
82  SFP0_RXN : IN std_logic;
83  SFP0_RXP : IN std_logic;
84  SFP1_RXN : IN std_logic;
85  SFP1_RXP : IN std_logic;
86  SFP2_RXN : IN std_logic;
87  SFP2_RXP : IN std_logic;
88  SFP_REFCLK_P : IN std_logic;
89  SFP_REFCLK_N : IN std_logic;
90  xgmii_txd : IN array3x64;
91  xgmii_txc : IN array3x8;
92  SFP0_TXN : OUT std_logic;
93  SFP0_TXP : OUT std_logic;
94  SFP1_TXN : OUT std_logic;
95  SFP1_TXP : OUT std_logic;
96  SFP2_TXN : OUT std_logic;
97  SFP2_TXP : OUT std_logic;
98  clk156 : OUT std_logic;
99  PCS_lock : OUT std_logic_vector(2 downto 0);
100  gtx_rxresetdone : OUT std_logic_vector(2 downto 0);
101  xgmii_rxd : OUT array3x64;
102  xgmii_rxc : OUT array3x8
103  );
104 END COMPONENT;
105 COMPONENT ten_gig_eth_pcs_pma_0_example_design
106 PORT (
107  refclk_p : in std_logic;
108  refclk_n : in std_logic;
109  dclk : in std_logic;
110  core_clk156_out : out std_logic;
111  reset : in std_logic;
112  sim_speedup_control: in std_logic := '0';
113  xgmii_txd : in std_logic_vector(63 downto 0);
114  xgmii_txc : in std_logic_vector(7 downto 0);
115  xgmii_rxd : out std_logic_vector(63 downto 0);
116  xgmii_rxc : out std_logic_vector(7 downto 0);
117  xgmii_rx_clk : out std_logic;
118  txp : out std_logic;
119  txn : out std_logic;
120  rxp : in std_logic;
121  rxn : in std_logic;
122  pma_loopback : in std_logic;
123  pma_reset : in std_logic;
124  global_tx_disable: in std_logic;
125  pcs_loopback : in std_logic;
126  pcs_reset : in std_logic;
127  test_patt_a_b : in std_logic_vector(57 downto 0);
128  data_patt_sel : in std_logic;
129  test_patt_sel : in std_logic;
130  rx_test_patt_en : in std_logic;
131  tx_test_patt_en : in std_logic;
132  prbs31_tx_en : in std_logic;
133  prbs31_rx_en : in std_logic;
134  set_pma_link_status : in std_logic;
135  set_pcs_link_status : in std_logic;
136  clear_pcs_status2 : in std_logic;
137  clear_test_patt_err_count: in std_logic;
138 
139  pma_link_status : out std_logic;
140  rx_sig_det : out std_logic;
141  pcs_rx_link_status : out std_logic;
142  pcs_rx_locked : out std_logic;
143  pcs_hiber : out std_logic;
144  teng_pcs_rx_link_status : out std_logic;
145  pcs_err_block_count : out std_logic_vector(7 downto 0);
146  pcs_ber_count : out std_logic_vector(5 downto 0);
147  pcs_rx_hiber_lh : out std_logic;
148  pcs_rx_locked_ll : out std_logic;
149  pcs_test_patt_err_count : out std_logic_vector(15 downto 0);
150  core_status : out std_logic_vector(7 downto 0);
151  resetdone : out std_logic;
152  signal_detect : in std_logic;
153  tx_fault : in std_logic;
154  tx_disable : out std_logic);
155 END COMPONENT;
156 
157 -- Local signals
158 
159 signal sys_reset_bar : std_logic;
160 signal serdes_core_clk156_out : std_logic;
161 signal txdata, rxdata : array3x64;
162 signal rxcharisk, txcharisk, rxchariscomma, gtx_rxnotintable : array3x8;
163 signal gtx_rxresetdone : std_logic_vector(2 downto 0);
164 signal PCS_lock : std_logic_vector(2 downto 0);
165 signal serdes_status : array3x32 := (others => (others => '0'));
166 begin
167 txusrclk_o <= serdes_core_clk156_out;
168 rxusrclk_o <= serdes_core_clk156_out;
169 sync_loss <= not PCS_lock;
170 g_SLINK_opt : for i in 0 to 2 generate
171  Inst_SLINK_opt: SLINK_opt_XGMII
172 PORT MAP(
173 -- FROM FED logic
174  reset => sys_reset_bar, -- needs an active low reset
175  SYS_CLK => sys_clk,
176 -- DATA interface from FED
177  LINKWe => not LinkWe (i),
178  LINKCtrl => LinkCtrl(i),
179  LINKData => LinkData(i),
180  src_ID => srcID(i),
181  inject_err => (others =>'0'),
182  read_CE => '0',
183  Addr => status_addr,
184  status_data => status_port(i),
185  serdes_status => serdes_status(i),
186  LINKDown => LinkDown(i),
187  LINK_LFF => LinkFull(i),
188 -- SERDES interface
189  clock => serdes_core_clk156_out, --clk_156_service, -- clk tx from SERDES
190  serdes_init => serdes_status(i)(0), -- status that comes back from GTX
191  SD_Data_o => TXDATA(i), -- data sent to serdes (64 bit)
192  SD_Kb_o => TXCHARISK(i), -- control K associated to SD_Data_o (8 bits)
193  clock_r => serdes_core_clk156_out, -- reconstructed clock from SERDES
194  SD_Data_i => RXDATA(i), -- return data from SERDES 64 bit
195  SD_Kb_i => RXCHARISK(i) -- return control K associated to SD_Data_i (8 bits)
196  );
197  serdes_status(i)(0) <= PCS_lock(i);
198  serdes_status(i)(1) <= gtx_rxresetdone(i);
199 end generate;
200 sys_reset_bar <= not(sys_reset);
201 g_XGMII_serdes: if (N_SFP = 1) generate
202  XGMII_serdes: ten_gig_eth_pcs_pma_0_example_design
203  PORT MAP (
204  refclk_p => gtx_refclk_p,
205  refclk_n => gtx_refclk_n,
206  dclk => serdes_core_clk156_out,--clk_156_service,
207  core_clk156_out => serdes_core_clk156_out,
208  reset => gtx_reset,
209  sim_speedup_control => '0',
210  xgmii_txd => TXDATA(0),
211  xgmii_txc => TXCHARISK(0),
212  xgmii_rxd => RXDATA(0),
213  xgmii_rxc => RXCHARISK(0),
214  xgmii_rx_clk => rxusrclk_o,
215  txp => sfp_txp(0),
216  txn => sfp_txn(0),
217  rxp => sfp_rxp(0),
218  rxn => sfp_rxn(0),
219  pma_loopback => '0',
220  pma_reset => '0',
221  global_tx_disable => '0',
222  pcs_loopback => '0',
223  pcs_reset => '0',
224  test_patt_a_b => (others => '0'),
225  data_patt_sel => '0',
226  test_patt_sel => '0',
227  rx_test_patt_en => '0',
228  tx_test_patt_en => '0',
229  prbs31_tx_en => '0',
230  prbs31_rx_en => '0',
231  set_pma_link_status => '0',
232  set_pcs_link_status => '0',
233  clear_pcs_status2 => '0',
234  clear_test_patt_err_count => '0',
235 
236  pma_link_status => open,
237  rx_sig_det => open,
238  pcs_rx_link_status => open,
239  pcs_rx_locked => open,
240  pcs_hiber => open,
241  teng_pcs_rx_link_status => open,
242  pcs_err_block_count => open,
243  pcs_ber_count => open,
244  pcs_rx_hiber_lh => open,
245  pcs_rx_locked_ll => open,
246  pcs_test_patt_err_count => open,
247  core_status(0) => PCS_lock(0), -- goes to 1 when PCS block lock aquired
248  core_status(7 downto 1) => open,
249  resetdone => gtx_rxresetdone(0),
250  signal_detect => '1',
251  tx_fault => '0',
252  tx_disable => open
253  );
254 end generate;
255 g_XGMII_serdes_wapper: if (N_SFP > 1) generate
256  i_XGMII_serdes_wapper: XGMII_serdes_wapper PORT MAP(
257  DRPclk => DRP_clk,
258  reset => sys_reset,
259  gtx_reset => gtx_reset,
260  SFP0_RXN => sfp_rxn(0),
261  SFP0_RXP => sfp_rxp(0),
262  SFP1_RXN => sfp_rxn(1),
263  SFP1_RXP => sfp_rxp(1),
264  SFP2_RXN => sfp_rxn(2),
265  SFP2_RXP => sfp_rxp(2),
266  SFP0_TXN => sfp_txn(0),
267  SFP0_TXP => sfp_txp(0),
268  SFP1_TXN => sfp_txn(1),
269  SFP1_TXP => sfp_txp(1),
270  SFP2_TXN => sfp_txn(2),
271  SFP2_TXP => sfp_txp(2),
272  SFP_REFCLK_P => gtx_refclk_p,
273  SFP_REFCLK_N => gtx_refclk_n,
274  clk156 => serdes_core_clk156_out,
275  PCS_lock => PCS_lock,
276  gtx_rxresetdone => gtx_rxresetdone,
277  xgmii_txd => TXDATA,
278  xgmii_txc => TXCHARISK,
279  xgmii_rxd => RXDATA,
280  xgmii_rxc => RXCHARISK
281  );
282 end generate;
283 end Behavioral;
284 
Generated on Sun Mar 6 2016 12:24:18 for AMC13 by   doxygen 1.8.1