AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Files Variables
DAQLSCXG10G_if.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 14:07:47 10/07/2013
6 -- Design Name:
7 -- Module Name: TCPIP_if - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 use IEEE.numeric_std.all;
26 use work.amc13_pack.all;
27 
28 -- Uncomment the following library declaration if using
29 -- arithmetic functions with Signed or Unsigned values
30 --use IEEE.NUMERIC_STD.ALL;
31 
32 -- Uncomment the following library declaration if instantiating
33 -- any Xilinx primitives in this code.
34 library UNISIM;
35 use UNISIM.VComponents.all;
36 Library UNIMACRO;
37 use UNIMACRO.vcomponents.all;
38 
39 entity DAQLSCXG_if is
40  Port ( sysclk : in STD_LOGIC;
41  clk125 : in STD_LOGIC;
42  DRPclk : in STD_LOGIC;
43  reset : in STD_LOGIC;
44  daq_reset : in STD_LOGIC;
45  gtx_reset : in STD_LOGIC;
46  rstCntr : in STD_LOGIC;
47  Dis_pd : in STD_LOGIC;
48  test : in STD_LOGIC;
49  enSFP : IN std_logic_vector(3 downto 0);
50  SFP_ABS : IN std_logic_vector(2 downto 0);
51  LSC_ID : IN std_logic_vector(15 downto 0);
52  SFP_down : OUT std_logic_vector(2 downto 0);
53  inc_ddr_pa : in STD_LOGIC;
54 -- event data in
55  evt_data_rdy : in std_logic_vector(2 downto 0);
56  EventData_in : in array3X67;
57  EventData_we : in std_logic_VECTOR(2 downto 0);
58  EventData_re : out std_logic_VECTOR(2 downto 0); --
59  evt_buf_full : out std_logic_vector(2 downto 0);
60  buf_rqst : in std_logic_vector(3 downto 0);
61  WaitMonBuf : IN std_logic;
62  MonBufOverWrite : in STD_LOGIC;
63  MonBuf_avl : out STD_LOGIC;
64  MonBuf_empty : out STD_LOGIC;
65  MonBufOvfl : out STD_LOGIC;
66  mon_evt_cnt : out std_logic_vector(31 downto 0);
67  WrtMonBlkDone : in STD_LOGIC_VECTOR(2 downto 0);
68  WrtMonEvtDone : in STD_LOGIC_VECTOR(2 downto 0);
69 -- ddr wportA status
70  wport_rdy : in std_logic_vector(2 downto 0);
71  wport_FIFO_full : in std_logic_vector(2 downto 0);
72 -- signal to ddr_if, AMC_if to start moving data
73  EventBufAddr_we : out std_logic_VECTOR(2 downto 0);
74  EventBufAddr : out array3X14;
75 -- SFP ports
76  SFP0_RXN : in STD_LOGIC;
77  SFP0_RXP : in STD_LOGIC;
78  SFP1_RXN : in STD_LOGIC;
79  SFP1_RXP : in STD_LOGIC;
80  SFP2_RXN : in STD_LOGIC;
81  SFP2_RXP : in STD_LOGIC;
82  SFP0_TXN : out STD_LOGIC;
83  SFP0_TXP : out STD_LOGIC;
84  SFP1_TXN : out STD_LOGIC;
85  SFP1_TXP : out STD_LOGIC;
86  SFP2_TXN : out STD_LOGIC;
87  SFP2_TXP : out STD_LOGIC;
88  SFP_REFCLK_P : in STD_LOGIC;
89  SFP_REFCLK_N : in STD_LOGIC;
90 -- ipbus signals
91  ipb_clk : in STD_LOGIC;
92  ipb_write : in STD_LOGIC;
93  ipb_strobe : in STD_LOGIC;
94  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
95  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
96  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
97  ipb_ack : out STD_LOGIC
98  );
99 end DAQLSCXG_if;
100 
101 architecture Behavioral of DAQLSCXG_if is
102 COMPONENT DaqLSCXG
103  Port ( sys_reset : in STD_LOGIC; -- active high reset of all logic but GTX
104  sys_clk : in STD_LOGIC;
105  sfp_pd : in array3x2;
106  DRP_clk : in STD_LOGIC;
107  LinkWe : in STD_LOGIC_VECTOR (2 downto 0);
108  LinkCtrl : in STD_LOGIC_VECTOR (2 downto 0);
109  LinkData : in array3x64;
110  srcID : in array3x16;
111  LinkDown : out STD_LOGIC_VECTOR (2 downto 0);
112  LinkFull : out STD_LOGIC_VECTOR (2 downto 0);
113  sync_loss : out STD_LOGIC_VECTOR (2 downto 0); -- goes to '1' (rxusrclk) when SERDES is out of synch
114  status_ce : in std_logic_VECTOR (2 downto 0); -- not implemented yet
115  status_addr : in STD_LOGIC_VECTOR (15 downto 0); -- not implemented yet
116  status_port : out array3x64; -- first 32 bits are hard-wired
117  --
118  txusrclk_o : out STD_LOGIC; -- reconstructed tx clock, to be used to clock sending circuitry
119  rxusrclk_o : out STD_LOGIC; -- reconstructed rx clock, to be used to clock receiving circuitry
120  --
121  gtx_reset : in std_logic; -- full reset of GTX only
122  gtx_refclk_p : in std_logic; -- iob for refclk neg
123  gtx_refclk_n : in std_logic; -- iob for refclk neg
124  sfp_rxn : in std_logic_VECTOR (2 downto 0); -- sfp iobs
125  sfp_rxp : in std_logic_VECTOR (2 downto 0);
126  sfp_txn : out std_logic_VECTOR (2 downto 0);
127  sfp_txp : out std_logic_VECTOR (2 downto 0)
128  );
129 END COMPONENT;
130 COMPONENT cmsCRC64
131  PORT(
132  clk : IN std_logic;
133  reset : IN std_logic;
134  crc_init : IN std_logic;
135  trailer : IN std_logic;
136  crc_d : IN std_logic_vector(63 downto 0);
137  crc_ce : IN std_logic;
138  crc : OUT std_logic_vector(15 downto 0);
139  crc_err : OUT std_logic;
140  dout : OUT std_logic_vector(63 downto 0);
141  dout_vld : OUT std_logic
142  );
143 END COMPONENT;
144 COMPONENT check_event
145  PORT(
146  clk : IN std_logic;
147  reset : IN std_logic;
148  en_stop : IN std_logic_vector(4 downto 0);
149  cmsCRC_err : IN std_logic_vector(2 downto 0);
150  EventData_in : IN array3X67;
151  EventData_we : IN std_logic_vector(2 downto 0);
152  inc_err : OUT array3X5;
153  stop : OUT std_logic
154  );
155 END COMPONENT;
156 function A_GT_B (A, B : std_logic_vector(10 downto 0)) return boolean is
157 variable tmp : std_logic_vector(10 downto 0);
158 begin
159  tmp := A - B;
160  if(tmp(10) = '0' and or_reduce(tmp(9 downto 0)) = '1')then
161  return true;
162  else
163  return false;
164  end if;
165 end A_GT_B;
166 function A_GE_B (A, B : std_logic_vector(10 downto 0)) return boolean is
167 variable tmp : std_logic_vector(10 downto 0);
168 begin
169  tmp := A - B;
170  if(tmp(10) = '0')then
171  return true;
172  else
173  return false;
174  end if;
175 end A_GE_B;
176 signal resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
177 signal daq_resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
178 signal inc_ddr_paSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
179 signal bldr2SFP_sel : array3X2 := (others => (others => '0'));
180 signal SFP2bldr_sel : array3X2 := (others => (others => '0'));
181 signal EventBufAddr_we_i : std_logic_vector(2 downto 0) := (others => '0');
182 signal ReadBusy : std_logic_vector(2 downto 0) := (others => '0');
183 signal sysDIV2 : std_logic := '0';
184 --signal MonBuf_avl_i : std_logic := '0';
185 signal MonBuf_wa : std_logic_vector(10 downto 0) := (others => '0');
186 signal MonBuf_ra : std_logic_vector(10 downto 0) := (others => '0');
187 signal MonBufUsed : std_logic_vector(9 downto 0) := (others => '0');
188 signal NXT_MonBuf : array3X11 := (others => (others => '0'));
189 signal Written_MonBuf : array4X11 := (others => (others => '0'));
190 signal Written_MonBufMatch : std_logic_vector(2 downto 0) := (others => '0');
191 signal AddrOffset : array3X10 := (others => (others => '0'));
192 signal header : std_logic_vector(2 downto 0) := (others => '0');
193 signal header_q : std_logic_vector(2 downto 0) := (others => '0');
194 signal sfp_rxn : std_logic_vector(2 downto 0) := (others => '0');
195 signal sfp_rxp : std_logic_vector(2 downto 0) := (others => '0');
196 signal sfp_txn : std_logic_vector(2 downto 0) := (others => '0');
197 signal sfp_txp : std_logic_vector(2 downto 0) := (others => '0');
198 signal sync_loss : std_logic_vector(2 downto 0) := (others => '0');
199 signal LinkFull_n : std_logic_vector(2 downto 0) := (others => '0');
200 signal LinkFull : std_logic_vector(2 downto 0) := (others => '0');
201 signal LinkCtrl : std_logic_vector(2 downto 0) := (others => '0');
202 signal LinkWe : std_logic_vector(2 downto 0) := (others => '0');
203 signal LinkDown : std_logic_vector(2 downto 0) := (others => '0');
204 signal DaqLSC_status : array3X64 := (others => (others => '0'));
205 signal LinkData : array3X65 := (others => (others => '0'));
206 signal sync_loss_cntr : array3X32 := (others => (others => '0'));
207 signal SFP_we : std_logic_vector(2 downto 0) := (others => '0');
208 signal EoB : std_logic_vector(2 downto 0) := (others => '0');
209 signal SFP_evt_cntr : array3X32 := (others => (others => '0'));
210 signal SFP_blk_cntr : array3X32 := (others => (others => '0'));
211 signal SFP_word_cntr : array3X32 := (others => (others => '0'));
212 signal event_cntr : array3X32 := (others => (others => '0'));
213 signal word_cntr : array3X32 := (others => (others => '0'));
214 signal EventBufAddr_we_cntr : array3X32 := (others => (others => '0'));
215 signal src_ID : array3X16 := (others => (others => '0'));
216 signal txusrclk : std_logic := '0';
217 signal LinkDatap : array3X64 := (others => (others => '0'));
218 signal sfp_pd : array3X2 := (others => (others => '0'));
219 signal WrtMonEvtDoneCntr : array3X8 := (others => (others => '0'));
220 signal chk_MonBuf_avl : std_logic := '0';
221 signal FirstBlkAddrDo : array2x3x12 := (others => (others => (others => '0')));
222 signal FirstBlkAddr_ra : array2x3x5 := (others => (others => (others => '0')));
223 signal FirstBlkAddr_re : array2X3 := (others => (others => '0'));
224 signal WrtMonEvtDone_l : std_logic_vector(2 downto 0) := (others => '0');
225 signal MonEvtQueued : std_logic_vector(2 downto 0) := (others => '0');
226 signal FirstBlkAddrDoValid : array2X3 := (others => (others => '0'));
227 signal FirstBlkAddr_wa : std_logic_vector(4 downto 0) := (others => '0');
228 signal FirstBlkAddrDi : std_logic_vector(11 downto 0) := (others => '0');
229 signal FirstBlkAddr_we : std_logic := '0';
230 signal MonBuf_full : std_logic := '0';
231 signal mon_evt_cnt_i : std_logic_vector(10 downto 0) := (others => '0');
232 signal status_addr : std_logic_vector(15 downto 0) := (others => '0');
233 signal cmsCRC_initp : std_logic_vector(2 downto 0) := (others => '0');
234 signal cmsCRC_init : std_logic_vector(2 downto 0) := (others => '0');
235 signal cmsCRC_err : std_logic_vector(2 downto 0) := (others => '0');
236 signal cmsCRC_errCntr : array3X32 := (others => (others => '0'));
237 signal TotalEvtLengthCntr24q : std_logic_vector(2 downto 0) := (others => '0');
238 signal EvtLength_errCntr : array3X32 := (others => (others => '0'));
239 signal AMClength_errCntr : array3X32 := (others => (others => '0'));
240 signal AMCvalid_errCntr : array3X32 := (others => (others => '0'));
241 signal AMCcrc_errCntr : array3X32 := (others => (others => '0'));
242 signal TotalEvtLengthCntr : array3X56 := (others => (others => '0'));
243 signal StopOverWrite : std_logic := '0';
244 signal en_stop : std_logic_vector(4 downto 0) := (others => '1');
245 signal stop : std_logic := '0';
246 signal inc_err : array3x5 := (others => (others => '0'));
247 component chipscope1 is
248  generic (N : integer := 5);
249  Port ( clk : in STD_LOGIC;
250  Din : in STD_LOGIC_VECTOR (303 downto 0));
251 end component;
252 signal cs : std_logic_vector(303 downto 0) := (others => '0');
253 begin
254 --i_chipscope: chipscope1
255 -- Port map( clk => sysclk, Din => cs);
256 MonBufOvfl <= '0';
257 EventBufAddr_we <= EventBufAddr_we_i;
258 mon_evt_cnt(31 downto 11) <= (others => '0');
259 mon_evt_cnt(10 downto 0) <= mon_evt_cnt_i;
260 ipb_ack <= '0';
261 sfp_pd(0) <= "00" when Dis_pd = '1' or SFP_ABS(0) = '0' else "11";
262 sfp_pd(1) <= "00" when Dis_pd = '1' or SFP_ABS(1) = '0' else "11";
263 sfp_pd(2) <= "00" when Dis_pd = '1' or SFP_ABS(2) = '0' else "11";
264 SFP_down(2) <= not LinkDown(2) and not enSFP(3) and enSFP(2);
265 SFP_down(1) <= not LinkDown(1) and not enSFP(3) and enSFP(1);
266 SFP_down(0) <= not LinkDown(0) and not enSFP(3) and enSFP(0);
267 LinkFull(2) <= not LinkFull_n(2) and not enSFP(3) and enSFP(2);
268 LinkFull(1) <= not LinkFull_n(1) and not enSFP(3) and enSFP(1);
269 LinkFull(0) <= not LinkFull_n(0) and not enSFP(3) and enSFP(0);
270 i_DaqLSCXG: DaqLSCXG PORT MAP(
271  sys_reset => daq_resetSyncRegs (2),
272  sys_clk => sysclk,
273  sfp_pd => sfp_pd,
274  DRP_clk => DRPclk,
275  LinkWe => LinkWe,
276  LinkCtrl => LinkCtrl,
277  LinkData => LinkDatap,
278  srcID => src_ID,
279  LinkDown => LinkDown,
280  LinkFull => LinkFull_n,
281  sync_loss => sync_loss,
282  status_ce => "000",
283  status_addr => status_addr ,
284  status_port => DaqLSC_status ,
285  txusrclk_o => txusrclk,
286  rxusrclk_o => open,
287  gtx_reset => gtx_reset,
288  gtx_refclk_p => SFP_REFCLK_P ,
289  gtx_refclk_n => SFP_REFCLK_N ,
290  sfp_rxn => sfp_rxn,
291  sfp_rxp => sfp_rxp,
292  sfp_txn => sfp_txn,
293  sfp_txp => sfp_txp
294  );
295 status_addr <= x"000" & ipb_addr(3 downto 0);
296 LinkDatap(0) <= LinkData(0)(63 downto 0);
297 LinkDatap(1) <= LinkData(1)(63 downto 0);
298 LinkDatap(2) <= LinkData(2)(63 downto 0);
299 src_ID(0) <= LSC_ID(15 downto 2) & "00";
300 src_ID(1) <= LSC_ID(15 downto 2) & "01";
301 src_ID(2) <= LSC_ID(15 downto 2) & "10";
302 sfp_rxn(0) <= SFP0_RXN;
303 sfp_rxp(0) <= SFP0_RXP;
304 SFP0_TXN <= sfp_txn(0);
305 SFP0_TXP <= sfp_txp(0);
306 sfp_rxn(1) <= SFP1_RXN;
307 sfp_rxp(1) <= SFP1_RXP;
308 SFP1_TXN <= sfp_txn(1);
309 SFP1_TXP <= sfp_txp(1);
310 sfp_rxn(2) <= SFP2_RXN;
311 sfp_rxp(2) <= SFP2_RXP;
312 SFP2_TXN <= sfp_txn(2);
313 SFP2_TXP <= sfp_txp(2);
314 process(sysclk,daq_reset)
315 begin
316  if(daq_reset = '1')then
317  daq_resetSyncRegs <= (others => '1');
318  elsif(sysclk'event and sysclk = '1')then
319  daq_resetSyncRegs <= daq_resetSyncRegs(1 downto 0) & '0';
320  end if;
321 end process;
322 process(sysclk,reset)
323 begin
324  if(reset = '1')then
325  resetSyncRegs <= (others => '1');
326  elsif(sysclk'event and sysclk = '1')then
327  resetSyncRegs <= resetSyncRegs(1 downto 0) & '0';
328  end if;
329 end process;
330 g_FirstBlkAddr: for j in 0 to 1 generate
331  g1_FirstBlkAddr: for i in 0 to 5 generate
332  i_FirstBlkAddr : RAM32M
333  port map (
334  DOA => FirstBlkAddrDo(j)(0)(i*2+1 downto i*2), -- Read port A 2-bit output
335  DOB => FirstBlkAddrDo(j)(1)(i*2+1 downto i*2), -- Read port B 2-bit output
336  DOC => FirstBlkAddrDo(j)(2)(i*2+1 downto i*2), -- Read port C 2-bit output
337  DOD => open, -- Read/Write port D 2-bit output
338  ADDRA => FirstBlkAddr_ra(j)(0), -- Read port A 5-bit address input
339  ADDRB => FirstBlkAddr_ra(j)(1), -- Read port B 5-bit address input
340  ADDRC => FirstBlkAddr_ra(j)(2), -- Read port C 5-bit address input
341  ADDRD => FirstBlkAddr_wa, -- Read/Write port D 5-bit address input
342  DIA => FirstBlkAddrDi(i*2+1 downto i*2), -- RAM 2-bit data write input addressed by ADDRD,
343  -- read addressed by ADDRA
344  DIB => FirstBlkAddrDi(i*2+1 downto i*2), -- RAM 2-bit data write input addressed by ADDRD,
345  -- read addressed by ADDRB
346  DIC => FirstBlkAddrDi(i*2+1 downto i*2), -- RAM 2-bit data write input addressed by ADDRD,
347  -- read addressed by ADDRC
348  DID => "00", -- RAM 2-bit data write input addressed by ADDRD,
349  -- read addressed by ADDRD
350  WCLK => sysclk, -- Write clock input
351  WE => FirstBlkAddr_we -- Write enable input
352  );
353  end generate;
354 end generate;
355 FirstBlkAddrDi <= '0' & MonBuf_wa;
356 process(sysclk)
357 begin
358  if(sysclk'event and sysclk = '1')then
359  if(resetSyncRegs(2) = '1')then
360  chk_MonBuf_avl <= '1';
361  elsif(buf_rqst(0) = '1')then
362  chk_MonBuf_avl <= buf_rqst(3);
363  end if;
364  if(resetSyncRegs(2) = '1')then
365  MonBuf_avl <= '1';
366  elsif(WaitMonBuf = '1' or MonBufOverWrite = '1')then
367  if((MonBuf_wa(10) /= MonBuf_ra(10) and MonBuf_wa(9 downto 0) = MonBuf_ra(9 downto 0)))then
368  MonBuf_avl <= '0';
369  else
370  MonBuf_avl <= '1';
371  end if;
372  elsif(chk_MonBuf_avl = '1')then
373  if(MonBufUsed(9 downto 8) = "11")then
374  MonBuf_avl <= '0';
375  else
376  MonBuf_avl <= '1';
377  end if;
378  end if;
379  if(MonBufOverWrite = '1')then
380  mon_evt_cnt_i <= '0' & Written_MonBuf(3)(9 downto 0);
381  else
382  mon_evt_cnt_i <= Written_MonBuf(3) - MonBuf_ra;
383  end if;
384  if(MonBufOverWrite = '0')then
385  MonBuf_empty <= not or_reduce(mon_evt_cnt_i);
386  elsif(Written_MonBuf(3) /= MonBuf_ra or MonBuf_full = '1')then
387  MonBuf_empty <= '0';
388  else
389  MonBuf_empty <= '1';
390  end if;
391  if(resetSyncRegs(2) = '1')then
392  ReadBusy <= (others => '0');
393  EventData_re <= (others => '0');
394  EventBufAddr_we_i <= (others => '0');
395  MonBuf_wa <= (others => '0');
396  MonBuf_ra <= (others => '0');
397  MonBufUsed <= (others => '0');
398  Written_MonBufMatch <= (others => '1');
399  Written_MonBuf <= (others => (others => '0'));
400  NXT_MonBuf <= (others => (others => '0'));
401  inc_ddr_paSyncRegs <= (others => '0');
402  FirstBlkAddr_we <= '0';
403  FirstBlkAddr_re <= (others => (others => '0'));
404  FirstBlkAddrDoValid <= (others => (others => '0'));
405  WrtMonEvtDone_l <= (others => '0');
406  WrtMonEvtDoneCntr <= (others => (others => '0'));
407  MonEvtQueued <= (others => '0');
408  FirstBlkAddr_wa <= (others => '0');
409  FirstBlkAddr_ra <= (others => (others => (others => '0')));
410  MonBuf_full <= '0';
411  else
412  for i in 0 to 2 loop
413  if(EVENTdata_in(i)(64) = '1' and EVENTdata_we(i) = '1')then
414  ReadBusy(i) <= '0';
415  elsif(evt_data_rdy(i) = '1' and wport_rdy(i) = '1')then
416  ReadBusy(i) <= '1';
417  end if;
418  EventData_re(i) <= evt_data_rdy(i) and wport_rdy(i) and not ReadBusy(i);
419  if(EventData_in(i)(66) = '0' and evt_data_rdy(i) = '1' and wport_rdy(i) = '1' and ReadBusy(i) = '0')then
420  EventBufAddr_we_i(i) <= '1';
421  else
422  EventBufAddr_we_i(i) <= '0';
423  end if;
424  end loop;
425  if(MonBufOverWrite = '1' and Written_MonBuf(3)(10) = '1')then
426  MonBuf_full <= '1';
427  end if;
428  for j in 0 to 1 loop
429  for i in 0 to 2 loop
430  if(FirstBlkAddr_re(j)(i) = '1')then
431  FirstBlkAddr_ra(j)(i) <= FirstBlkAddr_ra(j)(i) + 1;
432  end if;
433  if(FirstBlkAddr_ra(j)(i) = FirstBlkAddr_wa)then
434  FirstBlkAddrDoValid(j)(i) <= '0';
435  else
436  FirstBlkAddrDoValid(j)(i) <= '1';
437  end if;
438  end loop;
439  end loop;
440  if(FirstBlkAddr_we = '1')then
441  FirstBlkAddr_wa <= FirstBlkAddr_wa + 1;
442  end if;
443  for i in 0 to 2 loop
444  if(WrtMonEvtDone(i) = '1')then
445  WrtMonEvtDoneCntr(i) <= WrtMonEvtDoneCntr(i) + 1;
446  end if;
447  if(WrtMonEvtDone(i) = '1')then
448  WrtMonEvtDone_l(i) <= '1';
449  elsif(FirstBlkAddrDoValid(0)(i) = '1')then
450  WrtMonEvtDone_l(i) <= '0';
451  end if;
452  FirstBlkAddr_re(0)(i) <= FirstBlkAddrDoValid(0)(i) and WrtMonEvtDone_l(i);
453  if(EventData_we(i) = '1' and EventData_in(i)(66 downto 65) = "01")then
454  MonEvtQueued(i) <= '1';
455  elsif(FirstBlkAddrDoValid(1)(i) = '1')then
456  MonEvtQueued(i) <= '0';
457  end if;
458  FirstBlkAddr_re(1)(i) <= FirstBlkAddrDoValid(1)(i) and MonEvtQueued(i);
459  end loop;
460 -- FirstBlkAddr_we <= buf_rqst(3) and buf_rqst(0) and MonBuf_avl_i;
461  FirstBlkAddr_we <= buf_rqst(3) and buf_rqst(0);
462 -- if(buf_rqst(0) = '1' and MonBuf_avl_i = '1')then
463  if(buf_rqst(0) = '1')then
464  MonBuf_wa <= MonBuf_wa + 1;
465  end if;
466  MonBufUsed <= MonBuf_wa(9 downto 0) - MonBuf_ra(9 downto 0);
467  if(inc_ddr_paSyncRegs(3 downto 2) = "10" or (MonBufOverWrite = '1' and StopOverWrite = '0' and and_reduce(MonBufUsed) = '1' and buf_rqst(0) = '1'))then
468  MonBuf_ra <= MonBuf_ra + 1;
469  end if;
470  if(Written_MonBuf(0) = Written_MonBuf(3) and WrtMonEvtDone_l(0) = '0')then
471  Written_MonBufMatch(0) <= '1';
472  else
473  Written_MonBufMatch(0) <= '0';
474  end if;
475  if((EnSFP(2 downto 0) = "111" or EnSFP(2 downto 0) = "011" or EnSFP(2 downto 0) = "110" or EnSFP(2 downto 0) = "101") and Written_MonBuf(1) = Written_MonBuf(3) and WrtMonEvtDone_l(1) = '0')then
476  Written_MonBufMatch(1) <= '1';
477  else
478  Written_MonBufMatch(1) <= '0';
479  end if;
480  if(EnSFP(2 downto 0) = "111" and Written_MonBuf(2) = Written_MonBuf(3) and WrtMonEvtDone_l(2) = '0')then
481  Written_MonBufMatch(2) <= '1';
482  else
483  Written_MonBufMatch(2) <= '0';
484  end if;
485  if(Written_MonBufMatch = "000" and sysDIV2 = '0')then
486  Written_MonBuf(3) <= Written_MonBuf(3) + 1;
487  end if;
488  for i in 0 to 2 loop
489  if(FirstBlkAddr_re(0)(i) = '1')then
490  Written_MonBuf(i) <= FirstBlkAddrDo(0)(i)(10 downto 0);
491  elsif(WrtMonBlkDone(i) = '1')then
492  Written_MonBuf(i) <= Written_MonBuf(i) + 1;
493  end if;
494  if(FirstBlkAddr_re(1)(i) = '1')then
495  NXT_MonBuf(i) <= FirstBlkAddrDo(1)(i)(10 downto 0);
496  elsif(EventBufAddr_we_i(i) = '1' and EventData_in(i)(66) = '0')then
497  NXT_MonBuf(i) <= NXT_MonBuf(i) + 1;
498  end if;
499  end loop;
500  inc_ddr_paSyncRegs <= inc_ddr_paSyncRegs(2 downto 0) & inc_ddr_pa;
501  end if;
502  case EnSFP(2 downto 0) is
503  when "011" | "101" | "110" => AddrOffset(0)(9 downto 6) <= x"8";
504  when "111" => AddrOffset(0)(9 downto 6) <= x"5";
505  when others => AddrOffset(0)(9 downto 6) <= x"0";
506  end case;
507  AddrOffset(1)(9 downto 6) <= x"0";
508  AddrOffset(2)(9 downto 6) <= x"a";
509  for i in 0 to 2 loop
510  EventBufAddr(i) <= NXT_MonBuf(i)(9 downto 0) & AddrOffset(i)(9 downto 6);
511  end loop;
512  end if;
513 end process;
514 process(sysclk)
515 begin
516  if(sysclk'event and sysclk = '1')then
517  sysDIV2 <= not sysDIV2;
518  for i in 0 to 2 loop
519  if(resetSyncRegs(2) = '1')then
520  header(i) <= '1';
521  header_q(i) <= '0';
522  elsif(EventData_we(i) = '1')then
523  header(i) <= EventData_in(i)(65) or (header(i) and not header_q(i));
524  header_q(i) <= header(i);
525  end if;
526  end loop;
527  if(EnSFP(2 downto 1) = "00")then
528  SFP_we(0) <= EventData_we(0);
529  EoB(0) <= EventData_in(0)(64);
530  else
531  SFP_we(0) <= EventData_we(1) and EnSFP(0);
532  EoB(0) <= EventData_in(1)(64);
533  end if;
534  if(EnSFP(2 downto 0) = "110")then
535  SFP_we(1) <= EventData_we(1);
536  EoB(1) <= EventData_in(1)(64);
537  else
538  SFP_we(1) <= EventData_we(0) and EnSFP(1);
539  EoB(1) <= EventData_in(0)(64);
540  end if;
541  if(EnSFP(2 downto 0) = "111")then
542  SFP_we(2) <= EventData_we(2);
543  EoB(2) <= EventData_in(2)(64);
544  else
545  SFP_we(2) <= EventData_we(0) and EnSFP(2);
546  EoB(2) <= EventData_in(0)(64);
547  end if;
548  if(EnSFP(2 downto 0) = "001")then
549  LinkData(0) <= EventData_in(0)(65) & EventData_in(0)(63 downto 0);
550  LinkCtrl(0) <= not(header(0) or EventData_in(0)(65));
551  LinkWe(0) <= EventData_we(0) and not EnSFP(3);
552  else
553  LinkData(0) <= EventData_in(1)(65) & EventData_in(1)(63 downto 0);
554  LinkCtrl(0) <= not(header(1) or EventData_in(1)(65));
555  LinkWe(0) <= EventData_we(1) and EnSFP(0) and not EnSFP(3);
556  end if;
557  if(EnSFP(2 downto 0) = "110")then
558  LinkData(1) <= EventData_in(1)(65) & EventData_in(1)(63 downto 0);
559  LinkCtrl(1) <= not(header(1) or EventData_in(1)(65));
560  LinkWe(1) <= EventData_we(1) and not EnSFP(3);
561  else
562  LinkData(1) <= EventData_in(0)(65) & EventData_in(0)(63 downto 0);
563  LinkCtrl(1) <= not(header(0) or EventData_in(0)(65));
564  LinkWe(1) <= EventData_we(0) and EnSFP(1) and not EnSFP(3);
565  end if;
566  if(EnSFP(2 downto 0) = "111")then
567  LinkData(2) <= EventData_in(2)(65) & EventData_in(2)(63 downto 0);
568  LinkCtrl(2) <= not(header(2) or EventData_in(2)(65));
569  LinkWe(2) <= EventData_we(2) and not EnSFP(3);
570  else
571  LinkData(2) <= EventData_in(0)(65) & EventData_in(0)(63 downto 0);
572  LinkCtrl(2) <= not(header(0) or EventData_in(0)(65));
573  LinkWe(2) <= EventData_we(0) and EnSFP(2) and not EnSFP(3);
574  end if;
575  case EnSFP(2 downto 0) is
576  when "010" | "011" | "111" => SFP2bldr_sel(0) <= "01";
577  when "100" | "101" | "110" => SFP2bldr_sel(0) <= "10";
578  when others => SFP2bldr_sel(0) <= "00";
579  end case;
580  case EnSFP(2 downto 0) is
581  when "010" | "011" | "101" | "111" => SFP2bldr_sel(1) <= "00";
582  when others => SFP2bldr_sel(1) <= "01";
583  end case;
584  case EnSFP(2 downto 0) is
585  when "100" | "110" => SFP2bldr_sel(2) <= "00";
586  when "101" => SFP2bldr_sel(2) <= "01";
587  when others => SFP2bldr_sel(2) <= "10";
588  end case;
589  evt_buf_full(0) <= (not LinkFull_n(conv_integer(SFP2bldr_sel(0))) and EnSFP(conv_integer(SFP2bldr_sel(0))) and not EnSFP(3)) or wport_FIFO_full(0);
590  if(SFP2bldr_sel(1)(0) = '0')then
591  evt_buf_full(1) <= (not LinkFull_n(0) and EnSFP(0) and not EnSFP(3)) or wport_FIFO_full(1);
592  else
593  evt_buf_full(1) <= (not LinkFull_n(1) and EnSFP(1) and not EnSFP(3)) or wport_FIFO_full(1);
594  end if;
595  evt_buf_full(2) <= (not LinkFull_n(conv_integer(SFP2bldr_sel(2))) and EnSFP(conv_integer(SFP2bldr_sel(2))) and not EnSFP(3)) or wport_FIFO_full(2);
596  end if;
597 end process;
598 process(txusrclk,rstCntr)
599 begin
600  if(rstCntr = '1')then
601  sync_loss_cntr <= (others => (others => '0'));
602  elsif(txusrclk'event and txusrclk = '1')then
603  for i in 0 to 2 loop
604  if(sync_loss(i) = '1')then
605  sync_loss_cntr(i) <= sync_loss_cntr(i) + 1;
606  end if;
607  end loop;
608  end if;
609 end process;
610 process(sysclk,rstCntr)
611 begin
612  if(rstCntr = '1')then
613  cmsCRC_errCntr <= (others => (others => '0'));
614  EvtLength_errCntr <= (others => (others => '0'));
615  AMCLength_errCntr <= (others => (others => '0'));
616  AMCvalid_errCntr <= (others => (others => '0'));
617  AMCcrc_errCntr <= (others => (others => '0'));
618  StopOverWrite <= '0';
619  elsif(sysclk'event and sysclk = '1')then
620  for i in 0 to 2 loop
621  if(inc_err(i)(0) = '1')then
622  cmsCRC_errCntr(i) <= cmsCRC_errCntr(i) + 1;
623  end if;
624  if(inc_err(i)(1) = '1')then
625  EvtLength_errCntr(i) <= EvtLength_errCntr(i) + 1;
626  end if;
627  if(inc_err(i)(2) = '1')then
628  AMClength_errCntr(i) <= AMClength_errCntr(i) + 1;
629  end if;
630  if(inc_err(i)(3) = '1')then
631  AMCvalid_errCntr(i) <= AMCvalid_errCntr(i) + 1;
632  end if;
633  if(inc_err(i)(4) = '1')then
634  AMCcrc_errCntr(i) <= AMCcrc_errCntr(i) + 1;
635  end if;
636  end loop;
637  if(stop = '1')then
638  StopOverWrite <= '1';
639  end if;
640  end if;
641 end process;
642 i_check_event: check_event PORT MAP(
643  clk => sysclk ,
644  reset => resetSyncRegs(2),
645  en_stop => en_stop,
646  cmsCRC_err => cmsCRC_err,
647  EventData_in => EventData_in ,
648  EventData_we => EventData_we ,
649  inc_err => inc_err,
650  stop => stop
651  );
652 process(ipb_clk)
653 begin
654  if(ipb_clk'event and ipb_clk = '1')then
655  if(ipb_addr(15 downto 7) = LSC_addr(15 downto 7) and ipb_addr(6 downto 0) = "1110001" and ipb_write = '1' and ipb_strobe = '1')then
656  en_stop <= ipb_wdata(4 downto 0);
657  end if;
658  end if;
659 end process;
660 process(ipb_addr)
661 begin
662  if(ipb_addr(15 downto 7) = LSC_addr(15 downto 7))then
663  case ipb_addr(6 downto 4) is
664  when "000" =>
665  ipb_rdata <= DaqLSC_status(0)(31 downto 0);
666  when "001" =>
667  ipb_rdata <= DaqLSC_status(1)(31 downto 0);
668  when "010" =>
669  ipb_rdata <= DaqLSC_status(2)(31 downto 0);
670  when "011" =>
671  case ipb_addr(3 downto 0) is
672  when x"0" => ipb_rdata <= sync_loss_cntr(0);
673  when x"1" => ipb_rdata <= sync_loss_cntr(1);
674  when x"2" => ipb_rdata <= sync_loss_cntr(2);
675  when x"3" => ipb_rdata <= cmsCRC_errCntr(0);
676  when x"4" => ipb_rdata <= cmsCRC_errCntr(1);
677  when x"5" => ipb_rdata <= cmsCRC_errCntr(2);
678  when x"6" => ipb_rdata <= EvtLength_errCntr(0);
679  when x"7" => ipb_rdata <= EvtLength_errCntr(1);
680  when x"8" => ipb_rdata <= EvtLength_errCntr(2);
681  when x"a" => ipb_rdata <= TotalEvtLengthCntr(0)(31 downto 0);
682  when x"b" => ipb_rdata <= x"00" & TotalEvtLengthCntr(0)(55 downto 32);
683  when x"c" => ipb_rdata <= TotalEvtLengthCntr(1)(31 downto 0);
684  when x"d" => ipb_rdata <= x"00" & TotalEvtLengthCntr(1)(55 downto 32);
685  when x"e" => ipb_rdata <= TotalEvtLengthCntr(2)(31 downto 0);
686  when x"f" => ipb_rdata <= x"00" & TotalEvtLengthCntr(2)(55 downto 32);
687  when others => ipb_rdata <= (others => '0');
688  end case;
689  when "100" =>
690  case ipb_addr(3 downto 0) is
691  when x"0" => ipb_rdata <= SFP_evt_cntr(0);
692  when x"1" => ipb_rdata <= SFP_evt_cntr(1);
693  when x"2" => ipb_rdata <= SFP_evt_cntr(2);
694  when x"4" => ipb_rdata <= SFP_word_cntr(0);
695  when x"5" => ipb_rdata <= SFP_word_cntr(1);
696  when x"6" => ipb_rdata <= SFP_word_cntr(2);
697  when x"8" => ipb_rdata <= SFP_blk_cntr(0);
698  when x"9" => ipb_rdata <= SFP_blk_cntr(1);
699  when x"a" => ipb_rdata <= SFP_blk_cntr(2);
700  when others => ipb_rdata <= (others => '0');
701  end case;
702  when "101" =>
703  case ipb_addr(3 downto 0) is
704  when x"0" => ipb_rdata <= "00000" & Written_MonBuf(1) & "00000" & Written_MonBuf(0);
705  when x"1" => ipb_rdata <= "00000" & Written_MonBuf(3) & "00000" & Written_MonBuf(2);
706  when x"2" => ipb_rdata <= "00000" & NXT_MonBuf(1) & "00000" & NXT_MonBuf(0);
707  when x"3" => ipb_rdata <= "00000" & MonBuf_wa & "00000" & NXT_MonBuf(2);
708  when x"4" => ipb_rdata <= x"00" & '0' & header & '0' & LinkFull & '0' & ReadBusy & '0' & evt_data_rdy & '0' & wport_FIFO_full & '0' & wport_rdy;
709  when x"5" => ipb_rdata <= event_cntr(0);
710  when x"6" => ipb_rdata <= event_cntr(1);
711  when x"7" => ipb_rdata <= event_cntr(2);
712  when x"8" => ipb_rdata <= word_cntr(0);
713  when x"9" => ipb_rdata <= word_cntr(1);
714  when x"a" => ipb_rdata <= word_cntr(2);
715  when x"b" => ipb_rdata <= EventBufAddr_we_cntr(0);
716  when x"c" => ipb_rdata <= EventBufAddr_we_cntr(1);
717  when x"d" => ipb_rdata <= EventBufAddr_we_cntr(2);
718  when others => ipb_rdata <= (others => '0');
719  end case;
720  when "110" =>
721  case ipb_addr(3 downto 0) is
722  when x"0" => ipb_rdata <= AMClength_errCntr(0);
723  when x"1" => ipb_rdata <= AMClength_errCntr(1);
724  when x"2" => ipb_rdata <= AMClength_errCntr(2);
725  when x"4" => ipb_rdata <= AMCvalid_errCntr(0);
726  when x"5" => ipb_rdata <= AMCvalid_errCntr(1);
727  when x"6" => ipb_rdata <= AMCvalid_errCntr(2);
728  when x"8" => ipb_rdata <= AMCcrc_errCntr(0);
729  when x"9" => ipb_rdata <= AMCcrc_errCntr(1);
730  when x"a" => ipb_rdata <= AMCcrc_errCntr(2);
731  when others => ipb_rdata <= (others => '0');
732  end case;
733  when others =>
734  case ipb_addr(3 downto 0) is
735  when x"0" => ipb_rdata <= x"000000" & "000" & en_stop;
736  when x"1" => ipb_rdata <= "000" & FirstBlkAddr_ra(1)(1) & "000" & FirstBlkAddr_ra(0)(1) & "000" & FirstBlkAddr_ra(1)(0) & "000" & FirstBlkAddr_ra(0)(0);
737  when x"2" => ipb_rdata <= x"00" & "000" & FirstBlkAddr_wa & "000" & FirstBlkAddr_ra(1)(2) & "000" & FirstBlkAddr_ra(0)(2);
738  when x"3" => ipb_rdata <= x"0" & FirstBlkAddrDo(1)(0) & x"0" & FirstBlkAddrDo(0)(0);
739  when x"4" => ipb_rdata <= x"0" & FirstBlkAddrDo(1)(1) & x"0" & FirstBlkAddrDo(0)(1);
740  when x"5" => ipb_rdata <= x"0" & FirstBlkAddrDo(1)(2) & x"0" & FirstBlkAddrDo(0)(2);
741  when x"6" => ipb_rdata <= x"0000" & '0' & MonEvtQueued & '0' & WrtMonEvtDone_l & '0' & FirstBlkAddrDoValid(1) & '0' & FirstBlkAddrDoValid(0);
742  when x"7" => ipb_rdata <= x"00" & WrtMonEvtDoneCntr(2) & WrtMonEvtDoneCntr(1) & WrtMonEvtDoneCntr(0);
743  when others => ipb_rdata <= (others => '0');
744  end case;
745  end case;
746  else
747  ipb_rdata <= (others => '0');
748  end if;
749 end process;
750 g_cmsCRC : for i in 0 to 2 generate
751  i_cmsCRC: cmsCRC64 PORT MAP(
752  clk => sysclk ,
753  reset => '0',
754  crc_init => cmsCRC_init(i),
755  trailer => LinkData(i)(64),
756  crc_d => LinkData(i)(63 downto 0),
757  crc_ce => LinkWe(i),
758  crc => open,
759  crc_err => cmsCRC_err(i),
760  dout => open,
761  dout_vld => open
762  );
763 end generate;
764 process(sysclk)
765 begin
766  if(sysclk'event and sysclk = '1')then
767  if(resetSyncRegs(2) = '1')then
768  cmsCRC_initp <= "000";
769  cmsCRC_init <= "111";
770  SFP_blk_cntr <= (others => (others => '0'));
771  SFP_evt_cntr <= (others => (others => '0'));
772  SFP_word_cntr <= (others => (others => '0'));
773  event_cntr <= (others => (others => '0'));
774  word_cntr <= (others => (others => '0'));
775  EventBufAddr_we_cntr <= (others => (others => '0'));
776  TotalEvtLengthCntr <= (others => (others => '0'));
777  TotalEvtLengthCntr24q <= "000";
778  else
779  for i in 0 to 2 loop
780  cmsCRC_initp(i) <= LinkData(i)(64) and LinkWe(i);
781  if(LinkWe(i) = '1')then
782  word_cntr(i) <= word_cntr(i) + 1;
783  end if;
784  if(LinkWe(i) = '1' and LinkData(i)(64) = '1')then
785  event_cntr(i) <= event_cntr(i) + 1;
786  end if;
787  if(SFP_we(i) = '1' and EoB(i) = '1')then
788  SFP_blk_cntr(i) <= SFP_blk_cntr(i) + 1;
789  end if;
790  if(SFP_we(i) = '1' and LinkData(i)(64) = '1')then
791  SFP_evt_cntr(i) <= SFP_evt_cntr(i) + 1;
792  end if;
793  if(SFP_we(i) = '1')then
794  SFP_word_cntr(i) <= SFP_word_cntr(i) + 1;
795  end if;
796  if(EventBufAddr_we_i(i) = '1')then
797  EventBufAddr_we_cntr(i) <= EventBufAddr_we_cntr(i) + 1;
798  end if;
799  if(EventData_we(i) = '1')then
800  if(EventData_in(i)(65) = '1')then
801  TotalEvtLengthCntr(i)(24 downto 0) <= TotalEvtLengthCntr(i)(24 downto 0) + ('0' & EventData_in(i)(55 downto 32));
802  end if;
803  end if;
804  TotalEvtLengthCntr24q(i) <= TotalEvtLengthCntr(i)(24);
805  if(TotalEvtLengthCntr24q(i) = '1' and TotalEvtLengthCntr(i)(24) = '0')then
806  TotalEvtLengthCntr(i)(55 downto 25) <= TotalEvtLengthCntr(i)(55 downto 25) + 1;
807  end if;
808  end loop;
809  cmsCRC_init <= cmsCRC_initp;
810  end if;
811  end if;
812 end process;
813 end Behavioral;
814 
Generated on Sun Mar 6 2016 12:24:18 for AMC13 by   doxygen 1.8.1