AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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DaqLSCXG10G.vhd
1 
2 library IEEE;
3 use IEEE.STD_LOGIC_1164.ALL;
4 use ieee.std_logic_unsigned.all;
5 use work.amc13_pack.all;
6 use work.mydefs.all;
7 
8 
9 library UNISIM;
10 use UNISIM.VComponents.all;
11 
12 entity DaqLSCXG is
13  Port ( sys_reset : in STD_LOGIC; -- active high reset of all logic but GTX
14  sys_clk : in STD_LOGIC;
15  sfp_pd : in array2x2;
16  DRP_clk : in STD_LOGIC;
17  LinkWe : in STD_LOGIC_VECTOR (1 downto 0);
18  LinkCtrl : in STD_LOGIC_VECTOR (1 downto 0);
19  LinkData : in array2x64;
20  srcID : in array2x16;
21  LinkDown : out STD_LOGIC_VECTOR (1 downto 0);
22  LinkFull : out STD_LOGIC_VECTOR (1 downto 0);
23  --
24 -- ack_cnt : out STD_LOGIC_VECTOR (2 downto 0); -- 1 ck pulse (txusrclk) indicating a received acknowledge
25 -- pckt_cnt : out STD_LOGIC_VECTOR (2 downto 0); -- 1 ck pulse (txusrclk) indicating a transmit packet
26 -- retransmit_cnt : out STD_LOGIC_VECTOR (2 downto 0); -- 1 ck pulse (txusrclk) indicating a retransmit packet
27 -- event_cnt : out STD_LOGIC_VECTOR (2 downto 0); -- 1 ck pulse (sys_clk) indicating a sent event
28  sync_loss : out STD_LOGIC_VECTOR (1 downto 0); -- goes to '1' (rxusrclk) when SERDES is out of synch
29  status_ce : in std_logic_VECTOR (1 downto 0); -- not implemented yet
30  status_addr : in STD_LOGIC_VECTOR (15 downto 0); -- not implemented yet
31  status_port : out array2x64; -- first 32 bits are hard-wired
32  --
33  txusrclk_o : out STD_LOGIC; -- reconstructed tx clock, to be used to clock sending circuitry
34  rxusrclk_o : out STD_LOGIC; -- reconstructed rx clock, to be used to clock receiving circuitry
35  --
36  gtx_reset : in std_logic; -- full reset of GTX only
37  gtx_refclk_p : in std_logic; -- iob for refclk neg
38  gtx_refclk_n : in std_logic; -- iob for refclk neg
39  sfp_rxn : in std_logic_VECTOR (1 downto 0); -- sfp iobs
40  sfp_rxp : in std_logic_VECTOR (1 downto 0);
41  sfp_txn : out std_logic_VECTOR (1 downto 0);
42  sfp_txp : out std_logic_VECTOR (1 downto 0)
43  );
44 end DaqLSCXG;
45 
46 architecture Behavioral of DaqLSCXG is
47 COMPONENT SLINK_opt_XGMII
48 port (
49  reset : in std_logic;
50  -- FED interface
51  SYS_CLK : in std_logic;
52  LINKWe : in std_logic;
53  LINKCtrl : in std_logic;
54  LINKData : in std_logic_vector(63 downto 0);
55  src_ID : in std_logic_vector(15 downto 0);
56  inject_err : in std_logic_vector(17 downto 0);
57  read_CE : in std_logic;
58  Addr : in std_logic_vector(15 downto 0);
59  status_data : out std_logic_vector(63 downto 0);
60  LINKDown : out std_logic;
61  LINK_LFF : out std_logic;
62 
63  -- interface SERDES
64  clock : in std_logic;
65  serdes_init : in std_logic;
66  SD_Data_o : out std_logic_vector(63 downto 0);
67  SD_Kb_o : out std_logic_vector(7 downto 0);
68  clock_r : in std_logic;
69  SD_Data_i : in std_logic_vector(63 downto 0);
70  SD_Kb_i : in std_logic_vector(7 downto 0);
71 
72  Serdes_status : in std_logic_vector(31 downto 0)
73 
74  );
75 END COMPONENT;
76 COMPONENT XGMII_serdes_wapper
77  PORT(
78  DRPclk : IN std_logic;
79  reset : IN std_logic;
80  gtx_reset : IN std_logic;
81  SFP0_RXN : IN std_logic;
82  SFP0_RXP : IN std_logic;
83  SFP1_RXN : IN std_logic;
84  SFP1_RXP : IN std_logic;
85  SFP_REFCLK_P : IN std_logic;
86  SFP_REFCLK_N : IN std_logic;
87  xgmii_txd : IN array2x64;
88  xgmii_txc : IN array2x8;
89  SFP0_TXN : OUT std_logic;
90  SFP0_TXP : OUT std_logic;
91  SFP1_TXN : OUT std_logic;
92  SFP1_TXP : OUT std_logic;
93  clk156 : OUT std_logic;
94  PCS_lock : OUT std_logic_vector(1 downto 0);
95  gtx_rxresetdone : OUT std_logic_vector(1 downto 0);
96  xgmii_rxd : OUT array2x64;
97  xgmii_rxc : OUT array2x8
98  );
99 END COMPONENT;
100 
101 -- Local signals
102 
103 signal sys_reset_bar : std_logic;
104 signal serdes_core_clk156_out : std_logic;
105 signal txdata, rxdata : array2x64;
106 signal rxcharisk, txcharisk, rxchariscomma, gtx_rxnotintable : array2x8;
107 signal gtx_rxresetdone : std_logic_vector(1 downto 0);
108 signal PCS_lock : std_logic_vector(1 downto 0);
109 signal serdes_status : array2x32 := (others => (others => '0'));
110 begin
111 txusrclk_o <= serdes_core_clk156_out;
112 rxusrclk_o <= serdes_core_clk156_out;
113 sync_loss <= not PCS_lock;
114 g_SLINK_opt : for i in 0 to 1 generate
115  Inst_SLINK_opt: SLINK_opt_XGMII
116 PORT MAP(
117 -- FROM FED logic
118  reset => sys_reset_bar, -- needs an active low reset
119  SYS_CLK => sys_clk,
120 -- DATA interface from FED
121  LINKWe => not LinkWe (i),
122  LINKCtrl => LinkCtrl(i),
123  LINKData => LinkData(i),
124  src_ID => srcID(i),
125  inject_err => (others =>'0'),
126  read_CE => '0',
127  Addr => status_addr,
128  status_data => status_port(i),
129  serdes_status => serdes_status(i),
130  LINKDown => LinkDown(i),
131  LINK_LFF => LinkFull(i),
132 -- SERDES interface
133  clock => serdes_core_clk156_out, --clk_156_service, -- clk tx from SERDES
134  serdes_init => serdes_status(i)(0), -- status that comes back from GTX
135  SD_Data_o => TXDATA(i), -- data sent to serdes (64 bit)
136  SD_Kb_o => TXCHARISK(i), -- control K associated to SD_Data_o (8 bits)
137  clock_r => serdes_core_clk156_out, -- reconstructed clock from SERDES
138  SD_Data_i => RXDATA(i), -- return data from SERDES 64 bit
139  SD_Kb_i => RXCHARISK(i) -- return control K associated to SD_Data_i (8 bits)
140  );
141  serdes_status(i)(0) <= PCS_lock(i);
142  serdes_status(i)(1) <= gtx_rxresetdone(i);
143 end generate;
144 sys_reset_bar <= not(sys_reset);
145 i_XGMII_serdes_wapper: XGMII_serdes_wapper PORT MAP(
146  DRPclk => DRP_clk,
147  reset => sys_reset,
148  gtx_reset => gtx_reset,
149  SFP0_RXN => sfp_rxn(0),
150  SFP0_RXP => sfp_rxp(0),
151  SFP1_RXN => sfp_rxn(1),
152  SFP1_RXP => sfp_rxp(1),
153  SFP0_TXN => sfp_txn(0),
154  SFP0_TXP => sfp_txp(0),
155  SFP1_TXN => sfp_txn(1),
156  SFP1_TXP => sfp_txp(1),
157  SFP_REFCLK_P => gtx_refclk_p ,
158  SFP_REFCLK_N => gtx_refclk_n ,
159  clk156 => serdes_core_clk156_out,
160  PCS_lock => PCS_lock,
161  gtx_rxresetdone => gtx_rxresetdone ,
162  xgmii_txd => TXDATA,
163  xgmii_txc => TXCHARISK,
164  xgmii_rxd => RXDATA,
165  xgmii_rxc => RXCHARISK
166  );
167 end Behavioral;
168 
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