AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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DAQLSCXG10G_if.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 14:07:47 10/07/2013
6 -- Design Name:
7 -- Module Name: TCPIP_if - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 use IEEE.numeric_std.all;
26 use work.amc13_pack.all;
27 
28 -- Uncomment the following library declaration if using
29 -- arithmetic functions with Signed or Unsigned values
30 --use IEEE.NUMERIC_STD.ALL;
31 
32 -- Uncomment the following library declaration if instantiating
33 -- any Xilinx primitives in this code.
34 library UNISIM;
35 use UNISIM.VComponents.all;
36 Library UNIMACRO;
37 use UNIMACRO.vcomponents.all;
38 
39 entity DAQLSCXG_2x_if is
40  Port ( sysclk : in STD_LOGIC;
41  clk125 : in STD_LOGIC;
42  DRPclk : in STD_LOGIC;
43  reset : in STD_LOGIC;
44  daq_reset : in STD_LOGIC;
45  gtx_reset : in STD_LOGIC;
46  rstCntr : in STD_LOGIC;
47  Dis_pd : in STD_LOGIC;
48  test : in STD_LOGIC;
49  enSFP : IN std_logic_vector(3 downto 0);
50  SFP_ABS : IN std_logic_vector(1 downto 0);
51  LSC_ID : IN std_logic_vector(15 downto 0);
52  SFP_down : OUT std_logic_vector(2 downto 0);
53  inc_ddr_pa : in STD_LOGIC;
54 -- event data in
55  evt_data_rdy : in std_logic_vector(2 downto 0);
56  EventData_in : in array3X67;
57  EventData_we : in std_logic_VECTOR(2 downto 0);
58  EventData_re : out std_logic_VECTOR(2 downto 0); --
59  evt_buf_full : out std_logic_vector(2 downto 0);
60  buf_rqst : in std_logic_vector(3 downto 0);
61  WaitMonBuf : IN std_logic;
62  MonBufOverWrite : in STD_LOGIC;
63  MonBuf_avl : out STD_LOGIC;
64  MonBuf_empty : out STD_LOGIC;
65  MonBufOvfl : out STD_LOGIC;
66  mon_evt_cnt : out std_logic_vector(31 downto 0);
67  WrtMonBlkDone : in STD_LOGIC_VECTOR(2 downto 0);
68  WrtMonEvtDone : in STD_LOGIC_VECTOR(2 downto 0);
69 -- ddr wportA status
70  wport_rdy : in std_logic_vector(2 downto 0);
71  wport_FIFO_full : in std_logic_vector(2 downto 0);
72 -- signal to ddr_if, AMC_if to start moving data
73  EventBufAddr_we : out std_logic_VECTOR(2 downto 0);
74  EventBufAddr : out array3X14;
75 -- SFP ports
76  SFP0_RXN : in STD_LOGIC;
77  SFP0_RXP : in STD_LOGIC;
78  SFP1_RXN : in STD_LOGIC;
79  SFP1_RXP : in STD_LOGIC;
80  SFP0_TXN : out STD_LOGIC;
81  SFP0_TXP : out STD_LOGIC;
82  SFP1_TXN : out STD_LOGIC;
83  SFP1_TXP : out STD_LOGIC;
84  SFP_REFCLK_P : in STD_LOGIC;
85  SFP_REFCLK_N : in STD_LOGIC;
86 -- ipbus signals
87  ipb_clk : in STD_LOGIC;
88  ipb_write : in STD_LOGIC;
89  ipb_strobe : in STD_LOGIC;
90  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
91  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
92  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
93  ipb_ack : out STD_LOGIC
94  );
95 end DAQLSCXG_2x_if;
96 
97 architecture Behavioral of DAQLSCXG_2x_if is
98 COMPONENT DaqLSCXG
99  Port ( sys_reset : in STD_LOGIC; -- active high reset of all logic but GTX
100  sys_clk : in STD_LOGIC;
101  sfp_pd : in array2x2;
102  DRP_clk : in STD_LOGIC;
103  LinkWe : in STD_LOGIC_VECTOR (1 downto 0);
104  LinkCtrl : in STD_LOGIC_VECTOR (1 downto 0);
105  LinkData : in array2x64;
106  srcID : in array2x16;
107  LinkDown : out STD_LOGIC_VECTOR (1 downto 0);
108  LinkFull : out STD_LOGIC_VECTOR (1 downto 0);
109  --
110  sync_loss : out STD_LOGIC_VECTOR (1 downto 0); -- goes to '1' (rxusrclk) when SERDES is out of synch
111  status_ce : in std_logic_VECTOR (1 downto 0); -- not implemented yet
112  status_addr : in STD_LOGIC_VECTOR (15 downto 0); -- not implemented yet
113  status_port : out array2x64; -- first 32 bits are hard-wired
114  --
115  txusrclk_o : out STD_LOGIC; -- reconstructed tx clock, to be used to clock sending circuitry
116  rxusrclk_o : out STD_LOGIC; -- reconstructed rx clock, to be used to clock receiving circuitry
117  --
118  gtx_reset : in std_logic; -- full reset of GTX only
119  gtx_refclk_p : in std_logic; -- iob for refclk neg
120  gtx_refclk_n : in std_logic; -- iob for refclk neg
121  sfp_rxn : in std_logic_VECTOR (1 downto 0); -- sfp iobs
122  sfp_rxp : in std_logic_VECTOR (1 downto 0);
123  sfp_txn : out std_logic_VECTOR (1 downto 0);
124  sfp_txp : out std_logic_VECTOR (1 downto 0)
125  );
126 END COMPONENT;
127 COMPONENT cmsCRC64
128  PORT(
129  clk : IN std_logic;
130  reset : IN std_logic;
131  crc_init : IN std_logic;
132  trailer : IN std_logic;
133  crc_d : IN std_logic_vector(63 downto 0);
134  crc_ce : IN std_logic;
135  crc : OUT std_logic_vector(15 downto 0);
136  crc_err : OUT std_logic;
137  dout : OUT std_logic_vector(63 downto 0);
138  dout_vld : OUT std_logic
139  );
140 END COMPONENT;
141 COMPONENT check_event
142  PORT(
143  clk : IN std_logic;
144  reset : IN std_logic;
145  en_stop : IN std_logic_vector(4 downto 0);
146  cmsCRC_err : IN std_logic_vector(2 downto 0);
147  EventData_in : IN array3X67;
148  EventData_we : IN std_logic_vector(2 downto 0);
149  inc_err : OUT array3X5;
150  stop : OUT std_logic
151  );
152 END COMPONENT;
153 function A_GT_B (A, B : std_logic_vector(10 downto 0)) return boolean is
154 variable tmp : std_logic_vector(10 downto 0);
155 begin
156  tmp := A - B;
157  if(tmp(10) = '0' and or_reduce(tmp(9 downto 0)) = '1')then
158  return true;
159  else
160  return false;
161  end if;
162 end A_GT_B;
163 function A_GE_B (A, B : std_logic_vector(10 downto 0)) return boolean is
164 variable tmp : std_logic_vector(10 downto 0);
165 begin
166  tmp := A - B;
167  if(tmp(10) = '0')then
168  return true;
169  else
170  return false;
171  end if;
172 end A_GE_B;
173 signal resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
174 signal daq_resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
175 signal inc_ddr_paSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
176 signal bldr2SFP_sel : array3X2 := (others => (others => '0'));
177 signal SFP2bldr_sel : array3X2 := (others => (others => '0'));
178 signal EventBufAddr_we_i : std_logic_vector(2 downto 0) := (others => '0');
179 signal ReadBusy : std_logic_vector(1 downto 0) := (others => '0');
180 signal sysDIV2 : std_logic := '0';
181 signal MonBuf_wa : std_logic_vector(10 downto 0) := (others => '0');
182 signal MonBuf_ra : std_logic_vector(10 downto 0) := (others => '0');
183 signal MonBufUsed : std_logic_vector(9 downto 0) := (others => '0');
184 signal NXT_MonBuf : array3X11 := (others => (others => '0'));
185 signal Written_MonBuf : array4X11 := (others => (others => '0'));
186 signal Written_MonBufMatch : std_logic_vector(2 downto 0) := (others => '0');
187 signal AddrOffset : array3X10 := (others => (others => '0'));
188 signal header : std_logic_vector(1 downto 0) := (others => '0');
189 signal header_q : std_logic_vector(1 downto 0) := (others => '0');
190 signal sfp_rxn : std_logic_vector(1 downto 0) := (others => '0');
191 signal sfp_rxp : std_logic_vector(1 downto 0) := (others => '0');
192 signal sfp_txn : std_logic_vector(1 downto 0) := (others => '0');
193 signal sfp_txp : std_logic_vector(1 downto 0) := (others => '0');
194 signal sync_loss : std_logic_vector(1 downto 0) := (others => '0');
195 signal LinkFull_n : std_logic_vector(1 downto 0) := (others => '0');
196 signal LinkFull : std_logic_vector(2 downto 0) := (others => '0');
197 signal LinkCtrl : std_logic_vector(1 downto 0) := (others => '0');
198 signal LinkWe : std_logic_vector(1 downto 0) := (others => '0');
199 signal LinkDown : std_logic_vector(1 downto 0) := (others => '0');
200 signal DaqLSC_status : array2x64 := (others => (others => '0'));
201 signal LinkData : array2x65 := (others => (others => '0'));
202 signal sync_loss_cntr : array2x32 := (others => (others => '0'));
203 signal SFP_we : std_logic_vector(1 downto 0) := (others => '0');
204 signal EoB : std_logic_vector(1 downto 0) := (others => '0');
205 signal SFP_evt_cntr : array2X32 := (others => (others => '0'));
206 signal SFP_blk_cntr : array2X32 := (others => (others => '0'));
207 signal SFP_word_cntr : array2X32 := (others => (others => '0'));
208 signal event_cntr : array2x32 := (others => (others => '0'));
209 signal word_cntr : array2x32 := (others => (others => '0'));
210 signal EventBufAddr_we_cntr : array2x32 := (others => (others => '0'));
211 signal src_ID : array2x16 := (others => (others => '0'));
212 signal txusrclk : std_logic := '0';
213 signal LinkDatap : array2x64 := (others => (others => '0'));
214 signal sfp_pd : array2x2 := (others => (others => '0'));
215 signal chk_MonBuf_avl : std_logic := '0';
216 signal FirstBlkAddrDo : array2x3x12 := (others => (others => (others => '0')));
217 signal FirstBlkAddr_ra : array2x3x5 := (others => (others => (others => '0')));
218 signal FirstBlkAddr_re : array2X3 := (others => (others => '0'));
219 signal WrtMonEvtDone_l : std_logic_vector(2 downto 0) := (others => '0');
220 signal MonEvtQueued : std_logic_vector(2 downto 0) := (others => '0');
221 signal FirstBlkAddrDoValid : array2X3 := (others => (others => '0'));
222 signal FirstBlkAddr_wa : std_logic_vector(4 downto 0) := (others => '0');
223 signal FirstBlkAddrDi : std_logic_vector(11 downto 0) := (others => '0');
224 signal FirstBlkAddr_we : std_logic := '0';
225 signal MonBuf_full : std_logic := '0';
226 signal mon_evt_cnt_i : std_logic_vector(10 downto 0) := (others => '0');
227 signal status_addr : std_logic_vector(15 downto 0) := (others => '0');
228 signal cmsCRC_initp : std_logic_vector(2 downto 0) := (others => '0');
229 signal cmsCRC_init : std_logic_vector(2 downto 0) := (others => '0');
230 signal cmsCRC_err : std_logic_vector(2 downto 0) := (others => '0');
231 signal cmsCRC_errCntr : array3X32 := (others => (others => '0'));
232 signal TotalEvtLengthCntr24q : std_logic_vector(2 downto 0) := (others => '0');
233 signal EvtLength_errCntr : array3X32 := (others => (others => '0'));
234 signal AMClength_errCntr : array3X32 := (others => (others => '0'));
235 signal AMCvalid_errCntr : array3X32 := (others => (others => '0'));
236 signal AMCcrc_errCntr : array3X32 := (others => (others => '0'));
237 signal TotalEvtLengthCntr : array3X56 := (others => (others => '0'));
238 signal StopOverWrite : std_logic := '0';
239 signal inc_err : array3x5 := (others => (others => '0'));
240 signal en_stop : std_logic_vector(4 downto 0) := (others => '1');
241 signal stop : std_logic := '0';
242 component chipscope1 is
243  generic (N : integer := 5);
244  Port ( clk : in STD_LOGIC;
245  Din : in STD_LOGIC_VECTOR (303 downto 0));
246 end component;
247 signal cs : std_logic_vector(303 downto 0) := (others => '0');
248 begin
249 MonBufOvfl <= '0';
250 EventBufAddr_we <= EventBufAddr_we_i;
251 mon_evt_cnt(31 downto 11) <= (others => '0');
252 mon_evt_cnt(10 downto 0) <= mon_evt_cnt_i;
253 ipb_ack <= '0';
254 sfp_pd(0) <= "00" when Dis_pd = '1' or SFP_ABS(0) = '0' else "11";
255 sfp_pd(1) <= "00" when Dis_pd = '1' or SFP_ABS(1) = '0' else "11";
256 EventBufAddr_we(2) <= '0';
257 EventBufAddr(2) <= (others => '0');
258 evt_buf_full(2) <= '1';
259 EventData_re(2) <= '0';
260 SFP_down(2) <= '0';
261 SFP_down(1) <= not LinkDown(1) and not enSFP(3) and enSFP(1);
262 SFP_down(0) <= not LinkDown(0) and not enSFP(3) and enSFP(0);
263 LinkFull(2) <= '0';
264 LinkFull(1) <= not LinkFull_n(1) and not enSFP(3) and enSFP(1);
265 LinkFull(0) <= not LinkFull_n(0) and not enSFP(3) and enSFP(0);
266 i_DaqLSCXG: DaqLSCXG PORT MAP(
267  sys_reset => daq_resetSyncRegs (2),
268  sys_clk => sysclk,
269  sfp_pd => sfp_pd,
270  DRP_clk => DRPclk,
271  LinkWe => LinkWe,
272  LinkCtrl => LinkCtrl,
273  LinkData => LinkDatap,
274  srcID => src_ID,
275  LinkDown => LinkDown,
276  LinkFull => LinkFull_n,
277  sync_loss => sync_loss,
278  status_ce => "00",
279  status_addr => status_addr ,
280  status_port => DaqLSC_status ,
281  txusrclk_o => txusrclk,
282  rxusrclk_o => open,
283  gtx_reset => gtx_reset,
284  gtx_refclk_p => SFP_REFCLK_P ,
285  gtx_refclk_n => SFP_REFCLK_N ,
286  sfp_rxn => sfp_rxn,
287  sfp_rxp => sfp_rxp,
288  sfp_txn => sfp_txn,
289  sfp_txp => sfp_txp
290  );
291 status_addr <= x"000" & ipb_addr(3 downto 0);
292 LinkDatap(0) <= LinkData(0)(63 downto 0);
293 LinkDatap(1) <= LinkData(1)(63 downto 0);
294 src_ID(0) <= LSC_ID(15 downto 2) & "00";
295 src_ID(1) <= LSC_ID(15 downto 2) & "01";
296 sfp_rxn(0) <= SFP0_RXN;
297 sfp_rxp(0) <= SFP0_RXP;
298 SFP0_TXN <= sfp_txn(0);
299 SFP0_TXP <= sfp_txp(0);
300 sfp_rxn(1) <= SFP1_RXN;
301 sfp_rxp(1) <= SFP1_RXP;
302 SFP1_TXN <= sfp_txn(1);
303 SFP1_TXP <= sfp_txp(1);
304 process(sysclk,daq_reset)
305 begin
306  if(daq_reset = '1')then
307  daq_resetSyncRegs <= (others => '1');
308  elsif(sysclk'event and sysclk = '1')then
309  daq_resetSyncRegs <= daq_resetSyncRegs(1 downto 0) & '0';
310  end if;
311 end process;
312 process(sysclk,reset)
313 begin
314  if(reset = '1')then
315  resetSyncRegs <= (others => '1');
316  elsif(sysclk'event and sysclk = '1')then
317  resetSyncRegs <= resetSyncRegs(1 downto 0) & '0';
318  end if;
319 end process;
320 g_FirstBlkAddr: for j in 0 to 1 generate
321  g1_FirstBlkAddr: for i in 0 to 5 generate
322  i_FirstBlkAddr : RAM32M
323  port map (
324  DOA => FirstBlkAddrDo(j)(0)(i*2+1 downto i*2), -- Read port A 2-bit output
325  DOB => FirstBlkAddrDo(j)(1)(i*2+1 downto i*2), -- Read port B 2-bit output
326  DOC => FirstBlkAddrDo(j)(2)(i*2+1 downto i*2), -- Read port C 2-bit output
327  DOD => open, -- Read/Write port D 2-bit output
328  ADDRA => FirstBlkAddr_ra(j)(0), -- Read port A 5-bit address input
329  ADDRB => FirstBlkAddr_ra(j)(1), -- Read port B 5-bit address input
330  ADDRC => FirstBlkAddr_ra(j)(2), -- Read port C 5-bit address input
331  ADDRD => FirstBlkAddr_wa, -- Read/Write port D 5-bit address input
332  DIA => FirstBlkAddrDi(i*2+1 downto i*2), -- RAM 2-bit data write input addressed by ADDRD,
333  -- read addressed by ADDRA
334  DIB => FirstBlkAddrDi(i*2+1 downto i*2), -- RAM 2-bit data write input addressed by ADDRD,
335  -- read addressed by ADDRB
336  DIC => FirstBlkAddrDi(i*2+1 downto i*2), -- RAM 2-bit data write input addressed by ADDRD,
337  -- read addressed by ADDRC
338  DID => "00", -- RAM 2-bit data write input addressed by ADDRD,
339  -- read addressed by ADDRD
340  WCLK => sysclk, -- Write clock input
341  WE => FirstBlkAddr_we -- Write enable input
342  );
343  end generate;
344 end generate;
345 FirstBlkAddrDi <= '0' & MonBuf_wa;
346 process(sysclk)
347 begin
348  if(sysclk'event and sysclk = '1')then
349  if(resetSyncRegs(2) = '1')then
350  chk_MonBuf_avl <= '1';
351  elsif(buf_rqst(0) = '1')then
352  chk_MonBuf_avl <= buf_rqst(3);
353  end if;
354  if(resetSyncRegs(2) = '1')then
355  MonBuf_avl <= '1';
356  elsif(WaitMonBuf = '1' or MonBufOverWrite = '1')then
357  if((MonBuf_wa(10) /= MonBuf_ra(10) and MonBuf_wa(9 downto 0) = MonBuf_ra(9 downto 0)))then
358  MonBuf_avl <= '0';
359  else
360  MonBuf_avl <= '1';
361  end if;
362  elsif(chk_MonBuf_avl = '1')then
363  if(MonBufUsed(9 downto 8) = "11")then
364  MonBuf_avl <= '0';
365  else
366  MonBuf_avl <= '1';
367  end if;
368  end if;
369  if(MonBufOverWrite = '1')then
370  mon_evt_cnt_i <= '0' & Written_MonBuf(3)(9 downto 0);
371  else
372  mon_evt_cnt_i <= Written_MonBuf(3) - MonBuf_ra;
373  end if;
374  if(MonBufOverWrite = '0')then
375  MonBuf_empty <= not or_reduce(mon_evt_cnt_i);
376  elsif(Written_MonBuf(3) /= MonBuf_ra or MonBuf_full = '1')then
377  MonBuf_empty <= '0';
378  else
379  MonBuf_empty <= '1';
380  end if;
381  if(resetSyncRegs(2) = '1')then
382  ReadBusy <= (others => '0');
383  EventData_re <= (others => '0');
384  EventBufAddr_we_i <= (others => '0');
385  MonBuf_wa <= (others => '0');
386  MonBuf_ra <= (others => '0');
387  MonBufUsed <= (others => '0');
388  Written_MonBufMatch <= (others => '1');
389  Written_MonBuf <= (others => (others => '0'));
390  NXT_MonBuf <= (others => (others => '0'));
391  inc_ddr_paSyncRegs <= (others => '0');
392  FirstBlkAddr_we <= '0';
393  FirstBlkAddr_re <= (others => (others => '0'));
394  FirstBlkAddrDoValid <= (others => (others => '0'));
395  WrtMonEvtDone_l <= (others => '0');
396  MonEvtQueued <= (others => '0');
397  FirstBlkAddr_wa <= (others => '0');
398  FirstBlkAddr_ra <= (others => (others => (others => '0')));
399  MonBuf_full <= '0';
400  else
401  for i in 0 to 1 loop
402  if(EVENTdata_in(i)(64) = '1' and EVENTdata_we(i) = '1')then
403  ReadBusy(i) <= '0';
404  elsif(evt_data_rdy(i) = '1' and wport_rdy(i) = '1')then
405  ReadBusy(i) <= '1';
406  end if;
407  EventData_re(i) <= evt_data_rdy(i) and wport_rdy(i) and not ReadBusy(i);
408  if(EventData_in(i)(66) = '0' and evt_data_rdy(i) = '1' and wport_rdy(i) = '1' and ReadBusy(i) = '0')then
409  EventBufAddr_we_i(i) <= '1';
410  else
411  EventBufAddr_we_i(i) <= '0';
412  end if;
413  end loop;
414  for j in 0 to 1 loop
415  for i in 0 to 1 loop
416  if(FirstBlkAddr_re(j)(i) = '1')then
417  FirstBlkAddr_ra(j)(i) <= FirstBlkAddr_ra(j)(i) + 1;
418  end if;
419  if(FirstBlkAddr_ra(j)(i) = FirstBlkAddr_wa)then
420  FirstBlkAddrDoValid(j)(i) <= '0';
421  else
422  FirstBlkAddrDoValid(j)(i) <= '1';
423  end if;
424  end loop;
425  end loop;
426  if(FirstBlkAddr_we = '1')then
427  FirstBlkAddr_wa <= FirstBlkAddr_wa + 1;
428  end if;
429  for i in 0 to 1 loop
430  if(WrtMonEvtDone(i) = '1')then
431  WrtMonEvtDone_l(i) <= '1';
432  elsif(FirstBlkAddrDoValid(0)(i) = '1')then
433  WrtMonEvtDone_l(i) <= '0';
434  end if;
435  FirstBlkAddr_re(0)(i) <= FirstBlkAddrDoValid(0)(i) and WrtMonEvtDone_l(i);
436  if(EventData_we(i) = '1' and EventData_in(i)(66 downto 65) = "01")then
437  MonEvtQueued(i) <= '1';
438  elsif(FirstBlkAddrDoValid(1)(i) = '1')then
439  MonEvtQueued(i) <= '0';
440  end if;
441  FirstBlkAddr_re(1)(i) <= FirstBlkAddrDoValid(1)(i) and MonEvtQueued(i);
442  end loop;
443  FirstBlkAddr_we <= buf_rqst(3) and buf_rqst(0);
444  if(MonBufOverWrite = '1' and Written_MonBuf(3)(10) = '1')then
445  MonBuf_full <= '1';
446  end if;
447  if(buf_rqst(0) = '1')then
448  MonBuf_wa <= MonBuf_wa + 1;
449  end if;
450  MonBufUsed <= MonBuf_wa(9 downto 0) - MonBuf_ra(9 downto 0);
451  if(inc_ddr_paSyncRegs(3 downto 2) = "10" or (MonBufOverWrite = '1' and StopOverWrite = '0' and and_reduce(MonBufUsed) = '1' and buf_rqst(0) = '1'))then
452  MonBuf_ra <= MonBuf_ra + 1;
453  end if;
454  if(Written_MonBuf(0) = Written_MonBuf(3) and WrtMonEvtDone_l(0) = '0')then
455  Written_MonBufMatch(0) <= '1';
456  else
457  Written_MonBufMatch(0) <= '0';
458  end if;
459  if(EnSFP(1 downto 0) = "11" and Written_MonBuf(1) = Written_MonBuf(3) and WrtMonEvtDone_l(1) = '0')then
460  Written_MonBufMatch(1) <= '1';
461  else
462  Written_MonBufMatch(1) <= '0';
463  end if;
464  Written_MonBufMatch(2) <= '0';
465  if(Written_MonBufMatch = "000" and sysDIV2 = '0')then
466  Written_MonBuf(3) <= Written_MonBuf(3) + 1;
467  end if;
468  for i in 0 to 1 loop
469  if(FirstBlkAddr_re(0)(i) = '1')then
470  Written_MonBuf(i) <= FirstBlkAddrDo(0)(i)(10 downto 0);
471  elsif(WrtMonBlkDone(i) = '1')then
472  Written_MonBuf(i) <= Written_MonBuf(i) + 1;
473  end if;
474  if(FirstBlkAddr_re(1)(i) = '1')then
475  NXT_MonBuf(i) <= FirstBlkAddrDo(1)(i)(10 downto 0);
476  elsif(EventBufAddr_we_i(i) = '1' and EventData_in(i)(66) = '0')then
477  NXT_MonBuf(i) <= NXT_MonBuf(i) + 1;
478  end if;
479  end loop;
480  inc_ddr_paSyncRegs <= inc_ddr_paSyncRegs(2 downto 0) & inc_ddr_pa;
481  end if;
482  case EnSFP(1 downto 0) is
483  when "11" => AddrOffset(0)(9 downto 6) <= x"8";
484  when others => AddrOffset(0)(9 downto 6) <= x"0";
485  end case;
486  AddrOffset(1)(9 downto 6) <= x"0";
487  for i in 0 to 1 loop
488  EventBufAddr(i) <= NXT_MonBuf(i)(9 downto 0) & AddrOffset(i)(9 downto 6);
489  end loop;
490  end if;
491 end process;
492 process(sysclk)
493 begin
494  if(sysclk'event and sysclk = '1')then
495  sysDIV2 <= not sysDIV2;
496  for i in 0 to 1 loop
497  if(resetSyncRegs(2) = '1')then
498  header(i) <= '1';
499  header_q(i) <= '0';
500  elsif(EventData_we(i) = '1')then
501  header(i) <= EventData_in(i)(65) or (header(i) and not header_q(i));
502  header_q(i) <= header(i);
503  end if;
504  end loop;
505  if(EnSFP(1) = '0')then
506  SFP_we(0) <= EventData_we(0);
507  EoB(0) <= EventData_in(0)(64);
508  else
509  SFP_we(0) <= EventData_we(1) and EnSFP(0);
510  EoB(0) <= EventData_in(1)(64);
511  end if;
512  if(EnSFP(1 downto 0) = "10")then
513  SFP_we(1) <= EventData_we(1);
514  EoB(1) <= EventData_in(1)(64);
515  else
516  SFP_we(1) <= EventData_we(0) and EnSFP(1);
517  EoB(1) <= EventData_in(0)(64);
518  end if;
519  if(EnSFP(1 downto 0) = "01")then
520  LinkData(0) <= EventData_in(0)(65) & EventData_in(0)(63 downto 0);
521  LinkCtrl(0) <= not(header(0) or EventData_in(0)(65));
522  LinkWe(0) <= EventData_we(0) and not EnSFP(3);
523  else
524  LinkData(0) <= EventData_in(1)(65) & EventData_in(1)(63 downto 0);
525  LinkCtrl(0) <= not(header(1) or EventData_in(1)(65));
526  LinkWe(0) <= EventData_we(1) and EnSFP(0) and not EnSFP(3);
527  end if;
528  LinkData(1) <= EventData_in(0)(65) & EventData_in(0)(63 downto 0);
529  LinkCtrl(1) <= not(header(0) or EventData_in(0)(65));
530  LinkWe(1) <= EventData_we(0) and EnSFP(1) and not EnSFP(3);
531  if(EnSFP(0) = '1')then
532  evt_buf_full(0) <= (not LinkFull_n(0) and not EnSFP(3)) or wport_FIFO_full(0);
533  else
534  evt_buf_full(0) <= (not LinkFull_n(1) and not EnSFP(3)) or wport_FIFO_full(0);
535  end if;
536  evt_buf_full(1) <= (not LinkFull_n(0) and not EnSFP(3)) or wport_FIFO_full(1);
537  end if;
538 end process;
539 process(txusrclk,rstCntr)
540 begin
541  if(rstCntr = '1')then
542  sync_loss_cntr <= (others => (others => '0'));
543  elsif(txusrclk'event and txusrclk = '1')then
544  for i in 0 to 1 loop
545  if(sync_loss(i) = '1')then
546  sync_loss_cntr(i) <= sync_loss_cntr(i) + 1;
547  end if;
548  end loop;
549  end if;
550 end process;
551 process(sysclk,rstCntr)
552 begin
553  if(rstCntr = '1')then
554  cmsCRC_errCntr <= (others => (others => '0'));
555  EvtLength_errCntr <= (others => (others => '0'));
556  AMCLength_errCntr <= (others => (others => '0'));
557  AMCvalid_errCntr <= (others => (others => '0'));
558  AMCcrc_errCntr <= (others => (others => '0'));
559  StopOverWrite <= '0';
560  elsif(sysclk'event and sysclk = '1')then
561  for i in 0 to 1 loop
562  if(inc_err(i)(0) = '1')then
563  cmsCRC_errCntr(i) <= cmsCRC_errCntr(i) + 1;
564  end if;
565  if(inc_err(i)(1) = '1')then
566  EvtLength_errCntr(i) <= EvtLength_errCntr(i) + 1;
567  end if;
568  if(inc_err(i)(2) = '1')then
569  AMClength_errCntr(i) <= AMClength_errCntr(i) + 1;
570  end if;
571  if(inc_err(i)(3) = '1')then
572  AMCvalid_errCntr(i) <= AMCvalid_errCntr(i) + 1;
573  end if;
574  if(inc_err(i)(4) = '1')then
575  AMCcrc_errCntr(i) <= AMCcrc_errCntr(i) + 1;
576  end if;
577  end loop;
578  if(stop = '1')then
579  StopOverWrite <= '1';
580  end if;
581  end if;
582 end process;
583 i_check_event: check_event PORT MAP(
584  clk => sysclk ,
585  reset => resetSyncRegs(2),
586  en_stop => en_stop,
587  cmsCRC_err => cmsCRC_err,
588  EventData_in => EventData_in ,
589  EventData_we => EventData_we ,
590  inc_err => inc_err,
591  stop => stop
592  );
593 process(ipb_clk)
594 begin
595  if(ipb_clk'event and ipb_clk = '1')then
596  if(ipb_addr(15 downto 7) = LSC_addr(15 downto 7) and ipb_addr(6 downto 0) = "1110001" and ipb_write = '1' and ipb_strobe = '1')then
597  en_stop <= ipb_wdata(4 downto 0);
598  end if;
599  end if;
600 end process;
601 process(ipb_addr)
602 begin
603  if(ipb_addr(15 downto 7) = LSC_addr(15 downto 7))then
604  case ipb_addr(6 downto 4) is
605  when "000" =>
606  ipb_rdata <= DaqLSC_status(0)(31 downto 0);
607  when "001" =>
608  ipb_rdata <= DaqLSC_status(1)(31 downto 0);
609  when "011" =>
610  case ipb_addr(3 downto 0) is
611  when x"0" => ipb_rdata <= sync_loss_cntr(0);
612  when x"1" => ipb_rdata <= sync_loss_cntr(1);
613  when x"3" => ipb_rdata <= cmsCRC_errCntr(0);
614  when x"4" => ipb_rdata <= cmsCRC_errCntr(1);
615  when x"6" => ipb_rdata <= EvtLength_errCntr(0);
616  when x"7" => ipb_rdata <= EvtLength_errCntr(1);
617  when x"a" => ipb_rdata <= TotalEvtLengthCntr(0)(31 downto 0);
618  when x"b" => ipb_rdata <= x"00" & TotalEvtLengthCntr(0)(55 downto 32);
619  when x"c" => ipb_rdata <= TotalEvtLengthCntr(1)(31 downto 0);
620  when x"d" => ipb_rdata <= x"00" & TotalEvtLengthCntr(1)(55 downto 32);
621  when others => ipb_rdata <= (others => '0');
622  end case;
623  when "100" =>
624  case ipb_addr(3 downto 0) is
625  when x"0" => ipb_rdata <= SFP_evt_cntr(0);
626  when x"1" => ipb_rdata <= SFP_evt_cntr(1);
627  when x"4" => ipb_rdata <= SFP_word_cntr(0);
628  when x"5" => ipb_rdata <= SFP_word_cntr(1);
629  when x"8" => ipb_rdata <= SFP_blk_cntr(0);
630  when x"9" => ipb_rdata <= SFP_blk_cntr(1);
631  when others => ipb_rdata <= (others => '0');
632  end case;
633  when "101" =>
634  case ipb_addr(3 downto 0) is
635  when x"1" => ipb_rdata <= x"00000" & '0' & Written_MonBuf(3);
636  when x"2" => ipb_rdata <= "00000" & NXT_MonBuf(1) & "00000" & NXT_MonBuf(0);
637  when x"3" => ipb_rdata <= "00000" & MonBuf_wa & x"0000";
638  when x"4" => ipb_rdata <= x"00" & "00" & header & '0' & LinkFull & "00" & ReadBusy & '0' & evt_data_rdy & '0' & wport_FIFO_full & '0' & wport_rdy;
639  when x"5" => ipb_rdata <= event_cntr(0);
640  when x"6" => ipb_rdata <= event_cntr(1);
641  when x"8" => ipb_rdata <= word_cntr(0);
642  when x"9" => ipb_rdata <= word_cntr(1);
643  when x"b" => ipb_rdata <= EventBufAddr_we_cntr(0);
644  when x"c" => ipb_rdata <= EventBufAddr_we_cntr(1);
645  when others => ipb_rdata <= (others => '0');
646  end case;
647  when "110" =>
648  case ipb_addr(3 downto 0) is
649  when x"0" => ipb_rdata <= AMClength_errCntr(0);
650  when x"1" => ipb_rdata <= AMClength_errCntr(1);
651  when x"4" => ipb_rdata <= AMCvalid_errCntr(0);
652  when x"5" => ipb_rdata <= AMCvalid_errCntr(1);
653  when x"8" => ipb_rdata <= AMCcrc_errCntr(0);
654  when x"9" => ipb_rdata <= AMCcrc_errCntr(1);
655  when others => ipb_rdata <= (others => '0');
656  end case;
657  when others =>
658  case ipb_addr(3 downto 0) is
659  when x"0" => ipb_rdata <= x"000000" & "000" & en_stop;
660  when others => ipb_rdata <= (others => '0');
661  end case;
662  end case;
663  else
664  ipb_rdata <= (others => '0');
665  end if;
666 end process;
667 g_cmsCRC : for i in 0 to 1 generate
668  i_cmsCRC: cmsCRC64 PORT MAP(
669  clk => sysclk ,
670  reset => '0',
671  crc_init => cmsCRC_init(i),
672  trailer => LinkData(i)(64),
673  crc_d => LinkData(i)(63 downto 0),
674  crc_ce => LinkWe(i),
675  crc => open,
676  crc_err => cmsCRC_err(i),
677  dout => open,
678  dout_vld => open
679  );
680 end generate;
681 process(sysclk)
682 begin
683  if(sysclk'event and sysclk = '1')then
684  if(resetSyncRegs(2) = '1')then
685  cmsCRC_initp <= "000";
686  cmsCRC_init <= "111";
687  SFP_blk_cntr <= (others => (others => '0'));
688  SFP_evt_cntr <= (others => (others => '0'));
689  SFP_word_cntr <= (others => (others => '0'));
690  event_cntr <= (others => (others => '0'));
691  word_cntr <= (others => (others => '0'));
692  EventBufAddr_we_cntr <= (others => (others => '0'));
693  TotalEvtLengthCntr <= (others => (others => '0'));
694  TotalEvtLengthCntr24q <= "000";
695  else
696  for i in 0 to 1 loop
697  cmsCRC_initp(i) <= LinkData(i)(64) and LinkWe(i);
698  if(LinkWe(i) = '1')then
699  word_cntr(i) <= word_cntr(i) + 1;
700  end if;
701  if(LinkWe(i) = '1' and LinkData(i)(64) = '1')then
702  event_cntr(i) <= event_cntr(i) + 1;
703  end if;
704  if(SFP_we(i) = '1' and EoB(i) = '1')then
705  SFP_blk_cntr(i) <= SFP_blk_cntr(i) + 1;
706  end if;
707  if(SFP_we(i) = '1' and LinkData(i)(64) = '1')then
708  SFP_evt_cntr(i) <= SFP_evt_cntr(i) + 1;
709  end if;
710  if(SFP_we(i) = '1')then
711  SFP_word_cntr(i) <= SFP_word_cntr(i) + 1;
712  end if;
713  if(EventBufAddr_we_i(i) = '1')then
714  EventBufAddr_we_cntr(i) <= EventBufAddr_we_cntr(i) + 1;
715  end if;
716  if(EventData_we(i) = '1')then
717  if(EventData_in(i)(65) = '1')then
718  TotalEvtLengthCntr(i)(24 downto 0) <= TotalEvtLengthCntr(i)(24 downto 0) + ('0' & EventData_in(i)(55 downto 32));
719  end if;
720  end if;
721  TotalEvtLengthCntr24q(i) <= TotalEvtLengthCntr(i)(24);
722  if(TotalEvtLengthCntr24q(i) = '1' and TotalEvtLengthCntr(i)(24) = '0')then
723  TotalEvtLengthCntr(i)(55 downto 25) <= TotalEvtLengthCntr(i)(55 downto 25) + 1;
724  end if;
725  end loop;
726  cmsCRC_init <= cmsCRC_initp;
727  end if;
728  end if;
729 end process;
730 end Behavioral;
731 
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