AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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AMC13_T1_fakeAMC.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 14:49:29 05/12/2010
6 -- Design Name:
7 -- Module Name: DTC_T2 - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 use work.ipbus.ALL;
26 use work.amc13_pack.all;
27 
28 -- Uncomment the following library declaration if using
29 -- arithmetic functions with Signed or Unsigned values
30 -- use IEEE.NUMERIC_STD.ALL;
31 
32 -- Uncomment the following library declaration if instantiating
33 -- any Xilinx primitives in this code.
34 library UNISIM;
35 use UNISIM.VComponents.all;
36 Library UNIMACRO;
37 use UNIMACRO.vcomponents.all;
38 
39 entity AMC13_T1_fakeAMC is
40  Port (
41  VAUXP : in STD_LOGIC_VECTOR(12 downto 0);
42  VAUXN : in STD_LOGIC_VECTOR(12 downto 0);
43 -- I2C interface
44  CLK_SCL : out STD_LOGIC;
45  CLK_SDA : inout STD_LOGIC;
46  SFP_SCL : out STD_LOGIC_VECTOR(3 downto 0);
47  SFP_SDA : inout STD_LOGIC_VECTOR(3 downto 0);
48 -- SFP slow control
49  SFP_LOS : in STD_LOGIC_VECTOR(2 downto 0);
50  SFP_ABS : in STD_LOGIC_VECTOR(3 downto 0);
51  TxFault : in STD_LOGIC_VECTOR(3 downto 0);
52  TxDisable : out STD_LOGIC_VECTOR(3 downto 0);
53 -- RATE : out STD_LOGIC_VECTOR(3 downto 0);
54 -- CDR signals
55  DIV4 : out STD_LOGIC;
56  DIV_nRST : out STD_LOGIC;
57  CDRclk_p : in STD_LOGIC;
58  CDRclk_n : in STD_LOGIC;
59  CDRdata_p : in STD_LOGIC;
60  CDRdata_n : in STD_LOGIC;
61  TTCdata_p : out STD_LOGIC;
62  TTCdata_n : out STD_LOGIC;
63  TTCclk_p : in STD_LOGIC;
64  TTCclk_n : in STD_LOGIC;
65  TTC_LOS : in STD_LOGIC;
66  TTC_LOL : in STD_LOGIC;
67  TTS_out_p : out STD_LOGIC;
68  TTS_out_n : out STD_LOGIC;
69 -- SPI interface
70  SPI_SCK : in STD_LOGIC;
71  SPI_CS_b : in STD_LOGIC;
72  SPI_MOSI : in STD_LOGIC;
73  SPI_MISO : out STD_LOGIC;
74  AMC_REFCLK_N : in STD_LOGIC;
75  AMC_REFCLK_P : in STD_LOGIC;
76  AMC_RXN : in STD_LOGIC;
77  AMC_RXP : in STD_LOGIC;
78  AMC_TXN : out STD_LOGIC;
79  AMC_TXP : out STD_LOGIC;
80 -- signal to/from DTC_T2
81  S6LINK_RXN : in STD_LOGIC;
82  S6LINK_RXP : in STD_LOGIC;
83  S6LINK_TXN : out STD_LOGIC;
84  S6LINK_TXP : out STD_LOGIC;
85  S2V_p : in STD_LOGIC;
86  S2V_n : in STD_LOGIC;
87  V2S_p : out STD_LOGIC;
88  V2S_n : out STD_LOGIC;
89  GbE_REFCLK_N : in STD_LOGIC;
90  GbE_REFCLK_P : in STD_LOGIC);
91 end AMC13_T1_fakeAMC;
92 
93 architecture Behavioral of AMC13_T1_fakeAMC is
94 COMPONENT TTS_if
95  PORT(
96  sysclk : IN std_logic;
97  TTS_clk : IN std_logic;
98  reset : IN std_logic;
99  local_TTC : in STD_LOGIC;
100  TTS : IN std_logic_vector(3 downto 0);
101  TTS_out_p : OUT std_logic;
102  TTS_out_n : OUT std_logic
103  );
104 END COMPONENT;
105 COMPONENT ttc_if
106  PORT(
107  clk : IN std_logic;
108  refclk : IN std_logic;
109  reset : IN std_logic;
110  run : IN std_logic;
111  sys_lock : IN std_logic;
112  local_TTC : IN std_logic;
113  local_TTCcmd : IN std_logic;
114  CDRclk_p : IN std_logic;
115  CDRclk_n : IN std_logic;
116  CDRdata_p : IN std_logic;
117  CDRdata_n : IN std_logic;
118  TTC_LOS : IN std_logic;
119  TTC_LOL : IN std_logic;
120  BCN_off : IN std_logic_vector(12 downto 0);
121  OC_off : IN std_logic_vector(3 downto 0);
122  en_cal_win : IN std_logic;
123  cal_win_high : IN std_logic_vector(11 downto 0);
124  cal_win_low : IN std_logic_vector(11 downto 0);
125  en_localL1A : IN std_logic;
126  LocalL1A_cfg : IN std_logic_vector(31 downto 0);
127  localL1A_s : IN std_logic;
128  localL1A_r : IN std_logic;
129  T3_trigger : in std_logic;
130  EvnRSt_l : in std_logic;
131  OcnRSt_l : in std_logic;
132  ovfl_warning : IN std_logic;
133  ipb_clk : IN std_logic;
134  ipb_write : in STD_LOGIC;
135  ipb_strobe : in STD_LOGIC;
136  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
137  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
138  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
139  en_brcst : IN std_logic;
140  state : IN std_logic_vector(3 downto 0);
141  evn_fifo_full : IN std_logic;
142  BC0 : OUT std_logic;
143  TTC_strobe : OUT std_logic;
144  TTS_clk : OUT std_logic;
145  DIV4 : OUT std_logic;
146  DIV_nRST : OUT std_logic;
147  CDRclk_out : OUT std_logic;
148  TTCdata_p : OUT std_logic;
149  TTCdata_n : OUT std_logic;
150  CalType : OUT std_logic_vector(3 downto 0);
151  TTC_Brcst : OUT std_logic_vector(3 downto 0);
152  localL1A_periodic : OUT std_logic;
153  ttc_start : OUT std_logic;
154  ttc_stop : OUT std_logic;
155  ttc_soft_reset : OUT std_logic;
156  ttc_ready : OUT std_logic;
157  ttc_serr : OUT std_logic;
158  ttc_derr : OUT std_logic;
159  ttc_bcnt_err : OUT std_logic;
160  rate_OFW : OUT std_logic;
161  sync_lost : OUT std_logic;
162  inc_oc : OUT std_logic;
163  inc_l1ac : OUT std_logic;
164  inc_bcnterr : OUT std_logic;
165  inc_serr : OUT std_logic;
166  inc_derr : OUT std_logic;
167  ttc_evcnt_reset : OUT std_logic;
168  event_number_avl : OUT std_logic;
169  event_number : OUT std_logic_vector(59 downto 0)
170  );
171 END COMPONENT;
172 COMPONENT I2C
173  PORT(
174  clk : IN std_logic;
175  ipb_clk : IN std_logic;
176  reset : IN std_logic;
177 -- ns2500 : IN std_logic;
178  addr : IN std_logic_vector(31 downto 0);
179  SFP_ABS : IN std_logic_vector(3 downto 0);
180  SFP_LOS : IN std_logic_vector(2 downto 0);
181  CLK_SDA : INOUT std_logic;
182  SFP_SDA : INOUT std_logic_vector(3 downto 0);
183  rdata : OUT std_logic_vector(31 downto 0);
184  CLK_rdy : OUT std_logic;
185  CLK_SCL : OUT std_logic;
186  SFP_SCL : OUT std_logic_vector(3 downto 0)
187  );
188 END COMPONENT;
189 COMPONENT SPI_if
190  PORT(
191  SCK : IN std_logic;
192  CSn : IN std_logic;
193  MOSI : IN std_logic;
194  SN : IN std_logic_vector(7 downto 0);
195  OT : IN std_logic;
196  IsT1 : IN std_logic;
197  SPI_rdata : IN std_logic_vector(7 downto 0);
198  MISO : OUT std_logic;
199  SPI_we : OUT std_logic;
200  en_RARP : OUT std_logic;
201  newIPADDR : OUT std_logic;
202  IPADDR : OUT std_logic_vector(31 downto 0);
203  SPI_wdata : OUT std_logic_vector(7 downto 0);
204  SPI_addr : OUT std_logic_vector(7 downto 0)
205  );
206 END COMPONENT;
207 COMPONENT ipbus_if
208  generic(RXPOLARITY : std_logic := '0'; TXPOLARITY : std_logic := '0');
209  port(
210  ipb_clk : IN std_logic;
211  UsRclk : IN std_logic;
212  DRPclk : IN std_logic;
213  got_SN : out std_logic;
214  reset : IN std_logic;
215  en_RARP : IN std_logic;
216  GTX_RESET : IN std_logic;
217  GbE_REFCLK : in std_logic;
218  S6LINK_RXN : in std_logic;
219  S6LINK_RXP : in std_logic;
220  S6LINK_TXN : out std_logic;
221  S6LINK_TXP : out std_logic;
222  wr_amc_en : in std_logic;
223  amc_en : in STD_LOGIC_VECTOR(11 downto 0);
224  IPADDR : in STD_LOGIC_VECTOR(31 downto 0);
225  MACADDR : in STD_LOGIC_VECTOR(47 downto 0);
226  ipb_out : out ipb_wbus;
227  ipb_in : in ipb_rbus;
228  SN : out STD_LOGIC_VECTOR(7 downto 0);
229  debug_in : IN std_logic_vector(31 downto 0);
230  debug_out : OUT std_logic_vector(127 downto 0)
231  );
232 end COMPONENT;
233 COMPONENT sysmon_if
234  PORT(
235  DRPclk : IN std_logic;
236  SN : IN std_logic_vector(7 downto 0);
237  VAUXN_IN : IN std_logic_vector(12 downto 0);
238  VAUXP_IN : IN std_logic_vector(12 downto 0);
239  addr : IN std_logic_vector(15 downto 0);
240  data : OUT std_logic_vector(31 downto 0);
241  device_temp : OUT std_logic_vector(11 downto 0);
242  ALM : OUT std_logic_vector(7 downto 0);
243  OT : OUT std_logic
244  );
245 END COMPONENT;
246 COMPONENT DAQ_LINK
247  Generic (
248 -- REFCLK frequency, select one among 100, 125, 200 and 250
249 -- If your REFCLK frequency is not in the list, please contact wusx@bu.edu
250  F_REFCLK : integer := 250;
251  DRPclk_period : integer := 20; -- unit is ns
252 -- If you do not use the trigger port, set it to false
253 -- USE_TRIGGER_PORT : boolean := false;
254  simulation : boolean := false);
255  PORT(
256  sysclk : IN std_logic;
257  DRPclk : IN std_logic;
258  fake_clk : IN std_logic;
259  EventDataClk : IN std_logic;
260  reset : IN std_logic;
261  USE_TRIGGER_PORT : boolean;
262  test : IN std_logic;
263  ovfl_warning : IN std_logic;
264  ForceError : in STD_LOGIC_VECTOR (3 downto 0);
265  fake_lengthA : IN std_logic_vector(17 downto 0);
266  fake_lengthB : IN std_logic_vector(17 downto 0);
267  fake_seed : IN std_logic_vector(16 downto 0);
268  event_number_avl : in std_logic;
269  event_number : in std_logic_vector(59 downto 0);
270  board_ID : in std_logic_vector(15 downto 0);
271  status : OUT std_logic_vector(31 downto 0);
272  AMC_REFCLK_N : IN std_logic;
273  AMC_REFCLK_P : IN std_logic;
274  AMC_RXN : IN std_logic;
275  AMC_RXP : IN std_logic;
276  TTCclk : IN std_logic;
277  TTSclk : IN std_logic;
278  TTS : IN std_logic_vector(3 downto 0);
279  AMC_TXN : OUT std_logic;
280  AMC_TXP : OUT std_logic
281  );
282 END COMPONENT;
283 constant ipbus_ver_addr : std_logic_vector(15 downto 0) := x"0000";
284 constant ipbus_sfp_addr: std_logic_vector(15 downto 0) := x"0002";
285 constant CDRclk_pol : std_logic := '0';
286 constant CDRdata_pol : std_logic := '1';
287 constant TTCclk_pol : std_logic := '1';
288 constant TTCdata_pol : std_logic := '1';
289 constant Coarse_Delay: std_logic_vector(3 downto 0) := x"0";
290 signal ISuHTR : std_logic := '0';
291 signal USE_TRIGGER_PORT : boolean := false;
292 signal rst_ipbus : std_logic := '0';
293 signal LDC_UsrClk : std_logic := '0';
294 signal wr_AMC_en : std_logic := '0';
295 signal fake_lengthA : std_logic_vector(17 downto 0) := "000000010000000000";
296 signal fake_lengthB : std_logic_vector(17 downto 0) := "000000010000000000";
297 signal fake_seed : std_logic_vector(16 downto 0) := (others =>'1');
298 signal AMC_en : std_logic_vector(11 downto 0) := (others =>'0');
299 signal AMC_Ready : std_logic_vector(11 downto 0) := (others =>'0');
300 signal BC0_lock : std_logic_vector(11 downto 0) := (others =>'0');
301 signal AMC_status : std_logic_vector(31 downto 0) := (others =>'0');
302 signal AMC_DATA : std_logic_vector(31 downto 0) := (others =>'0');
303 signal AMC_ack : std_logic := '0';
304 signal L1Aovfl_warning : std_logic := '0';
305 signal TRIGDATA : std_logic_vector(7 downto 0) := (others =>'0');
306 signal TTS_coded : std_logic_vector(4 downto 0) := (others =>'0');
307 signal AMC_trig : std_logic := '0';
308 signal TTS_pattern : std_logic_vector(3 downto 0) := x"8";
309 signal ForceError : std_logic_vector(3 downto 0) := x"0";
310 signal SPI_SCK_buf : std_logic := '0';
311 signal CLK_rdy : std_logic := '0';
312 signal I2C_data : std_logic_vector(31 downto 0) := (others =>'0');
313 signal TTCclk_in : std_logic := '0';
314 signal TTC_Clk : std_logic := '0';
315 signal TTC_strobe : std_logic := '0';
316 signal BcntErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
317 signal SinErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
318 signal DbErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
319 signal L1_reg : std_logic_vector(15 downto 0) := (others =>'0');
320 signal Bcnt_reg : std_logic_vector(11 downto 0) := (others =>'0');
321 signal OC_reg : std_logic_vector(31 downto 0) := (others =>'0');
322 signal V2S : std_logic := '0';
323 signal S2V : std_logic := '0';
324 signal S2V_cntr : std_logic_vector(5 downto 0) := (others => '0');
325 signal S2V_sr : std_logic_vector(3 downto 0) := (others => '0');
326 signal ddr_rdata : std_logic_vector(7 downto 0) := (others =>'0');
327 signal ipb_clk_dcm : std_logic := '0';
328 signal ipb_clk : std_logic := '0';
329 signal clk125_dcm : std_logic := '0';
330 signal clk125 : std_logic := '0';
331 signal DRPclk_dcm : std_logic := '0';
332 signal DRPclk : std_logic := '0';
333 signal sysclk_dcm : std_logic := '0';
334 signal sysclk : std_logic := '0';
335 signal clkfb : std_logic := '0';
336 signal EventDataClk_dcm : std_logic := '0';
337 signal EventDataClk : std_logic := '0';
338 signal fake_clk_dcm : std_logic := '0';
339 signal fake_clk : std_logic := '0';
340 signal sysclk_inp : std_logic := '0';
341 signal sysclk_in : std_logic := '0';
342 --signal clk125 : std_logic := '0';
343 signal sys_lock : std_logic := '0';
344 signal sys_lock_n : std_logic := '0';
345 signal ldc_reset : std_logic := '0';
346 signal ldc_GTXreset : std_logic := '0';
347 signal lsc_reset : std_logic := '0';
348 signal lsc_GTXreset : std_logic := '0';
349 signal amc_reset : std_logic := '0';
350 signal TTC_reset : std_logic := '0';
351 signal amc_GTXreset : std_logic := '0';
352 signal run : std_logic := '0';
353 signal LSC_LinkDown : std_logic := '0';
354 signal mem_rst : std_logic := '0';
355 signal mem_test : std_logic_vector(1 downto 0) := (others =>'0');
356 signal mem_stat : std_logic_vector(63 downto 0) := (others =>'0');
357 signal mem_ack : std_logic := '0';
358 signal mem_data : std_logic_vector(31 downto 0) := (others =>'0');
359 signal EventData : array3X66 := (others => (others => '0'));
360 signal wport_rdy : std_logic_vector(2 downto 0) := (others =>'0');
361 signal EventBufAddr : array3x14;
362 signal EventBufAddr_we : std_logic_vector(2 downto 0) := (others =>'0');
363 signal evt_buf_full : std_logic_vector(2 downto 0) := (others =>'0');
364 signal wport_FIFO_full : std_logic_vector(2 downto 0) := (others =>'0');
365 signal mon_bufFull : std_logic := '0';
366 signal mon_bufAlmostFull : std_logic := '0';
367 signal mon_buf_empty : std_logic := '0';
368 signal inc_mon_cntr : std_logic := '0';
369 signal mon_evt_wc : std_logic_vector(47 downto 0) := (others =>'0');
370 signal mon_evt_cnt : std_logic_vector(31 downto 0) := (others =>'0');
371 signal mon_ctrl : std_logic_vector(31 downto 0) := (others =>'0');
372 --signal TCPbuf_avl : std_logic := '0';
373 signal mon_buf_avl : std_logic := '0';
374 signal EventBufAddrAvl : std_logic := '0';
375 signal EventBufAddrRe : std_logic := '0';
376 signal mon_wp : std_logic_vector(31 downto 0) := (others =>'0');
377 signal EventBuf_rqst : std_logic_vector(1 downto 0) := (others =>'0');
378 signal rst_cntr : std_logic := '0';
379 signal rst_ddr_pa : std_logic := '0';
380 signal inc_ddr_pa : std_logic := '0';
381 signal board_ID : std_logic_vector(15 downto 0) := (others =>'0');
382 signal ddr_pa : std_logic_vector(9 downto 0) := (others =>'0');
383 signal CDRclk : std_logic := '0';
384 signal TTS_clk : std_logic := '0';
385 signal BC0 : std_logic := '0';
386 signal BC0_dlp : std_logic := '0';
387 signal BC0_dlp2 : std_logic := '0';
388 signal BC0_dl : std_logic := '0';
389 signal BC0_delay : std_logic_vector(4 downto 0) := "11000";
390 signal bcnt : std_logic_vector(3 downto 0) := x"0";
391 signal LocalL1A_cfg : std_logic_vector(31 downto 0) := (others =>'0');
392 signal BCN_off : std_logic_vector(12 downto 0) := (others =>'0');
393 signal OC_off : std_logic_vector(3 downto 0) := (others =>'0');
394 signal en_cal_win : std_logic := '0';
395 signal CalibCtrl : std_logic_vector(31 downto 0) := x"0d800d80";
396 signal cal_win_high : std_logic_vector(11 downto 0) := (others =>'0');
397 signal cal_win_low : std_logic_vector(11 downto 0) := (others =>'0');
398 signal CalType : std_logic_vector(3 downto 0) := (others =>'0');
399 signal TTC_Brcst : std_logic_vector(3 downto 0) := (others =>'0');
400 signal en_brcst : std_logic := '0';
401 signal ttc_start : std_logic := '0';
402 signal ttc_stop : std_logic := '0';
403 signal ttc_soft_reset : std_logic := '0';
404 signal ttc_soft_resetp : std_logic := '0';
405 signal ttc_ready : std_logic := '0';
406 signal ttc_serr : std_logic := '0';
407 signal ttc_derr : std_logic := '0';
408 signal ttc_bcnt_err : std_logic := '0';
409 signal ttc_evcnt_reset : std_logic := '0';
410 signal inc_rate_ofw : std_logic := '0';
411 signal rate_ofw : std_logic := '0';
412 signal rate_ofwp : std_logic := '0';
413 signal rate_ofw_q : std_logic := '0';
414 signal sync_lost : std_logic := '0';
415 signal oc_cntr : std_logic_vector(3 downto 0) := (others =>'0');
416 signal ttc_resync : std_logic := '0';
417 signal resync_done : std_logic := '0';
418 signal dcc_quiet : std_logic := '0';
419 signal inc_oc : std_logic := '0';
420 signal inc_L1ac : std_logic := '0';
421 signal inc_bcnterr : std_logic := '0';
422 signal inc_serr : std_logic := '0';
423 signal inc_derr : std_logic := '0';
424 signal evn_fifo_full : std_logic := '0';
425 signal event_number_avl : std_logic := '0';
426 signal state : std_logic_vector(3 downto 0) := (others =>'0');
427 signal event_number : std_logic_vector(59 downto 0) := (others =>'0');
428 signal TTC_serr_cntr : std_logic_vector(7 downto 0) := (others =>'0');
429 signal TTC_derr_cntr : std_logic_vector(7 downto 0) := (others =>'0');
430 signal TTC_BcntErr_cntr : std_logic_vector(7 downto 0) := (others =>'0');
431 signal L1A_cntr : std_logic_vector(7 downto 0) := (others =>'0');
432 signal run_cntr : std_logic_vector(7 downto 0) := (others =>'0');
433 signal ready_cntr : std_logic_vector(7 downto 0) := (others =>'0');
434 signal busy_cntr : std_logic_vector(7 downto 0) := (others =>'0');
435 signal sync_cntr : std_logic_vector(7 downto 0) := (others =>'0');
436 signal ovfl_cntr : std_logic_vector(7 downto 0) := (others =>'0');
437 signal monitorEvent_cntr : std_logic_vector(7 downto 0) := (others =>'0');
438 signal counter_we : std_logic_vector(3 downto 0) := (others => '0');
439 signal counter_wa : std_logic_vector(9 downto 0) := (others => '0');
440 signal counter_ra_l : std_logic_vector(9 downto 0) := (others => '0');
441 signal counter_ra_h : std_logic_vector(9 downto 0) := (others => '0');
442 signal CounterDi : std_logic_vector(47 downto 0) := (others => '0');
443 signal CounterDoA : std_logic_vector(47 downto 0) := (others => '0');
444 signal CounterDoB : std_logic_vector(63 downto 0) := (others => '0');
445 signal div : std_logic_vector(7 downto 0) := (others =>'0');
446 signal CntrRst : std_logic := '0';
447 signal CntrRstCycle : std_logic := '0';
448 signal CounterDoB_h : std_logic := '0';
449 signal got_SN : std_logic := '0';
450 signal ipb_strobe_q : std_logic := '0';
451 signal SFP_clk : std_logic := '0';
452 signal AMC_clk : std_logic := '0';
453 signal AMC_clk_in : std_logic := '0';
454 signal SV_Cntr : std_logic_vector(7 downto 0) := (others => '0');
455 signal sysclk_div : std_logic_vector(7 downto 0) := (others => '0');
456 signal SFP_UsrClk : std_logic := '0';
457 signal SFP_TxOutClk : std_logic := '0';
458 signal I2C_debug_out : std_logic_vector(15 downto 0) := (others =>'0');
459 signal SFPOSC_rdy : std_logic := '0';
460 signal reset : std_logic := '0';
461 signal DAQ_reset : std_logic := '0';
462 signal AMCOSC_rdy : std_logic := '0';
463 --signal cs_clk_in : std_logic := '0';
464 --signal cs_clk : std_logic := '0';
465 signal TTC_debug : std_logic_vector(63 downto 0) := (others =>'0');
466 signal TxDisable_i : std_logic_vector(3 downto 0) := (others => '0');
467 signal DAQfifo_re : std_logic := '0';
468 signal DAQfifoAlmostEmpty : std_logic := '0';
469 signal DAQfifoEmpty : std_logic := '0';
470 signal DAQfifo_do : std_logic_vector(63 downto 0) := (others =>'0');
471 signal DAQ_debug_in : std_logic_vector(63 downto 0) := (others =>'0');
472 signal LDC_debug_out : std_logic_vector(63 downto 0) := (others =>'0');
473 signal LSC_debug_out : std_logic_vector(63 downto 0) := (others =>'0');
474 signal ddr_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
475 signal ddr_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
476 signal GbE_REFCLK : std_logic := '0';
477 signal S6Link_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
478 signal S6Link_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
479 signal GbE_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
480 signal GbE_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
481 signal AMC_debug_in : std_logic_vector(255 downto 0) := (others =>'0');
482 signal AMC_debug_out : std_logic_vector(255 downto 0) := (others =>'0');
483 signal SFP0_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
484 signal SFP0_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
485 signal SFP1_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
486 signal SFP1_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
487 signal ipb_master_out : ipb_wbus;
488 signal ipb_master_in : ipb_rbus;
489 signal SN : std_logic_vector(7 downto 0) := (others =>'0');
490 signal MACADDR : std_logic_vector(47 downto 0) := (others =>'0');
491 signal ipaddr : std_logic_vector(31 downto 0) := (others =>'0');
492 --signal use_SPI_IP : std_logic := '0';
493 --signal SPI_IP : std_logic_vector(31 downto 0) := (others =>'0');
494 signal status : std_logic_vector(31 downto 0) := (others =>'0');
495 signal cmd : std_logic_vector(31 downto 0) := (others =>'0');
496 signal conf : std_logic_vector(15 downto 0) := x"1180";
497 signal LSC_ID : std_logic_vector(15 downto 0) := x"1234";
498 signal OT : std_logic := '0';
499 signal inc_HTRCRC_err : std_logic := '0';
500 signal sysmon_data : std_logic_vector(31 downto 0) := (others => '0');
501 signal device_temp : std_logic_vector(11 downto 0) := (others =>'0');
502 signal ALM : std_logic_vector(7 downto 0) := (others =>'0');
503 signal evt_data_rdy : std_logic_vector(2 downto 0) := (others => '0');
504 signal evt_data_re : std_logic_vector(2 downto 0) := (others => '0');
505 signal evt_data_we : std_logic_vector(2 downto 0) := (others => '0');
506 --signal event_size : array3x13;
507 signal SFP_data : std_logic_vector(31 downto 0) := (others =>'0');
508 signal SFP_ack : std_logic := '0';
509 --signal TCP_data : std_logic_vector(31 downto 0) := (others =>'0');
510 --signal TCP_ack : std_logic := '0';
511 signal S2V_SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
512 signal resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
513 signal sysclk_div7SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
514 signal resetCntr_SyncRegs : std_logic_vector(2 downto 0) := (others =>'0');
515 signal newIPADDR : std_logic := '0';
516 signal newIPADDRSyncRegs : std_logic_vector(2 downto 0) := (others =>'0');
517 signal en_RARP : std_logic := '0';
518 signal DNA_out : std_logic := '0';
519 signal load_DNA : std_logic := '0';
520 signal shift_DNA : std_logic_vector(2 downto 0) := (others =>'0');
521 signal DNA_cntr : std_logic_vector(5 downto 0) := (others =>'0');
522 signal DNA : std_logic_vector(56 downto 0) := (others =>'0');
523 signal enSFP : std_logic_vector(3 downto 0) := (others =>'0');
524 signal SFP_down : std_logic_vector(2 downto 0) := (others =>'0');
525 --signal evt_buf_space : std_logic_vector(2 downto 0) := (others =>'0');
526 signal WrtMonBufDone : std_logic := '0';
527 signal DAQ_status : std_logic_vector(31 downto 0) := (others =>'0');
528 component icon2
529  PORT (
530  CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
531  CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
532 
533 end component;
534 component ila16x32k
535  PORT (
536  CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
537  CLK : IN STD_LOGIC;
538  DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
539  TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
540 
541 end component;
542 signal CONTROL0 : std_logic_vector(35 downto 0) := (others => '0');
543 signal CONTROL1 : std_logic_vector(35 downto 0) := (others => '0');
544 signal TRIG0 : std_logic_vector(7 downto 0) := (others => '0');
545 signal TRIG1 : std_logic_vector(7 downto 0) := (others => '0');
546 signal DATA0 : std_logic_vector(15 downto 0) := (others => '0');
547 signal DATA1 : std_logic_vector(15 downto 0) := (others => '0');
548 begin
549 USE_TRIGGER_PORT <= true when ISuHTR = '1' else false;
550 i_DAQ_LINK: DAQ_LINK
551 -- Generic map(F_REFCLK => 250, DRPclk_period => 20, USE_TRIGGER_PORT => false, simulation => false)
552  Generic map(F_REFCLK => 250, DRPclk_period => 20, simulation => false)
553  PORT MAP(
554  sysclk => sysclk,
555  DRPclk => DRPclk,
556  fake_clk => fake_clk,
557  EventDataClk => EventDataClk ,
558  reset => AMC_reset,
559  USE_TRIGGER_PORT => USE_TRIGGER_PORT ,
560  test => conf(7),
561  ovfl_warning => L1Aovfl_warning ,
562  ForceError => ForceError,
563  fake_lengthA => fake_lengthA ,
564  fake_lengthB => fake_lengthB ,
565  fake_seed => fake_seed,
566  event_number_avl => event_number_avl ,
567  event_number => event_number ,
568  board_ID => board_ID,
569  status => DAQ_status,
570  AMC_REFCLK_N => AMC_REFCLK_N ,
571  AMC_REFCLK_P => AMC_REFCLK_P ,
572  AMC_RXN => AMC_RXN,
573  AMC_RXP => AMC_RXP,
574  AMC_TXN => AMC_TXN,
575  AMC_TXP => AMC_TXP,
576  TTCclk => TTC_clk,
577  TTSclk => sysclk,
578  TTS => state
579  );
580 AMC_reset <= not sys_lock or cmd(0);
581 TTC_reset <= not sys_lock or cmd(3);
582 i_TTS_if: TTS_if PORT MAP(
583  sysclk => sysclk,
584  TTS_clk => TTS_clk,
585  reset => reset,
586  local_TTC => conf(8),
587  TTS => state,
588  TTS_out_p => TTS_out_p,
589  TTS_out_n => TTS_out_n
590  );
591 process(TTC_Clk)
592 begin
593  if(TTC_Clk'event and TTC_Clk = '1')then
594  AMC_trig <= or_reduce(TrigData);
595  BC0_dl <= BC0_dlp2;
596  if(BC0_dlp2 = '1')then
597  bcnt <= x"0";
598  else
599  bcnt <= bcnt + 1;
600  end if;
601  end if;
602 end process;
603 TxDisable <= TxDisable_i;
604 i_I2C: I2C PORT MAP(
605  clk => DRPclk ,
606  ipb_clk => clk125,
607  reset => sys_lock_n,
608  addr => ipb_master_out.ipb_addr,
609  rdata => I2C_data,
610  CLK_rdy => CLK_rdy,
611  CLK_SCL => CLK_SCL,
612  CLK_SDA => CLK_SDA,
613  SFP_ABS => SFP_ABS,
614  SFP_LOS => SFP_LOS,
615  SFP_SCL => SFP_SCL,
616  SFP_SDA => SFP_SDA
617  );
618 i_SPI_SCK_buf: bufh port map(i => SPI_SCK, o => SPI_SCK_buf);
619 i_SPI_if: SPI_if PORT MAP(
620  SCK => SPI_SCK ,
621  CSn => SPI_CS_b ,
622  MOSI => SPI_MOSI ,
623  MISO => SPI_MISO ,
624  SN => SN,
625  OT => '0',
626  IsT1 => '1',
627  SPI_we => open,
628  newIPADDR => newIPADDR,
629  en_RARP => en_RARP,
630  IPADDR => IPADDR,
631  SPI_rdata => (others => '0'),
632  SPI_wdata => open,
633  SPI_addr => open
634  );
635 i_ttc_if: ttc_if PORT MAP(
636  clk => sysclk ,
637  refclk => sysclk,
638  reset => reset,
639  run => run,
640  TTC_strobe => TTC_strobe,
641  sys_lock => sys_lock,
642  local_TTC => conf(8),
643  local_TTCcmd => conf(8),
644  TTS_clk => TTS_clk,
645  BC0 => BC0,
646  DIV4 => DIV4,
647  DIV_nRST => DIV_nRST,
648  CDRclk_p => CDRclk_p,
649  CDRclk_n => CDRclk_n,
650  CDRclk_out => CDRclk,
651  CDRdata_p => CDRdata_p,
652  CDRdata_n => CDRdata_n,
653  TTCdata_p => TTCdata_p,
654  TTCdata_n => TTCdata_n,
655  TTC_LOS => TTC_LOS,
656  TTC_LOL => TTC_LOL,
657  BCN_off => BCN_off,
658  OC_off => OC_off,
659  en_cal_win => en_cal_win,
660  cal_win_high => cal_win_high ,
661  cal_win_low => cal_win_low ,
662  CalType => CalType,
663  TTC_Brcst => TTC_Brcst,
664  ovfl_warning => L1Aovfl_warning ,
665  ipb_clk => ipb_clk,
666  ipb_write => ipb_master_out.ipb_write ,
667  ipb_strobe => ipb_master_out.ipb_strobe ,
668  ipb_addr => ipb_master_out.ipb_addr ,
669  ipb_wdata => ipb_master_out.ipb_wdata ,
670  ipb_rdata => open,
671  en_localL1A => conf(2),
672  LocalL1A_cfg => LocalL1A_cfg ,
673  localL1A_s => cmd(26),
674  localL1A_r => cmd(10),
675  localL1A_periodic => status(10),
676  EvnRSt_l => cmd(11),
677  OcnRSt_l => cmd(12),
678  T3_trigger => '0',
679  en_brcst => en_brcst,
680  ttc_start => ttc_start,
681  ttc_stop => ttc_stop,
682  ttc_soft_reset => ttc_soft_reset ,
683  ttc_ready => ttc_ready,
684  ttc_serr => ttc_serr,
685  ttc_derr => ttc_derr,
686  ttc_bcnt_err => ttc_bcnt_err ,
687  rate_OFW => rate_OFW,
688  sync_lost => sync_lost,
689  inc_oc => inc_oc,
690  inc_l1ac => inc_l1ac,
691  inc_bcnterr => inc_bcnterr ,
692  inc_serr => inc_serr,
693  inc_derr => inc_derr,
694  state => state,
695  evn_fifo_full => evn_fifo_full ,
696  ttc_evcnt_reset => ttc_evcnt_reset ,
697  event_number_avl => event_number_avl ,
698  event_number => event_number
699  );
700 CalibCtrl(31) <= en_cal_win;
701 CalibCtrl(30 downto 28) <= "000";
702 CalibCtrl(27 downto 16) <= cal_win_high;
703 CalibCtrl(15 downto 12) <= CalType;
704 CalibCtrl(11 downto 0) <= cal_win_low;
705 cal_win_high(11 downto 6) <= "110110";
706 cal_win_low(11 downto 6) <= "110110";
707 --i_S2V: IBUFDS generic map(DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25") port map(i => S2V_p, ib => S2V_n, o => S2V);
708 --i_V2S: OBUFDS generic map(IOSTANDARD => "LVDS_25") port map (O => V2S_p, OB => V2S_n, I => sysclk_div(7));
709 process(sysclk)
710 begin
711  if(sysclk'event and sysclk = '1')then
712 -- SPI_we_SyncRegs <= SPI_we_SyncRegs(1 downto 0) & SPI_we;
713 -- SPI_wr(0) <= SPI_we_SyncRegs(2) and not SPI_we_SyncRegs(1);
714 -- sysclk_div <= sysclk_div + 1;
715 -- sysclk_div7SyncRegs <= sysclk_div7SyncRegs(2 downto 0) & S2V;
716 -- if(resetSyncRegs(2) = '1')then
717 -- SV_Cntr <= (others => '0');
718 -- elsif(and_reduce(sysclk_div(6 downto 0)) = '1')then
719 -- SV_Cntr <= SV_Cntr + 1;
720 -- elsif(sysclk_div7SyncRegs(3) /= sysclk_div7SyncRegs(2))then
721 -- SV_Cntr <= SV_Cntr - 1;
722 -- end if;
723  end if;
724 end process;
725 i_GbE_REFCLK: IBUFDS_GTE2
726  port map
727  (
728  O => GbE_REFCLK,
729  ODIV2 => open,
730  CEB => '0',
731  I => GbE_REFCLK_P, -- Connect to package pin AB6
732  IB => GbE_REFCLK_N -- Connect to package pin AB5
733  );
734 i_TTCclk_in : IBUFGDS generic map (DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25")
735  port map (
736  O => TTCclk_in, -- Clock buffer output
737  I => TTCclk_p, -- Diff_p clock buffer input
738  IB => TTCclk_n -- Diff_n clock buffer input
739  );
740 i_TTC_CLK_buf: bufg port map(i => TTCclk_in, o => TTC_Clk);
741 i_sysclk_in_buf: bufh port map(i => GbE_REFCLK, o => sysclk_in);
742 i_PLL_sysclk : PLLE2_BASE
743  generic map (
744  BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
745  CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
746  CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
747  CLKIN1_PERIOD => 8.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
748  -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
749  CLKOUT0_DIVIDE => 5,
750  CLKOUT1_DIVIDE => 32,
751  CLKOUT2_DIVIDE => 20,
752  CLKOUT3_DIVIDE => 3,
753  CLKOUT4_DIVIDE => 12,
754  DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
755  REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
756  STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
757  )
758  port map (
759  -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
760  CLKOUT0 => sysclk_dcm,
761  CLKOUT1 => ipb_clk_dcm ,
762  CLKOUT2 => DRPclk_dcm,
763  CLKOUT3 => fake_clk_dcm,
764  CLKOUT4 => EventDataClk_dcm ,
765  -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
766  CLKFBOUT => clk125_dcm, -- 1-bit output: Feedback clock
767  -- Status Port: 1-bit (each) output: PLL status ports
768  LOCKED => sys_lock, -- 1-bit output: LOCK
769  -- Clock Input: 1-bit (each) input: Clock input
770  CLKIN1 => sysclk_in, -- 1-bit input: Input clock
771  -- Control Ports: 1-bit (each) input: PLL control ports
772  PWRDWN => '0', -- 1-bit input: Power-down
773  RST => '0', -- 1-bit input: Reset
774  -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
775  CLKFBIN => clk125 -- 1-bit input: Feedback clock
776  );
777 i_clk125_buf: bufg port map(i => clk125_dcm, o => clk125 );
778 i_ipb_clk_buf: bufg port map(i => ipb_clk_dcm, o => ipb_clk);
779 i_DRPclk_buf: bufg port map(i => DRPclk_dcm, o => DRPclk );
780 i_sysclk_buf: bufg port map(i => sysclk_dcm, o => sysclk );
781 i_fake_clk_buf: bufg port map(i => fake_clk_dcm, o => fake_clk);
782 i_EventDataClk_buf: bufg port map(i => EventDataClk_dcm, o => EventDataClk);
783 reset <= not sys_lock or cmd(0);
784 --sysclk <= refclk;
785 process(sysclk,reset)
786 begin
787  if(reset = '1')then
788  resetSyncRegs <= (others => '1');
789  elsif(sysclk'event and sysclk = '1')then
790  resetSyncRegs <= resetSyncRegs(1 downto 0) & '0';
791  end if;
792 end process;
793 MACADDR <= x"080030f30" & "000" & not SN(7 downto 6) & '1' & SN(5 downto 0);
794 i_ipbus_if: ipbus_if PORT MAP(
795  ipb_clk => ipb_clk,
796  UsRclk => clk125,
797  DRPclk => DRPclk,
798  reset => rst_ipbus,
799  en_RARP => en_RARP,
800  GTX_RESET => sys_lock_n,
801  MACADDR => MACADDR, -- new mac range 08-00-30-F3-00-00 to 08-00-30-F3-00-7F
802  IPADDR => IPADDR,
803  GbE_REFCLK => GbE_REFCLK,
804  S6LINK_RXN => S6LINK_RXN,
805  S6LINK_RXP => S6LINK_RXP,
806  S6LINK_TXN => S6LINK_TXN,
807  S6LINK_TXP => S6LINK_TXP,
808  wr_AMC_en => wr_AMC_en,
809  amc_en => AMC_en,
810  ipb_out => ipb_master_out,
811  ipb_in => ipb_master_in,
812  got_SN => got_SN,
813  SN => SN,
814  debug_in => (others => '0'),
815  debug_out => open
816  );
817 LSC_LinkDown <= '1' when conf(1) = '0' or or_reduce(EnSFP(2 downto 0) and SFP_down) = '1' else '0';
818 status(0) <= LSC_LinkDown;
819 --status(1) <= LSC_LinkAlmostFull;
820 status(2) <= mon_bufFull;
821 status(3) <= mon_buf_empty;
822 status(4) <= mem_stat(0); -- monitor input FIFO overflow
823 status(5) <= not ttc_ready;
824 status(6) <= ttc_bcnt_err;
825 status(7) <= ttc_serr;
826 status(8) <= ttc_derr;
827 status(9) <= sync_lost;
828 status(13) <= L1Aovfl_warning;
829 status(15) <= mem_stat(63);
830 status(23) <= '0';
831 run <= conf(0);
832 EnSFP(3) <= not conf(1);
833 mem_test <= conf(6) & conf(4);
834 en_brcst <= conf(5);
835 process(ipb_clk)
836 begin
837  if(ipb_clk'event and ipb_clk = '1')then
838  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = CSR_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
839  cmd <= ipb_master_out.ipb_wdata;
840  else
841  cmd <= (others => '0');
842  end if;
843  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = CFG_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
844  conf <= ipb_master_out.ipb_wdata(15 downto 0);
845  end if;
846  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = HTR_EN_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
847  EnSFP(2 downto 0) <= ipb_master_out.ipb_wdata(14 downto 12);
848  AMC_en <= x"000";
849  wr_AMC_en <= '1';
850  else
851  wr_AMC_en <= '0';
852  end if;
853  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = TTC_cal_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
854  en_cal_win <= ipb_master_out.ipb_wdata(31);
855  cal_win_high(5 downto 0) <= ipb_master_out.ipb_wdata(21 downto 16);
856  cal_win_low(5 downto 0) <= ipb_master_out.ipb_wdata(5 downto 0);
857  end if;
858  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = BC0_delay_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
859  BC0_delay <= ipb_master_out.ipb_wdata(4 downto 0);
860  end if;
861  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
862  board_ID <= ipb_master_out.ipb_wdata(15 downto 0);
863  end if;
864  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"001c" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
865  LocalL1A_cfg <= ipb_master_out.ipb_wdata;
866  end if;
867  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SFP_CSR_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
868  LSC_ID(15 downto 2) <= ipb_master_out.ipb_wdata(31 downto 18);
869  TxDisable_i <= ipb_master_out.ipb_wdata(15 downto 12);
870  end if;
871  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = TTC_bcnt_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
872  OC_OFF <= ipb_master_out.ipb_wdata(19 downto 16);
873  BCN_OFF <= ipb_master_out.ipb_wdata(12 downto 0);
874  end if;
875  if(ipb_master_out.ipb_addr(15 downto 1) = fake_length_addr(15 downto 1) and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
876  if(ipb_master_out.ipb_addr(0) = '0')then
877  fake_lengthA <= ipb_master_out.ipb_wdata(17 downto 0);
878  else
879  fake_lengthB <= ipb_master_out.ipb_wdata(17 downto 0);
880  end if;
881  end if;
882  if(ipb_master_out.ipb_addr(15 downto 0) = x"0017" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
883  ForceError <= ipb_master_out.ipb_wdata(3 downto 0);
884  ISuHTR <= ipb_master_out.ipb_wdata(31);
885  end if;
886  if(ipb_master_out.ipb_addr(15 downto 0) = x"001a" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
887  fake_seed <= ipb_master_out.ipb_wdata(16 downto 0);
888  end if;
889  if(ipb_master_out.ipb_addr(15 downto 0) = x"001b" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
890  TTS_pattern <= ipb_master_out.ipb_wdata(3 downto 0);
891  end if;
892  if(reset = '1' or (ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = MON_ctrl_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1'))then
893  ddr_pa <= (others => '0');
894  elsif(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = PAGE_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
895  if(run = '1')then
896  if(mon_buf_empty = '0')then
897  ddr_pa <= ddr_pa + 1;
898  end if;
899  else
900  ddr_pa <= ipb_master_out.ipb_wdata(9 downto 0);
901  end if;
902  end if;
903  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = PAGE_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1' and run = '1' and mon_buf_empty = '0')then
904  inc_ddr_pa <= '1';
905  else
906  inc_ddr_pa <= '0';
907  end if;
908  end if;
909 end process;
910 ipb_master_in.ipb_ack <= ipb_master_out.ipb_strobe when ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(17) = '0' else mem_ack;
911 process(ipb_master_out.ipb_addr)
912 begin
913  if(ipb_master_out.ipb_addr(27) = '1' or ipb_master_out.ipb_addr(17) = '1')then
914  ipb_master_in.ipb_rdata <= mem_data;
915  elsif(ipb_master_out.ipb_addr(20 downto 18) /= "000")then
916  if(ipb_master_out.ipb_addr(0) = '0')then
917  ipb_master_in.ipb_rdata <= mem_stat(31 downto 0);
918  else
919  ipb_master_in.ipb_rdata <= mem_stat(63 downto 32);
920  end if;
921  elsif(ipb_master_out.ipb_addr(15 downto 5) = CSR_addr(15 downto 5))then
922  case ipb_master_out.ipb_addr(4 downto 0) is
923  when "00000" => ipb_master_in.ipb_rdata <= not SN & status(23 downto 0);
924  when "00001" => ipb_master_in.ipb_rdata <= x"1009" & conf;
925  when "00010" => ipb_master_in.ipb_rdata <= DAQ_status;
926  when "00011" => ipb_master_in.ipb_rdata <= '0' & SFP_down & AMC_Ready & '0' & EnSFP(2 downto 0) & AMC_en;
927  when "00100" => ipb_master_in.ipb_rdata <= LSC_ID & TxDisable_i & TxFault & (TTC_LOL or TTC_LOL) & SFP_LOS & SFP_ABS;
928  when "00101" => ipb_master_in.ipb_rdata <= AMC_status;
929  when "00110" => ipb_master_in.ipb_rdata <= x"0" & BC0_lock & x"00" & "000" & BC0_delay;
930  when "00111" => ipb_master_in.ipb_rdata <= x"0000" & board_ID;
931  when "01000" => ipb_master_in.ipb_rdata <= x"000" & OC_OFF & "000" & BCN_OFF;
932  when "01001" => ipb_master_in.ipb_rdata <= CalibCtrl;
933  when "01100" => ipb_master_in.ipb_rdata <= x"00000" & "00" & ddr_pa;
934  when "01101" => ipb_master_in.ipb_rdata <= x"000" & "000" & mon_evt_wc(15 downto 0) & '0';
935  when "01110" => ipb_master_in.ipb_rdata <= mon_evt_cnt;
936  when "01111" => ipb_master_in.ipb_rdata <= x"000" & "000" & mon_evt_wc(31 downto 16) & '0';
937  when "10000" => ipb_master_in.ipb_rdata <= x"000" & "00" & mon_buf_avl & '1' & '0' & wport_FIFO_full & '0' & wport_rdy & '0' & "000" & '0' & evt_data_rdy;
938  when "10111" => ipb_master_in.ipb_rdata <= ISuHTR & "000" & x"000000" & ForceError;
939  when "11000" => ipb_master_in.ipb_rdata <= x"000" & "00" & fake_lengthA;
940  when "11001" => ipb_master_in.ipb_rdata <= x"000" & "00" & fake_lengthB;
941  when "11010" => ipb_master_in.ipb_rdata <= x"000" & "000" & fake_seed;
942  when "11011" => ipb_master_in.ipb_rdata <= x"0000000" & TTS_pattern;
943  when "11100" => ipb_master_in.ipb_rdata <= LocalL1A_cfg;
944  when "11101" => ipb_master_in.ipb_rdata <= x"000" & "000" & mon_evt_wc(47 downto 32) & '0';
945  when "11110" => ipb_master_in.ipb_rdata <= DNA(31 downto 0);
946  when "11111" => ipb_master_in.ipb_rdata <= "0000000" & DNA(56 downto 32);
947  when others => ipb_master_in.ipb_rdata <= (others => '0');
948  end case;
949  else
950  ipb_master_in.ipb_rdata <= AMC_data or CounterDoB(63 downto 32) or CounterDoB(31 downto 0) or I2C_data or sysmon_data or SFP_data;
951  end if;
952 end process;
953 rst_cntr <= cmd(1) or cmd(0);
954 process(sysClk, rst_cntr,reset)
955 begin
956  if(reset = '1' or rst_cntr = '1')then
957  TTC_serr_cntr <= (others =>'0');
958  TTC_derr_cntr <= (others =>'0');
959  TTC_BcntErr_cntr <= (others =>'0');
960  L1A_cntr <= (others =>'0');
961  run_cntr <= (others =>'0');
962  ready_cntr <= (others =>'0');
963  busy_cntr <= (others =>'0');
964  sync_cntr <= (others =>'0');
965  ovfl_cntr <= (others =>'0');
966  monitorEvent_cntr <= (others =>'0');
967  elsif(sysClk'event and sysClk = '1')then
968  if(inc_serr = '1')then
969  TTC_serr_cntr <= TTC_serr_cntr + 1;
970  end if;
971  if(inc_derr = '1')then
972  TTC_derr_cntr <= TTC_derr_cntr + 1;
973  end if;
974  if(inc_bcnterr = '1')then
975  TTC_BcntErr_cntr <= TTC_BcntErr_cntr + 1;
976  end if;
977  if(inc_l1ac = '1')then
978  L1A_cntr <= L1A_cntr + 1;
979  end if;
980  if(run = '1')then
981  run_cntr <= run_cntr + 1;
982  if(state(3 downto 2) = "10")then
983  ready_cntr <= ready_cntr + 1;
984  end if;
985  if(state(3 downto 2) = "01")then
986  busy_cntr <= busy_cntr + 1;
987  end if;
988  if(state(3) = '0' and state(1) = '1')then
989  sync_cntr <= sync_cntr + 1;
990  end if;
991  if(state(3) = '0' and state(0) = '1')then
992  ovfl_cntr <= ovfl_cntr + 1;
993  end if;
994  end if;
995  if(inc_mon_cntr = '1')then
996  monitorEvent_cntr <= monitorEvent_cntr + 1;
997  end if;
998  end if;
999 end process;
1000 process(sysClk)
1001 begin
1002  if(sysClk'event and sysClk = '1')then
1003  if(resync_done = '1' or run = '0')then
1004  ttc_resync <= '0';
1005  elsif(ttc_soft_reset = '1')then
1006  ttc_resync <= '1';
1007  end if;
1008  if(ttc_resync = '0' or conf(13) = '1')then
1009  oc_cntr <= "0000";
1010  elsif(inc_oc = '1')then
1011  oc_cntr <= oc_cntr + 1;
1012  end if;
1013  if(oc_cntr = "1010" or (conf(13) = '1' and ttc_soft_resetp = '1'))then
1014  resync_done <= '1';
1015  else
1016  resync_done <= '0';
1017  end if;
1018  if(ttc_resync = '0')then
1019  dcc_quiet <= '0';
1020  elsif(inc_oc = '1')then
1021  dcc_quiet <= '1';
1022  end if;
1023  if((conf(13) = '0' and oc_cntr(3) = '0' and ttc_resync = '1') or (conf(13) = '1' and dcc_quiet = '1' and inc_oc = '1'))then
1024  ttc_soft_resetp <= '1';
1025  else
1026  ttc_soft_resetp <= '0';
1027  end if;
1028  rate_OFW_q <= rate_OFW;
1029  inc_rate_OFW <= not rate_OFW_q and rate_OFW;
1030  rate_OFWp <= rate_OFW and conf(15);
1031  if(reset = '1')then
1032  state <= "0100";
1033  else
1034  if(conf(12) = '1')then
1035  state <= TTS_pattern;
1036  elsif(run = '0')then
1037  state <= "0100"; -- changed upon request starting version 0x3023
1038  elsif(ttc_resync = '1')then
1039  state <= "0100";
1040  else
1041  case state is
1042  when "1000" =>
1043  if(TTS_coded(4) = '1')then
1044  state <= "1111";
1045  elsif(TTS_coded(3) = '1')then
1046  state <= "1100";
1047  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1048  state <= "0010";
1049  elsif(L1Aovfl_warning = '1' or evn_fifo_full = '1' or rate_OFWp = '1' or TTS_coded(1) = '1' or TTS_coded(0) = '1')then
1050  state <= "0001";
1051  end if;
1052  when "0001" =>
1053  if(TTS_coded(4) = '1')then
1054  state <= "1111";
1055  elsif(TTS_coded(3) = '1')then
1056  state <= "1100";
1057  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1058  state <= "0010";
1059  elsif(evn_fifo_full = '1' or rate_OFWp = '1' or TTS_coded(1) = '1')then
1060  state <= "0100";
1061  elsif(L1Aovfl_warning = '0' and rate_OFWp = '0' and TTS_coded(0) = '0')then
1062  state <= "1000";
1063  end if;
1064  when "0100" =>
1065  if(TTS_coded(4) = '1')then
1066  state <= "1111";
1067  elsif(TTS_coded(3) = '1')then
1068  state <= "1100";
1069  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1070  state <= "0010";
1071  elsif(evn_fifo_full = '0' and rate_OFWp = '0' and TTS_coded(1) = '0')then
1072  state <= "0001";
1073  end if;
1074  when others => null;
1075  end case;
1076  end if;
1077  end if;
1078  end if;
1079 end process;
1080 ipb_master_in.ipb_err <= '0';
1081 sys_lock_n <= not sys_lock;
1082 i_sysmon_if: sysmon_if PORT MAP(
1083  DRPclk => DRPclk,
1084  SN => SN,
1085  VAUXN_IN => VAUXN,
1086  VAUXP_IN => VAUXP,
1087  addr => ipb_master_out.ipb_addr(15 downto 0),
1088  data => sysmon_data ,
1089  device_temp => device_temp ,
1090  ALM => ALM,
1091  OT => OT
1092  );
1093 i_counter_L : BRAM_TDP_MACRO
1094  generic map (
1095  BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
1096  DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1097  DOA_REG => 0, -- Optional port A output register (0 or 1)
1098  DOB_REG => 0, -- Optional port B output register (0 or 1)
1099  INIT_A => X"000000000", -- Initial values on A output port
1100  INIT_B => X"000000000", -- Initial values on B output port
1101  INIT_FILE => "NONE",
1102  READ_WIDTH_A => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1103  READ_WIDTH_B => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1104  SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY",
1105  -- "GENERATE_X_ONLY" or "NONE"
1106  SRVAL_A => X"000000000", -- Set/Reset value for A port output
1107  SRVAL_B => X"000000000", -- Set/Reset value for B port output
1108  WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
1109  WRITE_MODE_B => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
1110  WRITE_WIDTH_A => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1111  WRITE_WIDTH_B => 32) -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1112  port map (
1113  DOA => CounterDoA(31 downto 0), -- Output port-A data, width defined by READ_WIDTH_A parameter
1114  DOB => CounterDoB(31 downto 0), -- Output port-B data, width defined by READ_WIDTH_B parameter
1115  ADDRA => counter_wa, -- Input port-A address, width defined by Port A depth
1116  ADDRB => counter_ra_l, -- Input port-B address, width defined by Port B depth
1117  CLKA => sysclk, -- 1-bit input port-A clock
1118  CLKB => clk125, -- 1-bit input port-B clock
1119  DIA => CounterDi(31 downto 0), -- Input port-A data, width defined by WRITE_WIDTH_A parameter
1120  DIB => (others => '0'), -- Input port-B data, width defined by WRITE_WIDTH_B parameter
1121  ENA => '1', -- 1-bit input port-A enable
1122  ENB => '1', -- 1-bit input port-B enable
1123  REGCEA => '1', -- 1-bit input port-A output register enable
1124  REGCEB => '1', -- 1-bit input port-B output register enable
1125  RSTA => '0', -- 1-bit input port-A reset
1126  RSTB => '0', -- 1-bit input port-B reset
1127  WEA => counter_we, -- Input port-A write enable, width defined by Port A depth
1128  WEB => x"0" -- Input port-B write enable, width defined by Port B depth
1129  );
1130 i_counter_H : BRAM_TDP_MACRO
1131  generic map (
1132  BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
1133  DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1134  DOA_REG => 0, -- Optional port A output register (0 or 1)
1135  DOB_REG => 0, -- Optional port B output register (0 or 1)
1136  INIT_A => X"000000000", -- Initial values on A output port
1137  INIT_B => X"000000000", -- Initial values on B output port
1138  INIT_FILE => "NONE",
1139  READ_WIDTH_A => 16, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1140  READ_WIDTH_B => 16, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1141  SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY",
1142  -- "GENERATE_X_ONLY" or "NONE"
1143  SRVAL_A => X"000000000", -- Set/Reset value for A port output
1144  SRVAL_B => X"000000000", -- Set/Reset value for B port output
1145  WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
1146  WRITE_MODE_B => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
1147  WRITE_WIDTH_A => 16, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1148  WRITE_WIDTH_B => 16) -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1149  port map (
1150  DOA => CounterDoA(47 downto 32), -- Output port-A data, width defined by READ_WIDTH_A parameter
1151  DOB => CounterDoB(47 downto 32), -- Output port-B data, width defined by READ_WIDTH_B parameter
1152  ADDRA => counter_wa, -- Input port-A address, width defined by Port A depth
1153  ADDRB => counter_ra_h, -- Input port-B address, width defined by Port B depth
1154  CLKA => sysclk, -- 1-bit input port-A clock
1155  CLKB => clk125, -- 1-bit input port-B clock
1156  DIA => CounterDi(47 downto 32), -- Input port-A data, width defined by WRITE_WIDTH_A parameter
1157  DIB => (others => '0'), -- Input port-B data, width defined by WRITE_WIDTH_B parameter
1158  ENA => '1', -- 1-bit input port-A enable
1159  ENB => '1', -- 1-bit input port-B enable
1160  REGCEA => '1', -- 1-bit input port-A output register enable
1161  REGCEB => '1', -- 1-bit input port-B output register enable
1162  RSTA => '0', -- 1-bit input port-A reset
1163  RSTB => '0', -- 1-bit input port-B reset
1164  WEA => counter_we(1 downto 0), -- Input port-A write enable, width defined by Port A depth
1165  WEB => "00" -- Input port-B write enable, width defined by Port B depth
1166  );
1167 counter_we <= x"f" when div(1 downto 0) = "11" else x"0";
1168 process(ipb_clk)
1169 begin
1170  if(ipb_clk'event and ipb_clk = '1')then
1171  newIPADDRSyncRegs <= newIPADDRSyncRegs(1 downto 0) & newIPADDR;
1172  rst_ipbus <= not newIPADDRSyncRegs(2) and newIPADDR;
1173  end if;
1174 end process;
1175 CounterDi(47 downto 8) <= (others => '0') when CntrRstCycle = '1' else
1176 CounterDoA(47 downto 8) + 1 when CounterDi(7 downto 0) < CounterDoA(7 downto 0) else CounterDoA(47 downto 8);
1177 counter_wa <= "00000" & div(6 downto 2);
1178 counter_ra_l(4 downto 0) <= ipb_master_out.ipb_addr(5 downto 1);
1179 counter_ra_h(4 downto 0) <= ipb_master_out.ipb_addr(5 downto 1);
1180 counter_ra_l(5) <= ipb_master_out.ipb_addr(0);
1181 counter_ra_h(5) <= not ipb_master_out.ipb_addr(0);
1182 counter_ra_l(9 downto 6) <= x"0" when ipb_master_out.ipb_addr(15 downto 6) = misc_cntr_addr(15 downto 6) else x"1";
1183 counter_ra_h(9 downto 6) <= x"0" when ipb_master_out.ipb_addr(15 downto 6) = misc_cntr_addr(15 downto 6) else x"1";
1184 process(sysClk)
1185 begin
1186  if(sysclk'event and sysclk = '1')then
1187  if(CntrRst = '1')then
1188  div <= (others => '0');
1189  else
1190  div <= div + 1;
1191  end if;
1192  resetCntr_SyncRegs <= resetCntr_SyncRegs(1 downto 0) & rst_cntr;
1193  CntrRst <= not resetCntr_SyncRegs(2) and resetCntr_SyncRegs(1);
1194  if(CntrRst = '1')then
1195  CntrRstCycle <= '1';
1196  elsif(and_reduce(div) = '1')then
1197  CntrRstCycle <= '0';
1198  end if;
1199  if(CntrRstCycle = '1')then
1200  CounterDi(7 downto 0) <= (others => '0');
1201  else
1202  case div(6 downto 2) is
1203  when "00000" => CounterDi(7 downto 0) <= TTC_serr_cntr;
1204  when "00001" => CounterDi(7 downto 0) <= TTC_derr_cntr;
1205  when "00010" => CounterDi(7 downto 0) <= TTC_BcntErr_cntr;
1206  when "00011" => CounterDi(7 downto 0) <= L1A_cntr;
1207  when "00100" => CounterDi(7 downto 0) <= run_cntr;
1208  when "00101" => CounterDi(7 downto 0) <= ready_cntr;
1209  when "00110" => CounterDi(7 downto 0) <= busy_cntr;
1210  when "00111" => CounterDi(7 downto 0) <= sync_cntr;
1211  when "01000" => CounterDi(7 downto 0) <= ovfl_cntr;
1212  when "01011" => CounterDi(7 downto 0) <= monitorEvent_cntr;
1213  when others => CounterDi(7 downto 0) <= (others => '0');
1214  end case;
1215  end if;
1216  end if;
1217 end process;
1218 i_DNA_PORT : DNA_PORT
1219  generic map (
1220  SIM_DNA_VALUE => X"00123456789abcd" -- Specifies a sample 57-bit DNA value for simulation
1221  )
1222  port map (
1223  DOUT => DNA_out, -- 1-bit output: DNA output data.
1224  CLK => ipb_clk, -- 1-bit input: Clock input.
1225  DIN => '0', -- 1-bit input: User data input pin.
1226  READ => load_DNA, -- 1-bit input: Active high load DNA, active low read input.
1227  SHIFT => shift_DNA(1) -- 1-bit input: Active high shift enable input.
1228  );
1229 process(ipb_clk)
1230 begin
1231  if(ipb_clk'event and ipb_clk = '1')then
1232  load_DNA <= not sys_lock;
1233  if(sys_lock = '0')then
1234  shift_DNA(0) <= '0';
1235  elsif(load_DNA = '1')then
1236  shift_DNA(0) <= '1';
1237  elsif(shift_DNA(2) = '1' and or_reduce(DNA_cntr(5 downto 1)) = '0')then
1238  shift_DNA(0) <= '0';
1239  end if;
1240  shift_DNA(2) <= shift_DNA(0);
1241  if(shift_DNA(2) = '1')then
1242  DNA_cntr <= DNA_cntr - 1;
1243  elsif(shift_DNA(0) = '1')then
1244  DNA_cntr <= "110111";
1245  end if;
1246  if(shift_DNA(2) = '1')then
1247  DNA <= DNA(55 downto 0) & DNA_OUT;
1248  end if;
1249  end if;
1250 end process;
1251 process(ipb_clk)
1252 begin
1253  if(ipb_clk'event and ipb_clk = '0')then
1254  shift_DNA(1) <= shift_DNA(0);
1255  end if;
1256 end process;
1257 end Behavioral;
1258 
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