AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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IPBUS
ipbus2
ipbus_core
hdl
udp_buffer_selector.vhd
1
-- Dave Sankey May
2013
2
3
LIBRARY
ieee
;
4
USE
ieee.std_logic_1164.
all
;
5
use
ieee.numeric_std.
all
;
6
7
ENTITY
udp_buffer_selector
IS
8
generic
(
9
BUFWIDTH
:
natural
:=
0
10
)
;
11
port
(
12
mac_clk
:
in
std_logic
;
13
rst_macclk
:
in
std_logic
;
14
--
15
written
:
in
std_logic
;
16
we
:
in
std_logic
;
17
--
18
sent
:
in
std_logic
;
19
--
20
req_resend
:
in
std_logic
;
21
resend_buf
:
in
std_logic_vector
(
BUFWIDTH
-
1
downto
0
)
;
22
--
23
busy
:
out
std_logic
;
24
write_buf
:
out
std_logic_vector
(
BUFWIDTH
-
1
downto
0
)
;
25
--
26
req_send
:
out
std_logic
;
27
send_buf
:
out
std_logic_vector
(
BUFWIDTH
-
1
downto
0
)
;
28
clean_buf
:
out
std_logic_vector
(
2
*
*
BUFWIDTH
-
1
downto
0
)
29
)
;
30
end
udp_buffer_selector
;
31
32
architecture
simple
of
udp_buffer_selector
is
33
34
signal
free
,
clean
,
send_pending
:
std_logic_vector
(
2
*
*
BUFWIDTH
-
1
downto
0
)
;
35
signal
send_sig
,
write_sig
:
unsigned
(
BUFWIDTH
-
1
downto
0
)
;
36
signal
sending
,
busy_sig
:
std_logic
;
37
38
begin
39
40
write_buf
<=
std_logic_vector
(
write_sig
)
;
41
send_buf
<=
std_logic_vector
(
send_sig
)
;
42
busy
<=
busy_sig
;
43
clean_buf
<=
clean
;
44
45
free_block:
process
(mac_clk)
46
variable
free_i
:
std_logic_vector
(
2
*
*
BUFWIDTH
-
1
downto
0
)
;
47
begin
48
if
rising_edge
(
mac_clk
)
then
49
if
rst_macclk
=
'
1
'
then
50
free_i
:=
(
Others
=
>
'
1
'
)
;
51
else
52
if
written
=
'
1
'
then
53
free_i
(
to_integer
(
write_sig
)
)
:=
'
0
'
;
54
end
if
;
55
if
req_resend
=
'
1
'
and
clean
(
to_integer
(
unsigned
(
resend_buf
)
)
)
=
'
1
'
then
56
free_i
(
to_integer
(
unsigned
(
resend_buf
)
)
)
:=
'
0
'
;
57
end
if
;
58
if
sent
=
'
1
'
then
59
free_i
(
to_integer
(
send_sig
)
)
:=
'
1
'
;
60
end
if
;
61
end
if
;
62
free
<=
free_i
63
-- pragma translate_off
64
after
4
ns
65
-- pragma translate_on
66
;
67
end
if
;
68
end
process
;
69
70
clean_block:
process
(mac_clk)
71
variable
clean_i
:
std_logic_vector
(
2
*
*
BUFWIDTH
-
1
downto
0
)
;
72
begin
73
if
rising_edge
(
mac_clk
)
then
74
if
rst_macclk
=
'
1
'
then
75
clean_i
:=
(
Others
=
>
'
0
'
)
;
76
else
77
if
written
=
'
1
'
then
78
clean_i
(
to_integer
(
write_sig
)
)
:=
'
1
'
;
79
elsif
we
=
'
1
'
then
80
clean_i
(
to_integer
(
write_sig
)
)
:=
'
0
'
;
81
end
if
;
82
end
if
;
83
clean
<=
clean_i
84
-- pragma translate_off
85
after
4
ns
86
-- pragma translate_on
87
;
88
end
if
;
89
end
process
;
90
91
send_pending_block:
process
(mac_clk)
92
variable
send_pending_i
:
std_logic_vector
(
2
*
*
BUFWIDTH
-
1
downto
0
)
;
93
begin
94
if
rising_edge
(
mac_clk
)
then
95
if
rst_macclk
=
'
1
'
then
96
send_pending_i
:=
(
Others
=
>
'
0
'
)
;
97
else
98
if
written
=
'
1
'
then
99
send_pending_i
(
to_integer
(
write_sig
)
)
:=
'
1
'
;
100
end
if
;
101
if
req_resend
=
'
1
'
and
clean
(
to_integer
(
unsigned
(
resend_buf
)
)
)
=
'
1
'
then
102
send_pending_i
(
to_integer
(
unsigned
(
resend_buf
)
)
)
:=
'
1
'
;
103
end
if
;
104
if
sent
=
'
1
'
then
105
send_pending_i
(
to_integer
(
send_sig
)
)
:=
'
0
'
;
106
end
if
;
107
end
if
;
108
send_pending
<=
send_pending_i
109
-- pragma translate_off
110
after
4
ns
111
-- pragma translate_on
112
;
113
end
if
;
114
end
process
;
115
116
busy_block:
process
(mac_clk)
117
variable
busy_i
:
std_logic
;
118
begin
119
if
rising_edge
(
mac_clk
)
then
120
if
rst_macclk
=
'
1
'
then
121
busy_i
:=
'
1
'
;
122
else
123
if
busy_i
=
'
1
'
and
free
(
to_integer
(
write_sig
)
)
=
'
1
'
then
124
busy_i
:=
'
0
'
;
125
elsif
written
=
'
1
'
then
126
busy_i
:=
'
1
'
;
127
end
if
;
128
end
if
;
129
busy_sig
<=
busy_i
130
-- pragma translate_off
131
after
4
ns
132
-- pragma translate_on
133
;
134
end
if
;
135
end
process
;
136
137
req_send_block:
process
(mac_clk)
138
variable
req_send_i
,
sending_i
:
std_logic
;
139
begin
140
if
rising_edge
(
mac_clk
)
then
141
req_send_i
:=
'
0
'
;
142
if
rst_macclk
=
'
1
'
then
143
sending_i
:=
'
0
'
;
144
else
145
if
sending
=
'
0
'
and
send_pending
(
to_integer
(
send_sig
)
)
=
'
1
'
then
146
sending_i
:=
'
1
'
;
147
req_send_i
:=
'
1
'
;
148
elsif
sent
=
'
1
'
then
149
sending_i
:=
'
0
'
;
150
end
if
;
151
end
if
;
152
req_send
<=
req_send_i
153
-- pragma translate_off
154
after
4
ns
155
-- pragma translate_on
156
;
157
sending
<=
sending_i
158
-- pragma translate_off
159
after
4
ns
160
-- pragma translate_on
161
;
162
end
if
;
163
end
process
;
164
165
write_block:
process
(mac_clk)
166
variable
write_i
:
unsigned
(
BUFWIDTH
-
1
downto
0
)
;
167
begin
168
if
rising_edge
(
mac_clk
)
then
169
if
rst_macclk
=
'
1
'
then
170
write_i
:=
(
Others
=
>
'
0
'
)
;
171
else
172
if
busy_sig
=
'
1
'
and
free
(
to_integer
(
write_sig
)
)
=
'
0
'
then
173
if
write_sig
=
2
*
*
BUFWIDTH
-
1
then
174
write_i
:=
(
Others
=
>
'
0
'
)
;
175
else
176
write_i
:=
write_sig
+
1
;
177
end
if
;
178
end
if
;
179
end
if
;
180
write_sig
<=
write_i
181
-- pragma translate_off
182
after
4
ns
183
-- pragma translate_on
184
;
185
end
if
;
186
end
process
;
187
188
send_block:
process
(mac_clk)
189
variable
send_i
:
unsigned
(
BUFWIDTH
-
1
downto
0
)
;
190
begin
191
if
rising_edge
(
mac_clk
)
then
192
if
rst_macclk
=
'
1
'
then
193
send_i
:=
(
Others
=
>
'
0
'
)
;
194
else
195
if
sending
=
'
0
'
and
send_pending
(
to_integer
(
send_sig
)
)
=
'
0
'
then
196
if
send_sig
=
2
*
*
BUFWIDTH
-
1
then
197
send_i
:=
(
Others
=
>
'
0
'
)
;
198
else
199
send_i
:=
send_sig
+
1
;
200
end
if
;
201
end
if
;
202
end
if
;
203
send_sig
<=
send_i
204
-- pragma translate_off
205
after
4
ns
206
-- pragma translate_on
207
;
208
end
if
;
209
end
process
;
210
211
end
simple
;
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