AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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ttc_if.vhd
1 -- TTCrx interface module
2 -- TTCrx register file occupies 128 bytes of memory space
3 -- to simplify the design, all accesses are 32 bit wide,
4 -- although only the LSB byte carries data.
5 -- according to TTCrx manual, its SCL line is input only.
6 -- So no arbitration and no wait holding are assumed in this design.
7 -- TTC Hamming encoding (short)
8 -- hmg[0] = d[0]^d[1]^d[2]^d[3];
9 -- hmg[1] = d[0]^d[4]^d[5]^d[6];
10 -- hmg[2] = d[1]^d[2]^d[4]^d[5]^d[7];
11 -- hmg[3] = d[1]^d[3]^d[4]^d[6]^d[7];
12 -- hmg[4] = d[0]^d[2]^d[3]^d[5]^d[6]^d[7];
13 -- TTC Hamming encoding (long)
14 -- hmg(0) <= xor_reduce(d(5 downto 0));
15 -- hmg(1) <= xor_reduce(d(20 downto 6));
16 -- hmg(2) <= xor_reduce(d(27 downto 21)) xor xor_reduce(d(13 downto 6));
17 -- hmg(3) <= xor_reduce(d(30 downto 28)) xor xor_reduce(d(24 downto 21)) xor xor_reduce(d(17 downto 14)) xor xor_reduce(d(9 downto 6)) xor xor_reduce(d(2 downto 0));
18 -- hmg(4) <= d(31) xor d(29) xor d(28) xor d(26) xor d(25) xor d(22) xor d(21) xor d(19) xor d(18) xor d(15) xor d(14) xor d(11) xor d(10) xor d(7) xor d(6) xor d(4) xor d(3) xor d(0);
19 -- hmg(5) <= d(31) xor d(30) xor d(28) xor d(27) xor d(25) xor d(23) xor d(21) xor d(20) xor d(18) xor d(16) xor d(14) xor d(12) xor d(10) xor d(8) xor d(6) xor d(5) xor d(3) xor d(1);
20 -- hmg(6) <= d(31) xor d(30) xor d(29) xor d(27) xor d(26) xor d(24) xor d(21) xor d(20) xor d(19) xor d(17) xor d(14) xor d(13) xor d(10) xor d(8) xor d(7) xor d(5) xor d(4) xor d(2);
21 -- hmg(6) <= xor_reduce(d) xor xor_reduce(hmg(5 downto 0));
22 -- reset orbit counter command 001x1xxx
23 library IEEE;
24 use IEEE.STD_LOGIC_1164.ALL;
25 use IEEE.STD_LOGIC_ARITH.ALL;
26 use IEEE.STD_LOGIC_UNSIGNED.ALL;
27 use IEEE.std_logic_misc.all;
28 library UNISIM;
29 use UNISIM.VComponents.all;
30 entity ttc_if is
31 -- generic (rate_limit : std_logic_vector(9 downto 0) := "0111110010");
32  Port (
33  clk : in std_logic;
34  refclk : in std_logic;
35  reset : in std_logic;
36  run : in std_logic;
37  DB_cmd_in : in std_logic;
38  DB_cmd_out : out std_logic;
39  IsG2 : in std_logic;
40  BC0 : out std_logic;
41  TTC_strobe : out std_logic;
42  sys_lock : in std_logic;
43  local_TTC : in STD_LOGIC; --! Controls TTS output (for fake TTC output)
44  local_TTCcmd : in STD_LOGIC;
45  single_TTCcmd : in STD_LOGIC;
46  TTS_clk : out std_logic;
47 -- CDR signals
48  DIV4 : out STD_LOGIC;
49  DIV_nRST : out STD_LOGIC;
50  CDRclk_p : in STD_LOGIC;
51  CDRclk_n : in STD_LOGIC;
52  CDRclk_out : out STD_LOGIC;
53  CDRdata_p : in STD_LOGIC;
54  CDRdata_n : in STD_LOGIC;
55  TTCdata_p : out STD_LOGIC;
56  TTCdata_n : out STD_LOGIC;
57  TTC_LOS : in STD_LOGIC;
58  TTC_LOL : in STD_LOGIC;
59 -- bcn offset
60  BCN_off : in std_logic_vector(12 downto 0);
61  OC_off : in std_logic_vector(3 downto 0);
62  en_cal_win : in std_logic;
63  cal_win_high : in std_logic_vector(11 downto 0); -- five MSB is constant = "110110"
64  cal_win_low : in std_logic_vector(11 downto 0); -- five MSB is constant = "110110"
65  CalType : out std_logic_vector(3 downto 0);
66  TTC_Brcst : out std_logic_vector(3 downto 0);
67 -- Local L1A control
68  en_localL1A : in std_logic;
69  LocalL1A_cfg : in std_logic_vector(31 downto 0);
70  localL1A_s : in std_logic;
71  localL1A_r : in std_logic;
72  HCAL_trigger : in std_logic;
73  T3_trigger : in std_logic;
74  EvnRSt_l : in std_logic;
75  OcnRSt_l : in std_logic;
76  localL1A_periodic : out std_logic;
77  ovfl_warning : in std_logic;
78 -- ipbus signals
79  ipb_clk : in STD_LOGIC;
80  ipb_write : in STD_LOGIC;
81  ipb_strobe : in STD_LOGIC;
82  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
83  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
84  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
85 -- TTCrx status : ready, single error and double error
86  en_brcst : in std_logic;
87  ttc_start : out std_logic;
88  ttc_stop : out std_logic;
89  ttc_soft_reset : out std_logic; -- TTC ReSync
90  ttc_ready : out std_logic;
91  ttc_serr : out std_logic;
92  ttc_derr : out std_logic;
93  ttc_bcnt_err : out std_logic;
94  rate_OFW : out std_logic;
95  sync_lost : out std_logic;
96  inc_oc : out std_logic;
97  inc_l1ac : out std_logic;
98  inc_bcnterr : out std_logic;
99  inc_serr : out std_logic;
100  inc_derr : out std_logic;
101  state : in std_logic_vector(3 downto 0);
102  evn_fifo_full : in std_logic;
103  ttc_evcnt_reset : out std_logic;
104  event_number_avl : out std_logic;
105  event_number : out std_logic_vector(59 downto 0)
106  );
107 end ttc_if;
108 
109 architecture ttc_arch of ttc_if is
110  COMPONENT SCRAMBLER
111  generic
112  (
113  TX_DATA_WIDTH : integer := 32
114  );
115  PORT(
116  UNSCRAMBLED_DATA_IN : IN std_logic_vector((TX_DATA_WIDTH-1) downto 0);
117  DATA_VALID_IN : IN std_logic;
118  USER_CLK : IN std_logic;
119  SYSTEM_RESET : IN std_logic;
120  SCRAMBLED_DATA_OUT : OUT std_logic_vector((TX_DATA_WIDTH-1) downto 0)
121  );
122  END COMPONENT;
123  COMPONENT Threshold
124  PORT(
125  clk : IN std_logic;
126  din : IN std_logic_vector(15 downto 0);
127  nongap_size : IN std_logic_vector(11 downto 0);
128  dout : OUT std_logic_vector(31 downto 0)
129  );
130  END COMPONENT;
131  function hemming_s(d : std_logic_vector(7 downto 0)) return std_logic_vector is
132  variable hmg : std_logic_vector(4 downto 0);
133  begin
134  hmg(0) := d(0) xor d(1) xor d(2) xor d(3);
135  hmg(1) := d(0) xor d(4) xor d(5) xor d(6);
136  hmg(2) := d(1) xor d(2) xor d(4) xor d(5) xor d(7);
137  hmg(3) := d(1) xor d(3) xor d(4) xor d(6) xor d(7);
138  hmg(4) := d(0) xor d(2) xor d(3) xor d(5) xor d(6) xor d(7);
139  return hmg;
140  end hemming_s;
141  function hemming_l(d : std_logic_vector(31 downto 0)) return std_logic_vector is
142  variable hmg : std_logic_vector(6 downto 0);
143  begin
144  hmg(0) := d(5) xor d(4) xor d(3) xor d(2) xor d(1) xor d(0);
145  hmg(1) := d(20) xor d(19) xor d(18) xor d(17) xor d(16) xor d(15) xor d(14) xor d(13) xor d(12) xor d(11) xor d(10) xor d(9) xor d(8) xor d(7) xor d(6);
146  hmg(2) := d(27) xor d(26) xor d(25) xor d(24) xor d(23) xor d(22) xor d(21) xor d(13) xor d(12) xor d(11) xor d(10) xor d(9) xor d(8) xor d(7) xor d(6);
147  hmg(3) := d(30) xor d(29) xor d(28) xor d(24) xor d(23) xor d(22) xor d(21) xor d(17) xor d(16) xor d(15) xor d(14) xor d(9) xor d(8) xor d(7) xor d(6) xor d(2) xor d(1) xor d(0);
148  hmg(4) := d(31) xor d(29) xor d(28) xor d(26) xor d(25) xor d(22) xor d(21) xor d(19) xor d(18) xor d(15) xor d(14) xor d(11) xor d(10) xor d(7) xor d(6) xor d(4) xor d(3) xor d(0);
149  hmg(5) := d(31) xor d(30) xor d(28) xor d(27) xor d(25) xor d(23) xor d(21) xor d(20) xor d(18) xor d(16) xor d(14) xor d(12) xor d(10) xor d(8) xor d(6) xor d(5) xor d(3) xor d(1);
150  hmg(6) := d(31) xor d(30) xor d(29) xor d(27) xor d(26) xor d(24) xor d(21) xor d(20) xor d(19) xor d(17) xor d(14) xor d(13) xor d(10) xor d(8) xor d(7) xor d(5) xor d(4) xor d(2);
151  return hmg;
152  end hemming_l;
153  constant TTCclk_pol : std_logic := '1';
154  constant TTCdata_pol : std_logic := '1';
155  constant Coarse_Delay: std_logic_vector(3 downto 0) := x"0";
156  constant BX500: std_logic_vector(11 downto 0) := x"1f1";
157  signal ovfl_warning_SyncRegs : std_logic_vector(3 downto 0) := (others =>'0');
158  signal en_periodic : std_logic := '0';
159  signal en_burst : std_logic := '0';
160  signal NextL1A : std_logic := '0';
161  signal periodicL1A_a : std_logic := '0';
162  signal periodicL1A_b : std_logic := '0';
163  signal periodicL1A_bp : std_logic := '0';
164  signal periodicL1A : std_logic := '0';
165  signal Burst_cntr : std_logic_vector(11 downto 0) := (others =>'0');
166  signal L1A_dl : std_logic := '0';
167  signal L1A_dl24 : std_logic_vector(21 downto 0) := (others =>'0');
168  signal L1A_dl99 : std_logic_vector(74 downto 0) := (others =>'0');
169  signal L1A_dl239 : std_logic_vector(139 downto 0) := (others =>'0');
170  signal random_th : std_logic_vector(31 downto 0) := (others =>'0');
171  signal lfsr : std_logic_vector(31 downto 0) := (others =>'0');
172  signal lfsr_s : std_logic_vector(31 downto 0) := (others =>'0');
173  signal rules : std_logic_vector(4 downto 0) := (others =>'0');
174  signal rule1_cntr : std_logic := '0';
175  signal rule2_cntr : std_logic_vector(1 downto 0) := (others =>'0');
176  signal rule3_cntr : std_logic_vector(1 downto 0) := (others =>'0');
177  signal OrbitCntr : std_logic_vector(15 downto 0) := (others =>'0');
178  signal BXCntr : std_logic_vector(11 downto 0) := (others =>'0');
179  signal BXCntr_b : std_logic_vector(15 downto 0) := (others =>'0');
180  signal localL1A_s_SyncRegs : std_logic_vector(3 downto 0) := (others =>'0');
181  signal localL1A_r_SyncRegs : std_logic_vector(3 downto 0) := (others =>'0');
182  signal T3_triggerSyncRegs : std_logic_vector(3 downto 0) := (others =>'0');
183  signal EvnRst_SyncRegs : std_logic_vector(3 downto 0) := (others =>'0');
184  signal OcnRst_SyncRegs : std_logic_vector(3 downto 0) := (others =>'0');
185  signal reset_SyncRegs : std_logic_vector(3 downto 0) := (others =>'0');
186  signal SendEvnRst : std_logic := '0';
187  signal SendOcnRst : std_logic := '0';
188  signal SendBC0 : std_logic := '0';
189  signal TTC_cmd_avl : std_logic := '0';
190  signal busy_l : std_logic := '0';
191  signal start_l : std_logic := '0';
192  signal stop_l : std_logic := '0';
193  signal Bcnt_l : std_logic_vector(11 downto 0) := (others => '0');
194  signal sr_l : std_logic_vector(40 downto 0) := (others => '0');
195 --signal TTC_cmd : std_logic_vector(3 downto 0) := (others => '0');
196  signal clkfb : std_logic := '0';
197  signal clk160_dcm : std_logic := '0';
198  signal clk200_dcm : std_logic := '0';
199  signal sys_lock_n : std_logic := '0';
200  signal local_TTC_n : std_logic := '0';
201  signal CDR_bad : std_logic := '0';
202  signal CDRclk_in : std_logic := '0';
203  signal PllCDRclk_in : std_logic := '0';
204  signal CDRclk_dcm : std_logic := '0';
205  signal CDRclkFB_dcm : std_logic := '0';
206  signal CDRclkFB : std_logic := '0';
207  signal CDRclk : std_logic := '0';
208  signal CDR_lock : std_logic := '0';
209  signal TTCdata : std_logic := '0';
210  signal CDRdata_in : std_logic := '0';
211  signal TTCclk_q : std_logic_vector(1 downto 0) := (others =>'0');
212  signal CDRdata : std_logic := '0';
213  signal CDRdata_q : std_logic_vector(2 downto 0) := (others =>'0');
214  signal div8 : std_logic_vector(2 downto 0) := (others =>'0');
215  signal toggle_cnt : std_logic_vector(1 downto 0) := (others =>'0');
216  signal toggle_channel : std_logic := '1';
217  signal a_channel : std_logic := '1';
218  signal L1A : std_logic := '0';
219  signal strng_length : std_logic_vector(3 downto 0) := (others =>'0');
220  signal div_rst_cnt : std_logic_vector(4 downto 0) := (others =>'0');
221  signal TTC_str : std_logic := '0';
222  signal L1Accept : std_logic := '0';
223  signal sr : std_logic_vector(12 downto 0) := (others => '0');
224  signal rec_cntr : std_logic_vector(5 downto 0) := (others => '0');
225  signal rec_cmd : std_logic := '0';
226  signal FMT : std_logic := '0';
227  signal TTC_data : std_logic_vector(2 downto 0) := (others => '0');
228  signal brcst_str : std_logic_vector(3 downto 0) := (others => '0');
229  signal brcst_data : std_logic_vector(7 downto 0) := (others => '0');
230  signal brcst_syn : std_logic_vector(4 downto 0) := (others => '0');
231  signal frame_err : std_logic := '0';
232  signal single_err : std_logic := '0';
233  signal double_err : std_logic := '0';
234  signal EvCntReset : std_logic := '0';
235  signal BCntReset : std_logic := '0';
236  signal SinErrStr : std_logic := '0';
237  signal DbErrStr : std_logic := '0';
238  signal BrcstStr : std_logic := '0';
239  signal EvCntRes : std_logic := '0';
240  signal BCntRes : std_logic := '0';
241  signal OcRes : std_logic := '0';
242  signal ReSync : std_logic := '0';
243  signal BrcstCmd : std_logic_vector(3 downto 0) := (others => '0');
244  signal Brcst : std_logic_vector(7 downto 0) := (others => '0');
245  signal TTC_tune_cnt : std_logic_vector(7 downto 0) := (others =>'0');
246  signal ttc_brcst_i : std_logic_vector(3 downto 0) := (others => '0');
247  signal ttc_sinerrstr : std_logic := '0';
248  signal ttc_dberrstr : std_logic := '0';
249  signal ttc_l1accept : std_logic := '0';
250  signal ttc_evcntres : std_logic := '0';
251  signal ttc_l1accept_dl : std_logic := '0';
252  signal ttc_bcntres_dl : std_logic := '0';
253  signal ttc_OCres_dl : std_logic := '0';
254  signal ttc_soft_reset_i : std_logic := '0';
255  signal dl_a : std_logic_vector(3 downto 0) := (others => '0');
256  signal dl_b : std_logic_vector(3 downto 0) := (others => '0');
257  signal bcnt : std_logic_vector(11 downto 0) := (others => '0');
258  signal oc : std_logic_vector(31 downto 0) := (others => '0');
259  signal en_bcnt_res : std_logic := '0';
260  signal en_bcnt_err : std_logic_vector(1 downto 0) := (others => '0');
261  signal brcst_GapTrig : std_logic := '0';
262  signal brcst_GapPed : std_logic := '0';
263  signal brcst_GapLaser : std_logic := '0';
264  signal rst_bcnt : std_logic := '0';
265  signal cal_win : std_logic := '0';
266  signal Laser_TO : std_logic_vector(13 downto 0) := (others => '0');
267  signal bcn_offs1 : std_logic_vector(11 downto 0) := (others => '0');
268  signal cal_type : std_logic_vector(3 downto 0) := (others => '0');
269  signal rst_cnt : std_logic_vector(1 downto 0) := (others => '0');
270  signal event_number_avl_i : std_logic := '0';
271  signal dec_rate_cntr : std_logic := '0';
272  signal rate_div : std_logic_vector(7 downto 0) := (others => '0');
273  signal rate_cntr : std_logic_vector(5 downto 0) := (others => '0');
274  signal ttc_sync_wa : std_logic_vector(1 downto 0) := (others => '0');
275  signal ttc_sync_ra : std_logic_vector(1 downto 0) := (others => '0');
276  signal ttc_sync_din : std_logic_vector(11 downto 0) := (others => '0');
277  signal ttc_sync_dout : std_logic_vector(11 downto 0) := (others => '0');
278  signal ttc_sync_wa1_SyncRegs : std_logic_vector(1 downto 0) := (others => '0');
279  signal ttc_sync_wa0_SyncRegs : std_logic_vector(1 downto 0) := (others => '0');
280  signal ttc_sync_do : std_logic_vector(11 downto 0) := (others => '0');
281  signal ttc_sync_do_val : std_logic := '0';
282  type array4X16 is array(0 to 3) of std_logic_vector(15 downto 0);
283  type array4X32 is array(0 to 3) of std_logic_vector(31 downto 0);
284  signal ttc_cmd : array4x32 := (others => (others => '0'));
285  signal ttc_cmd_cfg : array4x32 := (others => (others => '0'));
286  signal OcPrescal : array4x16 := (others => x"ffff");
287  signal SendTTC_cmd : std_logic_vector(3 downto 0) := (others => '0');
288  signal TTC_cmd_done : std_logic_vector(3 downto 0) := (others => '0');
289  signal ld_sr_l : std_logic := '0';
290  signal SendFMT : std_logic := '0';
291  signal SendCmdData : std_logic_vector(31 downto 0) := (others => '0');
292  signal hmg_s : std_logic_vector(4 downto 0) := (others => '0');
293  signal hmg_l : std_logic_vector(6 downto 0) := (others => '0');
294  signal cmd_cntr : std_logic_vector(5 downto 0) := (others => '0');
295  signal bcnt_cmd : std_logic_vector(11 downto 0) := x"000";
296  signal gap_begin : std_logic_vector(11 downto 0) := x"000";
297  signal gap_end : std_logic_vector(11 downto 0) := x"000";
298  signal gap_beginp : std_logic_vector(11 downto 0) := x"000";
299  signal gap_endp : std_logic_vector(11 downto 0) := x"000";
300  signal nongap_size : std_logic_vector(11 downto 0) := x"000";
301  signal in_gap : std_logic := '0';
302  signal random_cnt : std_logic_vector(5 downto 0) := (others => '0');
303  signal OcNresetCmd : std_logic_vector(15 downto 0) := x"1728";
304  signal ReSyncCmd : std_logic_vector(15 downto 0) := x"1748";
305  signal DBCmd : std_logic_vector(15 downto 0) := x"1768";
306  signal second : std_logic_vector(25 downto 0) := (others => '0');
307  signal L1A_rate : std_logic_vector(24 downto 0) := (others => '0');
308  signal L1A_rate_q : std_logic_vector(24 downto 0) := (others => '0');
309  signal L1A_cntr : std_logic_vector(24 downto 0) := (others => '0');
310  signal L1AToggle : std_logic := '0';
311  signal L1AToggleSync : std_logic_vector(3 downto 0) := (others => '0');
312  signal DB : std_logic := '0';
313  signal DB_cmd_i : std_logic := '0';
314  signal DBSync : std_logic_vector(3 downto 0) := (others => '0');
315 begin
316 -- new code starts here
317  ttc_soft_reset <= ttc_soft_reset_i;
318  localL1A_periodic <= en_periodic;
319  CDRclk_out <= CDRclk;
320  TTC_strobe <= TTC_str;
321  CDR_bad <= TTC_LOL or TTC_LOS;
322  DB_cmd_out <= DB_cmd_i;
323  i_CDRclk_in: ibufgds generic map(DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25") port map(i => CDRclk_p, ib => CDRclk_n , o => CDRclk_in);
324  i_MMCM_CDRclk : PLLE2_BASE
325 -- generic map(CLKFBOUT_MULT => 10,CLKOUT0_DIVIDE => 8,CLKOUT1_DIVIDE => 10,CLKIN1_PERIOD => 6.237,CLKOUT1_DUTY_CYCLE => 0.33)
326  generic map(CLKFBOUT_MULT => 10,CLKOUT0_DIVIDE => 8,CLKIN1_PERIOD => 6.237)
327  port map (
328  CLKOUT0 => clk200_dcm,
329 -- CLKOUT1 => CDRclk_dcm,
330  -- Feedback Clocks: 1-bit (each) Clock feedback ports
331 -- CLKFBOUT => CDRclkFB_dcm, -- 1-bit Feedback clock output
332  CLKFBOUT => CDRclk_dcm, -- 1-bit Feedback clock output
333  -- Clock Inputs: 1-bit (each) Clock inputs
334  CLKIN1 => CDRclk_in, -- 1-bit Clock input
335  -- Control Ports: 1-bit (each) MMCM control ports
336  PWRDWN => '0', -- 1-bit Power-down input
337  RST => CDR_bad, -- 1-bit Reset input
338  LOCKED => CDR_lock, -- 1-bit LOCK output
339  -- Feedback Clocks: 1-bit (each) Clock feedback ports
340  CLKFBIN => CDRclk -- 1-bit Feedback clock input
341  );
342  i_CDRclk_buf: bufg port map(i => CDRclk_dcm, o => CDRclk );
343 --i_CDRclkFB_buf: bufg port map(i => CDRclkFB_dcm, o => CDRclkFB);
344  i_MMCM_clk_160 : MMCME2_BASE
345  generic map(CLKFBOUT_MULT_F => 4.0,CLKOUT0_DIVIDE_F => 5.0,CLKIN1_PERIOD => 5.0)
346  port map (
347  -- Feedback Clocks: 1-bit (each) Clock feedback ports
348  CLKFBOUT => clkfb, -- 1-bit Feedback clock output
349  CLKOUT0 => clk160_dcm, -- 1-bit CLKOUT0 output 400MHz
350  -- Clock Inputs: 1-bit (each) Clock inputs
351  CLKIN1 => refclk, -- 1-bit Clock input
352  -- Control Ports: 1-bit (each) MMCM control ports
353  PWRDWN => '0', -- 1-bit Power-down input
354  RST => sys_lock_n, -- 1-bit Reset input
355  LOCKED => open, -- 1-bit LOCK output
356  -- Feedback Clocks: 1-bit (each) Clock feedback ports
357  CLKFBIN => clkfb -- 1-bit Feedback clock input
358  );
359  sys_lock_n <= not sys_lock;
360  i_TTS_clk_buf : BUFGCTRL
361  generic map (
362  INIT_OUT => 0, -- Initial value of BUFGCTRL output (0/1)
363  PRESELECT_I0 => FALSE, -- BUFGCTRL output uses I0 input (TRUE/FALSE)
364  PRESELECT_I1 => FALSE -- BUFGCTRL output uses I1 input (TRUE/FALSE)
365  )
366  port map (
367  O => TTS_clk, -- 1-bit output: Clock Output pin
368  CE0 => '1', -- 1-bit input: Clock enable input for I0 input
369  CE1 => '1', -- 1-bit input: Clock enable input for I1 input
370  I0 => clk200_dcm, -- 1-bit input: Primary clock input
371  I1 => clk160_dcm, -- 1-bit input: Secondary clock input
372  IGNORE0 => '1', -- 1-bit input: Clock ignore input for I0
373  IGNORE1 => '1', -- 1-bit input: Clock ignore input for I1
374  S0 => local_TTC_n, -- 1-bit input: Clock select input for I0
375  S1 => local_TTC -- 1-bit input: Clock select input for I1
376  );
377  local_TTC_n <= not local_TTC;
378  i_CDRdata: ibufds generic map(DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25") port map(i => CDRdata_p, ib => CDRdata_n , o => CDRdata);
379  i_TTCdata: obufds generic map(IOSTANDARD => "LVDS_25") port map(o => TTCdata_p, ob => TTCdata_n , i => TTCdata);
380  DIV4 <= '1';
381  process(CDRclk)
382  begin
383  if(CDRclk'event and CDRclk = '0')then
384  CDRdata_q(0) <= CDRdata;
385  end if;
386  end process;
387  process(CDRclk)
388  begin
389  if(CDRclk'event and CDRclk = '1')then
390  ovfl_warning_SyncRegs <= ovfl_warning_SyncRegs(2 downto 0) & ovfl_warning;
391 -- CDRdata_q <= CDRdata_q(0) & CDRdata;
392  CDRdata_q(2 downto 1) <= CDRdata_q(1 downto 0);
393  if(toggle_channel = '1')then
394  if(a_channel = '1' and en_localL1A = '1')then
395  TTCdata <= TTCdata_pol xor (not ovfl_warning_SyncRegs(3) and periodicL1A);
396  elsif(a_channel = '0' and local_TTCcmd = '1')then
397  TTCdata <= TTCdata_pol xor sr_l(40);
398  else
399  TTCdata <= TTCdata_pol xor (CDRdata_q(1) xor CDRdata_q(2));
400  end if;
401  end if;
402  if(toggle_channel = '0')then
403  div8 <= div8 + 1;
404  end if;
405  if(div8 = "111" or toggle_cnt = "11")then
406  toggle_cnt <= (others => '0');
407 -- TTC signal should always toggle at a/b channel crossing, otherwise toggle_channel is at wrong position
408  elsif(CDRdata_q(1) = CDRdata_q(2) and toggle_channel = '0')then
409  toggle_cnt <= toggle_cnt + 1;
410  end if;
411  if(toggle_cnt /= "11")then
412  toggle_channel <= not toggle_channel;
413  end if;
414 -- if illegal L1A='1'/data = '0' sequence reaches 11, resync the phase
415  if(toggle_channel = '1' and (a_channel = '1' or strng_length /= x"b"))then
416  a_channel <= not a_channel;
417  end if;
418  if(a_channel = '1' and toggle_channel = '1')then
419  if(CDRdata_q(1) /= CDRdata_q(2))then
420  L1A <= '1';
421  else
422  L1A <= '0';
423  end if;
424  end if;
425  if(a_channel = '0' and toggle_channel = '1')then
426 -- L1A = '1' and b_channel data = '0' can not repeat 11 times
427  if(L1A = '0' or CDRdata_q(1) /= CDRdata_q(2) or strng_length = x"b")then
428  strng_length <= (others => '0');
429  else
430  strng_length <= strng_length + 1;
431  end if;
432  end if;
433  end if;
434  end process;
435 -- To get the right phase of TTC clock, we do not directly look at the divided clock signal.
436 -- Instead, phase of the divided TTC clock is determined by the time of release of the signal div_nrst
437  process(CDRclk,CDR_lock)
438  begin
439  if(CDR_lock = '0')then
440  div_nrst <= '0';
441  div_rst_cnt <= (others => '0');
442  elsif(CDRclk'event and CDRclk = '1')then
443  if(TTC_str = '1')then
444  div_nrst <= div_rst_cnt(4);
445  end if;
446  if(toggle_cnt = "11" or strng_length = x"b")then
447  div_rst_cnt <= (others => '0');
448  elsif(TTC_str = '1' and div_rst_cnt(4) = '0')then
449  div_rst_cnt <= div_rst_cnt + 1;
450  end if;
451  end if;
452  end process;
453  process(CDRclk,reset)
454  begin
455  if(reset = '1')then
456  TTC_tune_cnt <= (others => '0');
457  OcPrescal <= (others => x"ffff");
458  SendTTC_cmd <= x"0";
459  elsif(CDRclk'event and CDRclk = '1')then
460  if(toggle_cnt = "11" or strng_length = x"b")then
461  TTC_tune_cnt <= TTC_tune_cnt + 1;
462  end if;
463  if(TTC_str = '1')then
464  for i in 0 to 3 loop
465  if(TTC_cmd_done(i) = '1')then
466  SendTTC_cmd(i) <= '0';
467  elsif(single_TTCcmd = '1' and TTC_cmd_cfg(i)(30) = '1')then
468  SendTTC_cmd(i) <= '1';
469  elsif(Bcnt_l = x"002" and TTC_cmd_cfg(i)(29) = '1')then
470  if(OcPrescal(i) = x"ffff")then
471  OcPrescal(i) <= not TTC_cmd_cfg(i)(15 downto 0);
472  SendTTC_cmd(i) <= TTC_cmd_cfg(i)(29);
473  else
474  OcPrescal(i) <= OcPrescal(i) + 1;
475  end if;
476  end if;
477  end loop;
478  end if;
479  end if;
480  end process;
481  i_SCRAMBLER: SCRAMBLER PORT MAP(
482  UNSCRAMBLED_DATA_IN => lfsr,
483  SCRAMBLED_DATA_OUT => lfsr_s,
484  DATA_VALID_IN => TTC_str,
485  USER_CLK => CDRclk,
486  SYSTEM_RESET => reset_SyncRegs (3)
487  );
488  process(CDRclk)
489  begin
490  if(CDRclk'event and CDRclk = '1')then
491 -- 2 1 3 2 1 4 1 3 6 1 1 13 8 5 1 1 1
492 --TTC_debug <= "000000000" & CDRdata_q & toggle_channel & div8 & toggle_cnt & a_channel & strng_length & TTC_str & TTC_data & rec_cntr & rec_cmd & FMT & sr & brcst_data & brcst_syn & frame_err & single_err & double_err;
493  if(toggle_channel = '1' and a_channel = '0')then
494  TTC_data(2) <= CDRdata_q(1) xor CDRdata_q(2);
495  end if;
496  TTC_str <= not toggle_channel and a_channel;
497  if(TTC_str = '1')then
498 -- locally generated TTC commands
499  reset_SyncRegs <= reset_SyncRegs(2 downto 0) & reset;
500  EvnRst_SyncRegs <= EvnRst_SyncRegs(2 downto 0) & EvnRst_l;
501  OcnRst_SyncRegs <= OcnRst_SyncRegs(2 downto 0) & OcnRst_l;
502  if(Bcnt_l = x"deb")then
503  Bcnt_l <= (others => '0');
504  else
505  Bcnt_l <= Bcnt_l + 1;
506  end if;
507  if(Bcnt_l = x"de8")then
508  Bcnt_cmd <= (others => '0');
509  else
510  Bcnt_cmd <= Bcnt_cmd + 1;
511  end if;
512  if(busy_l = '0' and SendBC0 = '1')then
513  busy_l <= '1';
514  ld_sr_l <= '1';
515  SendFMT <= '0';
516  SendCmdData <= x"0000000" & "00" & SendEvnRst & SendBC0;
517  elsif(busy_l = '0' and SendOcnRst = '1' and Bcnt_l(9) = '1')then -- this keeps OcNreset away from BC0
518  busy_l <= '1';
519  ld_sr_l <= '1';
520  SendFMT <= '0';
521 -- SendCmdData <= x"000000" & "00" & SendOcnRst & '0' & SendOcnRst & '0' & SendEvnRst & SendBC0;
522  SendCmdData <= x"000000" & OcNresetCmd(7 downto 2) & '0' & SendBC0;
523  elsif(busy_l = '0')then
524  for i in 0 to 3 loop
525  if(SendTTC_cmd(i) = '1' and Bcnt_cmd = TTC_cmd_cfg(i)(27 downto 16))then
526  busy_l <= '1';
527  ld_sr_l <= '1';
528  SendFMT <= TTC_cmd_cfg(i)(28);
529  SendCmdData <= TTC_cmd(i);
530  TTC_cmd_done(i) <= '1';
531  end if;
532  end loop;
533  else
534  if(stop_l = '1')then
535  busy_l <= '0';
536  end if;
537  ld_sr_l <= '0';
538  TTC_cmd_done <= (others => '0');
539  end if;
540  if(busy_l = '0')then
541  if(SendFMT = '0')then
542  cmd_cntr <= "110010";
543  else
544  cmd_cntr <= "011000";
545  end if;
546  else
547  cmd_cntr <= cmd_cntr + 1;
548  end if;
549  if(cmd_cntr = "111111")then
550  stop_l <= '1';
551  else
552  stop_l <= '0';
553  end if;
554  if(Bcnt_l = x"dd2")then
555  SendBC0 <= '1';
556  else
557  SendBC0 <= '0';
558  end if;
559  if(reset_SyncRegs(3 downto 2) = "10" or EvnRst_SyncRegs(3 downto 2) = "01")then
560  SendEvnRst <= '1';
561  elsif(busy_l = '0' and SendBC0 = '1')then
562  SendEvnRst <= '0';
563  end if;
564 -- if(reset_SyncRegs(3 downto 2) = "10" or OcnRst_SyncRegs(3 downto 2) = "01")then
565  if(OcnRst_SyncRegs(3 downto 2) = "01")then
566  SendOcnRst <= '1';
567 -- elsif(busy_l = '0' and SendBC0 = '1')then
568  elsif(busy_l = '0' and Bcnt_l(9) = '1')then -- this keeps OcNreset away from BC0
569  SendOcnRst <= '0';
570  end if;
571  if(ld_sr_l = '1')then
572  start_l <= '1';
573  if(SendFMT = '0')then
574  sr_l(40 downto 26) <= "00" & SendCmdData(7 downto 0) & hemming_s(SendCmdData(7 downto 0));
575  sr_l(25 downto 0) <= (others => '1');
576  else
577  sr_l <= "01" & SendCmdData & hemming_l(SendCmdData);
578  end if;
579  else
580  start_l <= '0';
581  sr_l <= sr_l(39 downto 0) & '1';
582  end if;
583 -- locally generated TTC commands
584  localL1A_s_SyncRegs <= localL1A_s_SyncRegs(2 downto 0) & localL1A_s;
585  localL1A_r_SyncRegs <= localL1A_r_SyncRegs(2 downto 0) & localL1A_r;
586  T3_triggerSyncRegs <= T3_triggerSyncRegs(2 downto 0) & T3_trigger;
587  BC0 <= BCntRes;
588 -- TTC_data(1) <= TTC_data(2) or not div_rst_cnt(4);
589  if(div_rst_cnt(4) = '0')then
590  TTC_data(0) <= '0';
591  TTC_data(1) <= '1';
592  elsif(en_localL1A = '0')then
593  TTC_data(0) <= CDRdata_q(1) xor CDRdata_q(2);
594  TTC_data(1) <= TTC_data(2);
595  else
596  TTC_data(0) <= not ovfl_warning_SyncRegs(3) and periodicL1A;
597  TTC_data(1) <= sr_l(40);
598  end if;
599  if(rec_cmd = '0')then
600  rec_cntr <= (others => '0');
601  else
602  rec_cntr <= rec_cntr + 1;
603  end if;
604  if(div_rst_cnt(4) = '0' or rec_cntr(5 downto 3) = "101" or (FMT = '0' and rec_cntr(3 downto 0) = x"d"))then
605  rec_cmd <= '0';
606  elsif(TTC_data(1) = '0')then
607  rec_cmd <= '1';
608  end if;
609  if(or_reduce(rec_cntr) = '0')then
610  FMT <= TTC_data(1);
611  end if;
612  sr <= sr(11 downto 0) & TTC_data(1);
613  if(FMT = '0' and rec_cntr(3 downto 0) = x"e")then
614  brcst_data <= sr(12 downto 5);
615  brcst_syn(0) <= sr(0) xor sr(5) xor sr(6) xor sr(7) xor sr(8);
616  brcst_syn(1) <= sr(1) xor sr(5) xor sr(9) xor sr(10) xor sr(11);
617  brcst_syn(2) <= sr(2) xor sr(6) xor sr(7) xor sr(9) xor sr(10) xor sr(12);
618  brcst_syn(3) <= sr(3) xor sr(6) xor sr(8) xor sr(9) xor sr(11) xor sr(12);
619  brcst_syn(4) <= xor_reduce(sr);
620  frame_err <= not TTC_data(1);
621  brcst_str(0) <= '1';
622  else
623  brcst_str(0) <= '0';
624  end if;
625  single_err <= xor_reduce(brcst_syn) and not frame_err;
626  if((or_reduce(brcst_syn) = '1' and xor_reduce(brcst_syn) = '0') or frame_err = '1')then
627  double_err <= '1';
628  else
629  double_err <= '0';
630  end if;
631  SinErrStr <= single_err and brcst_str(1);
632  DbErrStr <= double_err and brcst_str(1);
633  brcst_str(2) <= brcst_str(1) and not double_err;
634  if(brcst_syn(3 downto 0) = x"c")then
635  Brcst(7) <= not brcst_data(7);
636  else
637  Brcst(7) <= brcst_data(7);
638  end if;
639  if(brcst_syn(3 downto 0) = x"a")then
640  Brcst(6) <= not brcst_data(6);
641  else
642  Brcst(6) <= brcst_data(6);
643  end if;
644  if(brcst_syn(3 downto 0) = x"6")then
645  Brcst(5) <= not brcst_data(5);
646  else
647  Brcst(5) <= brcst_data(5);
648  end if;
649  if(brcst_syn(3 downto 0) = x"e")then
650  Brcst(4) <= not brcst_data(4);
651  else
652  Brcst(4) <= brcst_data(4);
653  end if;
654  if(brcst_syn(3 downto 0) = x"9")then
655  Brcst(3) <= not brcst_data(3);
656  else
657  Brcst(3) <= brcst_data(3);
658  end if;
659  if(brcst_syn(3 downto 0) = x"5")then
660  Brcst(2) <= not brcst_data(2);
661  else
662  Brcst(2) <= brcst_data(2);
663  end if;
664  if(brcst_syn(3 downto 0) = x"d")then
665  Brcst(1) <= not brcst_data(1);
666  else
667  Brcst(1) <= brcst_data(1);
668  end if;
669  if(brcst_syn(3 downto 0) = x"3")then
670  Brcst(0) <= not brcst_data(0);
671  else
672  Brcst(0) <= brcst_data(0);
673  end if;
674  if(en_burst = '0' or reset = '1')then
675  Burst_cntr <= LocalL1A_cfg(27 downto 16);
676  elsif(periodicL1A = '1')then
677  Burst_cntr <= Burst_cntr - 1;
678  end if;
679  if(en_localL1A = '0' or reset = '1')then
680  en_periodic <= '0';
681  elsif(localL1A_s_SyncRegs(3 downto 2) = "01")then
682  en_periodic <= '1';
683  elsif(localL1A_r_SyncRegs(3 downto 2) = "01")then
684  en_periodic <= '0';
685  end if;
686  if(en_localL1A = '0' or en_periodic = '1')then
687  en_burst <= '0';
688  elsif(localL1A_r_SyncRegs(3 downto 2) = "01")then
689  en_burst <= '1';
690  elsif(periodicL1A = '1' and or_reduce(Burst_cntr) = '0')then
691  en_burst <= '0';
692  end if;
693  if(BCntRes = '1')then
694  BXCntr <= (others => '0');
695  else
696  BXCntr <= BXCntr + 1;
697  end if;
698  if(en_periodic = '0' and en_burst = '0')then
699  BXCntr_b <= LocalL1A_cfg(15 downto 0);
700  elsif(BXCntr_b = LocalL1A_cfg(15 downto 0) or LocalL1A_cfg(31 downto 30) /= "10")then
701  BXCntr_b <= (others => '0');
702  else
703  BXCntr_b <= BXCntr_b + 1;
704  end if;
705  if(BXCntr_b = LocalL1A_cfg(15 downto 0) and LocalL1A_cfg(31 downto 30) = "10" and (en_periodic = '1' or en_burst = '1'))then
706  periodicL1A_a <= '1';
707  else
708  periodicL1A_a <= '0';
709  end if;
710  if(random_th > lfsr_s and LocalL1A_cfg(31 downto 30) = "11" and (en_periodic = '1' or en_burst = '1'))then
711  periodicL1A_b <= '1';
712  else
713  periodicL1A_b <= '0';
714  end if;
715  if(reset_SyncRegs(3) = '1' or in_gap = '1')then
716  random_cnt <= (others => '0');
717  elsif(and_reduce(random_cnt) = '0' and periodicL1A_b = '1' and (and_reduce(rules) = '0' or or_reduce(random_cnt) = '0'))then
718  random_cnt <= random_cnt + 1;
719  elsif(or_reduce(random_cnt) = '1' and periodicL1A_b = '0' and and_reduce(rules) = '1')then
720  random_cnt <= random_cnt - 1;
721  end if;
722  if(en_periodic = '0' and en_burst = '0')then
723  orbitCntr <= LocalL1A_cfg(15 downto 0);
724  elsif(BCntRes = '1')then
725  if(NextL1A = '1' or LocalL1A_cfg(31) = '1')then
726  orbitCntr <= (others => '0');
727  else
728  orbitCntr <= orbitCntr + 1;
729  end if;
730  end if;
731  if(orbitCntr = LocalL1A_cfg(15 downto 0) and LocalL1A_cfg(31) = '0')then
732  NextL1A <= '1';
733  else
734  NextL1A <= '0';
735  end if;
736  if(gap_beginp = gap_endp or BXCntr = gap_endp)then
737  in_gap <= '0';
738  elsif(BXCntr = gap_beginp)then
739  in_gap <= '1';
740  end if;
741 -- if(T3_triggerSyncRegs(3 downto 2) = "01" or (HCAL_trigger = '1' and en_localL1A = '1'))then
742  if(T3_triggerSyncRegs(3 downto 2) = "01")then
743  periodicL1A <= '1';
744  elsif(en_periodic = '0' and en_burst = '0')then
745  periodicL1A <= '0';
746 -- elsif(((BXCntr = BX500 and NextL1A = '1') or periodicL1A_a = '1' or periodicL1A_bp = '1') and and_reduce(rules) = '1')then
747  elsif(((BXCntr = BX500 and NextL1A = '1') or periodicL1A_a = '1' or periodicL1A_bp = '1' or (HCAL_trigger = '1' and en_localL1A = '1')) and and_reduce(rules) = '1')then
748  periodicL1A <= '1';
749  else
750  periodicL1A <= '0';
751  end if;
752  L1A_dl <= periodicL1A;
753  if(L1A_dl = '1' or (en_periodic = '0' and en_burst = '0'))then
754  rules(0) <= '1';
755 -- elsif((periodicL1A_a = '1' or periodicL1A_bp = '1') and and_reduce(rules) = '1')then
756  elsif((periodicL1A_a = '1' or periodicL1A_bp = '1' or (HCAL_trigger = '1' and en_localL1A = '1')) and and_reduce(rules) = '1')then
757  rules(0) <= '0';
758  end if;
759  rule1_cntr <= rule1_cntr xor periodicL1A xor L1A_dl24(21);
760  if(L1A_dl24(21) = '1' or (en_periodic = '0' and en_burst = '0') or LocalL1A_cfg(29 downto 28) = "11")then
761  rules(1) <= '1';
762 -- elsif(((periodicL1A_a = '1' or periodicL1A_bp = '1') and and_reduce(rules) = '1') and rule1_cntr = '1')then
763  elsif(((periodicL1A_a = '1' or periodicL1A_bp = '1' or (HCAL_trigger = '1' and en_localL1A = '1')) and and_reduce(rules) = '1') and rule1_cntr = '1')then
764  rules(1) <= '0';
765  end if;
766  if(periodicL1A = '1' and L1A_dl99(74) = '0')then
767  rule2_cntr(1) <= rule2_cntr(1) xor rule2_cntr(0);
768  rule2_cntr(0) <= not rule2_cntr(0);
769  elsif(periodicL1A = '0' and L1A_dl99(74) = '1')then
770  rule2_cntr(1) <= rule2_cntr(1) xnor rule2_cntr(0);
771  rule2_cntr(0) <= not rule2_cntr(0);
772  end if;
773  if(L1A_dl99(74) = '1' or (en_periodic = '0' and en_burst = '0') or LocalL1A_cfg(28) = '1')then
774  rules(2) <= '1';
775 -- elsif(((periodicL1A_a = '1' or periodicL1A_bp = '1') and and_reduce(rules) = '1') and rule2_cntr(1) = '1')then
776  elsif(((periodicL1A_a = '1' or periodicL1A_bp = '1' or (HCAL_trigger = '1' and en_localL1A = '1')) and and_reduce(rules) = '1') and rule2_cntr(1) = '1')then
777  rules(2) <= '0';
778  end if;
779  if(periodicL1A = '1' and L1A_dl239(139) = '0')then
780  rule3_cntr(1) <= rule3_cntr(1) xor rule3_cntr(0);
781  rule3_cntr(0) <= not rule3_cntr(0);
782  elsif(periodicL1A = '0' and L1A_dl239(139) = '1')then
783  rule3_cntr(1) <= rule3_cntr(1) xnor rule3_cntr(0);
784  rule3_cntr(0) <= not rule3_cntr(0);
785  end if;
786  if(L1A_dl239(139) = '1' or (en_periodic = '0' and en_burst = '0') or LocalL1A_cfg(29 downto 28) /= "00")then
787  rules(3) <= '1';
788 -- elsif(((periodicL1A_a = '1' or periodicL1A_bp = '1') and and_reduce(rules) = '1') and rule3_cntr = "11")then
789  elsif(((periodicL1A_a = '1' or periodicL1A_bp = '1' or (HCAL_trigger = '1' and en_localL1A = '1')) and and_reduce(rules) = '1') and rule3_cntr = "11")then
790  rules(3) <= '0';
791  end if;
792  rules(4) <= not in_gap;
793  L1A_dl24 <= L1A_dl24(20 downto 0) & L1A_dl;
794  L1A_dl99 <= L1A_dl99(73 downto 0) & L1A_dl24(21);
795  L1A_dl239 <= L1A_dl239(138 downto 0) & L1A_dl99(74);
796  BCntRes <= brcst_str(3) and Brcst(0);
797  EvCntRes <= brcst_str(3) and Brcst(1);
798  BrcstStr <= brcst_str(3) and or_reduce(Brcst);
799  OcRes <= brcst_str(3) and and_reduce((Brcst xnor OcNresetCmd(7 downto 0)) or OcNresetCmd(15 downto 8));
800  ReSync <= brcst_str(3) and and_reduce((Brcst xnor ReSyncCmd(7 downto 0)) or ReSyncCmd(15 downto 8));
801  DB <= DB xor (brcst_str(3) and and_reduce((Brcst xnor DBCmd(7 downto 0)) or DBCmd(15 downto 8)));
802  if(brcst_str(3) = '1')then
803  BrcstCmd <= Brcst(7 downto 5) & Brcst(3);
804  end if;
805  if(LocalL1A_cfg(31 downto 30) /= "11")then
806  lfsr <= (others => '0');
807  else
808  lfsr <= lfsr(30 downto 0) & not(lfsr(31) xor lfsr(21) xor lfsr(1) xor lfsr(0));
809  end if;
810  if(L1Accept = '1')then
811  L1AToggle <= not L1AToggle;
812  end if;
813 -- if(second(26) = '1')then
814 -- L1A_cntr <= (others => '0');
815 -- second <= "001100111000110000001010011";
816 -- L1A_rate <= L1A_cntr;
817 -- else
818 -- if(L1Accept = '1')then
819 -- L1A_cntr <= L1A_cntr + 1;
820 -- end if;
821 -- second <= second + 1;
822 -- end if;
823  end if;
824  end if;
825  end process;
826  periodicL1A_bp <= or_reduce(random_cnt);
827 --rules(4) <= not in_gap;
828  i_Threshold: Threshold PORT MAP(
829  clk => ipb_clk,
830  din => LocalL1A_cfg(15 downto 0),
831  nongap_size => nongap_size,
832  dout => random_th
833  );
834  nongap_size <= gap_begin - gap_end when gap_end < gap_begin else gap_begin - gap_end + x"dec";
835  i_L1Accept : SRL16E
836  port map (
837  Q => L1Accept, -- SRL data output
838  A0 => Coarse_Delay(0), -- Select[0] input
839  A1 => Coarse_Delay(1), -- Select[1] input
840  A2 => Coarse_Delay(2), -- Select[2] input
841  A3 => Coarse_Delay(3), -- Select[3] input
842  CE => TTC_str, -- Clock enable input
843  CLK => CDRclk, -- Clock input
844  D => TTC_data(0) -- SRL data input
845  );
846  i_brcst_str1 : SRL16E
847  port map (
848  Q => brcst_str(1), -- SRL data output
849  A0 => '1', -- Select[0] input
850  A1 => '0', -- Select[1] input
851  A2 => '0', -- Select[2] input
852  A3 => '0', -- Select[3] input
853  CE => TTC_str, -- Clock enable input
854  CLK => CDRclk, -- Clock input
855  D => brcst_str(0) -- SRL data input
856  );
857  i_brcst_str3 : SRL16E
858  port map (
859  Q => brcst_str(3), -- SRL data output
860  A0 => Coarse_Delay(0), -- Select[0] input
861  A1 => Coarse_Delay(1), -- Select[1] input
862  A2 => Coarse_Delay(2), -- Select[2] input
863  A3 => Coarse_Delay(3), -- Select[3] input
864  CE => TTC_str, -- Clock enable input
865  CLK => CDRclk, -- Clock input
866  D => brcst_str(2) -- SRL data input
867  );
868 -- old ttc_if code
869  event_number_avl <= event_number_avl_i;
870  inc_l1ac <= ttc_l1accept_dl;
871  inc_serr <= ttc_sinerrstr;
872  inc_derr <= ttc_dberrstr;
873  ttc_ready <= CDR_lock;
874  TTC_brcst <= ttc_brcst_i;
875  CalType <= cal_type;
876  process(CDRclk)
877  begin
878  if(CDRclk'event and CDRclk = '1')then
879 -- ttc_sync_din(10) <= BrcstStr and not Brcst(7) and not Brcst(6) and Brcst(5) and Brcst(3);
880  if(TTC_str = '1')then
881 -- if(and_reduce((Brcst xnor OcNresetCmd(7 downto 0)) or OcNresetCmd(15 downto 8)) = '1' and BrcstStr = '1')then
882 -- ttc_sync_din(10) <= '1';
883 -- else
884 -- ttc_sync_din(10) <= '0';
885 -- end if;
886  ttc_sync_din(11) <= ReSync;
887  ttc_sync_din(10) <= OcRes;
888  ttc_sync_din(9) <= SinErrStr;
889  ttc_sync_din(8) <= DbErrStr;
890  ttc_sync_din(7) <= L1Accept;
891  ttc_sync_din(6) <= BCntRes;
892  ttc_sync_din(5) <= EvCntRes;
893  ttc_sync_din(4) <= BrcstStr;
894  ttc_sync_din(3 downto 0) <= BrcstCmd;
895  ttc_sync_wa(1 downto 0) <= ttc_sync_wa(0) & not ttc_sync_wa(1);
896  end if;
897  end if;
898  end process;
899  g_ttc_sync : for i in 0 to 11 generate
900  i_ttc_sync : RAM32X1D
901  port map (
902  DPO => ttc_sync_dout(i), -- Read-only 1-bit data output
903  A0 => ttc_sync_wa(0), -- R/W address[0] input bit
904  A1 => ttc_sync_wa(1), -- R/W address[1] input bit
905  A2 => '0', -- R/W address[2] input bit
906  A3 => '0', -- R/W address[3] input bit
907  A4 => '0', -- R/W address[4] input bit
908  D => ttc_sync_din(i), -- Write 1-bit data input
909  DPRA0 => ttc_sync_ra (0), -- Read-only address[0] input bit
910  DPRA1 => ttc_sync_ra (1), -- Read-only address[1] input bit
911  DPRA2 => '0', -- Read-only address[2] input bit
912  DPRA3 => '0', -- Read-only address[3] input bit
913  DPRA4 => '0', -- Read-only address[4] input bit
914  WCLK => CDRclk, -- Write clock input
915  WE => TTC_str -- Write enable input
916  );
917  end generate;
918  process(clk)
919  begin
920  if(clk'event and clk = '1')then
921  ttc_sync_wa1_SyncRegs <= ttc_sync_wa1_SyncRegs(0) & ttc_sync_wa(1);
922  ttc_sync_wa0_SyncRegs <= ttc_sync_wa0_SyncRegs(0) & ttc_sync_wa(0);
923  if(ttc_sync_wa1_SyncRegs(1) /= ttc_sync_ra(1) or ttc_sync_wa0_SyncRegs(1) /= ttc_sync_ra(0))then
924  ttc_sync_ra(1 downto 0) <= ttc_sync_ra(0) & not ttc_sync_ra(1);
925  ttc_sync_do_val <= '1';
926  else
927  ttc_sync_do_val <= '0';
928  end if;
929  ttc_sync_do <= ttc_sync_dout;
930  end if;
931  end process;
932  process(clk)
933  begin
934  if(clk'event and clk = '1')then
935  if(ttc_sync_do_val = '0')then
936  ttc_soft_reset_i <= '0';
937  ttc_OCres_dl <= '0';
938  ttc_sinerrstr <= '0';
939  ttc_dberrstr <= '0';
940  ttc_l1accept_dl <= '0';
941  ttc_evcnt_reset <= '0';
942  ttc_brcst_i <= x"0";
943  else
944  ttc_soft_reset_i <= ttc_sync_do(11);
945  ttc_OCres_dl <= ttc_sync_do(10);
946  ttc_sinerrstr <= ttc_sync_do(9);
947  ttc_dberrstr <= ttc_sync_do(8);
948  ttc_l1accept_dl <= ttc_sync_do(7);
949  ttc_evcnt_reset <= ttc_sync_do(5);
950  if(ttc_sync_do(4) = '1')then
951  ttc_brcst_i <= ttc_sync_do(3 downto 0);
952  else
953  ttc_brcst_i <= x"0";
954  end if;
955  end if;
956  if(ttc_sync_do_val = '1')then
957  if(IsG2 = '0')then
958  ttc_bcntres_dl <= ttc_sync_do(6);
959  else
960  ttc_bcntres_dl <= ttc_sync_do(10);
961  end if;
962  if(IsG2 = '0' and bcnt = x"dea")then
963  rst_bcnt <= '1';
964  elsif(IsG2 = '1' and bcnt = x"ffe")then
965  rst_bcnt <= '1';
966  else
967  rst_bcnt <= '0';
968  end if;
969  end if;
970  if(ttc_sync_do_val = '1')then
971  if(ttc_bcntres_dl = '1' and en_bcnt_res = '1')then
972  bcnt <= bcn_off(11 downto 0);
973  elsif(rst_bcnt = '1')then
974  bcnt <= x"000";
975  else
976  bcnt <= bcnt + 1;
977  end if;
978  end if;
979  if(ttc_OCres_dl = '1')then
980  oc <= x"0000000" & OC_off;
981  elsif(rst_bcnt = '1' and ttc_sync_do_val = '1')then
982  oc <= oc + 1;
983  end if;
984  inc_oc <= ttc_bcntres_dl;
985  if(bcnt = cal_win_low and en_cal_win = '1')then
986  cal_win <= '1';
987  elsif(bcnt(5 downto 0) = cal_win_high(5 downto 0))then
988  cal_win <= '0';
989  end if;
990  if(bcn_off(11 downto 0) = x"000")then
991  bcn_offs1 <= x"deb";
992  else
993  bcn_offs1 <= bcn_off(11 downto 0) - 1;
994  end if;
995  if(reset = '1' or CDR_lock = '0')then -- modified for dsp_chip301f
996  en_bcnt_err <= "00";
997  elsif(rst_bcnt = '1' and ttc_sync_do_val = '1')then
998  en_bcnt_err <= en_bcnt_err(0) & '1';
999  end if;
1000  if(reset = '1' or IsG2 = '1')then
1001  inc_bcnterr <= '0';
1002  ttc_bcnt_err <= '0';
1003  elsif(((ttc_bcntres_dl = '1' and bcnt /= bcn_offs1) or (ttc_bcntres_dl = '0' and bcnt = bcn_offs1)) and en_bcnt_err(1) = '1')then
1004  inc_bcnterr <= '1';
1005  ttc_bcnt_err <= '1';
1006  else
1007  inc_bcnterr <= '0';
1008  end if;
1009 -- if(ttc_brcst_i = x"7" or ttc_brcst_i = x"5")then
1010 -- ttc_soft_reset <= en_brcst;
1011 -- else
1012 -- ttc_soft_reset <= '0';
1013 -- end if;
1014  if(ttc_brcst_i = x"9")then
1015  ttc_start <= en_brcst;
1016  else
1017  ttc_start <= '0';
1018  end if;
1019  if(ttc_brcst_i = x"b")then
1020  ttc_stop <= en_brcst;
1021  else
1022  ttc_stop <= '0';
1023  end if;
1024  if(ttc_brcst_i = x"4")then
1025  brcst_GapTrig <= '1';
1026  elsif(rst_bcnt = '1')then
1027  brcst_GapTrig <= '0';
1028  end if;
1029  if(ttc_brcst_i = x"6")then
1030  brcst_GapPed <= '1';
1031  elsif(rst_bcnt = '1')then
1032  brcst_GapPed <= '0';
1033  end if;
1034  if(ttc_brcst_i = x"8")then
1035  brcst_GapLaser <= '1';
1036  else
1037  brcst_GapLaser <= '0';
1038  end if;
1039  if(ttc_OCres_dl = '1')then
1040  cal_type <= x"0";
1041  elsif(brcst_GapLaser = '1')then
1042  if(Laser_TO(13) = '1')then
1043  cal_type <= x"1";
1044  elsif(cal_type /= x"f")then
1045  cal_type <= cal_type + 1;
1046  end if;
1047  end if;
1048  if(brcst_GapLaser = '1')then
1049  Laser_To <= (others => '0');
1050  elsif(Laser_TO(13) = '0' and ttc_bcntres_dl = '1')then
1051  Laser_To <= Laser_To + 1;
1052  end if;
1053  end if;
1054  end process;
1055  process(clk)
1056  begin
1057  if(clk'event and clk = '1')then
1058  if(reset = '1')then
1059  en_bcnt_res <= '1';
1060  elsif(ttc_bcntres_dl = '1' and bcn_off(12) = '1')then
1061  en_bcnt_res <= '0';
1062  end if;
1063  end if;
1064  end process;
1065  process(clk)
1066  begin
1067  if(clk'event and clk = '1')then
1068  if(reset = '1')then
1069  ttc_serr <= '0';
1070  ttc_derr <= '0';
1071  rate_div <= (others => '0');
1072  rate_cntr <= "000010";
1073  rate_OFW <= '0';
1074  else
1075  if(ttc_sinerrstr = '1')then
1076  ttc_serr <= '1';
1077  end if;
1078  if(ttc_dberrstr = '1')then
1079  ttc_derr <= '1';
1080  end if;
1081  if(ttc_sync_do_val = '1')then
1082  if(rate_div(7 downto 6) = "11" and rate_div(3) = '1')then
1083  dec_rate_cntr <= '1';
1084  rate_div <= (others => '0');
1085  else
1086  dec_rate_cntr <= '0';
1087  rate_div <= rate_div + 1;
1088  end if;
1089  if(dec_rate_cntr /= ttc_sync_do(7))then
1090  if(ttc_sync_do(7) = '1')then
1091  rate_cntr <= rate_cntr + 1;
1092  elsif(rate_cntr /= "000010")then
1093  rate_cntr <= rate_cntr - 1;
1094  end if;
1095  end if;
1096  end if;
1097  if(rate_cntr(5) = '1')then
1098  rate_OFW <= '1';
1099  elsif(rate_cntr(4) = '0')then
1100  rate_OFW <= '0';
1101  end if;
1102  end if;
1103  end if;
1104  end process;
1105  process(clk)
1106  begin
1107  if(clk'event and clk = '1')then
1108  if(reset = '1')then
1109  event_number_avl_i <= '0';
1110  else
1111  event_number_avl_i <= ttc_l1accept_dl and run;
1112  end if;
1113 -- if(en_cal_win = '0')then
1114 -- event_number(51 downto 48) <= x"0";
1115 -- event_number(44) <= '0';
1116 -- else
1117  event_number(51) <= cal_win and brcst_GapTrig and cal_type(3) and not brcst_GapPed;
1118  event_number(50) <= cal_win and brcst_GapTrig and cal_type(2) and not brcst_GapPed;
1119  event_number(49) <= cal_win and brcst_GapTrig and cal_type(1) and not brcst_GapPed;
1120  event_number(48) <= cal_win and ((brcst_GapTrig and cal_type(0)) or brcst_GapPed);
1121  event_number(44) <= cal_win and (brcst_GapTrig or brcst_GapPed);
1122 -- end if;
1123  event_number(59 downto 56) <= cal_type;
1124  event_number(55 downto 52) <= state;
1125  event_number(47) <= brcst_GapTrig;
1126  event_number(46) <= brcst_GapPed;
1127  event_number(45) <= cal_win;
1128  event_number(43 downto 0) <= oc & bcnt;
1129  end if;
1130  end process;
1131  process(clk)
1132  begin
1133  if(clk'event and clk = '1')then
1134 -- if(reset = '1' or ttc_soft_reset_i = '1')then
1135  if(reset = '1')then
1136  sync_lost <= '0';
1137  elsif(evn_fifo_full = '1' and event_number_avl_i = '1')then
1138  sync_lost <= '1';
1139  end if;
1140  end if;
1141  end process;
1142  process(ipb_clk)
1143  begin
1144  if(ipb_clk'event and ipb_clk = '1')then
1145  DBSync <= DBSync(2 downto 0) & DB;
1146  if(DBSync(3) /= DBSync(2) or DB_cmd_in = '1')then
1147  DB_cmd_i <= '1';
1148  else
1149  DB_cmd_i <= '0';
1150  end if;
1151  if(DB_cmd_i = '1')then
1152  L1A_rate_q <= L1A_rate;
1153  end if;
1154  if(ipb_strobe = '1' and ipb_write = '1' and ipb_addr(15 downto 4) = x"002" and ipb_addr(27) = '0')then
1155  case ipb_addr(3 downto 0) is
1156  when x"0" => ttc_cmd(0) <= ipb_wdata(31 downto 0);
1157  when x"1" => ttc_cmd(1) <= ipb_wdata(31 downto 0);
1158  when x"2" => ttc_cmd(2) <= ipb_wdata(31 downto 0);
1159  when x"3" => ttc_cmd(3) <= ipb_wdata(31 downto 0);
1160  when x"4" => ttc_cmd_cfg(0) <= '0' & ipb_wdata(30 downto 0);
1161  when x"5" => ttc_cmd_cfg(1) <= '0' & ipb_wdata(30 downto 0);
1162  when x"6" => ttc_cmd_cfg(2) <= '0' & ipb_wdata(30 downto 0);
1163  when x"7" => ttc_cmd_cfg(3) <= '0' & ipb_wdata(30 downto 0);
1164  when x"8" => gap_begin <= ipb_wdata(11 downto 0);
1165  when x"9" => gap_end <= ipb_wdata(11 downto 0);
1166  when x"a" => OcNresetCmd <= ipb_wdata(15 downto 0);
1167  when x"b" => ReSyncCmd <= ipb_wdata(15 downto 0);
1168  when x"d" => DBCmd <= ipb_wdata(15 downto 0);
1169  when others => NULL;
1170  end case;
1171  end if;
1172  L1AToggleSync <= L1AToggleSync(2 downto 0) & L1AToggle;
1173  if(second(25) = '1')then
1174  L1A_cntr <= (others => '0');
1175  second <= "00001000110010100110101111";
1176  L1A_rate <= L1A_cntr;
1177  else
1178  if(L1AToggleSync(3) /= L1AToggleSync(2))then
1179  L1A_cntr <= L1A_cntr + 1;
1180  end if;
1181  second <= second + 1;
1182  end if;
1183  end if;
1184  end process;
1185 --ipb_ack <= '0' when ipb_addr(27) = '1' or ipb_addr(15 downto 4) /= x"002" or ipb_write = '1' else ipb_strobe;
1186  process(ipb_addr)
1187  begin
1188  if(ipb_addr(14 downto 4) /= "00000000010")then
1189  ipb_rdata <= (others => '0');
1190  else
1191  case ipb_addr(3 downto 0) is
1192  when x"0" => ipb_rdata <= ttc_cmd(0);
1193  when x"1" => ipb_rdata <= ttc_cmd(1);
1194  when x"2" => ipb_rdata <= ttc_cmd(2);
1195  when x"3" => ipb_rdata <= ttc_cmd(3);
1196  when x"4" => ipb_rdata <= ttc_cmd_cfg(0);
1197  when x"5" => ipb_rdata <= ttc_cmd_cfg(1);
1198  when x"6" => ipb_rdata <= ttc_cmd_cfg(2);
1199  when x"7" => ipb_rdata <= ttc_cmd_cfg(3);
1200  when x"8" => ipb_rdata <= x"00000" & gap_begin;
1201  when x"9" => ipb_rdata <= x"00000" & gap_end;
1202  when x"a" => ipb_rdata <= x"0000" & OcNresetCmd;
1203  when x"b" => ipb_rdata <= x"0000" & ReSyncCmd;
1204  when x"c" =>
1205  if(ipb_addr(15) = '0')then
1206  ipb_rdata <= "0000000" & L1A_rate;
1207  else
1208  ipb_rdata <= "0000000" & L1A_rate_q;
1209  end if;
1210  when x"d" => ipb_rdata <= x"0000" & DBCmd;
1211  when others => ipb_rdata <= (others => '0');
1212  end case;
1213  end if;
1214  end process;
1215  gap_beginp <= gap_begin - 5 when gap_begin > 4 else gap_begin + x"de7";
1216  gap_endp <= gap_end - 5 when gap_end > 4 else gap_end + x"de7";
1217 end ttc_arch;
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