AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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thresholdNew.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 11:53:01 07/21/2011
6 -- Design Name:
7 -- Module Name:
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 ----------------------------------------------------------------------------------
19 library IEEE;
20 use IEEE.STD_LOGIC_1164.ALL;
21 use IEEE.STD_LOGIC_ARITH.ALL;
22 use IEEE.STD_LOGIC_UNSIGNED.ALL;
23 use IEEE.std_logic_misc.all;
24 
25 -- Uncomment the following library declaration if using
26 -- arithmetic functions with Signed or Unsigned values
27 --use IEEE.NUMERIC_STD.ALL;
28 
29 -- Uncomment the following library declaration if instantiating
30 -- any Xilinx primitives in this code.
31 library UNISIM;
32 use UNISIM.VComponents.all;
33 Library UNIMACRO;
34 use UNIMACRO.vcomponents.all;
35 
36 entity Threshold is
37  Port ( clk : in STD_LOGIC; -- clk input
38  din : in STD_LOGIC_VECTOR(15 downto 0);
39  nongap_size : in STD_LOGIC_VECTOR(11 downto 0);
40  dout : out STD_LOGIC_VECTOR(31 downto 0));
41 end Threshold;
42 
43 architecture Behavioral of Threshold is
44 signal old_din : std_logic_vector(15 downto 0) := (others => '0');
45 signal old_nongap_size : std_logic_vector(11 downto 0) := (others => '0');
46 signal start : std_logic := '0';
47 signal busy : std_logic := '0';
48 signal CEP : std_logic := '0';
49 signal divide : std_logic := '0';
50 signal shift : std_logic := '0';
51 signal check_denom : std_logic := '0';
52 signal denom : std_logic_vector(12 downto 0) := (others => '0');
53 signal div_cntr : std_logic_vector(4 downto 0) := (others => '0');
54 signal nom : std_logic_vector(16 downto 0) := (others => '0');
55 signal divident : std_logic_vector(29 downto 0) := (others => '0');
56 signal Mult_P : std_logic_vector(47 downto 0) := (others => '0');
57 begin
58 dout <= Mult_P(41 downto 10);
59 process(clk)
60 begin
61  if(clk'event and clk = '1')then
62  if(start = '1')then
63  old_nongap_size <= nongap_size;
64  old_din <= din;
65  end if;
66  if(start = '1')then
67  busy <= '1';
68  elsif(or_reduce(div_cntr) = '0' and divide = '1')then
69  busy <= '0';
70  end if;
71  if((din /= old_din or nongap_size /= old_nongap_size) and busy = '0' and start = '0')then
72  start <= '1';
73  else
74  start <= '0';
75  end if;
76  if(start = '1')then
77  if(or_reduce(nongap_size(11 downto 5)) = '0')then
78  denom(11 downto 0) <= x"020";
79  else
80  denom(11 downto 0) <= nongap_size;
81  end if;
82  div_cntr <= "10001";
83  check_denom <= '1';
84  nom <= '0' & din;
85  divident <= (others => '0');
86  shift <= '0';
87  elsif(check_denom = '1')then
88  if(denom(11) = '0')then
89  div_cntr <= div_cntr + 1;
90  denom(11 downto 0) <= denom(10 downto 0) & '0';
91  else
92  check_denom <= '0';
93  divide <= '1';
94  end if;
95  elsif(divide = '1')then
96  if(shift = '0')then
97  div_cntr <= div_cntr - 1;
98  if(nom(16 downto 4) >= denom)then
99  nom(16 downto 4) <= nom(16 downto 4) - denom;
100  divident(0) <= '1';
101  end if;
102  shift <= '1';
103  else
104  nom <= nom(15 downto 0) & '0';
105  divident(23 downto 0) <= divident(22 downto 0) & '0';
106  shift <= '0';
107  if(or_reduce(div_cntr) = '0')then
108  divide <= '0';
109  end if;
110  end if;
111  end if;
112  CEP <= divide and not or_reduce(div_cntr);
113  end if;
114 end process;
115  DSP48E1_inst : DSP48E1
116  generic map (
117  -- Feature Control Attributes: Data Path Selection
118  A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
119  B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
120  USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
121  USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
122  USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
123  -- Pattern Detector Attributes: Pattern Detection Configuration
124  AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
125  MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
126  PATTERN => X"000000000000" , -- 48-bit pattern match for pattern detect
127  SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
128  SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
129  USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
130  -- Register Control Attributes: Pipeline Register Configuration
131  ACASCREG => 0, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
132  ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
133  ALUMODEREG => 0, -- Number of pipeline stages for ALUMODE (0 or 1)
134  AREG => 0, -- Number of pipeline stages for A (0, 1 or 2)
135  BCASCREG => 0, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
136  BREG => 0, -- Number of pipeline stages for B (0, 1 or 2)
137  CARRYINREG => 0, -- Number of pipeline stages for CARRYIN (0 or 1)
138  CARRYINSELREG => 0, -- Number of pipeline stages for CARRYINSEL (0 or 1)
139  CREG => 0, -- Number of pipeline stages for C (0 or 1)
140  DREG => 0, -- Number of pipeline stages for D (0 or 1)
141  INMODEREG => 0, -- Number of pipeline stages for INMODE (0 or 1)
142  MREG => 0, -- Number of multiplier pipeline stages (0 or 1)
143  OPMODEREG => 0, -- Number of pipeline stages for OPMODE (0 or 1)
144  PREG => 1 -- Number of pipeline stages for P (0 or 1)
145  )
146  port map (
147  -- Cascade: 30-bit (each) output: Cascade Ports
148  ACOUT => open, -- 30-bit output: A port cascade output
149  BCOUT => open, -- 18-bit output: B port cascade output
150  CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
151  MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
152  PCOUT => open, -- 48-bit output: Cascade output
153  -- Control: 1-bit (each) output: Control Inputs/Status Bits
154  OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
155  PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
156  PATTERNDETECT => open, -- 1-bit output: Pattern detect output
157  UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
158  -- Data: 4-bit (each) output: Data Ports
159  CARRYOUT => open, -- 4-bit output: Carry output
160  P => Mult_P, -- 48-bit output: Primary data output
161  -- Cascade: 30-bit (each) input: Cascade Ports
162  ACIN => (others => '0'), -- 30-bit input: A cascade data input
163  BCIN => (others => '0'), -- 18-bit input: B cascade input
164  CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
165  MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
166  PCIN => (others => '0'), -- 48-bit input: P cascade input
167  -- Control: 4-bit (each) input: Control Inputs/Status Bits
168  ALUMODE => "0000", -- 4-bit input: ALU control input
169  CARRYINSEL => "000", -- 3-bit input: Carry select input
170  CLK => clk, -- 1-bit input: Clock input
171  INMODE => "00000", -- 5-bit input: INMODE control input
172  OPMODE => "0000101", -- 7-bit input: Operation mode input
173  -- Data: 30-bit (each) input: Data Ports
174  A => divident, -- 30-bit input: A data input
175  B => "010111010011101111", -- 18-bit input: B data input
176  C => (others => '0'), -- 48-bit input: C data input
177  CARRYIN => '0', -- 1-bit input: Carry input signal
178  D => (others => '0'), -- 25-bit input: D data input
179  -- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
180  CEA1 => '0', -- 1-bit input: Clock enable input for 1st stage AREG
181  CEA2 => '0', -- 1-bit input: Clock enable input for 2nd stage AREG
182  CEAD => '0', -- 1-bit input: Clock enable input for ADREG
183  CEALUMODE => '0', -- 1-bit input: Clock enable input for ALUMODE
184  CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
185  CEB2 => '0', -- 1-bit input: Clock enable input for 2nd stage BREG
186  CEC => '0', -- 1-bit input: Clock enable input for CREG
187  CECARRYIN => '0', -- 1-bit input: Clock enable input for CARRYINREG
188  CECTRL => '0', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
189  CED => '0', -- 1-bit input: Clock enable input for DREG
190  CEINMODE => '0', -- 1-bit input: Clock enable input for INMODEREG
191  CEM => '0', -- 1-bit input: Clock enable input for MREG
192  CEP => CEP, -- 1-bit input: Clock enable input for PREG
193  RSTA => '0', -- 1-bit input: Reset input for AREG
194  RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
195  RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
196  RSTB => '0', -- 1-bit input: Reset input for BREG
197  RSTC => '0', -- 1-bit input: Reset input for CREG
198  RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
199  RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
200  RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
201  RSTM => '0', -- 1-bit input: Reset input for MREG
202  RSTP => '0' -- 1-bit input: Reset input for PREG
203  );
204 end Behavioral;
205 
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