AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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serdes5gpdprod.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : serdes5gpdprod.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module serdes5GpdProd (a GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 library UNISIM;
68 use UNISIM.VCOMPONENTS.ALL;
69 
70 
71 --***************************** Entity Declaration ****************************
72 
73 entity serdes5GpdProd is
74 generic
75 (
76  QPLL_FBDIV_TOP : integer := 80;
77 
78  -- Simulation attributes
79  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
80  RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
81  PMA_RSV_IN : bit_vector := x"001E7080"
82 
83 );
84 port
85 (
86  --_________________________________________________________________________
87  --_________________________________________________________________________
88  --GT0 (X0Y12)
89  --____________________________CHANNEL PORTS________________________________
90  ---------------------------- Channel - DRP Ports --------------------------
91  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
92  GT0_DRPCLK_IN : in std_logic;
93  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
94  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
95  GT0_DRPEN_IN : in std_logic;
96  GT0_DRPRDY_OUT : out std_logic;
97  GT0_DRPWE_IN : in std_logic;
98  ------------------------------ Power-Down Ports ----------------------------
99  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
100  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
101  --------------------- RX Initialization and Reset Ports --------------------
102  GT0_RXUSERRDY_IN : in std_logic;
103  -------------------------- RX Margin Analysis Ports ------------------------
104  GT0_EYESCANDATAERROR_OUT : out std_logic;
105  ------------------------- Receive Ports - CDR Ports ------------------------
106  GT0_RXCDRLOCK_OUT : out std_logic;
107  ------------------- Receive Ports - Clock Correction Ports -----------------
108  GT0_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
109  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
110  GT0_RXUSRCLK_IN : in std_logic;
111  GT0_RXUSRCLK2_IN : in std_logic;
112  ------------------ Receive Ports - FPGA RX interface Ports -----------------
113  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
114  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
115  GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
116  GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
117  --------------------------- Receive Ports - RX AFE -------------------------
118  GT0_GTXRXP_IN : in std_logic;
119  ------------------------ Receive Ports - RX AFE Ports ----------------------
120  GT0_GTXRXN_IN : in std_logic;
121  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
122  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
123  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
124  GT0_RXBYTEISALIGNED_OUT : out std_logic;
125  GT0_RXBYTEREALIGN_OUT : out std_logic;
126  GT0_RXCOMMADET_OUT : out std_logic;
127  GT0_RXMCOMMAALIGNEN_IN : in std_logic;
128  GT0_RXPCOMMAALIGNEN_IN : in std_logic;
129  --------------------- Receive Ports - RX Equalizer Ports -------------------
130  GT0_RXDFEAGCHOLD_IN : in std_logic;
131  GT0_RXDFELFHOLD_IN : in std_logic;
132  --------------- Receive Ports - RX Fabric Output Control Ports -------------
133  GT0_RXOUTCLK_OUT : out std_logic;
134  ------------- Receive Ports - RX Initialization and Reset Ports ------------
135  GT0_GTRXRESET_IN : in std_logic;
136  GT0_RXPMARESET_IN : in std_logic;
137  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
138  GT0_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
139  GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
140  -------------- Receive Ports -RX Initialization and Reset Ports ------------
141  GT0_RXRESETDONE_OUT : out std_logic;
142  --------------------- TX Initialization and Reset Ports --------------------
143  GT0_GTTXRESET_IN : in std_logic;
144  GT0_TXUSERRDY_IN : in std_logic;
145  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
146  GT0_TXUSRCLK_IN : in std_logic;
147  GT0_TXUSRCLK2_IN : in std_logic;
148  ------------------ Transmit Ports - TX Data Path interface -----------------
149  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
150  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
151  GT0_GTXTXN_OUT : out std_logic;
152  GT0_GTXTXP_OUT : out std_logic;
153  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
154  GT0_TXOUTCLK_OUT : out std_logic;
155  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
156  GT0_TXOUTCLKPCS_OUT : out std_logic;
157  --------------------- Transmit Ports - TX Gearbox Ports --------------------
158  GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
159  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
160  GT0_TXRESETDONE_OUT : out std_logic;
161 
162  --GT1 (X0Y13)
163  --____________________________CHANNEL PORTS________________________________
164  ---------------------------- Channel - DRP Ports --------------------------
165  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
166  GT1_DRPCLK_IN : in std_logic;
167  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
168  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
169  GT1_DRPEN_IN : in std_logic;
170  GT1_DRPRDY_OUT : out std_logic;
171  GT1_DRPWE_IN : in std_logic;
172  ------------------------------ Power-Down Ports ----------------------------
173  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
174  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
175  --------------------- RX Initialization and Reset Ports --------------------
176  GT1_RXUSERRDY_IN : in std_logic;
177  -------------------------- RX Margin Analysis Ports ------------------------
178  GT1_EYESCANDATAERROR_OUT : out std_logic;
179  ------------------------- Receive Ports - CDR Ports ------------------------
180  GT1_RXCDRLOCK_OUT : out std_logic;
181  ------------------- Receive Ports - Clock Correction Ports -----------------
182  GT1_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
183  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
184  GT1_RXUSRCLK_IN : in std_logic;
185  GT1_RXUSRCLK2_IN : in std_logic;
186  ------------------ Receive Ports - FPGA RX interface Ports -----------------
187  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
188  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
189  GT1_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
190  GT1_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
191  --------------------------- Receive Ports - RX AFE -------------------------
192  GT1_GTXRXP_IN : in std_logic;
193  ------------------------ Receive Ports - RX AFE Ports ----------------------
194  GT1_GTXRXN_IN : in std_logic;
195  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
196  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
197  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
198  GT1_RXBYTEISALIGNED_OUT : out std_logic;
199  GT1_RXBYTEREALIGN_OUT : out std_logic;
200  GT1_RXCOMMADET_OUT : out std_logic;
201  GT1_RXMCOMMAALIGNEN_IN : in std_logic;
202  GT1_RXPCOMMAALIGNEN_IN : in std_logic;
203  --------------------- Receive Ports - RX Equalizer Ports -------------------
204  GT1_RXDFEAGCHOLD_IN : in std_logic;
205  GT1_RXDFELFHOLD_IN : in std_logic;
206  --------------- Receive Ports - RX Fabric Output Control Ports -------------
207  GT1_RXOUTCLK_OUT : out std_logic;
208  ------------- Receive Ports - RX Initialization and Reset Ports ------------
209  GT1_GTRXRESET_IN : in std_logic;
210  GT1_RXPMARESET_IN : in std_logic;
211  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
212  GT1_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
213  GT1_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
214  -------------- Receive Ports -RX Initialization and Reset Ports ------------
215  GT1_RXRESETDONE_OUT : out std_logic;
216  --------------------- TX Initialization and Reset Ports --------------------
217  GT1_GTTXRESET_IN : in std_logic;
218  GT1_TXUSERRDY_IN : in std_logic;
219  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
220  GT1_TXUSRCLK_IN : in std_logic;
221  GT1_TXUSRCLK2_IN : in std_logic;
222  ------------------ Transmit Ports - TX Data Path interface -----------------
223  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
224  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
225  GT1_GTXTXN_OUT : out std_logic;
226  GT1_GTXTXP_OUT : out std_logic;
227  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
228  GT1_TXOUTCLK_OUT : out std_logic;
229  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
230  GT1_TXOUTCLKPCS_OUT : out std_logic;
231  --------------------- Transmit Ports - TX Gearbox Ports --------------------
232  GT1_TXCHARISK_IN : in std_logic_vector(3 downto 0);
233  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
234  GT1_TXRESETDONE_OUT : out std_logic;
235 
236  --GT2 (X0Y14)
237  --____________________________CHANNEL PORTS________________________________
238  ---------------------------- Channel - DRP Ports --------------------------
239  GT2_DRPADDR_IN : in std_logic_vector(8 downto 0);
240  GT2_DRPCLK_IN : in std_logic;
241  GT2_DRPDI_IN : in std_logic_vector(15 downto 0);
242  GT2_DRPDO_OUT : out std_logic_vector(15 downto 0);
243  GT2_DRPEN_IN : in std_logic;
244  GT2_DRPRDY_OUT : out std_logic;
245  GT2_DRPWE_IN : in std_logic;
246  ------------------------------ Power-Down Ports ----------------------------
247  GT2_RXPD_IN : in std_logic_vector(1 downto 0);
248  GT2_TXPD_IN : in std_logic_vector(1 downto 0);
249  --------------------- RX Initialization and Reset Ports --------------------
250  GT2_RXUSERRDY_IN : in std_logic;
251  -------------------------- RX Margin Analysis Ports ------------------------
252  GT2_EYESCANDATAERROR_OUT : out std_logic;
253  ------------------------- Receive Ports - CDR Ports ------------------------
254  GT2_RXCDRLOCK_OUT : out std_logic;
255  ------------------- Receive Ports - Clock Correction Ports -----------------
256  GT2_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
257  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
258  GT2_RXUSRCLK_IN : in std_logic;
259  GT2_RXUSRCLK2_IN : in std_logic;
260  ------------------ Receive Ports - FPGA RX interface Ports -----------------
261  GT2_RXDATA_OUT : out std_logic_vector(31 downto 0);
262  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
263  GT2_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
264  GT2_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
265  --------------------------- Receive Ports - RX AFE -------------------------
266  GT2_GTXRXP_IN : in std_logic;
267  ------------------------ Receive Ports - RX AFE Ports ----------------------
268  GT2_GTXRXN_IN : in std_logic;
269  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
270  GT2_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
271  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
272  GT2_RXBYTEISALIGNED_OUT : out std_logic;
273  GT2_RXBYTEREALIGN_OUT : out std_logic;
274  GT2_RXCOMMADET_OUT : out std_logic;
275  GT2_RXMCOMMAALIGNEN_IN : in std_logic;
276  GT2_RXPCOMMAALIGNEN_IN : in std_logic;
277  --------------------- Receive Ports - RX Equalizer Ports -------------------
278  GT2_RXDFEAGCHOLD_IN : in std_logic;
279  GT2_RXDFELFHOLD_IN : in std_logic;
280  --------------- Receive Ports - RX Fabric Output Control Ports -------------
281  GT2_RXOUTCLK_OUT : out std_logic;
282  ------------- Receive Ports - RX Initialization and Reset Ports ------------
283  GT2_GTRXRESET_IN : in std_logic;
284  GT2_RXPMARESET_IN : in std_logic;
285  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
286  GT2_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
287  GT2_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
288  -------------- Receive Ports -RX Initialization and Reset Ports ------------
289  GT2_RXRESETDONE_OUT : out std_logic;
290  --------------------- TX Initialization and Reset Ports --------------------
291  GT2_GTTXRESET_IN : in std_logic;
292  GT2_TXUSERRDY_IN : in std_logic;
293  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
294  GT2_TXUSRCLK_IN : in std_logic;
295  GT2_TXUSRCLK2_IN : in std_logic;
296  ------------------ Transmit Ports - TX Data Path interface -----------------
297  GT2_TXDATA_IN : in std_logic_vector(31 downto 0);
298  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
299  GT2_GTXTXN_OUT : out std_logic;
300  GT2_GTXTXP_OUT : out std_logic;
301  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
302  GT2_TXOUTCLK_OUT : out std_logic;
303  GT2_TXOUTCLKFABRIC_OUT : out std_logic;
304  GT2_TXOUTCLKPCS_OUT : out std_logic;
305  --------------------- Transmit Ports - TX Gearbox Ports --------------------
306  GT2_TXCHARISK_IN : in std_logic_vector(3 downto 0);
307  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
308  GT2_TXRESETDONE_OUT : out std_logic;
309 
310 
311  --____________________________COMMON PORTS________________________________
312  ---------------------- Common Block - Ref Clock Ports ---------------------
313  GT0_GTREFCLK0_COMMON_IN : in std_logic;
314  ------------------------- Common Block - QPLL Ports ------------------------
315  GT0_QPLLLOCK_OUT : out std_logic;
316  GT0_QPLLLOCKDETCLK_IN : in std_logic;
317  GT0_QPLLREFCLKLOST_OUT : out std_logic;
318  GT0_QPLLRESET_IN : in std_logic
319 
320 
321 );
322 
323 
324 end serdes5GpdProd;
325 
326 architecture RTL of serdes5GpdProd is
327 
328  attribute CORE_GENERATION_INFO : string;
329  attribute CORE_GENERATION_INFO of RTL : architecture is "serdes5GpdProd,gtwizard_v2_7,{protocol_file=Start_from_scratch}";
330 
331 
332 --***********************************Parameter Declarations********************
333 
334  constant DLY : time := 1 ns;
335 
336 --***************************** Signal Declarations *****************************
337 
338  -- ground and tied_to_vcc_i signals
339  signal tied_to_ground_i : std_logic;
340  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
341  signal tied_to_vcc_i : std_logic;
342  signal gt0_qplloutclk_i : std_logic;
343  signal gt0_qplloutrefclk_i : std_logic;
344 
345 
346  signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0);
347  signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0);
348 
349  signal gt1_mgtrefclktx_i : std_logic_vector(1 downto 0);
350  signal gt1_mgtrefclkrx_i : std_logic_vector(1 downto 0);
351 
352  signal gt2_mgtrefclktx_i : std_logic_vector(1 downto 0);
353  signal gt2_mgtrefclkrx_i : std_logic_vector(1 downto 0);
354 
355 
356  signal gt0_qpllclk_i : std_logic;
357  signal gt0_qpllrefclk_i : std_logic;
358  signal gt1_qpllclk_i : std_logic;
359  signal gt1_qpllrefclk_i : std_logic;
360  signal gt2_qpllclk_i : std_logic;
361  signal gt2_qpllrefclk_i : std_logic;
362 
363 
364 --*************************** Component Declarations **************************
365 component serdes5GpdProd_GT
366 generic
367 (
368  -- Simulation attributes
369  GT_SIM_GTRESET_SPEEDUP : string := "FALSE";
370  RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
371  PMA_RSV_IN : bit_vector := X"00000000";
372  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
373 );
374 port
375 (
376  ---------------------------- Channel - DRP Ports --------------------------
377  DRPADDR_IN : in std_logic_vector(8 downto 0);
378  DRPCLK_IN : in std_logic;
379  DRPDI_IN : in std_logic_vector(15 downto 0);
380  DRPDO_OUT : out std_logic_vector(15 downto 0);
381  DRPEN_IN : in std_logic;
382  DRPRDY_OUT : out std_logic;
383  DRPWE_IN : in std_logic;
384  ------------------------------- Clocking Ports -----------------------------
385  QPLLCLK_IN : in std_logic;
386  QPLLREFCLK_IN : in std_logic;
387  ------------------------------ Power-Down Ports ----------------------------
388  RXPD_IN : in std_logic_vector(1 downto 0);
389  TXPD_IN : in std_logic_vector(1 downto 0);
390  --------------------- RX Initialization and Reset Ports --------------------
391  RXUSERRDY_IN : in std_logic;
392  -------------------------- RX Margin Analysis Ports ------------------------
393  EYESCANDATAERROR_OUT : out std_logic;
394  ------------------------- Receive Ports - CDR Ports ------------------------
395  RXCDRLOCK_OUT : out std_logic;
396  ------------------- Receive Ports - Clock Correction Ports -----------------
397  RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
398  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
399  RXUSRCLK_IN : in std_logic;
400  RXUSRCLK2_IN : in std_logic;
401  ------------------ Receive Ports - FPGA RX interface Ports -----------------
402  RXDATA_OUT : out std_logic_vector(31 downto 0);
403  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
404  RXDISPERR_OUT : out std_logic_vector(3 downto 0);
405  RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
406  --------------------------- Receive Ports - RX AFE -------------------------
407  GTXRXP_IN : in std_logic;
408  ------------------------ Receive Ports - RX AFE Ports ----------------------
409  GTXRXN_IN : in std_logic;
410  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
411  RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
412  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
413  RXBYTEISALIGNED_OUT : out std_logic;
414  RXBYTEREALIGN_OUT : out std_logic;
415  RXCOMMADET_OUT : out std_logic;
416  RXMCOMMAALIGNEN_IN : in std_logic;
417  RXPCOMMAALIGNEN_IN : in std_logic;
418  --------------------- Receive Ports - RX Equalizer Ports -------------------
419  RXDFEAGCHOLD_IN : in std_logic;
420  RXDFELFHOLD_IN : in std_logic;
421  --------------- Receive Ports - RX Fabric Output Control Ports -------------
422  RXOUTCLK_OUT : out std_logic;
423  ------------- Receive Ports - RX Initialization and Reset Ports ------------
424  GTRXRESET_IN : in std_logic;
425  RXPMARESET_IN : in std_logic;
426  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
427  RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
428  RXCHARISK_OUT : out std_logic_vector(3 downto 0);
429  -------------- Receive Ports -RX Initialization and Reset Ports ------------
430  RXRESETDONE_OUT : out std_logic;
431  --------------------- TX Initialization and Reset Ports --------------------
432  GTTXRESET_IN : in std_logic;
433  TXUSERRDY_IN : in std_logic;
434  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
435  TXUSRCLK_IN : in std_logic;
436  TXUSRCLK2_IN : in std_logic;
437  ------------------ Transmit Ports - TX Data Path interface -----------------
438  TXDATA_IN : in std_logic_vector(31 downto 0);
439  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
440  GTXTXN_OUT : out std_logic;
441  GTXTXP_OUT : out std_logic;
442  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
443  TXOUTCLK_OUT : out std_logic;
444  TXOUTCLKFABRIC_OUT : out std_logic;
445  TXOUTCLKPCS_OUT : out std_logic;
446  --------------------- Transmit Ports - TX Gearbox Ports --------------------
447  TXCHARISK_IN : in std_logic_vector(3 downto 0);
448  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
449  TXRESETDONE_OUT : out std_logic
450 
451 
452 );
453 end component;
454 
455 
456 
457 --*************************Logic to set Attribute QPLL_FB_DIV*****************************
458  impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
459  begin
460  if (qpllfbdiv_top = 16) then
461  return "0000100000";
462  elsif (qpllfbdiv_top = 20) then
463  return "0000110000" ;
464  elsif (qpllfbdiv_top = 32) then
465  return "0001100000" ;
466  elsif (qpllfbdiv_top = 40) then
467  return "0010000000" ;
468  elsif (qpllfbdiv_top = 64) then
469  return "0011100000" ;
470  elsif (qpllfbdiv_top = 66) then
471  return "0101000000" ;
472  elsif (qpllfbdiv_top = 80) then
473  return "0100100000" ;
474  elsif (qpllfbdiv_top = 100) then
475  return "0101110000" ;
476  else
477  return "0000000000" ;
478  end if;
479  end function;
480 
481  impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
482  begin
483  if (qpllfbdiv_top = 16) then
484  return '1';
485  elsif (qpllfbdiv_top = 20) then
486  return '1' ;
487  elsif (qpllfbdiv_top = 32) then
488  return '1' ;
489  elsif (qpllfbdiv_top = 40) then
490  return '1' ;
491  elsif (qpllfbdiv_top = 64) then
492  return '1' ;
493  elsif (qpllfbdiv_top = 66) then
494  return '0' ;
495  elsif (qpllfbdiv_top = 80) then
496  return '1' ;
497  elsif (qpllfbdiv_top = 100) then
498  return '1' ;
499  else
500  return '1' ;
501  end if;
502  end function;
503 
504  constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
505  constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
506 
507 --********************************* Main Body of Code**************************
508 
509 begin
510 
511  tied_to_ground_i <= '0';
512  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
513  tied_to_vcc_i <= '1';
514  gt0_qpllclk_i <= gt0_qplloutclk_i;
515  gt0_qpllrefclk_i <= gt0_qplloutrefclk_i;
516 
517  gt1_qpllclk_i <= gt0_qplloutclk_i;
518  gt1_qpllrefclk_i <= gt0_qplloutrefclk_i;
519 
520  gt2_qpllclk_i <= gt0_qplloutclk_i;
521  gt2_qpllrefclk_i <= gt0_qplloutrefclk_i;
522 
523 
524 
525  --------------------------- GT Instances -------------------------------
526 
527  --_________________________________________________________________________
528  --_________________________________________________________________________
529  --GT0 (X0Y12)
530 
531  gt0_serdes5GpdProd_i : serdes5GpdProd_GT
532  generic map
533  (
534  -- Simulation attributes
535  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
536  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
537  PMA_RSV_IN => PMA_RSV_IN,
538  PCS_RSVD_ATTR_IN => X"000000000000"
539  )
540  port map
541  (
542  ---------------------------- Channel - DRP Ports --------------------------
543  DRPADDR_IN => GT0_DRPADDR_IN,
544  DRPCLK_IN => GT0_DRPCLK_IN,
545  DRPDI_IN => GT0_DRPDI_IN ,
546  DRPDO_OUT => GT0_DRPDO_OUT,
547  DRPEN_IN => GT0_DRPEN_IN ,
548  DRPRDY_OUT => GT0_DRPRDY_OUT,
549  DRPWE_IN => GT0_DRPWE_IN ,
550  ------------------------------- Clocking Ports -----------------------------
551  QPLLCLK_IN => gt0_qpllclk_i,
552  QPLLREFCLK_IN => gt0_qpllrefclk_i,
553  ------------------------------ Power-Down Ports ----------------------------
554  RXPD_IN => GT0_RXPD_IN ,
555  TXPD_IN => GT0_TXPD_IN ,
556  --------------------- RX Initialization and Reset Ports --------------------
557  RXUSERRDY_IN => GT0_RXUSERRDY_IN,
558  -------------------------- RX Margin Analysis Ports ------------------------
559  EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
560  ------------------------- Receive Ports - CDR Ports ------------------------
561  RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
562  ------------------- Receive Ports - Clock Correction Ports -----------------
563  RXCLKCORCNT_OUT => GT0_RXCLKCORCNT_OUT ,
564  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
565  RXUSRCLK_IN => GT0_RXUSRCLK_IN,
566  RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
567  ------------------ Receive Ports - FPGA RX interface Ports -----------------
568  RXDATA_OUT => GT0_RXDATA_OUT,
569  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
570  RXDISPERR_OUT => GT0_RXDISPERR_OUT,
571  RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT ,
572  --------------------------- Receive Ports - RX AFE -------------------------
573  GTXRXP_IN => GT0_GTXRXP_IN,
574  ------------------------ Receive Ports - RX AFE Ports ----------------------
575  GTXRXN_IN => GT0_GTXRXN_IN,
576  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
577  RXBUFSTATUS_OUT => GT0_RXBUFSTATUS_OUT ,
578  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
579  RXBYTEISALIGNED_OUT => GT0_RXBYTEISALIGNED_OUT ,
580  RXBYTEREALIGN_OUT => GT0_RXBYTEREALIGN_OUT ,
581  RXCOMMADET_OUT => GT0_RXCOMMADET_OUT,
582  RXMCOMMAALIGNEN_IN => GT0_RXMCOMMAALIGNEN_IN ,
583  RXPCOMMAALIGNEN_IN => GT0_RXPCOMMAALIGNEN_IN ,
584  --------------------- Receive Ports - RX Equalizer Ports -------------------
585  RXDFEAGCHOLD_IN => GT0_RXDFEAGCHOLD_IN ,
586  RXDFELFHOLD_IN => GT0_RXDFELFHOLD_IN,
587  --------------- Receive Ports - RX Fabric Output Control Ports -------------
588  RXOUTCLK_OUT => GT0_RXOUTCLK_OUT,
589  ------------- Receive Ports - RX Initialization and Reset Ports ------------
590  GTRXRESET_IN => GT0_GTRXRESET_IN,
591  RXPMARESET_IN => GT0_RXPMARESET_IN,
592  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
593  RXCHARISCOMMA_OUT => GT0_RXCHARISCOMMA_OUT ,
594  RXCHARISK_OUT => GT0_RXCHARISK_OUT,
595  -------------- Receive Ports -RX Initialization and Reset Ports ------------
596  RXRESETDONE_OUT => GT0_RXRESETDONE_OUT ,
597  --------------------- TX Initialization and Reset Ports --------------------
598  GTTXRESET_IN => GT0_GTTXRESET_IN,
599  TXUSERRDY_IN => GT0_TXUSERRDY_IN,
600  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
601  TXUSRCLK_IN => GT0_TXUSRCLK_IN,
602  TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
603  ------------------ Transmit Ports - TX Data Path interface -----------------
604  TXDATA_IN => GT0_TXDATA_IN,
605  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
606  GTXTXN_OUT => GT0_GTXTXN_OUT,
607  GTXTXP_OUT => GT0_GTXTXP_OUT,
608  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
609  TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
610  TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT ,
611  TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT ,
612  --------------------- Transmit Ports - TX Gearbox Ports --------------------
613  TXCHARISK_IN => GT0_TXCHARISK_IN,
614  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
615  TXRESETDONE_OUT => GT0_TXRESETDONE_OUT
616 
617  );
618 
619  --_________________________________________________________________________
620  --_________________________________________________________________________
621  --GT1 (X0Y13)
622 
623  gt1_serdes5GpdProd_i : serdes5GpdProd_GT
624  generic map
625  (
626  -- Simulation attributes
627  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
628  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
629  PMA_RSV_IN => PMA_RSV_IN,
630  PCS_RSVD_ATTR_IN => X"000000000000"
631  )
632  port map
633  (
634  ---------------------------- Channel - DRP Ports --------------------------
635  DRPADDR_IN => GT1_DRPADDR_IN,
636  DRPCLK_IN => GT1_DRPCLK_IN,
637  DRPDI_IN => GT1_DRPDI_IN ,
638  DRPDO_OUT => GT1_DRPDO_OUT,
639  DRPEN_IN => GT1_DRPEN_IN ,
640  DRPRDY_OUT => GT1_DRPRDY_OUT,
641  DRPWE_IN => GT1_DRPWE_IN ,
642  ------------------------------- Clocking Ports -----------------------------
643  QPLLCLK_IN => gt1_qpllclk_i,
644  QPLLREFCLK_IN => gt1_qpllrefclk_i,
645  ------------------------------ Power-Down Ports ----------------------------
646  RXPD_IN => GT1_RXPD_IN ,
647  TXPD_IN => GT1_TXPD_IN ,
648  --------------------- RX Initialization and Reset Ports --------------------
649  RXUSERRDY_IN => GT1_RXUSERRDY_IN,
650  -------------------------- RX Margin Analysis Ports ------------------------
651  EYESCANDATAERROR_OUT => GT1_EYESCANDATAERROR_OUT,
652  ------------------------- Receive Ports - CDR Ports ------------------------
653  RXCDRLOCK_OUT => GT1_RXCDRLOCK_OUT,
654  ------------------- Receive Ports - Clock Correction Ports -----------------
655  RXCLKCORCNT_OUT => GT1_RXCLKCORCNT_OUT ,
656  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
657  RXUSRCLK_IN => GT1_RXUSRCLK_IN,
658  RXUSRCLK2_IN => GT1_RXUSRCLK2_IN,
659  ------------------ Receive Ports - FPGA RX interface Ports -----------------
660  RXDATA_OUT => GT1_RXDATA_OUT,
661  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
662  RXDISPERR_OUT => GT1_RXDISPERR_OUT,
663  RXNOTINTABLE_OUT => GT1_RXNOTINTABLE_OUT ,
664  --------------------------- Receive Ports - RX AFE -------------------------
665  GTXRXP_IN => GT1_GTXRXP_IN,
666  ------------------------ Receive Ports - RX AFE Ports ----------------------
667  GTXRXN_IN => GT1_GTXRXN_IN,
668  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
669  RXBUFSTATUS_OUT => GT1_RXBUFSTATUS_OUT ,
670  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
671  RXBYTEISALIGNED_OUT => GT1_RXBYTEISALIGNED_OUT ,
672  RXBYTEREALIGN_OUT => GT1_RXBYTEREALIGN_OUT ,
673  RXCOMMADET_OUT => GT1_RXCOMMADET_OUT,
674  RXMCOMMAALIGNEN_IN => GT1_RXMCOMMAALIGNEN_IN ,
675  RXPCOMMAALIGNEN_IN => GT1_RXPCOMMAALIGNEN_IN ,
676  --------------------- Receive Ports - RX Equalizer Ports -------------------
677  RXDFEAGCHOLD_IN => GT1_RXDFEAGCHOLD_IN ,
678  RXDFELFHOLD_IN => GT1_RXDFELFHOLD_IN,
679  --------------- Receive Ports - RX Fabric Output Control Ports -------------
680  RXOUTCLK_OUT => GT1_RXOUTCLK_OUT,
681  ------------- Receive Ports - RX Initialization and Reset Ports ------------
682  GTRXRESET_IN => GT1_GTRXRESET_IN,
683  RXPMARESET_IN => GT1_RXPMARESET_IN,
684  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
685  RXCHARISCOMMA_OUT => GT1_RXCHARISCOMMA_OUT ,
686  RXCHARISK_OUT => GT1_RXCHARISK_OUT,
687  -------------- Receive Ports -RX Initialization and Reset Ports ------------
688  RXRESETDONE_OUT => GT1_RXRESETDONE_OUT ,
689  --------------------- TX Initialization and Reset Ports --------------------
690  GTTXRESET_IN => GT1_GTTXRESET_IN,
691  TXUSERRDY_IN => GT1_TXUSERRDY_IN,
692  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
693  TXUSRCLK_IN => GT1_TXUSRCLK_IN,
694  TXUSRCLK2_IN => GT1_TXUSRCLK2_IN,
695  ------------------ Transmit Ports - TX Data Path interface -----------------
696  TXDATA_IN => GT1_TXDATA_IN,
697  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
698  GTXTXN_OUT => GT1_GTXTXN_OUT,
699  GTXTXP_OUT => GT1_GTXTXP_OUT,
700  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
701  TXOUTCLK_OUT => GT1_TXOUTCLK_OUT,
702  TXOUTCLKFABRIC_OUT => GT1_TXOUTCLKFABRIC_OUT ,
703  TXOUTCLKPCS_OUT => GT1_TXOUTCLKPCS_OUT ,
704  --------------------- Transmit Ports - TX Gearbox Ports --------------------
705  TXCHARISK_IN => GT1_TXCHARISK_IN,
706  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
707  TXRESETDONE_OUT => GT1_TXRESETDONE_OUT
708 
709  );
710 
711  --_________________________________________________________________________
712  --_________________________________________________________________________
713  --GT2 (X0Y14)
714 
715  gt2_serdes5GpdProd_i : serdes5GpdProd_GT
716  generic map
717  (
718  -- Simulation attributes
719  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
720  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
721  PMA_RSV_IN => PMA_RSV_IN,
722  PCS_RSVD_ATTR_IN => X"000000000000"
723  )
724  port map
725  (
726  ---------------------------- Channel - DRP Ports --------------------------
727  DRPADDR_IN => GT2_DRPADDR_IN,
728  DRPCLK_IN => GT2_DRPCLK_IN,
729  DRPDI_IN => GT2_DRPDI_IN ,
730  DRPDO_OUT => GT2_DRPDO_OUT,
731  DRPEN_IN => GT2_DRPEN_IN ,
732  DRPRDY_OUT => GT2_DRPRDY_OUT,
733  DRPWE_IN => GT2_DRPWE_IN ,
734  ------------------------------- Clocking Ports -----------------------------
735  QPLLCLK_IN => gt2_qpllclk_i,
736  QPLLREFCLK_IN => gt2_qpllrefclk_i,
737  ------------------------------ Power-Down Ports ----------------------------
738  RXPD_IN => GT2_RXPD_IN ,
739  TXPD_IN => GT2_TXPD_IN ,
740  --------------------- RX Initialization and Reset Ports --------------------
741  RXUSERRDY_IN => GT2_RXUSERRDY_IN,
742  -------------------------- RX Margin Analysis Ports ------------------------
743  EYESCANDATAERROR_OUT => GT2_EYESCANDATAERROR_OUT,
744  ------------------------- Receive Ports - CDR Ports ------------------------
745  RXCDRLOCK_OUT => GT2_RXCDRLOCK_OUT,
746  ------------------- Receive Ports - Clock Correction Ports -----------------
747  RXCLKCORCNT_OUT => GT2_RXCLKCORCNT_OUT ,
748  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
749  RXUSRCLK_IN => GT2_RXUSRCLK_IN,
750  RXUSRCLK2_IN => GT2_RXUSRCLK2_IN,
751  ------------------ Receive Ports - FPGA RX interface Ports -----------------
752  RXDATA_OUT => GT2_RXDATA_OUT,
753  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
754  RXDISPERR_OUT => GT2_RXDISPERR_OUT,
755  RXNOTINTABLE_OUT => GT2_RXNOTINTABLE_OUT ,
756  --------------------------- Receive Ports - RX AFE -------------------------
757  GTXRXP_IN => GT2_GTXRXP_IN,
758  ------------------------ Receive Ports - RX AFE Ports ----------------------
759  GTXRXN_IN => GT2_GTXRXN_IN,
760  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
761  RXBUFSTATUS_OUT => GT2_RXBUFSTATUS_OUT ,
762  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
763  RXBYTEISALIGNED_OUT => GT2_RXBYTEISALIGNED_OUT ,
764  RXBYTEREALIGN_OUT => GT2_RXBYTEREALIGN_OUT ,
765  RXCOMMADET_OUT => GT2_RXCOMMADET_OUT,
766  RXMCOMMAALIGNEN_IN => GT2_RXMCOMMAALIGNEN_IN ,
767  RXPCOMMAALIGNEN_IN => GT2_RXPCOMMAALIGNEN_IN ,
768  --------------------- Receive Ports - RX Equalizer Ports -------------------
769  RXDFEAGCHOLD_IN => GT2_RXDFEAGCHOLD_IN ,
770  RXDFELFHOLD_IN => GT2_RXDFELFHOLD_IN,
771  --------------- Receive Ports - RX Fabric Output Control Ports -------------
772  RXOUTCLK_OUT => GT2_RXOUTCLK_OUT,
773  ------------- Receive Ports - RX Initialization and Reset Ports ------------
774  GTRXRESET_IN => GT2_GTRXRESET_IN,
775  RXPMARESET_IN => GT2_RXPMARESET_IN,
776  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
777  RXCHARISCOMMA_OUT => GT2_RXCHARISCOMMA_OUT ,
778  RXCHARISK_OUT => GT2_RXCHARISK_OUT,
779  -------------- Receive Ports -RX Initialization and Reset Ports ------------
780  RXRESETDONE_OUT => GT2_RXRESETDONE_OUT ,
781  --------------------- TX Initialization and Reset Ports --------------------
782  GTTXRESET_IN => GT2_GTTXRESET_IN,
783  TXUSERRDY_IN => GT2_TXUSERRDY_IN,
784  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
785  TXUSRCLK_IN => GT2_TXUSRCLK_IN,
786  TXUSRCLK2_IN => GT2_TXUSRCLK2_IN,
787  ------------------ Transmit Ports - TX Data Path interface -----------------
788  TXDATA_IN => GT2_TXDATA_IN,
789  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
790  GTXTXN_OUT => GT2_GTXTXN_OUT,
791  GTXTXP_OUT => GT2_GTXTXP_OUT,
792  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
793  TXOUTCLK_OUT => GT2_TXOUTCLK_OUT,
794  TXOUTCLKFABRIC_OUT => GT2_TXOUTCLKFABRIC_OUT ,
795  TXOUTCLKPCS_OUT => GT2_TXOUTCLKPCS_OUT ,
796  --------------------- Transmit Ports - TX Gearbox Ports --------------------
797  TXCHARISK_IN => GT2_TXCHARISK_IN,
798  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
799  TXRESETDONE_OUT => GT2_TXRESETDONE_OUT
800 
801  );
802 
803  --_________________________________________________________________________
804  --_________________________________________________________________________
805  --_________________________GTXE2_COMMON____________________________________
806 
807  gtxe2_common_0_i : GTXE2_COMMON
808  generic map
809  (
810  -- Simulation attributes
811  SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
812  SIM_QPLLREFCLK_SEL => ("001"),
813  SIM_VERSION => "4.0",
814 
815 
816  ------------------COMMON BLOCK Attributes---------------
817  BIAS_CFG => (x"0000040000001000"),
818  COMMON_CFG => (x"00000000"),
819  QPLL_CFG => (x"0680181"),
820  QPLL_CLKOUT_CFG => ("0000"),
821  QPLL_COARSE_FREQ_OVRD => ("010000"),
822  QPLL_COARSE_FREQ_OVRD_EN => ('0'),
823  QPLL_CP => ("0000011111"),
824  QPLL_CP_MONITOR_EN => ('0'),
825  QPLL_DMONITOR_SEL => ('0'),
826  QPLL_FBDIV => (QPLL_FBDIV_IN),
827  QPLL_FBDIV_MONITOR_EN => ('0'),
828  QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
829  QPLL_INIT_CFG => (x"000006"),
830  QPLL_LOCK_CFG => (x"21E8"),
831  QPLL_LPF => ("1111"),
832  QPLL_REFCLK_DIV => (1)
833 
834 
835  )
836  port map
837  (
838  ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
839  DRPADDR => tied_to_ground_vec_i (7 downto 0),
840  DRPCLK => tied_to_ground_i,
841  DRPDI => tied_to_ground_vec_i (15 downto 0),
842  DRPDO => open,
843  DRPEN => tied_to_ground_i,
844  DRPRDY => open,
845  DRPWE => tied_to_ground_i,
846  ---------------------- Common Block - Ref Clock Ports ---------------------
847  GTGREFCLK => tied_to_ground_i,
848  GTNORTHREFCLK0 => tied_to_ground_i,
849  GTNORTHREFCLK1 => tied_to_ground_i,
850  GTREFCLK0 => GT0_GTREFCLK0_COMMON_IN ,
851  GTREFCLK1 => tied_to_ground_i,
852  GTSOUTHREFCLK0 => tied_to_ground_i,
853  GTSOUTHREFCLK1 => tied_to_ground_i,
854  ------------------------- Common Block - QPLL Ports -----------------------
855  QPLLDMONITOR => open,
856  ----------------------- Common Block - Clocking Ports ----------------------
857  QPLLOUTCLK => gt0_qplloutclk_i,
858  QPLLOUTREFCLK => gt0_qplloutrefclk_i ,
859  REFCLKOUTMONITOR => open,
860  ------------------------- Common Block - QPLL Ports ------------------------
861  QPLLFBCLKLOST => open,
862  QPLLLOCK => GT0_QPLLLOCK_OUT,
863  QPLLLOCKDETCLK => GT0_QPLLLOCKDETCLK_IN ,
864  QPLLLOCKEN => tied_to_vcc_i,
865  QPLLOUTRESET => tied_to_ground_i,
866  QPLLPD => tied_to_ground_i,
867  QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_OUT ,
868  QPLLREFCLKSEL => "001",
869  QPLLRESET => GT0_QPLLRESET_IN,
870  QPLLRSVD1 => "0000000000000000",
871  QPLLRSVD2 => "11111",
872  --------------------------------- QPLL Ports -------------------------------
873  BGBYPASSB => tied_to_vcc_i,
874  BGMONITORENB => tied_to_vcc_i,
875  BGPDB => tied_to_vcc_i,
876  BGRCALOVRD => "00000",
877  PMARSVD => "00000000",
878  RCALENB => tied_to_vcc_i
879 
880  );
881 
882 
883 
884 end RTL;
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