AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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serdes5gpd_hcalprod_init.vhd
1 ------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : serdes5gpd_hcalprod_init.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 -- Description : This module instantiates the modules required for
13 -- reset and initialisation of the Transceiver
14 --
15 -- Module serdes5Gpd_HCALProd_init
16 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
17 --
18 --
19 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
20 --
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64 
65 
66 library ieee;
67 use ieee.std_logic_1164.all;
68 use ieee.numeric_std.all;
69 use ieee.std_logic_unsigned.all;
70 library UNISIM;
71 use UNISIM.VCOMPONENTS.ALL;
72 
73 --***********************************Entity Declaration************************
74 
75 entity serdes5Gpd_HCALProd_init is
76 generic
77 (
78  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
79  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
80  STABLE_CLOCK_PERIOD : integer := 20; --Period of the stable clock driving this state-machine, unit is [ns]
81  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
82 
83 );
84 port
85 (
86  SYSCLK_IN : in std_logic;
87  SOFT_RESET_IN : in std_logic;
88  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
89  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
90  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
91  GT0_DATA_VALID_IN : in std_logic;
92  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
93  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
94  GT1_DATA_VALID_IN : in std_logic;
95 
96  --_________________________________________________________________________
97  --GT0 (X1Y13)
98  --____________________________CHANNEL PORTS________________________________
99  ---------------------------- Channel - DRP Ports --------------------------
100  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
101  GT0_DRPCLK_IN : in std_logic;
102  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
103  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
104  GT0_DRPEN_IN : in std_logic;
105  GT0_DRPRDY_OUT : out std_logic;
106  GT0_DRPWE_IN : in std_logic;
107  ------------------------------ Power-Down Ports ----------------------------
108  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
109  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
110  --------------------- RX Initialization and Reset Ports --------------------
111  GT0_RXUSERRDY_IN : in std_logic;
112  -------------------------- RX Margin Analysis Ports ------------------------
113  GT0_EYESCANDATAERROR_OUT : out std_logic;
114  ------------------------- Receive Ports - CDR Ports ------------------------
115  GT0_RXCDRLOCK_OUT : out std_logic;
116  ------------------- Receive Ports - Clock Correction Ports -----------------
117  GT0_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
118  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
119  GT0_RXUSRCLK_IN : in std_logic;
120  GT0_RXUSRCLK2_IN : in std_logic;
121  ------------------ Receive Ports - FPGA RX interface Ports -----------------
122  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
123  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
124  GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
125  GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
126  --------------------------- Receive Ports - RX AFE -------------------------
127  GT0_GTXRXP_IN : in std_logic;
128  ------------------------ Receive Ports - RX AFE Ports ----------------------
129  GT0_GTXRXN_IN : in std_logic;
130  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
131  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
132  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
133  GT0_RXBYTEISALIGNED_OUT : out std_logic;
134  GT0_RXBYTEREALIGN_OUT : out std_logic;
135  GT0_RXCOMMADET_OUT : out std_logic;
136  GT0_RXMCOMMAALIGNEN_IN : in std_logic;
137  GT0_RXPCOMMAALIGNEN_IN : in std_logic;
138  ------------- Receive Ports - RX Initialization and Reset Ports ------------
139  GT0_GTRXRESET_IN : in std_logic;
140  GT0_RXPMARESET_IN : in std_logic;
141  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
142  GT0_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
143  GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
144  -------------- Receive Ports -RX Initialization and Reset Ports ------------
145  GT0_RXRESETDONE_OUT : out std_logic;
146  --------------------- TX Initialization and Reset Ports --------------------
147  GT0_GTTXRESET_IN : in std_logic;
148  GT0_TXUSERRDY_IN : in std_logic;
149  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
150  GT0_TXUSRCLK_IN : in std_logic;
151  GT0_TXUSRCLK2_IN : in std_logic;
152  ------------------ Transmit Ports - TX Data Path interface -----------------
153  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
154  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
155  GT0_GTXTXN_OUT : out std_logic;
156  GT0_GTXTXP_OUT : out std_logic;
157  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
158  GT0_TXOUTCLK_OUT : out std_logic;
159  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
160  GT0_TXOUTCLKPCS_OUT : out std_logic;
161  --------------------- Transmit Ports - TX Gearbox Ports --------------------
162  GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
163  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
164  GT0_TXRESETDONE_OUT : out std_logic;
165 
166  --GT1 (X1Y14)
167  --____________________________CHANNEL PORTS________________________________
168  ---------------------------- Channel - DRP Ports --------------------------
169  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
170  GT1_DRPCLK_IN : in std_logic;
171  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
172  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
173  GT1_DRPEN_IN : in std_logic;
174  GT1_DRPRDY_OUT : out std_logic;
175  GT1_DRPWE_IN : in std_logic;
176  ------------------------------ Power-Down Ports ----------------------------
177  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
178  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
179  --------------------- RX Initialization and Reset Ports --------------------
180  GT1_RXUSERRDY_IN : in std_logic;
181  -------------------------- RX Margin Analysis Ports ------------------------
182  GT1_EYESCANDATAERROR_OUT : out std_logic;
183  ------------------------- Receive Ports - CDR Ports ------------------------
184  GT1_RXCDRLOCK_OUT : out std_logic;
185  ------------------- Receive Ports - Clock Correction Ports -----------------
186  GT1_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
187  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
188  GT1_RXUSRCLK_IN : in std_logic;
189  GT1_RXUSRCLK2_IN : in std_logic;
190  ------------------ Receive Ports - FPGA RX interface Ports -----------------
191  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
192  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
193  GT1_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
194  GT1_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
195  --------------------------- Receive Ports - RX AFE -------------------------
196  GT1_GTXRXP_IN : in std_logic;
197  ------------------------ Receive Ports - RX AFE Ports ----------------------
198  GT1_GTXRXN_IN : in std_logic;
199  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
200  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
201  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
202  GT1_RXBYTEISALIGNED_OUT : out std_logic;
203  GT1_RXBYTEREALIGN_OUT : out std_logic;
204  GT1_RXCOMMADET_OUT : out std_logic;
205  GT1_RXMCOMMAALIGNEN_IN : in std_logic;
206  GT1_RXPCOMMAALIGNEN_IN : in std_logic;
207  ------------- Receive Ports - RX Initialization and Reset Ports ------------
208  GT1_GTRXRESET_IN : in std_logic;
209  GT1_RXPMARESET_IN : in std_logic;
210  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
211  GT1_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
212  GT1_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
213  -------------- Receive Ports -RX Initialization and Reset Ports ------------
214  GT1_RXRESETDONE_OUT : out std_logic;
215  --------------------- TX Initialization and Reset Ports --------------------
216  GT1_GTTXRESET_IN : in std_logic;
217  GT1_TXUSERRDY_IN : in std_logic;
218  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
219  GT1_TXUSRCLK_IN : in std_logic;
220  GT1_TXUSRCLK2_IN : in std_logic;
221  ------------------ Transmit Ports - TX Data Path interface -----------------
222  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
223  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
224  GT1_GTXTXN_OUT : out std_logic;
225  GT1_GTXTXP_OUT : out std_logic;
226  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
227  GT1_TXOUTCLK_OUT : out std_logic;
228  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
229  GT1_TXOUTCLKPCS_OUT : out std_logic;
230  --------------------- Transmit Ports - TX Gearbox Ports --------------------
231  GT1_TXCHARISK_IN : in std_logic_vector(3 downto 0);
232  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
233  GT1_TXRESETDONE_OUT : out std_logic;
234 
235 
236  --____________________________COMMON PORTS________________________________
237  ---------------------- Common Block - Ref Clock Ports ---------------------
238  GT0_GTREFCLK0_COMMON_IN : in std_logic;
239  ------------------------- Common Block - QPLL Ports ------------------------
240  GT0_QPLLLOCK_OUT : out std_logic;
241  GT0_QPLLLOCKDETCLK_IN : in std_logic;
242  GT0_QPLLRESET_IN : in std_logic
243 
244 
245 );
246 
247 end serdes5Gpd_HCALProd_init;
248 
249 architecture RTL of serdes5Gpd_HCALProd_init is
250 
251 --**************************Component Declarations*****************************
252 
253 
254 component serdes5Gpd_HCALProd
255 generic
256 (
257  -- Simulation attributes
258  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to 1 to speed up sim reset
259 
260 );
261 port
262 (
263 
264  --_________________________________________________________________________
265  --_________________________________________________________________________
266  --GT0 (X1Y13)
267  --____________________________CHANNEL PORTS________________________________
268  ---------------------------- Channel - DRP Ports --------------------------
269  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
270  GT0_DRPCLK_IN : in std_logic;
271  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
272  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
273  GT0_DRPEN_IN : in std_logic;
274  GT0_DRPRDY_OUT : out std_logic;
275  GT0_DRPWE_IN : in std_logic;
276  ------------------------------ Power-Down Ports ----------------------------
277  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
278  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
279  --------------------- RX Initialization and Reset Ports --------------------
280  GT0_RXUSERRDY_IN : in std_logic;
281  -------------------------- RX Margin Analysis Ports ------------------------
282  GT0_EYESCANDATAERROR_OUT : out std_logic;
283  ------------------------- Receive Ports - CDR Ports ------------------------
284  GT0_RXCDRLOCK_OUT : out std_logic;
285  ------------------- Receive Ports - Clock Correction Ports -----------------
286  GT0_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
287  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
288  GT0_RXUSRCLK_IN : in std_logic;
289  GT0_RXUSRCLK2_IN : in std_logic;
290  ------------------ Receive Ports - FPGA RX interface Ports -----------------
291  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
292  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
293  GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
294  GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
295  --------------------------- Receive Ports - RX AFE -------------------------
296  GT0_GTXRXP_IN : in std_logic;
297  ------------------------ Receive Ports - RX AFE Ports ----------------------
298  GT0_GTXRXN_IN : in std_logic;
299  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
300  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
301  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
302  GT0_RXBYTEISALIGNED_OUT : out std_logic;
303  GT0_RXBYTEREALIGN_OUT : out std_logic;
304  GT0_RXCOMMADET_OUT : out std_logic;
305  GT0_RXMCOMMAALIGNEN_IN : in std_logic;
306  GT0_RXPCOMMAALIGNEN_IN : in std_logic;
307  --------------------- Receive Ports - RX Equalizer Ports -------------------
308  GT0_RXDFEAGCHOLD_IN : in std_logic;
309  GT0_RXDFELFHOLD_IN : in std_logic;
310  --------------- Receive Ports - RX Fabric Output Control Ports -------------
311  GT0_RXOUTCLK_OUT : out std_logic;
312  ------------- Receive Ports - RX Initialization and Reset Ports ------------
313  GT0_GTRXRESET_IN : in std_logic;
314  GT0_RXPMARESET_IN : in std_logic;
315  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
316  GT0_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
317  GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
318  -------------- Receive Ports -RX Initialization and Reset Ports ------------
319  GT0_RXRESETDONE_OUT : out std_logic;
320  --------------------- TX Initialization and Reset Ports --------------------
321  GT0_GTTXRESET_IN : in std_logic;
322  GT0_TXUSERRDY_IN : in std_logic;
323  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
324  GT0_TXUSRCLK_IN : in std_logic;
325  GT0_TXUSRCLK2_IN : in std_logic;
326  ------------------ Transmit Ports - TX Data Path interface -----------------
327  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
328  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
329  GT0_GTXTXN_OUT : out std_logic;
330  GT0_GTXTXP_OUT : out std_logic;
331  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
332  GT0_TXOUTCLK_OUT : out std_logic;
333  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
334  GT0_TXOUTCLKPCS_OUT : out std_logic;
335  --------------------- Transmit Ports - TX Gearbox Ports --------------------
336  GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
337  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
338  GT0_TXRESETDONE_OUT : out std_logic;
339 
340  --_________________________________________________________________________
341  --_________________________________________________________________________
342  --GT1 (X1Y14)
343  --____________________________CHANNEL PORTS________________________________
344  ---------------------------- Channel - DRP Ports --------------------------
345  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
346  GT1_DRPCLK_IN : in std_logic;
347  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
348  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
349  GT1_DRPEN_IN : in std_logic;
350  GT1_DRPRDY_OUT : out std_logic;
351  GT1_DRPWE_IN : in std_logic;
352  ------------------------------ Power-Down Ports ----------------------------
353  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
354  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
355  --------------------- RX Initialization and Reset Ports --------------------
356  GT1_RXUSERRDY_IN : in std_logic;
357  -------------------------- RX Margin Analysis Ports ------------------------
358  GT1_EYESCANDATAERROR_OUT : out std_logic;
359  ------------------------- Receive Ports - CDR Ports ------------------------
360  GT1_RXCDRLOCK_OUT : out std_logic;
361  ------------------- Receive Ports - Clock Correction Ports -----------------
362  GT1_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
363  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
364  GT1_RXUSRCLK_IN : in std_logic;
365  GT1_RXUSRCLK2_IN : in std_logic;
366  ------------------ Receive Ports - FPGA RX interface Ports -----------------
367  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
368  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
369  GT1_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
370  GT1_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
371  --------------------------- Receive Ports - RX AFE -------------------------
372  GT1_GTXRXP_IN : in std_logic;
373  ------------------------ Receive Ports - RX AFE Ports ----------------------
374  GT1_GTXRXN_IN : in std_logic;
375  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
376  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
377  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
378  GT1_RXBYTEISALIGNED_OUT : out std_logic;
379  GT1_RXBYTEREALIGN_OUT : out std_logic;
380  GT1_RXCOMMADET_OUT : out std_logic;
381  GT1_RXMCOMMAALIGNEN_IN : in std_logic;
382  GT1_RXPCOMMAALIGNEN_IN : in std_logic;
383  --------------------- Receive Ports - RX Equalizer Ports -------------------
384  GT1_RXDFEAGCHOLD_IN : in std_logic;
385  GT1_RXDFELFHOLD_IN : in std_logic;
386  --------------- Receive Ports - RX Fabric Output Control Ports -------------
387  GT1_RXOUTCLK_OUT : out std_logic;
388  ------------- Receive Ports - RX Initialization and Reset Ports ------------
389  GT1_GTRXRESET_IN : in std_logic;
390  GT1_RXPMARESET_IN : in std_logic;
391  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
392  GT1_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
393  GT1_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
394  -------------- Receive Ports -RX Initialization and Reset Ports ------------
395  GT1_RXRESETDONE_OUT : out std_logic;
396  --------------------- TX Initialization and Reset Ports --------------------
397  GT1_GTTXRESET_IN : in std_logic;
398  GT1_TXUSERRDY_IN : in std_logic;
399  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
400  GT1_TXUSRCLK_IN : in std_logic;
401  GT1_TXUSRCLK2_IN : in std_logic;
402  ------------------ Transmit Ports - TX Data Path interface -----------------
403  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
404  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
405  GT1_GTXTXN_OUT : out std_logic;
406  GT1_GTXTXP_OUT : out std_logic;
407  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
408  GT1_TXOUTCLK_OUT : out std_logic;
409  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
410  GT1_TXOUTCLKPCS_OUT : out std_logic;
411  --------------------- Transmit Ports - TX Gearbox Ports --------------------
412  GT1_TXCHARISK_IN : in std_logic_vector(3 downto 0);
413  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
414  GT1_TXRESETDONE_OUT : out std_logic;
415 
416 
417  --____________________________COMMON PORTS________________________________
418  ---------------------- Common Block - Ref Clock Ports ---------------------
419  GT0_GTREFCLK0_COMMON_IN : in std_logic;
420  ------------------------- Common Block - QPLL Ports ------------------------
421  GT0_QPLLLOCK_OUT : out std_logic;
422  GT0_QPLLLOCKDETCLK_IN : in std_logic;
423  GT0_QPLLREFCLKLOST_OUT : out std_logic;
424  GT0_QPLLRESET_IN : in std_logic
425 
426 
427 );
428 end component;
429 
430 component serdes5Gpd_HCALProd_TX_STARTUP_FSM
431  Generic(
432  GT_TYPE : string := "GTX";
433  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
434  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
435  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
436  RX_QPLL_USED : boolean := False; -- share these two generic values
437  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
438  -- is enough. For single-lane applications the automatic alignment is
439  -- sufficient
440  );
441  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
442  --or reference-clock present at startup.
443  TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
444  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
445  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
446  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
447  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
448  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
449  TXRESETDONE : in STD_LOGIC;
450  MMCM_LOCK : in STD_LOGIC;
451  GTTXRESET : out STD_LOGIC:='0';
452  MMCM_RESET : out STD_LOGIC:='0';
453  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
454  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
455  TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
456  TXUSERRDY : out STD_LOGIC:='0';
457  RUN_PHALIGNMENT : out STD_LOGIC:='0';
458  RESET_PHALIGNMENT : out STD_LOGIC:='0';
459  PHALIGNMENT_DONE : in STD_LOGIC;
460 
461  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
462  -- Retries it took to get the transceiver up and running
463  );
464 end component;
465 
466 component serdes5Gpd_HCALProd_RX_STARTUP_FSM
467  Generic(
468  EXAMPLE_SIMULATION : integer := 0;
469  EQ_MODE : string := "DFE";
470  GT_TYPE : string := "GTX";
471  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
472  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
473  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
474  RX_QPLL_USED : boolean := False; -- share these two generic values
475  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
476  -- is enough. For single-lane applications the automatic alignment is
477  -- sufficient
478  );
479  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
480  --or reference-clock present at startup.
481  RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
482  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
483  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
484  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
485  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
486  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
487  RXRESETDONE : in STD_LOGIC;
488  MMCM_LOCK : in STD_LOGIC;
489  RECCLK_STABLE : in STD_LOGIC;
490  RECCLK_MONITOR_RESTART : in STD_LOGIC;
491  DATA_VALID : in STD_LOGIC;
492  TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
493  DONT_RESET_ON_DATA_ERROR : in STD_LOGIC;
494  GTRXRESET : out STD_LOGIC:='0';
495  MMCM_RESET : out STD_LOGIC:='0';
496  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
497  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
498  RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
499  RXUSERRDY : out STD_LOGIC:='0';
500  RUN_PHALIGNMENT : out STD_LOGIC;
501  PHALIGNMENT_DONE : in STD_LOGIC;
502  RESET_PHALIGNMENT : out STD_LOGIC:='0';
503  RXDFEAGCHOLD : out STD_LOGIC;
504  RXDFELFHOLD : out STD_LOGIC;
505  RXLPMLFHOLD : out STD_LOGIC;
506  RXLPMHFHOLD : out STD_LOGIC;
507  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
508  -- Retries it took to get the transceiver up and running
509  );
510 end component;
511 
512 
513 
514 
515 
516 
517  function get_cdrlock_time(is_sim : in integer) return integer is
518  variable lock_time: integer;
519  begin
520  if (is_sim = 1) then
521  lock_time := 1000;
522  else
523  lock_time := 50000 / integer(5); --Typical CDR lock time is 50,000UI as per DS183
524  end if;
525  return lock_time;
526  end function;
527 
528 
529 --***********************************Parameter Declarations********************
530 
531  constant DLY : time := 1 ns;
532  constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us
533  constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out
534 
535  -------------------------- GT Wrapper Wires ------------------------------
536  signal gt0_txresetdone_i : std_logic;
537  signal gt0_rxresetdone_i : std_logic;
538  signal gt0_gttxreset_i : std_logic;
539  signal gt0_gttxreset_t : std_logic;
540  signal gt0_gtrxreset_i : std_logic;
541  signal gt0_gtrxreset_t : std_logic;
542  signal gt0_rxdfelpmreset_i : std_logic;
543  signal gt0_txuserrdy_i : std_logic;
544  signal gt0_txuserrdy_t : std_logic;
545  signal gt0_rxuserrdy_i : std_logic;
546  signal gt0_rxuserrdy_t : std_logic;
547 
548  signal gt0_rxdfeagchold_i : std_logic;
549  signal gt0_rxdfelfhold_i : std_logic;
550  signal gt0_rxlpmlfhold_i : std_logic;
551  signal gt0_rxlpmhfhold_i : std_logic;
552 
553 
554  signal gt1_txresetdone_i : std_logic;
555  signal gt1_rxresetdone_i : std_logic;
556  signal gt1_gttxreset_i : std_logic;
557  signal gt1_gttxreset_t : std_logic;
558  signal gt1_gtrxreset_i : std_logic;
559  signal gt1_gtrxreset_t : std_logic;
560  signal gt1_rxdfelpmreset_i : std_logic;
561  signal gt1_txuserrdy_i : std_logic;
562  signal gt1_txuserrdy_t : std_logic;
563  signal gt1_rxuserrdy_i : std_logic;
564  signal gt1_rxuserrdy_t : std_logic;
565 
566  signal gt1_rxdfeagchold_i : std_logic;
567  signal gt1_rxdfelfhold_i : std_logic;
568  signal gt1_rxlpmlfhold_i : std_logic;
569  signal gt1_rxlpmhfhold_i : std_logic;
570 
571 
572 
573  signal gt0_qpllreset_i : std_logic;
574  signal gt0_qpllreset_t : std_logic;
575  signal gt0_qpllrefclklost_i : std_logic;
576  signal gt0_qplllock_i : std_logic;
577 
578 
579  ------------------------------- Global Signals -----------------------------
580  signal tied_to_ground_i : std_logic;
581  signal tied_to_vcc_i : std_logic;
582 
583  signal gt0_rxoutclk_i : std_logic;
584  signal gt0_recclk_stable_i : std_logic;
585 
586  signal gt1_rxoutclk_i : std_logic;
587  signal gt1_recclk_stable_i : std_logic;
588 
589 
590 
591 
592 
593 
594  signal rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
595  signal rx_cdrlocked : std_logic;
596 
597 
598 
599 
600 
601 --**************************** Main Body of Code *******************************
602 begin
603  -- Static signal Assigments
604  tied_to_ground_i <= '0';
605  tied_to_vcc_i <= '1';
606 
607  ----------------------------- The GT Wrapper -----------------------------
608 
609  -- Use the instantiation template in the example directory to add the GT wrapper to your design.
610  -- In this example, the wrapper is wired up for basic operation with a frame generator and frame
611  -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
612  -- enabled, bonding should occur after alignment.
613 
614 
615  serdes5Gpd_HCALProd_i : serdes5Gpd_HCALProd
616  generic map
617  (
618  WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP
619  )
620  port map
621  (
622 
623  --_____________________________________________________________________
624  --_____________________________________________________________________
625  --GT0 (X1Y13)
626 
627  ---------------------------- Channel - DRP Ports --------------------------
628  GT0_DRPADDR_IN => GT0_DRPADDR_IN,
629  GT0_DRPCLK_IN => GT0_DRPCLK_IN,
630  GT0_DRPDI_IN => GT0_DRPDI_IN ,
631  GT0_DRPDO_OUT => GT0_DRPDO_OUT,
632  GT0_DRPEN_IN => GT0_DRPEN_IN ,
633  GT0_DRPRDY_OUT => GT0_DRPRDY_OUT,
634  GT0_DRPWE_IN => GT0_DRPWE_IN ,
635  ------------------------------ Power-Down Ports ----------------------------
636  GT0_RXPD_IN => GT0_RXPD_IN ,
637  GT0_TXPD_IN => GT0_TXPD_IN ,
638  --------------------- RX Initialization and Reset Ports --------------------
639  GT0_RXUSERRDY_IN => gt0_rxuserrdy_i,
640  -------------------------- RX Margin Analysis Ports ------------------------
641  GT0_EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
642  ------------------------- Receive Ports - CDR Ports ------------------------
643  GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
644  ------------------- Receive Ports - Clock Correction Ports -----------------
645  GT0_RXCLKCORCNT_OUT => GT0_RXCLKCORCNT_OUT ,
646  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
647  GT0_RXUSRCLK_IN => GT0_RXUSRCLK_IN,
648  GT0_RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
649  ------------------ Receive Ports - FPGA RX interface Ports -----------------
650  GT0_RXDATA_OUT => GT0_RXDATA_OUT,
651  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
652  GT0_RXDISPERR_OUT => GT0_RXDISPERR_OUT,
653  GT0_RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT ,
654  --------------------------- Receive Ports - RX AFE -------------------------
655  GT0_GTXRXP_IN => GT0_GTXRXP_IN,
656  ------------------------ Receive Ports - RX AFE Ports ----------------------
657  GT0_GTXRXN_IN => GT0_GTXRXN_IN,
658  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
659  GT0_RXBUFSTATUS_OUT => GT0_RXBUFSTATUS_OUT ,
660  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
661  GT0_RXBYTEISALIGNED_OUT => GT0_RXBYTEISALIGNED_OUT ,
662  GT0_RXBYTEREALIGN_OUT => GT0_RXBYTEREALIGN_OUT ,
663  GT0_RXCOMMADET_OUT => GT0_RXCOMMADET_OUT ,
664  GT0_RXMCOMMAALIGNEN_IN => GT0_RXMCOMMAALIGNEN_IN ,
665  GT0_RXPCOMMAALIGNEN_IN => GT0_RXPCOMMAALIGNEN_IN ,
666  --------------------- Receive Ports - RX Equalizer Ports -------------------
667  GT0_RXDFEAGCHOLD_IN => gt0_rxdfeagchold_i,
668  GT0_RXDFELFHOLD_IN => gt0_rxdfelfhold_i,
669  --------------- Receive Ports - RX Fabric Output Control Ports -------------
670  GT0_RXOUTCLK_OUT => gt0_rxoutclk_i,
671  ------------- Receive Ports - RX Initialization and Reset Ports ------------
672  GT0_GTRXRESET_IN => gt0_gtrxreset_i,
673  GT0_RXPMARESET_IN => GT0_RXPMARESET_IN,
674  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
675  GT0_RXCHARISCOMMA_OUT => GT0_RXCHARISCOMMA_OUT ,
676  GT0_RXCHARISK_OUT => GT0_RXCHARISK_OUT,
677  -------------- Receive Ports -RX Initialization and Reset Ports ------------
678  GT0_RXRESETDONE_OUT => gt0_rxresetdone_i,
679  --------------------- TX Initialization and Reset Ports --------------------
680  GT0_GTTXRESET_IN => gt0_gttxreset_i,
681  GT0_TXUSERRDY_IN => gt0_txuserrdy_i,
682  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
683  GT0_TXUSRCLK_IN => GT0_TXUSRCLK_IN,
684  GT0_TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
685  ------------------ Transmit Ports - TX Data Path interface -----------------
686  GT0_TXDATA_IN => GT0_TXDATA_IN,
687  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
688  GT0_GTXTXN_OUT => GT0_GTXTXN_OUT,
689  GT0_GTXTXP_OUT => GT0_GTXTXP_OUT,
690  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
691  GT0_TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
692  GT0_TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT ,
693  GT0_TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT ,
694  --------------------- Transmit Ports - TX Gearbox Ports --------------------
695  GT0_TXCHARISK_IN => GT0_TXCHARISK_IN,
696  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
697  GT0_TXRESETDONE_OUT => gt0_txresetdone_i,
698 
699 
700 
701  --_____________________________________________________________________
702  --_____________________________________________________________________
703  --GT1 (X1Y14)
704 
705  ---------------------------- Channel - DRP Ports --------------------------
706  GT1_DRPADDR_IN => GT1_DRPADDR_IN,
707  GT1_DRPCLK_IN => GT1_DRPCLK_IN,
708  GT1_DRPDI_IN => GT1_DRPDI_IN ,
709  GT1_DRPDO_OUT => GT1_DRPDO_OUT,
710  GT1_DRPEN_IN => GT1_DRPEN_IN ,
711  GT1_DRPRDY_OUT => GT1_DRPRDY_OUT,
712  GT1_DRPWE_IN => GT1_DRPWE_IN ,
713  ------------------------------ Power-Down Ports ----------------------------
714  GT1_RXPD_IN => GT1_RXPD_IN ,
715  GT1_TXPD_IN => GT1_TXPD_IN ,
716  --------------------- RX Initialization and Reset Ports --------------------
717  GT1_RXUSERRDY_IN => gt1_rxuserrdy_i,
718  -------------------------- RX Margin Analysis Ports ------------------------
719  GT1_EYESCANDATAERROR_OUT => GT1_EYESCANDATAERROR_OUT,
720  ------------------------- Receive Ports - CDR Ports ------------------------
721  GT1_RXCDRLOCK_OUT => GT1_RXCDRLOCK_OUT,
722  ------------------- Receive Ports - Clock Correction Ports -----------------
723  GT1_RXCLKCORCNT_OUT => GT1_RXCLKCORCNT_OUT ,
724  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
725  GT1_RXUSRCLK_IN => GT1_RXUSRCLK_IN,
726  GT1_RXUSRCLK2_IN => GT1_RXUSRCLK2_IN,
727  ------------------ Receive Ports - FPGA RX interface Ports -----------------
728  GT1_RXDATA_OUT => GT1_RXDATA_OUT,
729  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
730  GT1_RXDISPERR_OUT => GT1_RXDISPERR_OUT,
731  GT1_RXNOTINTABLE_OUT => GT1_RXNOTINTABLE_OUT ,
732  --------------------------- Receive Ports - RX AFE -------------------------
733  GT1_GTXRXP_IN => GT1_GTXRXP_IN,
734  ------------------------ Receive Ports - RX AFE Ports ----------------------
735  GT1_GTXRXN_IN => GT1_GTXRXN_IN,
736  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
737  GT1_RXBUFSTATUS_OUT => GT1_RXBUFSTATUS_OUT ,
738  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
739  GT1_RXBYTEISALIGNED_OUT => GT1_RXBYTEISALIGNED_OUT ,
740  GT1_RXBYTEREALIGN_OUT => GT1_RXBYTEREALIGN_OUT ,
741  GT1_RXCOMMADET_OUT => GT1_RXCOMMADET_OUT ,
742  GT1_RXMCOMMAALIGNEN_IN => GT1_RXMCOMMAALIGNEN_IN ,
743  GT1_RXPCOMMAALIGNEN_IN => GT1_RXPCOMMAALIGNEN_IN ,
744  --------------------- Receive Ports - RX Equalizer Ports -------------------
745  GT1_RXDFEAGCHOLD_IN => gt1_rxdfeagchold_i,
746  GT1_RXDFELFHOLD_IN => gt1_rxdfelfhold_i,
747  --------------- Receive Ports - RX Fabric Output Control Ports -------------
748  GT1_RXOUTCLK_OUT => gt1_rxoutclk_i,
749  ------------- Receive Ports - RX Initialization and Reset Ports ------------
750  GT1_GTRXRESET_IN => gt1_gtrxreset_i,
751  GT1_RXPMARESET_IN => GT1_RXPMARESET_IN,
752  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
753  GT1_RXCHARISCOMMA_OUT => GT1_RXCHARISCOMMA_OUT ,
754  GT1_RXCHARISK_OUT => GT1_RXCHARISK_OUT,
755  -------------- Receive Ports -RX Initialization and Reset Ports ------------
756  GT1_RXRESETDONE_OUT => gt1_rxresetdone_i,
757  --------------------- TX Initialization and Reset Ports --------------------
758  GT1_GTTXRESET_IN => gt1_gttxreset_i,
759  GT1_TXUSERRDY_IN => gt1_txuserrdy_i,
760  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
761  GT1_TXUSRCLK_IN => GT1_TXUSRCLK_IN,
762  GT1_TXUSRCLK2_IN => GT1_TXUSRCLK2_IN,
763  ------------------ Transmit Ports - TX Data Path interface -----------------
764  GT1_TXDATA_IN => GT1_TXDATA_IN,
765  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
766  GT1_GTXTXN_OUT => GT1_GTXTXN_OUT,
767  GT1_GTXTXP_OUT => GT1_GTXTXP_OUT,
768  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
769  GT1_TXOUTCLK_OUT => GT1_TXOUTCLK_OUT,
770  GT1_TXOUTCLKFABRIC_OUT => GT1_TXOUTCLKFABRIC_OUT ,
771  GT1_TXOUTCLKPCS_OUT => GT1_TXOUTCLKPCS_OUT ,
772  --------------------- Transmit Ports - TX Gearbox Ports --------------------
773  GT1_TXCHARISK_IN => GT1_TXCHARISK_IN,
774  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
775  GT1_TXRESETDONE_OUT => gt1_txresetdone_i,
776 
777 
778 
779 
780  --____________________________COMMON PORTS________________________________
781  ---------------------- Common Block - Ref Clock Ports ---------------------
782  GT0_GTREFCLK0_COMMON_IN => GT0_GTREFCLK0_COMMON_IN ,
783  ------------------------- Common Block - QPLL Ports ------------------------
784  GT0_QPLLLOCK_OUT => gt0_qplllock_i,
785  GT0_QPLLLOCKDETCLK_IN => GT0_QPLLLOCKDETCLK_IN ,
786  GT0_QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i ,
787  GT0_QPLLRESET_IN => gt0_qpllreset_i
788 
789  );
790 
791 
792  gt0_rxdfelpmreset_i <= tied_to_ground_i;
793  gt1_rxdfelpmreset_i <= tied_to_ground_i;
794 
795 
796 
797 
798  GT0_TXRESETDONE_OUT <= gt0_txresetdone_i;
799  GT0_RXRESETDONE_OUT <= gt0_rxresetdone_i;
800  GT1_TXRESETDONE_OUT <= gt1_txresetdone_i;
801  GT1_RXRESETDONE_OUT <= gt1_rxresetdone_i;
802  GT0_QPLLLOCK_OUT <= gt0_qplllock_i;
803 
804 chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
805  gt0_gttxreset_i <= GT0_GTTXRESET_IN or gt0_gttxreset_t;
806  gt0_gtrxreset_i <= GT0_GTRXRESET_IN or gt0_gtrxreset_t;
807  gt0_txuserrdy_i <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t;
808  gt0_rxuserrdy_i <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t;
809  gt1_gttxreset_i <= GT1_GTTXRESET_IN or gt1_gttxreset_t;
810  gt1_gtrxreset_i <= GT1_GTRXRESET_IN or gt1_gtrxreset_t;
811  gt1_txuserrdy_i <= GT1_TXUSERRDY_IN or gt1_txuserrdy_t;
812  gt1_rxuserrdy_i <= GT1_RXUSERRDY_IN or gt1_rxuserrdy_t;
813  gt0_qpllreset_i <= GT0_QPLLRESET_IN or gt0_qpllreset_t;
814 end generate chipscope;
815 
816 no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
817  gt0_gttxreset_i <= gt0_gttxreset_t;
818  gt0_gtrxreset_i <= gt0_gtrxreset_t;
819  gt0_txuserrdy_i <= gt0_txuserrdy_t;
820  gt0_rxuserrdy_i <= gt0_rxuserrdy_t;
821  gt1_gttxreset_i <= gt1_gttxreset_t;
822  gt1_gtrxreset_i <= gt1_gtrxreset_t;
823  gt1_txuserrdy_i <= gt1_txuserrdy_t;
824  gt1_rxuserrdy_i <= gt1_rxuserrdy_t;
825  gt0_qpllreset_i <= gt0_qpllreset_t;
826 end generate no_chipscope;
827 
828 
829 gt0_txresetfsm_i: serdes5Gpd_HCALProd_TX_STARTUP_FSM
830 
831  generic map(
832  GT_TYPE => "GTX", --GTX or GTH or GTP
833  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
834  RETRY_COUNTER_BITWIDTH => 8,
835  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
836  RX_QPLL_USED => TRUE, -- share these two generic values
837  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
838  -- is enough. For single-lane applications the automatic alignment is
839  -- sufficient
840  )
841  port map (
842  STABLE_CLOCK => SYSCLK_IN,
843  TXUSERCLK => GT0_TXUSRCLK_IN,
844  SOFT_RESET => SOFT_RESET_IN,
845  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
846  CPLLREFCLKLOST => tied_to_ground_i,
847  QPLLLOCK => gt0_qplllock_i,
848  CPLLLOCK => tied_to_vcc_i,
849  TXRESETDONE => gt0_txresetdone_i,
850  MMCM_LOCK => tied_to_vcc_i,
851  GTTXRESET => gt0_gttxreset_t,
852  MMCM_RESET => open,
853  QPLL_RESET => gt0_qpllreset_t,
854  CPLL_RESET => open,
855  TX_FSM_RESET_DONE => GT0_TX_FSM_RESET_DONE_OUT,
856  TXUSERRDY => gt0_txuserrdy_t,
857  RUN_PHALIGNMENT => open,
858  RESET_PHALIGNMENT => open,
859  PHALIGNMENT_DONE => tied_to_vcc_i,
860  RETRY_COUNTER => open
861  );
862 
863 
864 gt1_txresetfsm_i: serdes5Gpd_HCALProd_TX_STARTUP_FSM
865 
866  generic map(
867  GT_TYPE => "GTX", --GTX or GTH or GTP
868  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
869  RETRY_COUNTER_BITWIDTH => 8,
870  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
871  RX_QPLL_USED => TRUE, -- share these two generic values
872  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
873  -- is enough. For single-lane applications the automatic alignment is
874  -- sufficient
875  )
876  port map (
877  STABLE_CLOCK => SYSCLK_IN,
878  TXUSERCLK => GT1_TXUSRCLK_IN,
879  SOFT_RESET => SOFT_RESET_IN,
880  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
881  CPLLREFCLKLOST => tied_to_ground_i,
882  QPLLLOCK => gt0_qplllock_i,
883  CPLLLOCK => tied_to_vcc_i,
884  TXRESETDONE => gt1_txresetdone_i,
885  MMCM_LOCK => tied_to_vcc_i,
886  GTTXRESET => gt1_gttxreset_t,
887  MMCM_RESET => open,
888  QPLL_RESET => open,
889  CPLL_RESET => open,
890  TX_FSM_RESET_DONE => GT1_TX_FSM_RESET_DONE_OUT,
891  TXUSERRDY => gt1_txuserrdy_t,
892  RUN_PHALIGNMENT => open,
893  RESET_PHALIGNMENT => open,
894  PHALIGNMENT_DONE => tied_to_vcc_i,
895  RETRY_COUNTER => open
896  );
897 
898 
899 
900 
901 
902 
903 gt0_rxresetfsm_i: serdes5Gpd_HCALProd_RX_STARTUP_FSM
904 
905  generic map(
906  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
907  GT_TYPE => "GTX", --GTX or GTH or GTP
908  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
909  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
910  RETRY_COUNTER_BITWIDTH => 8,
911  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
912  RX_QPLL_USED => TRUE, -- share these two generic values
913  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
914  -- is enough. For single-lane applications the automatic alignment is
915  -- sufficient
916  )
917  port map (
918  STABLE_CLOCK => SYSCLK_IN,
919  RXUSERCLK => GT0_RXUSRCLK_IN,
920  SOFT_RESET => SOFT_RESET_IN,
921  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
922  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
923  CPLLREFCLKLOST => tied_to_ground_i,
924  QPLLLOCK => gt0_qplllock_i,
925  CPLLLOCK => tied_to_vcc_i,
926  RXRESETDONE => gt0_rxresetdone_i,
927  MMCM_LOCK => tied_to_vcc_i,
928  RECCLK_STABLE => gt0_recclk_stable_i ,
929  RECCLK_MONITOR_RESTART => tied_to_ground_i,
930  DATA_VALID => GT0_DATA_VALID_IN,
931  TXUSERRDY => gt0_txuserrdy_i,
932  GTRXRESET => gt0_gtrxreset_t,
933  MMCM_RESET => open,
934  QPLL_RESET => open,
935  CPLL_RESET => open,
936  RX_FSM_RESET_DONE => GT0_RX_FSM_RESET_DONE_OUT,
937  RXUSERRDY => gt0_rxuserrdy_t,
938  RUN_PHALIGNMENT => open,
939  RESET_PHALIGNMENT => open,
940  PHALIGNMENT_DONE => tied_to_vcc_i,
941  RXDFEAGCHOLD => gt0_rxdfeagchold_i ,
942  RXDFELFHOLD => gt0_rxdfelfhold_i,
943  RXLPMLFHOLD => gt0_rxlpmlfhold_i,
944  RXLPMHFHOLD => gt0_rxlpmhfhold_i,
945  RETRY_COUNTER => open
946  );
947 
948 gt1_rxresetfsm_i: serdes5Gpd_HCALProd_RX_STARTUP_FSM
949 
950  generic map(
951  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
952  GT_TYPE => "GTX", --GTX or GTH or GTP
953  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
954  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
955  RETRY_COUNTER_BITWIDTH => 8,
956  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
957  RX_QPLL_USED => TRUE, -- share these two generic values
958  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
959  -- is enough. For single-lane applications the automatic alignment is
960  -- sufficient
961  )
962  port map (
963  STABLE_CLOCK => SYSCLK_IN,
964  RXUSERCLK => GT1_RXUSRCLK_IN,
965  SOFT_RESET => SOFT_RESET_IN,
966  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
967  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
968  CPLLREFCLKLOST => tied_to_ground_i,
969  QPLLLOCK => gt0_qplllock_i,
970  CPLLLOCK => tied_to_vcc_i,
971  RXRESETDONE => gt1_rxresetdone_i,
972  MMCM_LOCK => tied_to_vcc_i,
973  RECCLK_STABLE => gt1_recclk_stable_i ,
974  RECCLK_MONITOR_RESTART => tied_to_ground_i,
975  DATA_VALID => GT1_DATA_VALID_IN,
976  TXUSERRDY => gt1_txuserrdy_i,
977  GTRXRESET => gt1_gtrxreset_t,
978  MMCM_RESET => open,
979  QPLL_RESET => open,
980  CPLL_RESET => open,
981  RX_FSM_RESET_DONE => GT1_RX_FSM_RESET_DONE_OUT,
982  RXUSERRDY => gt1_rxuserrdy_t,
983  RUN_PHALIGNMENT => open,
984  RESET_PHALIGNMENT => open,
985  PHALIGNMENT_DONE => tied_to_vcc_i,
986  RXDFEAGCHOLD => gt1_rxdfeagchold_i ,
987  RXDFELFHOLD => gt1_rxdfelfhold_i,
988  RXLPMLFHOLD => gt1_rxlpmlfhold_i,
989  RXLPMHFHOLD => gt1_rxlpmhfhold_i,
990  RETRY_COUNTER => open
991  );
992 
993 
994 
995  cdrlock_timeout:process(SYSCLK_IN)
996  begin
997  if rising_edge(SYSCLK_IN) then
998  if(gt0_gtrxreset_i = '1') then
999  rx_cdrlocked <= '0';
1000  rx_cdrlock_counter <= 0 after DLY;
1001  elsif (rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
1002  rx_cdrlocked <= '1';
1003  rx_cdrlock_counter <= rx_cdrlock_counter after DLY;
1004  else
1005  rx_cdrlock_counter <= rx_cdrlock_counter + 1 after DLY;
1006  end if;
1007  end if;
1008  end process;
1009 
1010 gt0_recclk_stable_i <= rx_cdrlocked;
1011 gt1_recclk_stable_i <= rx_cdrlocked;
1012 
1013 
1014 
1015 
1016 
1017 
1018 
1019 end RTL;
1020 
1021 
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