AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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serdes5gpd_hcalprod.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : serdes5gpd_hcalprod.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module serdes5Gpd_HCALProd (a GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 library UNISIM;
68 use UNISIM.VCOMPONENTS.ALL;
69 
70 
71 --***************************** Entity Declaration ****************************
72 
73 entity serdes5Gpd_HCALProd is
74 generic
75 (
76  QPLL_FBDIV_TOP : integer := 80;
77 
78  -- Simulation attributes
79  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
80  RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
81  PMA_RSV_IN : bit_vector := x"001E7080"
82 
83 );
84 port
85 (
86  --_________________________________________________________________________
87  --_________________________________________________________________________
88  --GT0 (X0Y13)
89  --____________________________CHANNEL PORTS________________________________
90  ---------------------------- Channel - DRP Ports --------------------------
91  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
92  GT0_DRPCLK_IN : in std_logic;
93  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
94  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
95  GT0_DRPEN_IN : in std_logic;
96  GT0_DRPRDY_OUT : out std_logic;
97  GT0_DRPWE_IN : in std_logic;
98  ------------------------------ Power-Down Ports ----------------------------
99  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
100  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
101  --------------------- RX Initialization and Reset Ports --------------------
102  GT0_RXUSERRDY_IN : in std_logic;
103  -------------------------- RX Margin Analysis Ports ------------------------
104  GT0_EYESCANDATAERROR_OUT : out std_logic;
105  ------------------------- Receive Ports - CDR Ports ------------------------
106  GT0_RXCDRLOCK_OUT : out std_logic;
107  ------------------- Receive Ports - Clock Correction Ports -----------------
108  GT0_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
109  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
110  GT0_RXUSRCLK_IN : in std_logic;
111  GT0_RXUSRCLK2_IN : in std_logic;
112  ------------------ Receive Ports - FPGA RX interface Ports -----------------
113  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
114  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
115  GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
116  GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
117  --------------------------- Receive Ports - RX AFE -------------------------
118  GT0_GTXRXP_IN : in std_logic;
119  ------------------------ Receive Ports - RX AFE Ports ----------------------
120  GT0_GTXRXN_IN : in std_logic;
121  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
122  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
123  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
124  GT0_RXBYTEISALIGNED_OUT : out std_logic;
125  GT0_RXBYTEREALIGN_OUT : out std_logic;
126  GT0_RXCOMMADET_OUT : out std_logic;
127  GT0_RXMCOMMAALIGNEN_IN : in std_logic;
128  GT0_RXPCOMMAALIGNEN_IN : in std_logic;
129  --------------------- Receive Ports - RX Equalizer Ports -------------------
130  GT0_RXDFEAGCHOLD_IN : in std_logic;
131  GT0_RXDFELFHOLD_IN : in std_logic;
132  --------------- Receive Ports - RX Fabric Output Control Ports -------------
133  GT0_RXOUTCLK_OUT : out std_logic;
134  ------------- Receive Ports - RX Initialization and Reset Ports ------------
135  GT0_GTRXRESET_IN : in std_logic;
136  GT0_RXPMARESET_IN : in std_logic;
137  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
138  GT0_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
139  GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
140  -------------- Receive Ports -RX Initialization and Reset Ports ------------
141  GT0_RXRESETDONE_OUT : out std_logic;
142  --------------------- TX Initialization and Reset Ports --------------------
143  GT0_GTTXRESET_IN : in std_logic;
144  GT0_TXUSERRDY_IN : in std_logic;
145  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
146  GT0_TXUSRCLK_IN : in std_logic;
147  GT0_TXUSRCLK2_IN : in std_logic;
148  ------------------ Transmit Ports - TX Data Path interface -----------------
149  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
150  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
151  GT0_GTXTXN_OUT : out std_logic;
152  GT0_GTXTXP_OUT : out std_logic;
153  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
154  GT0_TXOUTCLK_OUT : out std_logic;
155  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
156  GT0_TXOUTCLKPCS_OUT : out std_logic;
157  --------------------- Transmit Ports - TX Gearbox Ports --------------------
158  GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
159  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
160  GT0_TXRESETDONE_OUT : out std_logic;
161 
162  --GT1 (X0Y14)
163  --____________________________CHANNEL PORTS________________________________
164  ---------------------------- Channel - DRP Ports --------------------------
165  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
166  GT1_DRPCLK_IN : in std_logic;
167  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
168  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
169  GT1_DRPEN_IN : in std_logic;
170  GT1_DRPRDY_OUT : out std_logic;
171  GT1_DRPWE_IN : in std_logic;
172  ------------------------------ Power-Down Ports ----------------------------
173  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
174  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
175  --------------------- RX Initialization and Reset Ports --------------------
176  GT1_RXUSERRDY_IN : in std_logic;
177  -------------------------- RX Margin Analysis Ports ------------------------
178  GT1_EYESCANDATAERROR_OUT : out std_logic;
179  ------------------------- Receive Ports - CDR Ports ------------------------
180  GT1_RXCDRLOCK_OUT : out std_logic;
181  ------------------- Receive Ports - Clock Correction Ports -----------------
182  GT1_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
183  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
184  GT1_RXUSRCLK_IN : in std_logic;
185  GT1_RXUSRCLK2_IN : in std_logic;
186  ------------------ Receive Ports - FPGA RX interface Ports -----------------
187  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
188  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
189  GT1_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
190  GT1_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
191  --------------------------- Receive Ports - RX AFE -------------------------
192  GT1_GTXRXP_IN : in std_logic;
193  ------------------------ Receive Ports - RX AFE Ports ----------------------
194  GT1_GTXRXN_IN : in std_logic;
195  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
196  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
197  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
198  GT1_RXBYTEISALIGNED_OUT : out std_logic;
199  GT1_RXBYTEREALIGN_OUT : out std_logic;
200  GT1_RXCOMMADET_OUT : out std_logic;
201  GT1_RXMCOMMAALIGNEN_IN : in std_logic;
202  GT1_RXPCOMMAALIGNEN_IN : in std_logic;
203  --------------------- Receive Ports - RX Equalizer Ports -------------------
204  GT1_RXDFEAGCHOLD_IN : in std_logic;
205  GT1_RXDFELFHOLD_IN : in std_logic;
206  --------------- Receive Ports - RX Fabric Output Control Ports -------------
207  GT1_RXOUTCLK_OUT : out std_logic;
208  ------------- Receive Ports - RX Initialization and Reset Ports ------------
209  GT1_GTRXRESET_IN : in std_logic;
210  GT1_RXPMARESET_IN : in std_logic;
211  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
212  GT1_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
213  GT1_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
214  -------------- Receive Ports -RX Initialization and Reset Ports ------------
215  GT1_RXRESETDONE_OUT : out std_logic;
216  --------------------- TX Initialization and Reset Ports --------------------
217  GT1_GTTXRESET_IN : in std_logic;
218  GT1_TXUSERRDY_IN : in std_logic;
219  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
220  GT1_TXUSRCLK_IN : in std_logic;
221  GT1_TXUSRCLK2_IN : in std_logic;
222  ------------------ Transmit Ports - TX Data Path interface -----------------
223  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
224  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
225  GT1_GTXTXN_OUT : out std_logic;
226  GT1_GTXTXP_OUT : out std_logic;
227  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
228  GT1_TXOUTCLK_OUT : out std_logic;
229  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
230  GT1_TXOUTCLKPCS_OUT : out std_logic;
231  --------------------- Transmit Ports - TX Gearbox Ports --------------------
232  GT1_TXCHARISK_IN : in std_logic_vector(3 downto 0);
233  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
234  GT1_TXRESETDONE_OUT : out std_logic;
235 
236 
237  --____________________________COMMON PORTS________________________________
238  ---------------------- Common Block - Ref Clock Ports ---------------------
239  GT0_GTREFCLK0_COMMON_IN : in std_logic;
240  ------------------------- Common Block - QPLL Ports ------------------------
241  GT0_QPLLLOCK_OUT : out std_logic;
242  GT0_QPLLLOCKDETCLK_IN : in std_logic;
243  GT0_QPLLREFCLKLOST_OUT : out std_logic;
244  GT0_QPLLRESET_IN : in std_logic
245 
246 
247 );
248 
249 
250 end serdes5Gpd_HCALProd;
251 
252 architecture RTL of serdes5Gpd_HCALProd is
253 
254  attribute CORE_GENERATION_INFO : string;
255  attribute CORE_GENERATION_INFO of RTL : architecture is "serdes5Gpd_HCALProd,gtwizard_v2_7,{protocol_file=Start_from_scratch}";
256 
257 
258 --***********************************Parameter Declarations********************
259 
260  constant DLY : time := 1 ns;
261 
262 --***************************** Signal Declarations *****************************
263 
264  -- ground and tied_to_vcc_i signals
265  signal tied_to_ground_i : std_logic;
266  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
267  signal tied_to_vcc_i : std_logic;
268  signal gt0_qplloutclk_i : std_logic;
269  signal gt0_qplloutrefclk_i : std_logic;
270 
271 
272  signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0);
273  signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0);
274 
275  signal gt1_mgtrefclktx_i : std_logic_vector(1 downto 0);
276  signal gt1_mgtrefclkrx_i : std_logic_vector(1 downto 0);
277 
278 
279  signal gt0_qpllclk_i : std_logic;
280  signal gt0_qpllrefclk_i : std_logic;
281  signal gt1_qpllclk_i : std_logic;
282  signal gt1_qpllrefclk_i : std_logic;
283 
284 
285 --*************************** Component Declarations **************************
286 component serdes5Gpd_HCALProd_GT
287 generic
288 (
289  -- Simulation attributes
290  GT_SIM_GTRESET_SPEEDUP : string := "FALSE";
291  RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
292  PMA_RSV_IN : bit_vector := X"00000000";
293  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
294 );
295 port
296 (
297  ---------------------------- Channel - DRP Ports --------------------------
298  DRPADDR_IN : in std_logic_vector(8 downto 0);
299  DRPCLK_IN : in std_logic;
300  DRPDI_IN : in std_logic_vector(15 downto 0);
301  DRPDO_OUT : out std_logic_vector(15 downto 0);
302  DRPEN_IN : in std_logic;
303  DRPRDY_OUT : out std_logic;
304  DRPWE_IN : in std_logic;
305  ------------------------------- Clocking Ports -----------------------------
306  QPLLCLK_IN : in std_logic;
307  QPLLREFCLK_IN : in std_logic;
308  ------------------------------ Power-Down Ports ----------------------------
309  RXPD_IN : in std_logic_vector(1 downto 0);
310  TXPD_IN : in std_logic_vector(1 downto 0);
311  --------------------- RX Initialization and Reset Ports --------------------
312  RXUSERRDY_IN : in std_logic;
313  -------------------------- RX Margin Analysis Ports ------------------------
314  EYESCANDATAERROR_OUT : out std_logic;
315  ------------------------- Receive Ports - CDR Ports ------------------------
316  RXCDRLOCK_OUT : out std_logic;
317  ------------------- Receive Ports - Clock Correction Ports -----------------
318  RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
319  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
320  RXUSRCLK_IN : in std_logic;
321  RXUSRCLK2_IN : in std_logic;
322  ------------------ Receive Ports - FPGA RX interface Ports -----------------
323  RXDATA_OUT : out std_logic_vector(31 downto 0);
324  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
325  RXDISPERR_OUT : out std_logic_vector(3 downto 0);
326  RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
327  --------------------------- Receive Ports - RX AFE -------------------------
328  GTXRXP_IN : in std_logic;
329  ------------------------ Receive Ports - RX AFE Ports ----------------------
330  GTXRXN_IN : in std_logic;
331  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
332  RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
333  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
334  RXBYTEISALIGNED_OUT : out std_logic;
335  RXBYTEREALIGN_OUT : out std_logic;
336  RXCOMMADET_OUT : out std_logic;
337  RXMCOMMAALIGNEN_IN : in std_logic;
338  RXPCOMMAALIGNEN_IN : in std_logic;
339  --------------------- Receive Ports - RX Equalizer Ports -------------------
340  RXDFEAGCHOLD_IN : in std_logic;
341  RXDFELFHOLD_IN : in std_logic;
342  --------------- Receive Ports - RX Fabric Output Control Ports -------------
343  RXOUTCLK_OUT : out std_logic;
344  ------------- Receive Ports - RX Initialization and Reset Ports ------------
345  GTRXRESET_IN : in std_logic;
346  RXPMARESET_IN : in std_logic;
347  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
348  RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
349  RXCHARISK_OUT : out std_logic_vector(3 downto 0);
350  -------------- Receive Ports -RX Initialization and Reset Ports ------------
351  RXRESETDONE_OUT : out std_logic;
352  --------------------- TX Initialization and Reset Ports --------------------
353  GTTXRESET_IN : in std_logic;
354  TXUSERRDY_IN : in std_logic;
355  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
356  TXUSRCLK_IN : in std_logic;
357  TXUSRCLK2_IN : in std_logic;
358  ------------------ Transmit Ports - TX Data Path interface -----------------
359  TXDATA_IN : in std_logic_vector(31 downto 0);
360  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
361  GTXTXN_OUT : out std_logic;
362  GTXTXP_OUT : out std_logic;
363  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
364  TXOUTCLK_OUT : out std_logic;
365  TXOUTCLKFABRIC_OUT : out std_logic;
366  TXOUTCLKPCS_OUT : out std_logic;
367  --------------------- Transmit Ports - TX Gearbox Ports --------------------
368  TXCHARISK_IN : in std_logic_vector(3 downto 0);
369  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
370  TXRESETDONE_OUT : out std_logic
371 
372 
373 );
374 end component;
375 
376 
377 
378 --*************************Logic to set Attribute QPLL_FB_DIV*****************************
379  impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
380  begin
381  if (qpllfbdiv_top = 16) then
382  return "0000100000";
383  elsif (qpllfbdiv_top = 20) then
384  return "0000110000" ;
385  elsif (qpllfbdiv_top = 32) then
386  return "0001100000" ;
387  elsif (qpllfbdiv_top = 40) then
388  return "0010000000" ;
389  elsif (qpllfbdiv_top = 64) then
390  return "0011100000" ;
391  elsif (qpllfbdiv_top = 66) then
392  return "0101000000" ;
393  elsif (qpllfbdiv_top = 80) then
394  return "0100100000" ;
395  elsif (qpllfbdiv_top = 100) then
396  return "0101110000" ;
397  else
398  return "0000000000" ;
399  end if;
400  end function;
401 
402  impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
403  begin
404  if (qpllfbdiv_top = 16) then
405  return '1';
406  elsif (qpllfbdiv_top = 20) then
407  return '1' ;
408  elsif (qpllfbdiv_top = 32) then
409  return '1' ;
410  elsif (qpllfbdiv_top = 40) then
411  return '1' ;
412  elsif (qpllfbdiv_top = 64) then
413  return '1' ;
414  elsif (qpllfbdiv_top = 66) then
415  return '0' ;
416  elsif (qpllfbdiv_top = 80) then
417  return '1' ;
418  elsif (qpllfbdiv_top = 100) then
419  return '1' ;
420  else
421  return '1' ;
422  end if;
423  end function;
424 
425  constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
426  constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
427 
428 --********************************* Main Body of Code**************************
429 
430 begin
431 
432  tied_to_ground_i <= '0';
433  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
434  tied_to_vcc_i <= '1';
435  gt0_qpllclk_i <= gt0_qplloutclk_i;
436  gt0_qpllrefclk_i <= gt0_qplloutrefclk_i;
437 
438  gt1_qpllclk_i <= gt0_qplloutclk_i;
439  gt1_qpllrefclk_i <= gt0_qplloutrefclk_i;
440 
441 
442 
443  --------------------------- GT Instances -------------------------------
444 
445  --_________________________________________________________________________
446  --_________________________________________________________________________
447  --GT0 (X0Y13)
448 
449  gt0_serdes5Gpd_HCALProd_i : serdes5Gpd_HCALProd_GT
450  generic map
451  (
452  -- Simulation attributes
453  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
454  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
455  PMA_RSV_IN => PMA_RSV_IN,
456  PCS_RSVD_ATTR_IN => X"000000000000"
457  )
458  port map
459  (
460  ---------------------------- Channel - DRP Ports --------------------------
461  DRPADDR_IN => GT0_DRPADDR_IN,
462  DRPCLK_IN => GT0_DRPCLK_IN,
463  DRPDI_IN => GT0_DRPDI_IN ,
464  DRPDO_OUT => GT0_DRPDO_OUT,
465  DRPEN_IN => GT0_DRPEN_IN ,
466  DRPRDY_OUT => GT0_DRPRDY_OUT,
467  DRPWE_IN => GT0_DRPWE_IN ,
468  ------------------------------- Clocking Ports -----------------------------
469  QPLLCLK_IN => gt0_qpllclk_i,
470  QPLLREFCLK_IN => gt0_qpllrefclk_i,
471  ------------------------------ Power-Down Ports ----------------------------
472  RXPD_IN => GT0_RXPD_IN ,
473  TXPD_IN => GT0_TXPD_IN ,
474  --------------------- RX Initialization and Reset Ports --------------------
475  RXUSERRDY_IN => GT0_RXUSERRDY_IN,
476  -------------------------- RX Margin Analysis Ports ------------------------
477  EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
478  ------------------------- Receive Ports - CDR Ports ------------------------
479  RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
480  ------------------- Receive Ports - Clock Correction Ports -----------------
481  RXCLKCORCNT_OUT => GT0_RXCLKCORCNT_OUT ,
482  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
483  RXUSRCLK_IN => GT0_RXUSRCLK_IN,
484  RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
485  ------------------ Receive Ports - FPGA RX interface Ports -----------------
486  RXDATA_OUT => GT0_RXDATA_OUT,
487  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
488  RXDISPERR_OUT => GT0_RXDISPERR_OUT,
489  RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT ,
490  --------------------------- Receive Ports - RX AFE -------------------------
491  GTXRXP_IN => GT0_GTXRXP_IN,
492  ------------------------ Receive Ports - RX AFE Ports ----------------------
493  GTXRXN_IN => GT0_GTXRXN_IN,
494  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
495  RXBUFSTATUS_OUT => GT0_RXBUFSTATUS_OUT ,
496  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
497  RXBYTEISALIGNED_OUT => GT0_RXBYTEISALIGNED_OUT ,
498  RXBYTEREALIGN_OUT => GT0_RXBYTEREALIGN_OUT ,
499  RXCOMMADET_OUT => GT0_RXCOMMADET_OUT,
500  RXMCOMMAALIGNEN_IN => GT0_RXMCOMMAALIGNEN_IN ,
501  RXPCOMMAALIGNEN_IN => GT0_RXPCOMMAALIGNEN_IN ,
502  --------------------- Receive Ports - RX Equalizer Ports -------------------
503  RXDFEAGCHOLD_IN => GT0_RXDFEAGCHOLD_IN ,
504  RXDFELFHOLD_IN => GT0_RXDFELFHOLD_IN,
505  --------------- Receive Ports - RX Fabric Output Control Ports -------------
506  RXOUTCLK_OUT => GT0_RXOUTCLK_OUT,
507  ------------- Receive Ports - RX Initialization and Reset Ports ------------
508  GTRXRESET_IN => GT0_GTRXRESET_IN,
509  RXPMARESET_IN => GT0_RXPMARESET_IN,
510  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
511  RXCHARISCOMMA_OUT => GT0_RXCHARISCOMMA_OUT ,
512  RXCHARISK_OUT => GT0_RXCHARISK_OUT,
513  -------------- Receive Ports -RX Initialization and Reset Ports ------------
514  RXRESETDONE_OUT => GT0_RXRESETDONE_OUT ,
515  --------------------- TX Initialization and Reset Ports --------------------
516  GTTXRESET_IN => GT0_GTTXRESET_IN,
517  TXUSERRDY_IN => GT0_TXUSERRDY_IN,
518  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
519  TXUSRCLK_IN => GT0_TXUSRCLK_IN,
520  TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
521  ------------------ Transmit Ports - TX Data Path interface -----------------
522  TXDATA_IN => GT0_TXDATA_IN,
523  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
524  GTXTXN_OUT => GT0_GTXTXN_OUT,
525  GTXTXP_OUT => GT0_GTXTXP_OUT,
526  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
527  TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
528  TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT ,
529  TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT ,
530  --------------------- Transmit Ports - TX Gearbox Ports --------------------
531  TXCHARISK_IN => GT0_TXCHARISK_IN,
532  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
533  TXRESETDONE_OUT => GT0_TXRESETDONE_OUT
534 
535  );
536 
537  --_________________________________________________________________________
538  --_________________________________________________________________________
539  --GT1 (X0Y14)
540 
541  gt1_serdes5Gpd_HCALProd_i : serdes5Gpd_HCALProd_GT
542  generic map
543  (
544  -- Simulation attributes
545  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
546  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
547  PMA_RSV_IN => PMA_RSV_IN,
548  PCS_RSVD_ATTR_IN => X"000000000000"
549  )
550  port map
551  (
552  ---------------------------- Channel - DRP Ports --------------------------
553  DRPADDR_IN => GT1_DRPADDR_IN,
554  DRPCLK_IN => GT1_DRPCLK_IN,
555  DRPDI_IN => GT1_DRPDI_IN ,
556  DRPDO_OUT => GT1_DRPDO_OUT,
557  DRPEN_IN => GT1_DRPEN_IN ,
558  DRPRDY_OUT => GT1_DRPRDY_OUT,
559  DRPWE_IN => GT1_DRPWE_IN ,
560  ------------------------------- Clocking Ports -----------------------------
561  QPLLCLK_IN => gt1_qpllclk_i,
562  QPLLREFCLK_IN => gt1_qpllrefclk_i,
563  ------------------------------ Power-Down Ports ----------------------------
564  RXPD_IN => GT1_RXPD_IN ,
565  TXPD_IN => GT1_TXPD_IN ,
566  --------------------- RX Initialization and Reset Ports --------------------
567  RXUSERRDY_IN => GT1_RXUSERRDY_IN,
568  -------------------------- RX Margin Analysis Ports ------------------------
569  EYESCANDATAERROR_OUT => GT1_EYESCANDATAERROR_OUT,
570  ------------------------- Receive Ports - CDR Ports ------------------------
571  RXCDRLOCK_OUT => GT1_RXCDRLOCK_OUT,
572  ------------------- Receive Ports - Clock Correction Ports -----------------
573  RXCLKCORCNT_OUT => GT1_RXCLKCORCNT_OUT ,
574  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
575  RXUSRCLK_IN => GT1_RXUSRCLK_IN,
576  RXUSRCLK2_IN => GT1_RXUSRCLK2_IN,
577  ------------------ Receive Ports - FPGA RX interface Ports -----------------
578  RXDATA_OUT => GT1_RXDATA_OUT,
579  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
580  RXDISPERR_OUT => GT1_RXDISPERR_OUT,
581  RXNOTINTABLE_OUT => GT1_RXNOTINTABLE_OUT ,
582  --------------------------- Receive Ports - RX AFE -------------------------
583  GTXRXP_IN => GT1_GTXRXP_IN,
584  ------------------------ Receive Ports - RX AFE Ports ----------------------
585  GTXRXN_IN => GT1_GTXRXN_IN,
586  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
587  RXBUFSTATUS_OUT => GT1_RXBUFSTATUS_OUT ,
588  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
589  RXBYTEISALIGNED_OUT => GT1_RXBYTEISALIGNED_OUT ,
590  RXBYTEREALIGN_OUT => GT1_RXBYTEREALIGN_OUT ,
591  RXCOMMADET_OUT => GT1_RXCOMMADET_OUT,
592  RXMCOMMAALIGNEN_IN => GT1_RXMCOMMAALIGNEN_IN ,
593  RXPCOMMAALIGNEN_IN => GT1_RXPCOMMAALIGNEN_IN ,
594  --------------------- Receive Ports - RX Equalizer Ports -------------------
595  RXDFEAGCHOLD_IN => GT1_RXDFEAGCHOLD_IN ,
596  RXDFELFHOLD_IN => GT1_RXDFELFHOLD_IN,
597  --------------- Receive Ports - RX Fabric Output Control Ports -------------
598  RXOUTCLK_OUT => GT1_RXOUTCLK_OUT,
599  ------------- Receive Ports - RX Initialization and Reset Ports ------------
600  GTRXRESET_IN => GT1_GTRXRESET_IN,
601  RXPMARESET_IN => GT1_RXPMARESET_IN,
602  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
603  RXCHARISCOMMA_OUT => GT1_RXCHARISCOMMA_OUT ,
604  RXCHARISK_OUT => GT1_RXCHARISK_OUT,
605  -------------- Receive Ports -RX Initialization and Reset Ports ------------
606  RXRESETDONE_OUT => GT1_RXRESETDONE_OUT ,
607  --------------------- TX Initialization and Reset Ports --------------------
608  GTTXRESET_IN => GT1_GTTXRESET_IN,
609  TXUSERRDY_IN => GT1_TXUSERRDY_IN,
610  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
611  TXUSRCLK_IN => GT1_TXUSRCLK_IN,
612  TXUSRCLK2_IN => GT1_TXUSRCLK2_IN,
613  ------------------ Transmit Ports - TX Data Path interface -----------------
614  TXDATA_IN => GT1_TXDATA_IN,
615  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
616  GTXTXN_OUT => GT1_GTXTXN_OUT,
617  GTXTXP_OUT => GT1_GTXTXP_OUT,
618  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
619  TXOUTCLK_OUT => GT1_TXOUTCLK_OUT,
620  TXOUTCLKFABRIC_OUT => GT1_TXOUTCLKFABRIC_OUT ,
621  TXOUTCLKPCS_OUT => GT1_TXOUTCLKPCS_OUT ,
622  --------------------- Transmit Ports - TX Gearbox Ports --------------------
623  TXCHARISK_IN => GT1_TXCHARISK_IN,
624  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
625  TXRESETDONE_OUT => GT1_TXRESETDONE_OUT
626 
627  );
628 
629  --_________________________________________________________________________
630  --_________________________________________________________________________
631  --_________________________GTXE2_COMMON____________________________________
632 
633  gtxe2_common_0_i : GTXE2_COMMON
634  generic map
635  (
636  -- Simulation attributes
637  SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
638  SIM_QPLLREFCLK_SEL => ("001"),
639  SIM_VERSION => "4.0",
640 
641 
642  ------------------COMMON BLOCK Attributes---------------
643  BIAS_CFG => (x"0000040000001000"),
644  COMMON_CFG => (x"00000000"),
645  QPLL_CFG => (x"0680181"),
646  QPLL_CLKOUT_CFG => ("0000"),
647  QPLL_COARSE_FREQ_OVRD => ("010000"),
648  QPLL_COARSE_FREQ_OVRD_EN => ('0'),
649  QPLL_CP => ("0000011111"),
650  QPLL_CP_MONITOR_EN => ('0'),
651  QPLL_DMONITOR_SEL => ('0'),
652  QPLL_FBDIV => (QPLL_FBDIV_IN),
653  QPLL_FBDIV_MONITOR_EN => ('0'),
654  QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
655  QPLL_INIT_CFG => (x"000006"),
656  QPLL_LOCK_CFG => (x"21E8"),
657  QPLL_LPF => ("1111"),
658  QPLL_REFCLK_DIV => (1)
659 
660 
661  )
662  port map
663  (
664  ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
665  DRPADDR => tied_to_ground_vec_i (7 downto 0),
666  DRPCLK => tied_to_ground_i,
667  DRPDI => tied_to_ground_vec_i (15 downto 0),
668  DRPDO => open,
669  DRPEN => tied_to_ground_i,
670  DRPRDY => open,
671  DRPWE => tied_to_ground_i,
672  ---------------------- Common Block - Ref Clock Ports ---------------------
673  GTGREFCLK => tied_to_ground_i,
674  GTNORTHREFCLK0 => tied_to_ground_i,
675  GTNORTHREFCLK1 => tied_to_ground_i,
676  GTREFCLK0 => GT0_GTREFCLK0_COMMON_IN ,
677  GTREFCLK1 => tied_to_ground_i,
678  GTSOUTHREFCLK0 => tied_to_ground_i,
679  GTSOUTHREFCLK1 => tied_to_ground_i,
680  ------------------------- Common Block - QPLL Ports -----------------------
681  QPLLDMONITOR => open,
682  ----------------------- Common Block - Clocking Ports ----------------------
683  QPLLOUTCLK => gt0_qplloutclk_i,
684  QPLLOUTREFCLK => gt0_qplloutrefclk_i ,
685  REFCLKOUTMONITOR => open,
686  ------------------------- Common Block - QPLL Ports ------------------------
687  QPLLFBCLKLOST => open,
688  QPLLLOCK => GT0_QPLLLOCK_OUT,
689  QPLLLOCKDETCLK => GT0_QPLLLOCKDETCLK_IN ,
690  QPLLLOCKEN => tied_to_vcc_i,
691  QPLLOUTRESET => tied_to_ground_i,
692  QPLLPD => tied_to_ground_i,
693  QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_OUT ,
694  QPLLREFCLKSEL => "001",
695  QPLLRESET => GT0_QPLLRESET_IN,
696  QPLLRSVD1 => "0000000000000000",
697  QPLLRSVD2 => "11111",
698  --------------------------------- QPLL Ports -------------------------------
699  BGBYPASSB => tied_to_vcc_i,
700  BGMONITORENB => tied_to_vcc_i,
701  BGPDB => tied_to_vcc_i,
702  BGRCALOVRD => "00000",
703  PMARSVD => "00000000",
704  RCALENB => tied_to_vcc_i
705 
706  );
707 
708 
709 
710 end RTL;
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