AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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mig_7series_v1_9_memc_ui_top_std.v
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49 // ____ ____
50 // / /\/ /
51 // /___/ \ / Vendor : Xilinx
52 // \ \ \/ Version : 3.6
53 // \ \ Application : MIG
54 // / / Filename : memc_ui_top_std.v
55 // /___/ /\ Date Last Modified : $Date: 2011/06/17 11:11:25 $
56 // \ \ / \ Date Created : Fri Oct 08 2010
57 // \___\/\___\
58 //
59 // Device : 7 Series
60 // Design Name : DDR2 SDRAM & DDR3 SDRAM
61 // Purpose :
62 // Top level memory interface block. Instantiates a clock and
63 // reset generator, the memory controller, the phy and the
64 // user interface blocks.
65 // Reference :
66 // Revision History :
67 //*****************************************************************************
68 
69 `timescale 1 ps / 1 ps
70 
71 (* X_CORE_INFO = "mig_7series_v1_9_ddr3_7Series, Coregen 14.5" , CORE_GENERATION_INFO = "ddr3_7Series,mig_7series_v1_9,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Foundation_ISE, LEVEL=CONTROLLER, AXI_ENABLE=0, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, CLK_PERIOD=1072, PHY_RATIO=4, CLKIN_PERIOD=4288, VCCAUX_IO=2.0V, MEMORY_TYPE=COMP, MEMORY_PART=mt41j128m16xx-107g, DQ_WIDTH=32, ECC=OFF, DATA_MASK=1, ORDERING=NORM, BURST_MODE=8, BURST_TYPE=SEQ, CA_MIRROR=OFF, OUTPUT_DRV=LOW, USE_CS_PORT=0, USE_ODT_PORT=1, RTT_NOM=60, MEMORY_ADDRESS_MAP=BANK_ROW_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=0, SYSCLK_TYPE=DIFFERENTIAL, REFCLK_TYPE=NO_BUFFER}" *)
72 module mig_7series_v1_9_memc_ui_top_std #
73  (
74  parameter TCQ = 100,
75  parameter PAYLOAD_WIDTH = 64,
76  parameter ADDR_CMD_MODE = "UNBUF",
77  parameter AL = "0", // Additive Latency option
78  parameter BANK_WIDTH = 3, // # of bank bits
79  parameter BM_CNT_WIDTH = 2, // Bank machine counter width
80  parameter BURST_MODE = "8", // Burst length
81  parameter BURST_TYPE = "SEQ", // Burst type
82  parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
83  parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
84  parameter CL = 5,
85  parameter COL_WIDTH = 12, // column address width
86  parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
87  parameter CS_WIDTH = 1, // # of unique CS outputs
88  parameter CKE_WIDTH = 1, // # of cke outputs
89  parameter CWL = 5,
90  parameter DATA_WIDTH = 64,
91  parameter DATA_BUF_ADDR_WIDTH = 5,
92  parameter DATA_BUF_OFFSET_WIDTH = 1,
93  parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
94  parameter DM_WIDTH = 8, // # of DM (data mask)
95  parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
96  parameter DQ_WIDTH = 64, // # of DQ (data)
97  parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
98  parameter DQS_WIDTH = 8, // # of DQS (strobe)
99  parameter DRAM_TYPE = "DDR3",
100  parameter DRAM_WIDTH = 8, // # of DQ per DQS
101  parameter ECC = "OFF",
102  parameter ECC_WIDTH = 8,
103  parameter ECC_TEST = "OFF",
104  parameter MC_ERR_ADDR_WIDTH = 31,
105  parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
106  parameter nAL = 0, // Additive latency (in clk cyc)
107  parameter nBANK_MACHS = 4,
108  parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
109  parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
110  parameter ORDERING = "NORM",
111  parameter IBUF_LPWR_MODE = "OFF",
112  parameter IODELAY_HP_MODE = "ON",
113  parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
114  parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
115  parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
116  parameter IODELAY_GRP = "IODELAY_MIG",
117  parameter OUTPUT_DRV = "HIGH",
118  parameter REG_CTRL = "OFF",
119  parameter RTT_NOM = "60",
120  parameter RTT_WR = "120",
121  parameter STARVE_LIMIT = 2,
122  parameter tCK = 2500, // pS
123  parameter tCKE = 10000, // pS
124  parameter tFAW = 40000, // pS
125  parameter tPRDI = 1_000_000, // pS
126  parameter tRAS = 37500, // pS
127  parameter tRCD = 12500, // pS
128  parameter tREFI = 7800000, // pS
129  parameter tRFC = 110000, // pS
130  parameter tRP = 12500, // pS
131  parameter tRRD = 10000, // pS
132  parameter tRTP = 7500, // pS
133  parameter tWTR = 7500, // pS
134  parameter tZQI = 128_000_000, // nS
135  parameter tZQCS = 64, // CKs
136  parameter USER_REFRESH = "OFF", // Whether user manages REF
137  parameter TEMP_MON_EN = "ON", // Enable/Disable tempmon
138  parameter WRLVL = "OFF",
139  parameter DEBUG_PORT = "OFF",
140  parameter CAL_WIDTH = "HALF",
141  parameter RANK_WIDTH = 1,
142  parameter RANKS = 4,
143  parameter ODT_WIDTH = 1,
144  parameter ROW_WIDTH = 16, // DRAM address bus width
145  parameter ADDR_WIDTH = 32,
146  parameter APP_MASK_WIDTH = 8,
147  parameter APP_DATA_WIDTH = 64,
148  parameter [3:0] BYTE_LANES_B0 = 4'hF,
149  parameter [3:0] BYTE_LANES_B1 = 4'hF,
150  parameter [3:0] BYTE_LANES_B2 = 4'hF,
151  parameter [3:0] BYTE_LANES_B3 = 4'hF,
152  parameter [3:0] BYTE_LANES_B4 = 4'hF,
153  parameter [3:0] DATA_CTL_B0 = 4'hc,
154  parameter [3:0] DATA_CTL_B1 = 4'hf,
155  parameter [3:0] DATA_CTL_B2 = 4'hf,
156  parameter [3:0] DATA_CTL_B3 = 4'h0,
157  parameter [3:0] DATA_CTL_B4 = 4'h0,
158  parameter [47:0] PHY_0_BITLANES = 48'h0000_0000_0000,
159  parameter [47:0] PHY_1_BITLANES = 48'h0000_0000_0000,
160  parameter [47:0] PHY_2_BITLANES = 48'h0000_0000_0000,
161 
162  // control/address/data pin mapping parameters
163  parameter [143:0] CK_BYTE_MAP
164  = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
165  parameter [191:0] ADDR_MAP
166  = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
167  parameter [35:0] BANK_MAP = 36'h000_000_000,
168  parameter [11:0] CAS_MAP = 12'h000,
169  parameter [7:0] CKE_ODT_BYTE_MAP = 8'h00,
170  parameter [95:0] CKE_MAP = 96'h000_000_000_000_000_000_000_000,
171  parameter [95:0] ODT_MAP = 96'h000_000_000_000_000_000_000_000,
172  parameter CKE_ODT_AUX = "FALSE",
173  parameter [119:0] CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
174  parameter [11:0] PARITY_MAP = 12'h000,
175  parameter [11:0] RAS_MAP = 12'h000,
176  parameter [11:0] WE_MAP = 12'h000,
177  parameter [143:0] DQS_BYTE_MAP
178  = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
179  parameter [95:0] DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
180  parameter [95:0] DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
181  parameter [95:0] DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
182  parameter [95:0] DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
183  parameter [95:0] DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
184  parameter [95:0] DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
185  parameter [95:0] DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
186  parameter [95:0] DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
187  parameter [95:0] DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
188  parameter [95:0] DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
189  parameter [95:0] DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
190  parameter [95:0] DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
191  parameter [95:0] DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
192  parameter [95:0] DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
193  parameter [95:0] DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
194  parameter [95:0] DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
195  parameter [95:0] DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
196  parameter [95:0] DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
197  parameter [107:0] MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
198  parameter [107:0] MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
199 
200  parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
201  parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
202  parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
203  // calibration Address. The address given below will be used for calibration
204  // read and write operations.
205  parameter [15:0] CALIB_ROW_ADD = 16'h0000, // Calibration row address
206  parameter [11:0] CALIB_COL_ADD = 12'h000, // Calibration column address
207  parameter [2:0] CALIB_BA_ADD = 3'h0, // Calibration bank address
208  parameter SIM_BYPASS_INIT_CAL = "OFF",
209  parameter REFCLK_FREQ = 300.0,
210  parameter USE_CS_PORT = 1, // Support chip select output
211  parameter USE_DM_PORT = 1, // Support data mask output
212  parameter USE_ODT_PORT = 1 // Support ODT output
213  )
214  (
215  // Clock and reset ports
216  input clk,
217  input clk_ref,
218  input mem_refclk ,
219  input freq_refclk ,
220  input pll_lock,
221  input sync_pulse ,
222 
223  input rst,
224 
225  // memory interface ports
226  inout [DQ_WIDTH-1:0] ddr_dq,
227  inout [DQS_WIDTH-1:0] ddr_dqs_n,
228  inout [DQS_WIDTH-1:0] ddr_dqs,
229  output [ROW_WIDTH-1:0] ddr_addr,
230  output [BANK_WIDTH-1:0] ddr_ba,
231  output ddr_cas_n,
232  output [CK_WIDTH-1:0] ddr_ck_n,
233  output [CK_WIDTH-1:0] ddr_ck,
234  output [CKE_WIDTH-1:0] ddr_cke,
235  output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
236  output [DM_WIDTH-1:0] ddr_dm,
237  output [ODT_WIDTH-1:0] ddr_odt,
238  output ddr_ras_n,
239  output ddr_reset_n,
240  output ddr_parity,
241  output ddr_we_n,
242 
243  output [BM_CNT_WIDTH-1:0] bank_mach_next,
244 
245  // user interface ports
246  input [ADDR_WIDTH-1:0] app_addr,
247  input [2:0] app_cmd,
248  input app_en,
249  input app_hi_pri,
250  input [APP_DATA_WIDTH-1:0] app_wdf_data,
251  input app_wdf_end,
252  input [APP_MASK_WIDTH-1:0] app_wdf_mask,
253  input app_wdf_wren,
254  input app_correct_en_i,
255  input [2*nCK_PER_CLK-1:0] app_raw_not_ecc,
256  output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err,
257  output [APP_DATA_WIDTH-1:0] app_rd_data,
258  output app_rd_data_end,
259  output app_rd_data_valid,
260  output app_rdy,
261  output app_wdf_rdy,
262 
263  input app_sr_req,
264  output app_sr_active,
265  input app_ref_req,
266  output app_ref_ack,
267  input app_zq_req,
268  output app_zq_ack,
269 
270  // temperature monitor ports
271  input [11:0] device_temp,
272 
273  // debug logic ports
274  input dbg_idel_down_all,
275  input dbg_idel_down_cpt,
276  input dbg_idel_up_all,
277  input dbg_idel_up_cpt,
278  input dbg_sel_all_idel_cpt,
279  input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
280  output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
281  output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
282  output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
283  output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
284  output [1:0] dbg_rdlvl_done,
285  output [1:0] dbg_rdlvl_err,
286  output [1:0] dbg_rdlvl_start,
287  output [5:0] dbg_tap_cnt_during_wrlvl,
288  output dbg_wl_edge_detect_valid,
289  output dbg_wrlvl_done,
290  output dbg_wrlvl_err,
291  output dbg_wrlvl_start,
292  output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
293  output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
294 
295  output init_calib_complete,
296  input dbg_sel_pi_incdec,
297  input dbg_sel_po_incdec,
298  input [DQS_CNT_WIDTH:0] dbg_byte_sel,
299  input dbg_pi_f_inc,
300  input dbg_pi_f_dec,
301  input dbg_po_f_inc,
302  input dbg_po_f_stg23_sel,
303  input dbg_po_f_dec,
304  output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
305  output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
306  output dbg_rddata_valid,
307  output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
308  output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
309  output ref_dll_lock,
310  input rst_phaser_ref,
311  output [6*RANKS-1:0] dbg_rd_data_offset,
312  output [255:0] dbg_calib_top,
313  output [255:0] dbg_phy_wrlvl,
314  output [255:0] dbg_phy_rdlvl,
315  output [99:0] dbg_phy_wrcal,
316  output [255:0] dbg_phy_init,
317  output [255:0] dbg_prbs_rdlvl,
318  output [255:0] dbg_dqs_found_cal,
319  output [5:0] dbg_pi_counter_read_val,
320  output [8:0] dbg_po_counter_read_val,
321  output dbg_pi_phaselock_start,
322  output dbg_pi_phaselocked_done,
323  output dbg_pi_phaselock_err,
324  output dbg_pi_dqsfound_start,
325  output dbg_pi_dqsfound_done,
326  output dbg_pi_dqsfound_err,
327  output dbg_wrcal_start,
328  output dbg_wrcal_done,
329  output dbg_wrcal_err,
330  output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,
331  output [11:0] dbg_pi_phase_locked_phy4lanes,
332  output [6*RANKS-1:0] dbg_calib_rd_data_offset_1,
333  output [6*RANKS-1:0] dbg_calib_rd_data_offset_2,
334  output [5:0] dbg_data_offset,
335  output [5:0] dbg_data_offset_1,
336  output [5:0] dbg_data_offset_2,
337  output dbg_oclkdelay_calib_start,
338  output dbg_oclkdelay_calib_done,
339  output [255:0] dbg_phy_oclkdelay_cal,
340  output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data
341 
342  );
343 
344  wire correct_en;
345  wire [2*nCK_PER_CLK-1:0] raw_not_ecc;
346  wire [2*nCK_PER_CLK-1:0] ecc_single;
347  wire [2*nCK_PER_CLK-1:0] ecc_multiple;
348  wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
349 
350  wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
351  wire wr_data_en;
352  wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
353  wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
354  wire rd_data_en;
355  wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
356  wire accept;
357  wire accept_ns;
358  wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
359  wire rd_data_end;
360  wire use_addr;
361  wire size;
362  wire [ROW_WIDTH-1:0] row;
363  wire [RANK_WIDTH-1:0] rank;
364  wire hi_priority;
365  wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
366  wire [COL_WIDTH-1:0] col;
367  wire [2:0] cmd;
368  wire [BANK_WIDTH-1:0] bank;
369  wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
370  wire [2*nCK_PER_CLK*PAYLOAD_WIDTH/8-1:0] wr_data_mask;
371 
372  wire app_sr_req_i;
373  wire app_sr_active_i;
374  wire app_ref_req_i;
375  wire app_ref_ack_i;
376  wire app_zq_req_i;
377  wire app_zq_ack_i;
378 
379  wire rst_tg_mc;
380  wire error;
381  wire init_wrcal_complete;
382 (* keep = "true", max_fanout = 10 *) reg reset /* synthesis syn_maxfan = 10 **/;
383 
384  //***************************************************************************
385 
386  always @(posedge clk)
387  reset <= #TCQ (rst | rst_tg_mc);
388 
389  mig_7series_v1_9_mem_intfc #
390  (
391  .TCQ (TCQ),
392  .PAYLOAD_WIDTH (PAYLOAD_WIDTH),
393  .ADDR_CMD_MODE (ADDR_CMD_MODE),
394  .AL (AL),
395  .BANK_WIDTH (BANK_WIDTH),
396  .BM_CNT_WIDTH (BM_CNT_WIDTH),
397  .BURST_MODE (BURST_MODE),
398  .BURST_TYPE (BURST_TYPE),
399  .CA_MIRROR (CA_MIRROR),
400  .CK_WIDTH (CK_WIDTH),
401  .COL_WIDTH (COL_WIDTH),
402  .CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
403  .CS_WIDTH (CS_WIDTH),
404  .nCS_PER_RANK (nCS_PER_RANK),
405  .CKE_WIDTH (CKE_WIDTH),
406  .DATA_WIDTH (DATA_WIDTH),
407  .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
408  .MASTER_PHY_CTL (MASTER_PHY_CTL),
409  .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
410  .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
411  .DM_WIDTH (DM_WIDTH),
412  .DQ_CNT_WIDTH (DQ_CNT_WIDTH),
413  .DQ_WIDTH (DQ_WIDTH),
414  .DQS_CNT_WIDTH (DQS_CNT_WIDTH),
415  .DQS_WIDTH (DQS_WIDTH),
416  .DRAM_TYPE (DRAM_TYPE),
417  .DRAM_WIDTH (DRAM_WIDTH),
418  .ECC (ECC),
419  .ECC_WIDTH (ECC_WIDTH),
420  .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
421  .REFCLK_FREQ (REFCLK_FREQ),
422  .nAL (nAL),
423  .nBANK_MACHS (nBANK_MACHS),
424  .nCK_PER_CLK (nCK_PER_CLK),
425  .ORDERING (ORDERING),
426  .OUTPUT_DRV (OUTPUT_DRV),
427  .IBUF_LPWR_MODE (IBUF_LPWR_MODE),
428  .IODELAY_HP_MODE (IODELAY_HP_MODE),
429  .BANK_TYPE (BANK_TYPE),
430  .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
431  .DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
432  .IODELAY_GRP (IODELAY_GRP),
433  .REG_CTRL (REG_CTRL),
434  .RTT_NOM (RTT_NOM),
435  .RTT_WR (RTT_WR),
436  .CL (CL),
437  .CWL (CWL),
438  .tCK (tCK),
439  .tCKE (tCKE),
440  .tFAW (tFAW),
441  .tPRDI (tPRDI),
442  .tRAS (tRAS),
443  .tRCD (tRCD),
444  .tREFI (tREFI),
445  .tRFC (tRFC),
446  .tRP (tRP),
447  .tRRD (tRRD),
448  .tRTP (tRTP),
449  .tWTR (tWTR),
450  .tZQI (tZQI),
451  .tZQCS (tZQCS),
452  .USER_REFRESH (USER_REFRESH),
453  .TEMP_MON_EN (TEMP_MON_EN),
454  .WRLVL (WRLVL),
455  .DEBUG_PORT (DEBUG_PORT),
456  .CAL_WIDTH (CAL_WIDTH),
457  .RANK_WIDTH (RANK_WIDTH),
458  .RANKS (RANKS),
459  .ODT_WIDTH (ODT_WIDTH),
460  .ROW_WIDTH (ROW_WIDTH),
461  .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
462  .BYTE_LANES_B0 (BYTE_LANES_B0),
463  .BYTE_LANES_B1 (BYTE_LANES_B1),
464  .BYTE_LANES_B2 (BYTE_LANES_B2),
465  .BYTE_LANES_B3 (BYTE_LANES_B3),
466  .BYTE_LANES_B4 (BYTE_LANES_B4),
467  .DATA_CTL_B0 (DATA_CTL_B0),
468  .DATA_CTL_B1 (DATA_CTL_B1),
469  .DATA_CTL_B2 (DATA_CTL_B2),
470  .DATA_CTL_B3 (DATA_CTL_B3),
471  .DATA_CTL_B4 (DATA_CTL_B4),
472  .PHY_0_BITLANES (PHY_0_BITLANES),
473  .PHY_1_BITLANES (PHY_1_BITLANES),
474  .PHY_2_BITLANES (PHY_2_BITLANES),
475  .CK_BYTE_MAP (CK_BYTE_MAP),
476  .ADDR_MAP (ADDR_MAP),
477  .BANK_MAP (BANK_MAP),
478  .CAS_MAP (CAS_MAP),
479  .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
480  .CKE_MAP (CKE_MAP),
481  .ODT_MAP (ODT_MAP),
482  .CKE_ODT_AUX (CKE_ODT_AUX),
483  .CS_MAP (CS_MAP),
484  .PARITY_MAP (PARITY_MAP),
485  .RAS_MAP (RAS_MAP),
486  .WE_MAP (WE_MAP),
487  .DQS_BYTE_MAP (DQS_BYTE_MAP),
488  .DATA0_MAP (DATA0_MAP),
489  .DATA1_MAP (DATA1_MAP),
490  .DATA2_MAP (DATA2_MAP),
491  .DATA3_MAP (DATA3_MAP),
492  .DATA4_MAP (DATA4_MAP),
493  .DATA5_MAP (DATA5_MAP),
494  .DATA6_MAP (DATA6_MAP),
495  .DATA7_MAP (DATA7_MAP),
496  .DATA8_MAP (DATA8_MAP),
497  .DATA9_MAP (DATA9_MAP),
498  .DATA10_MAP (DATA10_MAP),
499  .DATA11_MAP (DATA11_MAP),
500  .DATA12_MAP (DATA12_MAP),
501  .DATA13_MAP (DATA13_MAP),
502  .DATA14_MAP (DATA14_MAP),
503  .DATA15_MAP (DATA15_MAP),
504  .DATA16_MAP (DATA16_MAP),
505  .DATA17_MAP (DATA17_MAP),
506  .MASK0_MAP (MASK0_MAP),
507  .MASK1_MAP (MASK1_MAP),
508  .SLOT_0_CONFIG (SLOT_0_CONFIG),
509  .SLOT_1_CONFIG (SLOT_1_CONFIG),
510  .CALIB_ROW_ADD (CALIB_ROW_ADD),
511  .CALIB_COL_ADD (CALIB_COL_ADD),
512  .CALIB_BA_ADD (CALIB_BA_ADD),
513  .STARVE_LIMIT (STARVE_LIMIT),
514  .USE_CS_PORT (USE_CS_PORT),
515  .USE_DM_PORT (USE_DM_PORT),
516  .USE_ODT_PORT (USE_ODT_PORT)
517  )
518  mem_intfc0
519  (
520  .clk (clk),
521  .clk_ref (clk_ref),
522  .mem_refclk (mem_refclk), //memory clock
523  .freq_refclk (freq_refclk),
524  .pll_lock (pll_lock),
525  .sync_pulse (sync_pulse),
526  .rst (rst),
527  .error (error),
528  .reset (reset),
529  .rst_tg_mc (rst_tg_mc),
530 
531  .ddr_dq (ddr_dq),
532  .ddr_dqs_n (ddr_dqs_n),
533  .ddr_dqs (ddr_dqs),
534  .ddr_addr (ddr_addr),
535  .ddr_ba (ddr_ba),
536  .ddr_cas_n (ddr_cas_n),
537  .ddr_ck_n (ddr_ck_n),
538  .ddr_ck (ddr_ck),
539  .ddr_cke (ddr_cke),
540  .ddr_cs_n (ddr_cs_n),
541  .ddr_dm (ddr_dm),
542  .ddr_odt (ddr_odt),
543  .ddr_ras_n (ddr_ras_n),
544  .ddr_reset_n (ddr_reset_n),
545  .ddr_parity (ddr_parity),
546  .ddr_we_n (ddr_we_n),
547 
548  .slot_0_present (SLOT_0_CONFIG),
549  .slot_1_present (SLOT_1_CONFIG),
550 
551  .correct_en (correct_en),
552  .bank (bank),
553  .cmd (cmd),
554  .col (col),
555  .data_buf_addr (data_buf_addr),
556  .wr_data (wr_data),
557  .wr_data_mask (wr_data_mask),
558  .rank (rank),
559  .raw_not_ecc (raw_not_ecc),
560  .row (row),
561  .hi_priority (hi_priority),
562  .size (size),
563  .use_addr (use_addr),
564  .accept (accept),
565  .accept_ns (accept_ns),
566  .ecc_single (ecc_single),
567  .ecc_multiple (ecc_multiple),
568  .ecc_err_addr (ecc_err_addr),
569  .rd_data (rd_data),
570  .rd_data_addr (rd_data_addr),
571  .rd_data_en (rd_data_en),
572  .rd_data_end (rd_data_end),
573  .rd_data_offset (rd_data_offset),
574  .wr_data_addr (wr_data_addr),
575  .wr_data_en (wr_data_en),
576  .wr_data_offset (wr_data_offset),
577  .bank_mach_next (bank_mach_next),
578  .init_calib_complete (init_calib_complete),
579  .init_wrcal_complete (init_wrcal_complete),
580  .app_sr_req (app_sr_req_i),
581  .app_sr_active (app_sr_active_i),
582  .app_ref_req (app_ref_req_i),
583  .app_ref_ack (app_ref_ack_i),
584  .app_zq_req (app_zq_req_i),
585  .app_zq_ack (app_zq_ack_i),
586 
587  .device_temp (device_temp),
588 
589  .dbg_idel_up_all (dbg_idel_up_all),
590  .dbg_idel_down_all (dbg_idel_down_all),
591  .dbg_idel_up_cpt (dbg_idel_up_cpt),
592  .dbg_idel_down_cpt (dbg_idel_down_cpt),
593  .dbg_sel_idel_cpt (dbg_sel_idel_cpt),
594  .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
595  .dbg_calib_top (dbg_calib_top),
596  .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
597  .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
598  .dbg_phy_rdlvl (dbg_phy_rdlvl),
599  .dbg_phy_wrcal (dbg_phy_wrcal),
600  .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
601  .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
602  .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
603  .dbg_rddata (dbg_rddata),
604  .dbg_rdlvl_done (dbg_rdlvl_done),
605  .dbg_rdlvl_err (dbg_rdlvl_err),
606  .dbg_rdlvl_start (dbg_rdlvl_start),
607  .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
608  .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
609  .dbg_wrlvl_done (dbg_wrlvl_done),
610  .dbg_wrlvl_err (dbg_wrlvl_err),
611  .dbg_wrlvl_start (dbg_wrlvl_start),
612 
613  .dbg_sel_pi_incdec (dbg_sel_pi_incdec),
614  .dbg_sel_po_incdec (dbg_sel_po_incdec),
615  .dbg_byte_sel (dbg_byte_sel),
616  .dbg_pi_f_inc (dbg_pi_f_inc),
617  .dbg_pi_f_dec (dbg_pi_f_dec),
618  .dbg_po_f_inc (dbg_po_f_inc),
619  .dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
620  .dbg_po_f_dec (dbg_po_f_dec),
621  .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
622  .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
623  .dbg_rddata_valid (dbg_rddata_valid),
624  .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
625  .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
626  .dbg_phy_wrlvl (dbg_phy_wrlvl),
627  .dbg_pi_counter_read_val (dbg_pi_counter_read_val),
628  .dbg_po_counter_read_val (dbg_po_counter_read_val),
629  .ref_dll_lock (ref_dll_lock),
630  .rst_phaser_ref (rst_phaser_ref),
631  .dbg_rd_data_offset (dbg_rd_data_offset),
632  .dbg_phy_init (dbg_phy_init),
633  .dbg_prbs_rdlvl (dbg_prbs_rdlvl),
634  .dbg_dqs_found_cal (dbg_dqs_found_cal),
635  .dbg_pi_phaselock_start (dbg_pi_phaselock_start),
636  .dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
637  .dbg_pi_phaselock_err (dbg_pi_phaselock_err),
638  .dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
639  .dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
640  .dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
641  .dbg_wrcal_start (dbg_wrcal_start),
642  .dbg_wrcal_done (dbg_wrcal_done),
643  .dbg_wrcal_err (dbg_wrcal_err),
644  .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
645  .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
646  .dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
647  .dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
648  .dbg_data_offset (dbg_data_offset),
649  .dbg_data_offset_1 (dbg_data_offset_1),
650  .dbg_data_offset_2 (dbg_data_offset_2),
651  .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
652  .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
653  .dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
654  .dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done)
655 
656  );
657 
658  mig_7series_v1_9_ui_top #
659  (
660  .TCQ (TCQ),
661  .APP_DATA_WIDTH (APP_DATA_WIDTH),
662  .APP_MASK_WIDTH (APP_MASK_WIDTH),
663  .BANK_WIDTH (BANK_WIDTH),
664  .COL_WIDTH (COL_WIDTH),
665  .CWL (CWL),
666  .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
667  .ECC (ECC),
668  .ECC_TEST (ECC_TEST),
669  .nCK_PER_CLK (nCK_PER_CLK),
670  .ORDERING (ORDERING),
671  .RANKS (RANKS),
672  .RANK_WIDTH (RANK_WIDTH),
673  .ROW_WIDTH (ROW_WIDTH),
674  .MEM_ADDR_ORDER (MEM_ADDR_ORDER)
675  )
676  u_ui_top
677  (
678  .wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
679  .wr_data (wr_data[APP_DATA_WIDTH-1:0]),
680  .use_addr (use_addr),
681  .size (size),
682  .row (row),
683  .raw_not_ecc (raw_not_ecc),
684  .rank (rank),
685  .hi_priority (hi_priority),
686  .data_buf_addr (data_buf_addr),
687  .col (col),
688  .cmd (cmd),
689  .bank (bank),
690  .app_wdf_rdy (app_wdf_rdy),
691  .app_rdy (app_rdy),
692  .app_rd_data_valid (app_rd_data_valid),
693  .app_rd_data_end (app_rd_data_end),
694  .app_rd_data (app_rd_data),
695  .app_ecc_multiple_err (app_ecc_multiple_err),
696  .correct_en (correct_en),
697  .wr_data_offset (wr_data_offset),
698  .wr_data_en (wr_data_en),
699  .wr_data_addr (wr_data_addr),
700  .rst (reset),
701  .rd_data_offset (rd_data_offset),
702  .rd_data_end (rd_data_end),
703  .rd_data_en (rd_data_en),
704  .rd_data_addr (rd_data_addr),
705  .rd_data (rd_data[APP_DATA_WIDTH-1:0]),
706  .ecc_multiple (ecc_multiple),
707  .clk (clk),
708  .app_wdf_wren (app_wdf_wren),
709  .app_wdf_mask (app_wdf_mask),
710  .app_wdf_end (app_wdf_end),
711  .app_wdf_data (app_wdf_data),
712  .app_sz (1'b1),
713  .app_raw_not_ecc (app_raw_not_ecc),
714  .app_hi_pri (app_hi_pri),
715  .app_en (app_en),
716  .app_cmd (app_cmd),
717  .app_addr (app_addr),
718  .accept_ns (accept_ns),
719  .accept (accept),
720  .app_correct_en (app_correct_en_i),
721  .app_sr_req (app_sr_req),
722  .sr_req (app_sr_req_i),
723  .sr_active (app_sr_active_i),
724  .app_sr_active (app_sr_active),
725  .app_ref_req (app_ref_req),
726  .ref_req (app_ref_req_i),
727  .ref_ack (app_ref_ack_i),
728  .app_ref_ack (app_ref_ack),
729  .app_zq_req (app_zq_req),
730  .zq_req (app_zq_req_i),
731  .zq_ack (app_zq_ack_i),
732  .app_zq_ack (app_zq_ack)
733  );
734 
735 endmodule
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