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mig_7series_v1_9_ddr_mc_phy_wrapper.v
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49 // ____ ____
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51 // /___/ \ / Vendor : Xilinx
52 // \ \ \/ Version : %version
53 // \ \ Application : MIG
54 // / / Filename : ddr_mc_phy_wrapper.v
55 // /___/ /\ Date Last Modified : $date$
56 // \ \ / \ Date Created : Oct 10 2010
57 // \___\/\___\
58 //
59 //Device : 7 Series
60 //Design Name : DDR3 SDRAM
61 //Purpose : Wrapper file that encompasses the MC_PHY module
62 // instantiation and handles the vector remapping between
63 // the MC_PHY ports and the user's DDR3 ports. Vector
64 // remapping affects DDR3 control, address, and DQ/DQS/DM.
65 //Reference :
66 //Revision History :
67 //*****************************************************************************
68 
69 `timescale 1 ps / 1 ps
70 
71 module mig_7series_v1_9_ddr_mc_phy_wrapper #
72  (
73  parameter TCQ = 100, // Register delay (simulation only)
74  parameter tCK = 2500, // ps
75  parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
76  parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
77  parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
78  parameter IODELAY_GRP = "IODELAY_MIG",
79  parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio
80  parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
81  parameter BANK_WIDTH = 3, // # of bank address
82  parameter CKE_WIDTH = 1, // # of clock enable outputs
83  parameter CS_WIDTH = 1, // # of chip select
84  parameter CK_WIDTH = 1, // # of CK
85  parameter CWL = 5, // CAS Write latency
86  parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
87  parameter DM_WIDTH = 8, // # of data mask
88  parameter DQ_WIDTH = 16, // # of data bits
89  parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH))
90  parameter DQS_WIDTH = 8, // # of strobe pairs
91  parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3)
92  parameter RANKS = 4, // # of ranks
93  parameter ODT_WIDTH = 1, // # of ODT outputs
94  parameter REG_CTRL = "OFF", // "ON" for registered DIMM
95  parameter ROW_WIDTH = 16, // # of row/column address
96  parameter USE_CS_PORT = 1, // Support chip select output
97  parameter USE_DM_PORT = 1, // Support data mask output
98  parameter USE_ODT_PORT = 1, // Support ODT output
99  parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
100  parameter LP_DDR_CK_WIDTH = 2,
101 
102  // Hard PHY parameters
103  parameter PHYCTL_CMD_FIFO = "FALSE",
104  parameter DATA_CTL_B0 = 4'hc,
105  parameter DATA_CTL_B1 = 4'hf,
106  parameter DATA_CTL_B2 = 4'hf,
107  parameter DATA_CTL_B3 = 4'hf,
108  parameter DATA_CTL_B4 = 4'hf,
109  parameter BYTE_LANES_B0 = 4'b1111,
110  parameter BYTE_LANES_B1 = 4'b0000,
111  parameter BYTE_LANES_B2 = 4'b0000,
112  parameter BYTE_LANES_B3 = 4'b0000,
113  parameter BYTE_LANES_B4 = 4'b0000,
114  parameter PHY_0_BITLANES = 48'h0000_0000_0000,
115  parameter PHY_1_BITLANES = 48'h0000_0000_0000,
116  parameter PHY_2_BITLANES = 48'h0000_0000_0000,
117  // Parameters calculated outside of this block
118  parameter HIGHEST_BANK = 3, // Highest I/O bank index
119  parameter HIGHEST_LANE = 12, // Highest byte lane index
120  // ** Pin mapping parameters
121  // Parameters for mapping between hard PHY and physical DDR3 signals
122  // There are 2 classes of parameters:
123  // - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of
124  // 8-bit elements. Each element indicates the bank and byte lane
125  // location of that particular signal. The bit lane in this case
126  // doesn't need to be specified, either because there's only one
127  // pin pair in each byte lane that the DQS or CK pair can be
128  // located at, or in the case of CKE_ODT_BYTE_MAP, only the byte
129  // lane needs to be specified in order to determine which byte
130  // lane generates the RCLK (Note that CKE, and ODT must be located
131  // in the same bank, thus only one element in CKE_ODT_BYTE_MAP)
132  // [7:4] = bank # (0-4)
133  // [3:0] = byte lane # (0-3)
134  // - All other MAP parameters: These consist of 12-bit elements. Each
135  // element indicates the bank, byte lane, and bit lane location of
136  // that particular signal:
137  // [11:8] = bank # (0-4)
138  // [7:4] = byte lane # (0-3)
139  // [3:0] = bit lane # (0-11)
140  // Note that not all elements in all parameters will be used - it
141  // depends on the actual widths of the DDR3 buses. The parameters are
142  // structured to support a maximum of:
143  // - DQS groups: 18
144  // - data mask bits: 18
145  // In addition, the default parameter size of some of the parameters will
146  // support a certain number of bits, however, this can be expanded at
147  // compile time by expanding the width of the vector passed into this
148  // parameter
149  // - chip selects: 10
150  // - bank bits: 3
151  // - address bits: 16
152  parameter CK_BYTE_MAP
153  = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
154  parameter ADDR_MAP
155  = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
156  parameter BANK_MAP = 36'h000_000_000,
157  parameter CAS_MAP = 12'h000,
158  parameter CKE_ODT_BYTE_MAP = 8'h00,
159  parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
160  parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
161  parameter CKE_ODT_AUX = "FALSE",
162  parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
163  parameter PARITY_MAP = 12'h000,
164  parameter RAS_MAP = 12'h000,
165  parameter WE_MAP = 12'h000,
166  parameter DQS_BYTE_MAP
167  = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
168  // DATAx_MAP parameter is used for byte lane X in the design
169  parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
170  parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
171  parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
172  parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
173  parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
174  parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
175  parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
176  parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
177  parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
178  parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
179  parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
180  parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
181  parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
182  parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
183  parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
184  parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
185  parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
186  parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
187  // MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9]
188  parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
189  parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
190  // Simulation options
191  parameter SIM_CAL_OPTION = "NONE",
192 
193  // The PHY_CONTROL primitive in the bank where PLL exists is declared
194  // as the Master PHY_CONTROL.
195  parameter MASTER_PHY_CTL = 1
196  )
197  (
198  input rst,
199  input clk,
200  input freq_refclk,
201  input mem_refclk,
202  input pll_lock,
203  input sync_pulse,
204  input idelayctrl_refclk,
205  input phy_cmd_wr_en,
206  input phy_data_wr_en,
207  input [31:0] phy_ctl_wd,
208  input phy_ctl_wr,
209  input phy_if_empty_def,
210  input phy_if_reset,
211  input [5:0] data_offset_1,
212  input [5:0] data_offset_2,
213  input [3:0] aux_in_1,
214  input [3:0] aux_in_2,
215  output [4:0] idelaye2_init_val,
216  output [5:0] oclkdelay_init_val,
217  output if_empty,
218  output phy_ctl_full,
219  output phy_cmd_full,
220  output phy_data_full,
221  output phy_pre_data_a_full,
222  output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
223  output phy_mc_go,
224  input phy_write_calib,
225  input phy_read_calib,
226  input calib_in_common,
227  input [5:0] calib_sel,
228  input [HIGHEST_BANK-1:0] calib_zero_inputs,
229  input [HIGHEST_BANK-1:0] calib_zero_ctrl,
230  input [2:0] po_fine_enable,
231  input [2:0] po_coarse_enable,
232  input [2:0] po_fine_inc,
233  input [2:0] po_coarse_inc,
234  input po_counter_load_en,
235  input po_counter_read_en,
236  input [2:0] po_sel_fine_oclk_delay,
237  input [8:0] po_counter_load_val,
238  output [8:0] po_counter_read_val,
239  output [5:0] pi_counter_read_val,
240  input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
241  input pi_fine_enable,
242  input pi_fine_inc,
243  input pi_counter_load_en,
244  input [5:0] pi_counter_load_val,
245  input idelay_ce,
246  input idelay_inc,
247  input idelay_ld,
248  input idle,
249  output pi_phase_locked,
250  output pi_phase_locked_all,
251  output pi_dqs_found,
252  output pi_dqs_found_all,
253  output pi_dqs_out_of_range,
254  // From/to calibration logic/soft PHY
255  input phy_init_data_sel,
256  input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address,
257  input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank,
258  input [nCK_PER_CLK-1:0] mux_cas_n,
259  input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n,
260  input [nCK_PER_CLK-1:0] mux_ras_n,
261  input [1:0] mux_odt,
262  input [nCK_PER_CLK-1:0] mux_cke,
263  input [nCK_PER_CLK-1:0] mux_we_n,
264  input [nCK_PER_CLK-1:0] parity_in,
265  input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata,
266  input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask,
267  input mux_reset_n,
268  output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
269  // Memory I/F
270  output [ROW_WIDTH-1:0] ddr_addr,
271  output [BANK_WIDTH-1:0] ddr_ba,
272  output ddr_cas_n,
273  output [CKE_WIDTH-1:0] ddr_cke,
274  output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
275  output [DM_WIDTH-1:0] ddr_dm,
276  output [ODT_WIDTH-1:0] ddr_odt,
277  output ddr_parity,
278  output ddr_ras_n,
279  output ddr_we_n,
280  output ddr_reset_n,
281  inout [DQ_WIDTH-1:0] ddr_dq,
282  inout [DQS_WIDTH-1:0] ddr_dqs,
283  inout [DQS_WIDTH-1:0] ddr_dqs_n
284 
285  ,input dbg_pi_counter_read_en
286  ,output ref_dll_lock
287  ,input rst_phaser_ref
288  ,output [11:0] dbg_pi_phase_locked_phy4lanes
289  ,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes
290  );
291 
292  function [71:0] generate_bytelanes_ddr_ck;
293  input [143:0] ck_byte_map;
294  integer v ;
295  begin
296  generate_bytelanes_ddr_ck = 'b0 ;
297  for (v = 0; v < CK_WIDTH; v = v + 1) begin
298  if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2)
299  generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
300  else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1)
301  generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
302  else
303  generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
304  end
305  end
306  endfunction
307 
308  function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map;
309  input [143:0] ck_byte_map;
310  integer g;
311  begin
312  generate_ddr_ck_map = 'b0 ;
313  for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin
314  generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" :
315  (ck_byte_map[(g*8)+:4] == 4'd1) ? "B" :
316  (ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ;
317  generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" :
318  (ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location
319  end
320  end
321  endfunction
322 
323 
324 
325  // Enable low power mode for input buffer
326  localparam IBUF_LOW_PWR
327  = (IBUF_LPWR_MODE == "OFF") ? "FALSE" :
328  ((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL");
329 
330  // Ratio of data to strobe
331  localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
332  // number of data phases per internal clock
333  localparam PHASE_PER_CLK = 2*nCK_PER_CLK;
334  // used to determine routing to OUT_FIFO for control/address for 2:1
335  // vs. 4:1 memory:internal clock ratio modes
336  localparam PHASE_DIV = 4 / nCK_PER_CLK;
337 
338  localparam CLK_PERIOD = tCK * nCK_PER_CLK;
339 
340  // Create an aggregate parameters for data mapping to reduce # of generate
341  // statements required in remapping code. Need to account for the case
342  // when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP
343  // parameter will have fewer than 8 elements used
344  localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0],
345  DATA16_MAP[12*DQ_PER_DQS-1:0],
346  DATA15_MAP[12*DQ_PER_DQS-1:0],
347  DATA14_MAP[12*DQ_PER_DQS-1:0],
348  DATA13_MAP[12*DQ_PER_DQS-1:0],
349  DATA12_MAP[12*DQ_PER_DQS-1:0],
350  DATA11_MAP[12*DQ_PER_DQS-1:0],
351  DATA10_MAP[12*DQ_PER_DQS-1:0],
352  DATA9_MAP[12*DQ_PER_DQS-1:0],
353  DATA8_MAP[12*DQ_PER_DQS-1:0],
354  DATA7_MAP[12*DQ_PER_DQS-1:0],
355  DATA6_MAP[12*DQ_PER_DQS-1:0],
356  DATA5_MAP[12*DQ_PER_DQS-1:0],
357  DATA4_MAP[12*DQ_PER_DQS-1:0],
358  DATA3_MAP[12*DQ_PER_DQS-1:0],
359  DATA2_MAP[12*DQ_PER_DQS-1:0],
360  DATA1_MAP[12*DQ_PER_DQS-1:0],
361  DATA0_MAP[12*DQ_PER_DQS-1:0]};
362  // Same deal, but for data mask mapping
363  localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP};
364  localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ;
365  localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ;
366 
367  // Temporary parameters to determine which bank is outputting the CK/CK#
368  // Eventually there will be support for multiple CK/CK# output
369  //localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]);
370  //// Temporary method to force MC_PHY to generate ODDR associated with
371  //// CK/CK# output only for a single byte lane in the design. All banks
372  //// that won't be generating the CK/CK# will have "UNUSED" as their
373  //// PHY_GENERATE_DDR_CK parameter
374  //localparam TMP_PHY_0_GENERATE_DDR_CK
375  // = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" :
376  // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
377  // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
378  // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
379  //localparam TMP_PHY_1_GENERATE_DDR_CK
380  // = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" :
381  // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
382  // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
383  // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
384  //localparam TMP_PHY_2_GENERATE_DDR_CK
385  // = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" :
386  // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
387  // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
388  // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
389 
390  // Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx
391  // which indicates which bit lanes in data byte lanes are
392  // output-only bitlanes (e.g. used specifically for data mask outputs)
393  function [143:0] calc_phy_bitlanes_outonly;
394  input [215:0] data_mask_in;
395  integer z;
396  begin
397  calc_phy_bitlanes_outonly = 'b0;
398  // Only enable BITLANES parameters for data masks if, well, if
399  // the data masks are actually enabled
400  if (USE_DM_PORT == 1)
401  for (z = 0; z < DM_WIDTH; z = z + 1)
402  calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] +
403  12*data_mask_in[(12*z+4)+:2] +
404  data_mask_in[12*z+:4]] = 1'b1;
405  end
406  endfunction
407 
408  localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP);
409  localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0];
410  localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48];
411  localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96];
412 
413  // Determine which bank and byte lane generates the RCLK used to clock
414  // out the auxilliary (ODT, CKE) outputs
415  localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON
416  = (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 :
417  ((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 :
418  ((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 :
419  ((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 :
420  ((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1))));
421  localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON
422  = (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" :
423  ((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" :
424  ((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" :
425  ((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL")));
426 
427  localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF
428  = (CKE_MAP[11:8] == 4'h0) ? 0 :
429  ((CKE_MAP[11:8] == 4'h1) ? 1 :
430  ((CKE_MAP[11:8] == 4'h2) ? 2 :
431  ((CKE_MAP[11:8] == 4'h3) ? 3 :
432  ((CKE_MAP[11:8] == 4'h4) ? 4 : -1))));
433  localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF
434  = (CKE_MAP[7:4] == 4'h0) ? "A" :
435  ((CKE_MAP[7:4] == 4'h1) ? "B" :
436  ((CKE_MAP[7:4] == 4'h2) ? "C" :
437  ((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL")));
438 
439 
440  localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ;
441  localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ;
442 
443 
444  //***************************************************************************
445  // OCLKDELAYED tap setting calculation:
446  // Parameters for calculating amount of phase shifting output clock to
447  // achieve 90 degree offset between DQS and DQ on writes
448  //***************************************************************************
449 
450  //90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz
451  // and 1.25 for Mem_RefClk > 300 MHz
452  localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE";
453 
454  //DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400,
455  //DIV4: MemRefClk < 200 MHz
456  localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" :
457  tCK > 2500 ? "DIV2": "NONE";
458 
459  localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 :
460  PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
461 
462  // Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output
463  localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK;
464 
465  // Whether OCLK_DELAY output comes inverted or not
466  localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0);
467 
468  // Phaser-Out Stage3 Tap delay for 90 deg shift.
469  // Maximum tap delay is FreqRefClk period distributed over 64 taps
470  // localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV;
471  localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) -
472  (INT_DELAY + HALF_CYCLE_DELAY))
473  * 63 * FREQ_REF_DIV;
474  //localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY;
475 
476  localparam integer PHY_0_A_PO_OCLK_DELAY_HW
477  = (tCK > 2273) ? 34 :
478  (tCK > 2000) ? 33 :
479  (tCK > 1724) ? 32 :
480  (tCK > 1515) ? 31 :
481  (tCK > 1315) ? 30 :
482  (tCK > 1136) ? 29 :
483  (tCK > 1021) ? 28 : 27;
484 
485  // Note that simulation requires a different value than in H/W because of the
486  // difference in the way delays are modeled
487  localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ?
488  ((tCK > 2500) ? 8 :
489  (DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) :
490  MC_OCLK_DELAY;
491 
492  // Initial DQ IDELAY value
493  localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 :
494  (tCK < 1000) ? 0 :
495  (tCK < 1330) ? 0 :
496  (tCK < 2300) ? 0 :
497  (tCK < 2500) ? 2 : 0;
498  //localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0;
499 
500  // Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3?
501  localparam PHY_0_RD_CMD_OFFSET_0 = 10;
502  localparam PHY_0_RD_CMD_OFFSET_1 = 10;
503  localparam PHY_0_RD_CMD_OFFSET_2 = 10;
504  localparam PHY_0_RD_CMD_OFFSET_3 = 10;
505  // 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing
506  localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4;
507  localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4;
508  localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4;
509  localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4;
510  // 4:1 and 2:1 have different values
511  localparam PHY_0_WR_DURATION_0 = 7;
512  localparam PHY_0_WR_DURATION_1 = 7;
513  localparam PHY_0_WR_DURATION_2 = 7;
514  localparam PHY_0_WR_DURATION_3 = 7;
515  // Aux_out parameters for toggle mode (CKE)
516  localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
517  localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 :
518  (CWL < 7) ?
519  4 + ((CWL_M % 2) ? 0 : 1) :
520  5 + ((CWL_M % 2) ? 0 : 1);
521 
522  // temporary parameter to enable/disable PHY PC counters. In both 4:1 and
523  // 2:1 cases, this should be disabled. For now, enable for 4:1 mode to
524  // avoid making too many changes at once.
525  localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE";
526 
527 
528  wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out;
529  wire [HIGHEST_LANE-1:0] mem_dqs_in;
530  wire [HIGHEST_LANE-1:0] mem_dqs_out;
531  wire [HIGHEST_LANE-1:0] mem_dqs_ts;
532  wire [HIGHEST_LANE*10-1:0] mem_dq_in;
533  wire [HIGHEST_LANE*12-1:0] mem_dq_out;
534  wire [HIGHEST_LANE*12-1:0] mem_dq_ts;
535  wire [DQ_WIDTH-1:0] in_dq;
536  wire [DQS_WIDTH-1:0] in_dqs;
537  wire [ROW_WIDTH-1:0] out_addr;
538  wire [BANK_WIDTH-1:0] out_ba;
539  wire out_cas_n;
540  wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n;
541  wire [DM_WIDTH-1:0] out_dm;
542  wire [ODT_WIDTH -1:0] out_odt;
543  wire [CKE_WIDTH -1 :0] out_cke ;
544  wire [DQ_WIDTH-1:0] out_dq;
545  wire [DQS_WIDTH-1:0] out_dqs;
546  wire out_parity;
547  wire out_ras_n;
548  wire out_we_n;
549  wire [HIGHEST_LANE*80-1:0] phy_din;
550  wire [HIGHEST_LANE*80-1:0] phy_dout;
551  wire phy_rd_en;
552  wire [DM_WIDTH-1:0] ts_dm;
553  wire [DQ_WIDTH-1:0] ts_dq;
554  wire [DQS_WIDTH-1:0] ts_dqs;
555 
556  reg [31:0] phy_ctl_wd_i1;
557  reg [31:0] phy_ctl_wd_i2;
558  reg phy_ctl_wr_i1;
559  reg phy_ctl_wr_i2;
560  reg [5:0] data_offset_1_i1;
561  reg [5:0] data_offset_1_i2;
562  reg [5:0] data_offset_2_i1;
563  reg [5:0] data_offset_2_i2;
564  wire [31:0] phy_ctl_wd_temp;
565  wire phy_ctl_wr_temp;
566  wire [5:0] data_offset_1_temp;
567  wire [5:0] data_offset_2_temp;
568  wire [5:0] data_offset_1_of;
569  wire [5:0] data_offset_2_of;
570  wire [31:0] phy_ctl_wd_of;
571 (* keep = "true", max_fanout = 3 *) wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 **/;
572  wire [3:0] phy_ctl_full_temp;
573 
574  wire data_io_idle_pwrdwn;
575 
576  // Always read from input data FIFOs when not empty
577  assign phy_rd_en = !if_empty;
578 
579  // IDELAYE2 initial value
580  assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE;
581  assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY;
582 
583  // Idle powerdown when there are no pending reads in the MC
584  assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0;
585 
586  //***************************************************************************
587  // Auxiliary output steering
588  //***************************************************************************
589 
590  // For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be
591  // mapped to ddr_odt and the aux_out[7:4] from one of the data banks
592  // will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the
593  // addr/ctl bank would bank would map to both ddr_odt and ddr_cke.
594  generate
595  if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins
596  if (CKE_WIDTH == 1) begin : gen_cke
597  // Explicitly instantiate OBUF to ensure that these are present
598  // in the netlist. Typically this is not required since NGDBUILD
599  // at the top-level knows to infer an I/O/IOBUF and therefore a
600  // top-level LOC constraint can be attached to that pin. This does
601  // not work when a hierarchical flow is used and the LOC is applied
602  // at the individual core-level UCF
603  OBUF u_cke_obuf
604  (
605  .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
606  .O (ddr_cke)
607  );
608  end else begin: gen_2rank_cke
609  OBUF u_cke0_obuf
610  (
611  .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
612  .O (ddr_cke[0])
613  );
614  OBUF u_cke1_obuf
615  (
616  .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
617  .O (ddr_cke[1])
618  );
619  end
620  end
621  endgenerate
622 
623  generate
624  if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins
625  if (USE_ODT_PORT == 1) begin : gen_use_odt
626  // Explicitly instantiate OBUF to ensure that these are present
627  // in the netlist. Typically this is not required since NGDBUILD
628  // at the top-level knows to infer an I/O/IOBUF and therefore a
629  // top-level LOC constraint can be attached to that pin. This does
630  // not work when a hierarchical flow is used and the LOC is applied
631  // at the individual core-level UCF
632  OBUF u_odt_obuf
633  (
634  .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]),
635  .O (ddr_odt[0])
636  );
637  if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt
638  OBUF u_odt1_obuf
639  (
640  .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
641  .O (ddr_odt[1])
642  );
643  end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt
644  OBUF u_odt1_obuf
645  (
646  .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
647  .O (ddr_odt[1])
648  );
649  end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt
650  OBUF u_odt1_obuf
651  (
652  .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
653  .O (ddr_odt[1])
654  );
655  OBUF u_odt2_obuf
656  (
657  .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
658  .O (ddr_odt[2])
659  );
660  end
661  end else begin
662  assign ddr_odt = 'b0;
663  end
664  end
665  endgenerate
666 
667  //***************************************************************************
668  // Read data bit steering
669  //***************************************************************************
670 
671  // Transpose elements of rd_data_map to form final read data output:
672  // phy_din elements are grouped according to "physical bit" - e.g.
673  // for nCK_PER_CLK = 4, there are 8 data phases transfered per physical
674  // bit per clock cycle:
675  // = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2,
676  // dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0}
677  // whereas rd_data is are grouped according to "phase" - e.g.
678  // = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0,
679  // dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0}
680  // therefore rd_data is formed by transposing phy_din - e.g.
681  // for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY
682  // bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then
683  // the assignments for bits of rd_data corresponding to DQ[1:0]
684  // would be:
685  // {rd_data[112], rd_data[96], rd_data[80], rd_data[64],
686  // rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0]
687  // {rd_data[113], rd_data[97], rd_data[81], rd_data[65],
688  // rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8]
689  generate
690  genvar i, j;
691  for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1
692  for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2
693  assign rd_data[DQ_WIDTH*j + i]
694  = phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+
695  80*FULL_DATA_MAP[(12*i+4)+:2] +
696  8*FULL_DATA_MAP[12*i+:4]) + j];
697  end
698  end
699  endgenerate
700 
701  //***************************************************************************
702  // Control/address
703  //***************************************************************************
704 
705  assign out_cas_n
706  = mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]];
707 
708  generate
709  // if signal placed on bit lanes [0-9]
710  if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10
711  // Determine routing based on clock ratio mode. If running in 4:1
712  // mode, then all four bits from logic are used. If 2:1 mode, only
713  // 2-bits are provided by logic, and each bit is repeated 2x to form
714  // 4-bit input to IN_FIFO, e.g.
715  // 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]}
716  // 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]}
717  assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
718  8*CAS_MAP[3:0])+:4]
719  = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
720  mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
721  end else begin: gen_cas_ge10
722  // If signal is placed in bit lane [10] or [11], route to upper
723  // nibble of phy_dout lane [5] or [6] respectively (in this case
724  // phy_dout lane [5, 6] are multiplexed to take input for two
725  // different SDR signals - this is how bits[10,11] need to be
726  // provided to the OUT_FIFO
727  assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
728  8*(CAS_MAP[3:0]-5) + 4)+:4]
729  = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
730  mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
731  end
732  endgenerate
733 
734  assign out_ras_n
735  = mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]];
736 
737  generate
738  if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10
739  assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
740  8*RAS_MAP[3:0])+:4]
741  = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
742  mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
743  end else begin: gen_ras_ge10
744  assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
745  8*(RAS_MAP[3:0]-5) + 4)+:4]
746  = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
747  mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
748  end
749  endgenerate
750 
751  assign out_we_n
752  = mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]];
753 
754  generate
755  if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10
756  assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
757  8*WE_MAP[3:0])+:4]
758  = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
759  mux_we_n[1/PHASE_DIV], mux_we_n[0]};
760  end else begin: gen_we_ge10
761  assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
762  8*(WE_MAP[3:0]-5) + 4)+:4]
763  = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
764  mux_we_n[1/PHASE_DIV], mux_we_n[0]};
765  end
766  endgenerate
767 
768  generate
769  if (REG_CTRL == "ON") begin: gen_parity_out
770  // Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs
771  assign out_parity
772  = mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] +
773  PARITY_MAP[3:0]];
774  if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10
775  assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
776  8*PARITY_MAP[3:0])+:4]
777  = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
778  parity_in[1/PHASE_DIV], parity_in[0]};
779  end else begin: gen_ge10
780  assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
781  8*(PARITY_MAP[3:0]-5) + 4)+:4]
782  = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
783  parity_in[1/PHASE_DIV], parity_in[0]};
784  end
785  end
786  endgenerate
787 
788  //*****************************************************************
789 
790  generate
791  genvar m, n,x;
792 
793  //*****************************************************************
794  // Control/address (multi-bit) buses
795  //*****************************************************************
796 
797  // Row/Column address
798  for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out
799  assign out_addr[m]
800  = mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] +
801  12*ADDR_MAP[(12*m+4)+:2] +
802  ADDR_MAP[12*m+:4]];
803 
804  if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10
805  // For multi-bit buses, we also have to deal with transposition
806  // when going from the logic-side control bus to phy_dout
807  for (n = 0; n < 4; n = n + 1) begin: loop_xpose
808  assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
809  80*ADDR_MAP[(12*m+4)+:2] +
810  8*ADDR_MAP[12*m+:4] + n]
811  = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
812  end
813  end else begin: gen_ge10
814  for (n = 0; n < 4; n = n + 1) begin: loop_xpose
815  assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
816  80*ADDR_MAP[(12*m+4)+:2] +
817  8*(ADDR_MAP[12*m+:4]-5) + 4 + n]
818  = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
819  end
820  end
821  end
822 
823  // Bank address
824  for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out
825  assign out_ba[m]
826  = mem_dq_out[48*BANK_MAP[(12*m+8)+:3] +
827  12*BANK_MAP[(12*m+4)+:2] +
828  BANK_MAP[12*m+:4]];
829 
830  if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10
831  for (n = 0; n < 4; n = n + 1) begin: loop_xpose
832  assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
833  80*BANK_MAP[(12*m+4)+:2] +
834  8*BANK_MAP[12*m+:4] + n]
835  = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
836  end
837  end else begin: gen_ge10
838  for (n = 0; n < 4; n = n + 1) begin: loop_xpose
839  assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
840  80*BANK_MAP[(12*m+4)+:2] +
841  8*(BANK_MAP[12*m+:4]-5) + 4 + n]
842  = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
843  end
844  end
845  end
846 
847  // Chip select
848  if (USE_CS_PORT == 1) begin: gen_cs_n_out
849  for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out
850  assign out_cs_n[m]
851  = mem_dq_out[48*CS_MAP[(12*m+8)+:3] +
852  12*CS_MAP[(12*m+4)+:2] +
853  CS_MAP[12*m+:4]];
854  if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10
855  for (n = 0; n < 4; n = n + 1) begin: loop_xpose
856  assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
857  80*CS_MAP[(12*m+4)+:2] +
858  8*CS_MAP[12*m+:4] + n]
859  = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
860  end
861  end else begin: gen_ge10
862  for (n = 0; n < 4; n = n + 1) begin: loop_xpose
863  assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
864  80*CS_MAP[(12*m+4)+:2] +
865  8*(CS_MAP[12*m+:4]-5) + 4 + n]
866  = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
867  end
868  end
869  end
870  end
871 
872 
873  if(CKE_ODT_AUX == "FALSE") begin
874  // ODT_ports
875  wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ;
876 
877  if(RANKS == 1) begin
878  for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin
879  assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ;
880  end
881  end else begin
882  for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin
883  assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ;
884  assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ;
885  end
886  end
887 
888  if (USE_ODT_PORT == 1) begin: gen_odt_out
889  for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1
890  assign out_odt[m]
891  = mem_dq_out[48*ODT_MAP[(12*m+8)+:3] +
892  12*ODT_MAP[(12*m+4)+:2] +
893  ODT_MAP[12*m+:4]];
894  if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10
895  for (n = 0; n < 4; n = n + 1) begin: loop_xpose
896  assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
897  80*ODT_MAP[(12*m+4)+:2] +
898  8*ODT_MAP[12*m+:4] + n]
899  = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
900  end
901  end else begin: gen_ge10
902  for (n = 0; n < 4; n = n + 1) begin: loop_xpose
903  assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
904  80*ODT_MAP[(12*m+4)+:2] +
905  8*(ODT_MAP[12*m+:4]-5) + 4 + n]
906  = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
907  end
908  end
909  end
910  end
911 
912 
913  wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ;
914 
915  for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin
916  assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ;
917  end
918 
919 
920 
921  for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out
922  assign out_cke[m]
923  = mem_dq_out[48*CKE_MAP[(12*m+8)+:3] +
924  12*CKE_MAP[(12*m+4)+:2] +
925  CKE_MAP[12*m+:4]];
926  if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10
927  for (n = 0; n < 4; n = n + 1) begin: loop_xpose
928  assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
929  80*CKE_MAP[(12*m+4)+:2] +
930  8*CKE_MAP[12*m+:4] + n]
931  = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
932  end
933  end else begin: gen_ge10
934  for (n = 0; n < 4; n = n + 1) begin: loop_xpose
935  assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
936  80*CKE_MAP[(12*m+4)+:2] +
937  8*(CKE_MAP[12*m+:4]-5) + 4 + n]
938  = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
939  end
940  end
941  end
942  end
943 
944  //*****************************************************************
945  // Data mask
946  //*****************************************************************
947 
948  if (USE_DM_PORT == 1) begin: gen_dm_out
949  for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out
950  assign out_dm[m]
951  = mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] +
952  12*FULL_MASK_MAP[(12*m+4)+:2] +
953  FULL_MASK_MAP[12*m+:4]];
954  assign ts_dm[m]
955  = mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] +
956  12*FULL_MASK_MAP[(12*m+4)+:2] +
957  FULL_MASK_MAP[12*m+:4]];
958  for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
959  assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] +
960  80*FULL_MASK_MAP[(12*m+4)+:2] +
961  8*FULL_MASK_MAP[12*m+:4] + n]
962  = mux_wrdata_mask[DM_WIDTH*n + m];
963  end
964  end
965  end
966 
967  //*****************************************************************
968  // Input and output DQ
969  //*****************************************************************
970 
971  for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout
972  // to MC_PHY
973  assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] +
974  10*FULL_DATA_MAP[(12*m+4)+:2] +
975  FULL_DATA_MAP[12*m+:4]]
976  = in_dq[m];
977  // to I/O buffers
978  assign out_dq[m]
979  = mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] +
980  12*FULL_DATA_MAP[(12*m+4)+:2] +
981  FULL_DATA_MAP[12*m+:4]];
982  assign ts_dq[m]
983  = mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] +
984  12*FULL_DATA_MAP[(12*m+4)+:2] +
985  FULL_DATA_MAP[12*m+:4]];
986  for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
987  assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] +
988  80*FULL_DATA_MAP[(12*m+4)+:2] +
989  8*FULL_DATA_MAP[12*m+:4] + n]
990  = mux_wrdata[DQ_WIDTH*n + m];
991  end
992  end
993 
994  //*****************************************************************
995  // Input and output DQS
996  //*****************************************************************
997 
998  for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout
999  // to MC_PHY
1000  assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]
1001  = in_dqs[m];
1002  // to I/O buffers
1003  assign out_dqs[m]
1004  = mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
1005  assign ts_dqs[m]
1006  = mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
1007  end
1008  endgenerate
1009 
1010  //***************************************************************************
1011  // Memory I/F output and I/O buffer instantiation
1012  //***************************************************************************
1013 
1014  // Note on instantiation - generally at the minimum, it's not required to
1015  // instantiate the output buffers - they can be inferred by the synthesis
1016  // tool, and there aren't any attributes that need to be associated with
1017  // them. Consider as a future option to take out the OBUF instantiations
1018 
1019  OBUF u_cas_n_obuf
1020  (
1021  .I (out_cas_n),
1022  .O (ddr_cas_n)
1023  );
1024 
1025  OBUF u_ras_n_obuf
1026  (
1027  .I (out_ras_n),
1028  .O (ddr_ras_n)
1029  );
1030 
1031  OBUF u_we_n_obuf
1032  (
1033  .I (out_we_n),
1034  .O (ddr_we_n)
1035  );
1036 
1037  generate
1038  genvar p;
1039 
1040  for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf
1041  OBUF u_addr_obuf
1042  (
1043  .I (out_addr[p]),
1044  .O (ddr_addr[p])
1045  );
1046  end
1047 
1048  for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf
1049  OBUF u_bank_obuf
1050  (
1051  .I (out_ba[p]),
1052  .O (ddr_ba[p])
1053  );
1054  end
1055 
1056  if (USE_CS_PORT == 1) begin: gen_cs_n_obuf
1057  for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf
1058  OBUF u_cs_n_obuf
1059  (
1060  .I (out_cs_n[p]),
1061  .O (ddr_cs_n[p])
1062  );
1063  end
1064  end
1065  if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo
1066  if (USE_ODT_PORT== 1) begin: gen_odt_obuf
1067  for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf
1068  OBUF u_cs_n_obuf
1069  (
1070  .I (out_odt[p]),
1071  .O (ddr_odt[p])
1072  );
1073  end
1074  end
1075  for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf
1076  OBUF u_cs_n_obuf
1077  (
1078  .I (out_cke[p]),
1079  .O (ddr_cke[p])
1080  );
1081  end
1082  end
1083 
1084  if (REG_CTRL == "ON") begin: gen_parity_obuf
1085  // Generate addr/ctrl parity output only for DDR3 registered DIMMs
1086  OBUF u_parity_obuf
1087  (
1088  .I (out_parity),
1089  .O (ddr_parity)
1090  );
1091  end else begin: gen_parity_tieoff
1092  assign ddr_parity = 1'b0;
1093  end
1094 
1095  if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf
1096  // Generate reset output only for DDR3 and DDR2 RDIMMs
1097  OBUF u_reset_obuf
1098  (
1099  .I (mux_reset_n),
1100  .O (ddr_reset_n)
1101  );
1102  end else begin: gen_reset_tieoff
1103  assign ddr_reset_n = 1'b1;
1104  end
1105 
1106  if (USE_DM_PORT == 1) begin: gen_dm_obuf
1107  for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm
1108  OBUFT u_dm_obuf
1109  (
1110  .I (out_dm[p]),
1111  .T (ts_dm[p]),
1112  .O (ddr_dm[p])
1113  );
1114  end
1115  end else begin: gen_dm_tieoff
1116  assign ddr_dm = 'b0;
1117  end
1118 
1119  if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP
1120  for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
1121  IOBUF_DCIEN #
1122  (
1123  .IBUF_LOW_PWR (IBUF_LOW_PWR)
1124  )
1125  u_iobuf_dq
1126  (
1127  .DCITERMDISABLE (data_io_idle_pwrdwn),
1128  .IBUFDISABLE (data_io_idle_pwrdwn),
1129  .I (out_dq[p]),
1130  .T (ts_dq[p]),
1131  .O (in_dq[p]),
1132  .IO (ddr_dq[p])
1133  );
1134  end
1135  end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR
1136  for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
1137  IOBUF_INTERMDISABLE #
1138  (
1139  .IBUF_LOW_PWR (IBUF_LOW_PWR)
1140  )
1141  u_iobuf_dq
1142  (
1143  .INTERMDISABLE (data_io_idle_pwrdwn),
1144  .IBUFDISABLE (data_io_idle_pwrdwn),
1145  .I (out_dq[p]),
1146  .T (ts_dq[p]),
1147  .O (in_dq[p]),
1148  .IO (ddr_dq[p])
1149  );
1150  end
1151  end else begin: gen_dq_iobuf_default
1152  for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
1153  IOBUF #
1154  (
1155  .IBUF_LOW_PWR (IBUF_LOW_PWR)
1156  )
1157  u_iobuf_dq
1158  (
1159  .I (out_dq[p]),
1160  .T (ts_dq[p]),
1161  .O (in_dq[p]),
1162  .IO (ddr_dq[p])
1163  );
1164  end
1165  end
1166 
1167  if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP
1168  for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
1169  if ((DRAM_TYPE == "DDR2") &&
1170  (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
1171  IOBUF_DCIEN #
1172  (
1173  .IBUF_LOW_PWR (IBUF_LOW_PWR)
1174  )
1175  u_iobuf_dqs
1176  (
1177  .DCITERMDISABLE (data_io_idle_pwrdwn),
1178  .IBUFDISABLE (data_io_idle_pwrdwn),
1179  .I (out_dqs[p]),
1180  .T (ts_dqs[p]),
1181  .O (in_dqs[p]),
1182  .IO (ddr_dqs[p])
1183  );
1184  assign ddr_dqs_n[p] = 1'b0;
1185  end else begin: gen_dqs_diff
1186  IOBUFDS_DCIEN #
1187  (
1188  .IBUF_LOW_PWR (IBUF_LOW_PWR),
1189  .DQS_BIAS ("TRUE")
1190  )
1191  u_iobuf_dqs
1192  (
1193  .DCITERMDISABLE (data_io_idle_pwrdwn),
1194  .IBUFDISABLE (data_io_idle_pwrdwn),
1195  .I (out_dqs[p]),
1196  .T (ts_dqs[p]),
1197  .O (in_dqs[p]),
1198  .IO (ddr_dqs[p]),
1199  .IOB (ddr_dqs_n[p])
1200  );
1201  end
1202  end
1203  end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR
1204  for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
1205  if ((DRAM_TYPE == "DDR2") &&
1206  (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
1207  IOBUF_INTERMDISABLE #
1208  (
1209  .IBUF_LOW_PWR (IBUF_LOW_PWR)
1210  )
1211  u_iobuf_dqs
1212  (
1213  .INTERMDISABLE (data_io_idle_pwrdwn),
1214  .IBUFDISABLE (data_io_idle_pwrdwn),
1215  .I (out_dqs[p]),
1216  .T (ts_dqs[p]),
1217  .O (in_dqs[p]),
1218  .IO (ddr_dqs[p])
1219  );
1220  assign ddr_dqs_n[p] = 1'b0;
1221  end else begin: gen_dqs_diff
1222  IOBUFDS_INTERMDISABLE #
1223  (
1224  .IBUF_LOW_PWR (IBUF_LOW_PWR),
1225  .DQS_BIAS ("TRUE")
1226  )
1227  u_iobuf_dqs
1228  (
1229  .INTERMDISABLE (data_io_idle_pwrdwn),
1230  .IBUFDISABLE (data_io_idle_pwrdwn),
1231  .I (out_dqs[p]),
1232  .T (ts_dqs[p]),
1233  .O (in_dqs[p]),
1234  .IO (ddr_dqs[p]),
1235  .IOB (ddr_dqs_n[p])
1236  );
1237  end
1238  end
1239  end else begin: gen_dqs_iobuf_default
1240  for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
1241  if ((DRAM_TYPE == "DDR2") &&
1242  (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
1243  IOBUF #
1244  (
1245  .IBUF_LOW_PWR (IBUF_LOW_PWR)
1246  )
1247  u_iobuf_dqs
1248  (
1249  .I (out_dqs[p]),
1250  .T (ts_dqs[p]),
1251  .O (in_dqs[p]),
1252  .IO (ddr_dqs[p])
1253  );
1254  assign ddr_dqs_n[p] = 1'b0;
1255  end else begin: gen_dqs_diff
1256  IOBUFDS #
1257  (
1258  .IBUF_LOW_PWR (IBUF_LOW_PWR),
1259  .DQS_BIAS ("TRUE")
1260  )
1261  u_iobuf_dqs
1262  (
1263  .I (out_dqs[p]),
1264  .T (ts_dqs[p]),
1265  .O (in_dqs[p]),
1266  .IO (ddr_dqs[p]),
1267  .IOB (ddr_dqs_n[p])
1268  );
1269  end
1270  end
1271  end
1272 
1273  endgenerate
1274 
1275  always @(posedge clk) begin
1276  phy_ctl_wd_i1 <= #TCQ phy_ctl_wd;
1277  phy_ctl_wr_i1 <= #TCQ phy_ctl_wr;
1278  phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1;
1279  phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1;
1280  data_offset_1_i1 <= #TCQ data_offset_1;
1281  data_offset_1_i2 <= #TCQ data_offset_1_i1;
1282  data_offset_2_i1 <= #TCQ data_offset_2;
1283  data_offset_2_i2 <= #TCQ data_offset_2_i1;
1284  end
1285 
1286 
1287  // 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it.
1288  // 2:1 mode the command goes through pre fifo
1289  assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of;
1290  assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of;
1291  assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of;
1292  assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of;
1293 
1294  generate
1295  begin
1296 
1297  mig_7series_v1_9_ddr_of_pre_fifo #
1298  (
1299  .TCQ (25),
1300  .DEPTH (8),
1301  .WIDTH (32)
1302  )
1303  phy_ctl_pre_fifo_0
1304  (
1305  .clk (clk),
1306  .rst (rst),
1307  .full_in (phy_ctl_full_temp[1]),
1308  .wr_en_in (phy_ctl_wr),
1309  .d_in (phy_ctl_wd),
1310  .wr_en_out (phy_ctl_wr_of),
1311  .d_out (phy_ctl_wd_of)
1312  );
1313 
1314  mig_7series_v1_9_ddr_of_pre_fifo #
1315  (
1316  .TCQ (25),
1317  .DEPTH (8),
1318  .WIDTH (6)
1319  )
1320  phy_ctl_pre_fifo_1
1321  (
1322  .clk (clk),
1323  .rst (rst),
1324  .full_in (phy_ctl_full_temp[2]),
1325  .wr_en_in (phy_ctl_wr),
1326  .d_in (data_offset_1),
1327  .wr_en_out (),
1328  .d_out (data_offset_1_of)
1329  );
1330 
1331  mig_7series_v1_9_ddr_of_pre_fifo #
1332  (
1333  .TCQ (25),
1334  .DEPTH (8),
1335  .WIDTH (6)
1336  )
1337  phy_ctl_pre_fifo_2
1338  (
1339  .clk (clk),
1340  .rst (rst),
1341  .full_in (phy_ctl_full_temp[3]),
1342  .wr_en_in (phy_ctl_wr),
1343  .d_in (data_offset_2),
1344  .wr_en_out (),
1345  .d_out (data_offset_2_of)
1346  );
1347 
1348  end
1349  endgenerate
1350 
1351 
1352 
1353  //***************************************************************************
1354  // Hard PHY instantiation
1355  //***************************************************************************
1356 
1357  assign phy_ctl_full = phy_ctl_full_temp[0];
1358 
1359  mig_7series_v1_9_ddr_mc_phy #
1360  (
1361  .BYTE_LANES_B0 (BYTE_LANES_B0),
1362  .BYTE_LANES_B1 (BYTE_LANES_B1),
1363  .BYTE_LANES_B2 (BYTE_LANES_B2),
1364  .BYTE_LANES_B3 (BYTE_LANES_B3),
1365  .BYTE_LANES_B4 (BYTE_LANES_B4),
1366  .DATA_CTL_B0 (DATA_CTL_B0),
1367  .DATA_CTL_B1 (DATA_CTL_B1),
1368  .DATA_CTL_B2 (DATA_CTL_B2),
1369  .DATA_CTL_B3 (DATA_CTL_B3),
1370  .DATA_CTL_B4 (DATA_CTL_B4),
1371  .PHY_0_BITLANES (PHY_0_BITLANES),
1372  .PHY_1_BITLANES (PHY_1_BITLANES),
1373  .PHY_2_BITLANES (PHY_2_BITLANES),
1374  .PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
1375  .PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
1376  .PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
1377  .RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK),
1378  .RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE),
1379  //.CKE_ODT_AUX (CKE_ODT_AUX),
1380  .GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP),
1381  .BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK),
1382  .NUM_DDR_CK (CK_WIDTH),
1383  .LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),
1384  .PO_CTL_COARSE_BYPASS ("FALSE"),
1385  .PHYCTL_CMD_FIFO ("FALSE"),
1386  .PHY_CLK_RATIO (nCK_PER_CLK),
1387  .MASTER_PHY_CTL (MASTER_PHY_CTL),
1388  .PHY_FOUR_WINDOW_CLOCKS (63),
1389  .PHY_EVENTS_DELAY (18),
1390  .PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN
1391  .PHY_SYNC_MODE ("FALSE"),
1392  .SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"),
1393  .PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE"
1394  .PHY_0_GENERATE_IDELAYCTRL ("FALSE"),
1395  .PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
1396  .PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE
1397  .PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
1398  .PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
1399  .PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
1400  .PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
1401  .PHY_0_RD_DURATION_0 (6),
1402  .PHY_0_RD_DURATION_1 (6),
1403  .PHY_0_RD_DURATION_2 (6),
1404  .PHY_0_RD_DURATION_3 (6),
1405  .PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
1406  .PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
1407  .PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
1408  .PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
1409  .PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0),
1410  .PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1),
1411  .PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2),
1412  .PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3),
1413  .PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5),
1414  .PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
1415  .PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
1416  .PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
1417  .PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
1418  .PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV),
1419  .PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
1420  .PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
1421  .PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
1422  .PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
1423  .PHY_1_GENERATE_IDELAYCTRL ("FALSE"),
1424  //.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK),
1425  //.PHY_1_NUM_DDR_CK (1),
1426  .PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
1427  .PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
1428  .PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
1429  .PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
1430  .PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
1431  .PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
1432  .PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
1433  .PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
1434  .PHY_2_GENERATE_IDELAYCTRL ("FALSE"),
1435  //.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK),
1436  //.PHY_2_NUM_DDR_CK (1),
1437  .PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
1438  .PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
1439  .PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
1440  .PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
1441  .PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
1442  .PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
1443  .PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
1444  .PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
1445  .TCK (tCK),
1446  .PHY_0_IODELAY_GRP (IODELAY_GRP)
1447  ,.PHY_1_IODELAY_GRP (IODELAY_GRP)
1448  ,.PHY_2_IODELAY_GRP (IODELAY_GRP)
1449  ,.BANK_TYPE (BANK_TYPE)
1450  ,.CKE_ODT_AUX (CKE_ODT_AUX)
1451  )
1452  u_ddr_mc_phy
1453  (
1454  .rst (rst),
1455  // Don't use MC_PHY to generate DDR_RESET_N output. Instead
1456  // generate this output outside of MC_PHY (and synchronous to CLK)
1457  .ddr_rst_in_n (1'b1),
1458  .phy_clk (clk),
1459  .freq_refclk (freq_refclk),
1460  .mem_refclk (mem_refclk),
1461  // Remove later - always same connection as phy_clk port
1462  .mem_refclk_div4 (clk),
1463  .pll_lock (pll_lock),
1464  .auxout_clk (),
1465  .sync_pulse (sync_pulse),
1466  // IDELAYCTRL instantiated outside of mc_phy module
1467  .idelayctrl_refclk (),
1468  .phy_dout (phy_dout),
1469  .phy_cmd_wr_en (phy_cmd_wr_en),
1470  .phy_data_wr_en (phy_data_wr_en),
1471  .phy_rd_en (phy_rd_en),
1472  .phy_ctl_wd (phy_ctl_wd_temp),
1473  .phy_ctl_wr (phy_ctl_wr_temp),
1474  .if_empty_def (phy_if_empty_def),
1475  .if_rst (phy_if_reset),
1476  .phyGo ('b1),
1477  .aux_in_1 (aux_in_1),
1478  .aux_in_2 (aux_in_2),
1479  // No support yet for different data offsets for different I/O banks
1480  // (possible use in supporting wider range of skew among bytes)
1481  .data_offset_1 (data_offset_1_temp),
1482  .data_offset_2 (data_offset_2_temp),
1483  .cke_in (),
1484  .if_a_empty (),
1485  .if_empty (if_empty),
1486  .if_empty_or (),
1487  .if_empty_and (),
1488  .of_ctl_a_full (),
1489  // .of_data_a_full (phy_data_full),
1490  .of_ctl_full (phy_cmd_full),
1491  .of_data_full (),
1492  .pre_data_a_full (phy_pre_data_a_full),
1493  .idelay_ld (idelay_ld),
1494  .idelay_ce (idelay_ce),
1495  .idelay_inc (idelay_inc),
1496  .input_sink (),
1497  .phy_din (phy_din),
1498  .phy_ctl_a_full (),
1499  .phy_ctl_full (phy_ctl_full_temp),
1500  .mem_dq_out (mem_dq_out),
1501  .mem_dq_ts (mem_dq_ts),
1502  .mem_dq_in (mem_dq_in),
1503  .mem_dqs_out (mem_dqs_out),
1504  .mem_dqs_ts (mem_dqs_ts),
1505  .mem_dqs_in (mem_dqs_in),
1506  .aux_out (aux_out),
1507  .phy_ctl_ready (),
1508  .rst_out (),
1509  .ddr_clk (ddr_clk),
1510  //.rclk (),
1511  .mcGo (phy_mc_go),
1512  .phy_write_calib (phy_write_calib),
1513  .phy_read_calib (phy_read_calib),
1514  .calib_sel (calib_sel),
1515  .calib_in_common (calib_in_common),
1516  .calib_zero_inputs (calib_zero_inputs),
1517  .calib_zero_ctrl (calib_zero_ctrl),
1518  .calib_zero_lanes ('b0),
1519  .po_fine_enable (po_fine_enable),
1520  .po_coarse_enable (po_coarse_enable),
1521  .po_fine_inc (po_fine_inc),
1522  .po_coarse_inc (po_coarse_inc),
1523  .po_counter_load_en (po_counter_load_en),
1524  .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),
1525  .po_counter_load_val (po_counter_load_val),
1526  .po_counter_read_en (po_counter_read_en),
1527  .po_coarse_overflow (),
1528  .po_fine_overflow (),
1529  .po_counter_read_val (po_counter_read_val),
1530  .pi_rst_dqs_find (pi_rst_dqs_find),
1531  .pi_fine_enable (pi_fine_enable),
1532  .pi_fine_inc (pi_fine_inc),
1533  .pi_counter_load_en (pi_counter_load_en),
1534  .pi_counter_read_en (dbg_pi_counter_read_en),
1535  .pi_counter_load_val (pi_counter_load_val),
1536  .pi_fine_overflow (),
1537  .pi_counter_read_val (pi_counter_read_val),
1538  .pi_phase_locked (pi_phase_locked),
1539  .pi_phase_locked_all (pi_phase_locked_all),
1540  .pi_dqs_found (),
1541  .pi_dqs_found_any (pi_dqs_found),
1542  .pi_dqs_found_all (pi_dqs_found_all),
1543  .pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),
1544  // Currently not being used. May be used in future if periodic
1545  // reads become a requirement. This output could be used to signal
1546  // a catastrophic failure in read capture and the need for
1547  // re-calibration.
1548  .pi_dqs_out_of_range (pi_dqs_out_of_range)
1549 
1550  ,.ref_dll_lock (ref_dll_lock)
1551  ,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes)
1552 // ,.rst_phaser_ref (rst_phaser_ref)
1553  );
1554 
1555 endmodule
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