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mig_7series_v1_9_ddr_calib_top.v
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49 // ____ ____
50 // / /\/ /
51 // /___/ \ / Vendor: Xilinx
52 // \ \ \/ Version: %version
53 // \ \ Application: MIG
54 // / / Filename: ddr_calib_top.v
55 // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:06 $
56 // \ \ / \ Date Created: Aug 03 2009
57 // \___\/\___\
58 //
59 //Device: 7 Series
60 //Design Name: DDR3 SDRAM
61 //Purpose:
62 //Purpose:
63 // Top-level for memory physical layer (PHY) interface
64 // NOTES:
65 // 1. Need to support multiple copies of CS outputs
66 // 2. DFI_DRAM_CKE_DISABLE not supported
67 //
68 //Reference:
69 //Revision History:
70 //*****************************************************************************
71 
72 /******************************************************************************
73 **$Id: ddr_calib_top.v,v 1.1 2011/06/02 08:35:06 mishra Exp $
74 **$Date: 2011/06/02 08:35:06 $
75 **$Author: mishra $
76 **$Revision: 1.1 $
77 **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_calib_top.v,v $
78 *******************************************************************************/
79 
80 `timescale 1ps/1ps
81 
82 module mig_7series_v1_9_ddr_calib_top #
83  (
84  parameter TCQ = 100,
85  parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
86  parameter tCK = 2500, // DDR3 SDRAM clock period
87  parameter CLK_PERIOD = 3333, // Internal clock period (in ps)
88  parameter N_CTL_LANES = 3, // # of control byte lanes in the PHY
89  parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
90  parameter PRBS_WIDTH = 8, // The PRBS sequence is 2^PRBS_WIDTH
91  parameter HIGHEST_LANE = 4,
92  parameter HIGHEST_BANK = 3,
93  parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
94  // five fields, one per possible I/O bank, 4 bits in each field,
95  // 1 per lane data=1/ctl=0
96  parameter DATA_CTL_B0 = 4'hc,
97  parameter DATA_CTL_B1 = 4'hf,
98  parameter DATA_CTL_B2 = 4'hf,
99  parameter DATA_CTL_B3 = 4'hf,
100  parameter DATA_CTL_B4 = 4'hf,
101  // defines the byte lanes in I/O banks being used in the interface
102  // 1- Used, 0- Unused
103  parameter BYTE_LANES_B0 = 4'b1111,
104  parameter BYTE_LANES_B1 = 4'b0000,
105  parameter BYTE_LANES_B2 = 4'b0000,
106  parameter BYTE_LANES_B3 = 4'b0000,
107  parameter BYTE_LANES_B4 = 4'b0000,
108  parameter DQS_BYTE_MAP
109  = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
110  parameter CTL_BYTE_LANE = 8'hE4, // Control byte lane map
111  parameter CTL_BANK = 3'b000, // Bank used for control byte lanes
112  // Slot Conifg parameters
113  parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
114  // DRAM bus widths
115  parameter BANK_WIDTH = 2, // # of bank bits
116  parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
117  parameter COL_WIDTH = 10, // column address width
118  parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
119  parameter DQ_WIDTH = 64, // # of DQ (data)
120  parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
121  parameter DQS_WIDTH = 8, // # of DQS (strobe)
122  parameter DRAM_WIDTH = 8, // # of DQ per DQS
123  parameter ROW_WIDTH = 14, // DRAM address bus width
124  parameter RANKS = 1, // # of memory ranks in the interface
125  parameter CS_WIDTH = 1, // # of CS# signals in the interface
126  parameter CKE_WIDTH = 1, // # of cke outputs
127  parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
128  parameter PER_BIT_DESKEW = "ON",
129  // calibration Address. The address given below will be used for calibration
130  // read and write operations.
131  parameter NUM_DQSFOUND_CAL = 1020, // # of iteration of DQSFOUND calib
132  parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
133  parameter CALIB_COL_ADD = 12'h000, // Calibration column address
134  parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
135  // DRAM mode settings
136  parameter AL = "0", // Additive Latency option
137  parameter TEST_AL = "0", // Additive Latency for internal use
138  parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T"
139  parameter BURST_MODE = "8", // Burst length
140  parameter BURST_TYPE = "SEQ", // Burst type
141  parameter nCL = 5, // Read CAS latency (in clk cyc)
142  parameter nCWL = 5, // Write CAS latency (in clk cyc)
143  parameter tRFC = 110000, // Refresh-to-command delay
144  parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option
145  parameter REG_CTRL = "ON", // "ON" for registered DIMM
146  parameter RTT_NOM = "60", // ODT Nominal termination value
147  parameter RTT_WR = "60", // ODT Write termination value
148  parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA
149  // 1 - ODT output from FPGA
150  parameter WRLVL = "OFF", // Enable write leveling
151  parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
152 
153  // Simulation /debug options
154  parameter SIM_INIT_OPTION = "NONE", // Performs all initialization steps
155  parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
156  parameter CKE_ODT_AUX = "FALSE",
157  parameter DEBUG_PORT = "OFF" // Enable debug port
158  )
159  (
160  input clk, // Internal (logic) clock
161  input rst, // Reset sync'ed to CLK
162  // Slot present inputs
163  input [7:0] slot_0_present,
164  input [7:0] slot_1_present,
165  // Hard PHY signals
166  // From PHY Ctrl Block
167  input phy_ctl_ready,
168  input phy_ctl_full,
169  input phy_cmd_full,
170  input phy_data_full,
171  // To PHY Ctrl Block
172  output write_calib,
173  output read_calib,
174  output calib_ctl_wren,
175  output calib_cmd_wren,
176  output [1:0] calib_seq,
177  output [3:0] calib_aux_out,
178  output [nCK_PER_CLK -1:0] calib_cke,
179  output [1:0] calib_odt,
180  output [2:0] calib_cmd,
181  output calib_wrdata_en,
182  output [1:0] calib_rank_cnt,
183  output [1:0] calib_cas_slot,
184  output [5:0] calib_data_offset_0,
185  output [5:0] calib_data_offset_1,
186  output [5:0] calib_data_offset_2,
187  output [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address,
188  output [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank,
189  output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n,
190  output [nCK_PER_CLK-1:0] phy_ras_n,
191  output [nCK_PER_CLK-1:0] phy_cas_n,
192  output [nCK_PER_CLK-1:0] phy_we_n,
193  output phy_reset_n,
194  // To hard PHY wrapper
195 (* keep = "true", max_fanout = 10 *) output reg [5:0] calib_sel/* synthesis syn_maxfan = 10 **/,
196 (* keep = "true", max_fanout = 10 *) output reg calib_in_common/* synthesis syn_maxfan = 10 **/,
197 (* keep = "true", max_fanout = 10 *) output reg [HIGHEST_BANK-1:0] calib_zero_inputs/* synthesis syn_maxfan = 10 **/,
198  output reg [HIGHEST_BANK-1:0] calib_zero_ctrl,
199  output phy_if_empty_def,
200  output reg phy_if_reset,
201 // output reg ck_addr_ctl_delay_done,
202  // From DQS Phaser_In
203  input pi_phaselocked,
204  input pi_phase_locked_all,
205  input pi_found_dqs,
206  input pi_dqs_found_all,
207  input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
208  input [5:0] pi_counter_read_val,
209  // To DQS Phaser_In
210  output [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
211  output pi_en_stg2_f,
212  output pi_stg2_f_incdec,
213  output pi_stg2_load,
214  output [5:0] pi_stg2_reg_l,
215  // To DQ IDELAY
216  output idelay_ce,
217  output idelay_inc,
218  output idelay_ld,
219  // To DQS Phaser_Out
220 (* keep = "true", max_fanout = 3 *) output [2:0] po_sel_stg2stg3 /* synthesis syn_maxfan = 3 **/,
221 (* keep = "true", max_fanout = 3 *) output [2:0] po_stg2_c_incdec /* synthesis syn_maxfan = 3 **/,
222 (* keep = "true", max_fanout = 3 *) output [2:0] po_en_stg2_c /* synthesis syn_maxfan = 3 **/,
223 (* keep = "true", max_fanout = 3 *) output [2:0] po_stg2_f_incdec /* synthesis syn_maxfan = 3 **/,
224 (* keep = "true", max_fanout = 3 *) output [2:0] po_en_stg2_f /* synthesis syn_maxfan = 3 **/,
225  output po_counter_load_en,
226  input [8:0] po_counter_read_val,
227  // To command Phaser_Out
228  input phy_if_empty,
229  input [4:0] idelaye2_init_val,
230  input [5:0] oclkdelay_init_val,
231 
232  input tg_err,
233  output rst_tg_mc,
234  // Write data to OUT_FIFO
235  output [2*nCK_PER_CLK*DQ_WIDTH-1:0]phy_wrdata,
236  // To CNTVALUEIN input of DQ IDELAYs for perbit de-skew
237  output [5*RANKS*DQ_WIDTH-1:0] dlyval_dq,
238  // IN_FIFO read enable during write leveling, write calibration,
239  // and read leveling
240  // Read data from hard PHY fans out to mc and calib logic
241  input[2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata,
242  // To MC
243  output [6*RANKS-1:0] calib_rd_data_offset_0,
244  output [6*RANKS-1:0] calib_rd_data_offset_1,
245  output [6*RANKS-1:0] calib_rd_data_offset_2,
246  output phy_rddata_valid,
247  output calib_writes,
248 (* keep = "true", max_fanout = 10 *) output reg init_calib_complete/* synthesis syn_maxfan = 10 **/,
249  output init_wrcal_complete,
250  output pi_phase_locked_err,
251  output pi_dqsfound_err,
252  output wrcal_err,
253 
254  // Debug Port
255  output dbg_pi_phaselock_start,
256  output dbg_pi_dqsfound_start,
257  output dbg_pi_dqsfound_done,
258  output dbg_wrcal_start,
259  output dbg_wrcal_done,
260  output dbg_wrlvl_start,
261  output dbg_wrlvl_done,
262  output dbg_wrlvl_err,
263  output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
264  output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
265  output [255:0] dbg_phy_wrlvl,
266  output [5:0] dbg_tap_cnt_during_wrlvl,
267  output dbg_wl_edge_detect_valid,
268  output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
269 
270  // Write Calibration Logic
271  output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
272  output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
273  output [99:0] dbg_phy_wrcal,
274 
275  // Read leveling logic
276  output [1:0] dbg_rdlvl_start,
277  output [1:0] dbg_rdlvl_done,
278  output [1:0] dbg_rdlvl_err,
279  output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
280  output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
281  output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
282  output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
283 
284  // Delay control
285  input [11:0] device_temp,
286  input tempmon_sample_en,
287  input dbg_sel_pi_incdec,
288  input dbg_sel_po_incdec,
289  input [DQS_CNT_WIDTH:0] dbg_byte_sel,
290  input dbg_pi_f_inc,
291  input dbg_pi_f_dec,
292  input dbg_po_f_inc,
293  input dbg_po_f_stg23_sel,
294  input dbg_po_f_dec,
295  input dbg_idel_up_all,
296  input dbg_idel_down_all,
297  input dbg_idel_up_cpt,
298  input dbg_idel_down_cpt,
299  input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
300  input dbg_sel_all_idel_cpt,
301  output [255:0] dbg_phy_rdlvl, // Read leveling calibration
302  output [255:0] dbg_calib_top, // General PHY debug
303  output dbg_oclkdelay_calib_start,
304  output dbg_oclkdelay_calib_done,
305  output [255:0] dbg_phy_oclkdelay_cal,
306  output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
307  output [255:0] dbg_phy_init,
308  output [255:0] dbg_prbs_rdlvl,
309  output [255:0] dbg_dqs_found_cal
310  );
311 
312 // Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center
313 // align DQ and DQS on writes. Round (up or down) value to nearest integer
314 // localparam integer SHIFT_TBY4_TAP
315 // = (CLK_PERIOD + (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*2)-1) /
316 // (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*4);
317 
318 // Calculate number of slots in the system
319  localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
320 
321  localparam OCAL_EN = ((SIM_CAL_OPTION == "FAST_CAL") || (tCK > 2500)) ? "OFF" : "ON";
322 
323  // Different CTL_LANES value for DDR2. In DDR2 during DQS found all
324  // the add,ctl & data phaser out fine delays will be adjusted.
325  // In DDR3 only the add/ctrl lane delays will be adjusted
326  localparam DQS_FOUND_N_CTL_LANES = (DRAM_TYPE == "DDR3") ? N_CTL_LANES : 1;
327 
328  localparam DQSFOUND_CAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && tCK > 2500)) ? "LEFT" : "RIGHT"; // IO Bank used for Memory I/F: "LEFT", "RIGHT"
329 
330  wire [2*8*nCK_PER_CLK-1:0] prbs_seed;
331  wire [2*8*nCK_PER_CLK-1:0] prbs_out;
332  wire [7:0] prbs_rise0;
333  wire [7:0] prbs_fall0;
334  wire [7:0] prbs_rise1;
335  wire [7:0] prbs_fall1;
336  wire [7:0] prbs_rise2;
337  wire [7:0] prbs_fall2;
338  wire [7:0] prbs_rise3;
339  wire [7:0] prbs_fall3;
340  wire [2*8*nCK_PER_CLK-1:0] prbs_o;
341  wire dqsfound_retry;
342  wire dqsfound_retry_done;
343  wire phy_rddata_en;
344  wire prech_done;
345  wire rdlvl_stg1_done;
346  reg rdlvl_stg1_done_r1;
347  wire pi_dqs_found_done;
348  wire rdlvl_stg1_err;
349  wire pi_dqs_found_err;
350  wire wrcal_pat_resume;
351  wire wrcal_resume_w;
352  wire rdlvl_prech_req;
353  wire rdlvl_last_byte_done;
354  wire rdlvl_stg1_start;
355  wire rdlvl_stg1_rank_done;
356  wire rdlvl_assrt_common;
357  wire pi_dqs_found_start;
358  wire pi_dqs_found_rank_done;
359  wire wl_sm_start;
360  wire wrcal_start;
361  wire wrcal_rd_wait;
362  wire wrcal_prech_req;
363  wire wrcal_pat_err;
364  wire wrcal_done;
365  wire wrlvl_done;
366  wire wrlvl_err;
367  wire wrlvl_start;
368  wire ck_addr_cmd_delay_done;
369  wire po_ck_addr_cmd_delay_done;
370  wire pi_calib_done;
371  wire detect_pi_found_dqs;
372  wire [5:0] rd_data_offset_0;
373  wire [5:0] rd_data_offset_1;
374  wire [5:0] rd_data_offset_2;
375  wire [6*RANKS-1:0] rd_data_offset_ranks_0;
376  wire [6*RANKS-1:0] rd_data_offset_ranks_1;
377  wire [6*RANKS-1:0] rd_data_offset_ranks_2;
378  wire [6*RANKS-1:0] rd_data_offset_ranks_mc_0;
379  wire [6*RANKS-1:0] rd_data_offset_ranks_mc_1;
380  wire [6*RANKS-1:0] rd_data_offset_ranks_mc_2;
381  wire cmd_po_stg2_f_incdec;
382  wire cmd_po_stg2_incdec_ddr2_c;
383  wire cmd_po_en_stg2_f;
384  wire cmd_po_en_stg2_ddr2_c;
385  wire cmd_po_stg2_c_incdec;
386  wire cmd_po_en_stg2_c;
387  wire po_stg2_ddr2_incdec;
388  wire po_en_stg2_ddr2;
389  wire dqs_po_stg2_f_incdec;
390  wire dqs_po_en_stg2_f;
391  wire dqs_wl_po_stg2_c_incdec;
392  wire wrcal_po_stg2_c_incdec;
393  wire dqs_wl_po_en_stg2_c;
394  wire wrcal_po_en_stg2_c;
395  wire [N_CTL_LANES-1:0] ctl_lane_cnt;
396  reg [N_CTL_LANES-1:0] ctl_lane_sel;
397  wire [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt;
398  wire [DQS_CNT_WIDTH:0] po_stg2_wl_cnt;
399  wire [DQS_CNT_WIDTH:0] po_stg2_ddr2_cnt;
400  wire [8:0] dqs_wl_po_stg2_reg_l;
401  wire dqs_wl_po_stg2_load;
402  wire [8:0] dqs_po_stg2_reg_l;
403  wire dqs_po_stg2_load;
404  wire dqs_po_dec_done;
405  wire pi_fine_dly_dec_done;
406  wire rdlvl_pi_stg2_f_incdec;
407  wire rdlvl_pi_stg2_f_en;
408  wire [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt;
409  reg [DQS_CNT_WIDTH:0] byte_sel_cnt;
410  wire [3*DQS_WIDTH-1:0] wl_po_coarse_cnt;
411  wire [6*DQS_WIDTH-1:0] wl_po_fine_cnt;
412  wire phase_locked_err;
413  wire phy_ctl_rdy_dly;
414  wire idelay_ce_int;
415  wire idelay_inc_int;
416  reg idelay_ce_r1;
417  reg idelay_ce_r2;
418  reg idelay_inc_r1;
419 (* keep = "true", max_fanout = 30 *) reg idelay_inc_r2 /* synthesis syn_maxfan = 30 **/;
420  reg po_dly_req_r;
421  wire wrcal_read_req;
422  wire wrcal_act_req;
423  wire temp_wrcal_done;
424  wire tg_timer_done;
425  wire no_rst_tg_mc;
426  wire calib_complete;
427  reg reset_if_r1;
428  reg reset_if_r2;
429  reg reset_if_r3;
430  reg reset_if_r4;
431  reg reset_if_r5;
432  reg reset_if_r6;
433  reg reset_if_r7;
434  reg reset_if_r8;
435  reg reset_if_r9;
436  reg reset_if;
437  wire phy_if_reset_w;
438  wire pi_phaselock_start;
439 
440  reg dbg_pi_f_inc_r;
441  reg dbg_pi_f_en_r;
442  reg dbg_sel_pi_incdec_r;
443 
444  reg dbg_po_f_inc_r;
445  reg dbg_po_f_stg23_sel_r;
446  reg dbg_po_f_en_r;
447  reg dbg_sel_po_incdec_r;
448 
449  reg tempmon_pi_f_inc_r;
450  reg tempmon_pi_f_en_r;
451  reg tempmon_sel_pi_incdec_r;
452 
453  reg ck_addr_cmd_delay_done_r1;
454  reg ck_addr_cmd_delay_done_r2;
455  reg ck_addr_cmd_delay_done_r3;
456  reg ck_addr_cmd_delay_done_r4;
457  reg ck_addr_cmd_delay_done_r5;
458  reg ck_addr_cmd_delay_done_r6;
459  wire oclk_init_delay_start;
460  wire oclk_prech_req;
461  wire oclk_calib_resume;
462  wire oclk_init_delay_done;
463  wire [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
464  wire oclkdelay_calib_start;
465  wire oclkdelay_calib_done;
466  wire oclkdelay_calib_done_temp;
467  wire wrlvl_final;
468  wire wrlvl_final_if_rst;
469  wire wrlvl_byte_redo;
470  wire wrlvl_byte_done;
471  wire early1_data;
472  wire early2_data;
473  wire po_stg3_incdec;
474  wire po_en_stg3;
475  wire po_stg23_sel;
476  wire po_stg23_incdec;
477  wire po_en_stg23;
478  wire mpr_rdlvl_done;
479  wire mpr_rdlvl_start;
480  wire mpr_last_byte_done;
481  wire mpr_rnk_done;
482  wire mpr_end_if_reset;
483  wire mpr_rdlvl_err;
484  wire rdlvl_err;
485  wire prbs_rdlvl_start;
486  wire prbs_rdlvl_done;
487  reg prbs_rdlvl_done_r1;
488  wire prbs_last_byte_done;
489  wire prbs_rdlvl_prech_req;
490  wire prbs_pi_stg2_f_incdec;
491  wire prbs_pi_stg2_f_en;
492  wire [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt;
493  wire prbs_gen_clk_en;
494  wire rd_data_offset_cal_done;
495  wire fine_adjust_done;
496  wire [N_CTL_LANES-1:0] fine_adjust_lane_cnt;
497  wire ck_po_stg2_f_indec;
498  wire ck_po_stg2_f_en;
499  wire dqs_found_prech_req;
500  wire tempmon_pi_f_inc;
501  wire tempmon_pi_f_dec;
502  wire tempmon_sel_pi_incdec;
503  wire wrcal_sanity_chk;
504  wire wrcal_sanity_chk_done;
505 
506  //*****************************************************************************
507  // Assertions to check correctness of parameter values
508  //*****************************************************************************
509  // synthesis translate_off
510  initial
511  begin
512  if (RANKS == 0) begin
513  $display ("Error: Invalid RANKS parameter. Must be 1 or greater");
514  $finish;
515  end
516  if (phy_ctl_full == 1'b1) begin
517  $display ("Error: Incorrect phy_ctl_full input value in 2:1 or 4:1 mode");
518  $finish;
519  end
520  end
521  // synthesis translate_on
522 
523  //***************************************************************************
524  // Debug
525  //***************************************************************************
526 
527  assign dbg_pi_phaselock_start = pi_phaselock_start;
528  assign dbg_pi_dqsfound_start = pi_dqs_found_start;
529  assign dbg_pi_dqsfound_done = pi_dqs_found_done;
530  assign dbg_wrcal_start = wrcal_start;
531  assign dbg_wrcal_done = wrcal_done;
532 
533  // Unused for now - use these as needed to bring up lower level signals
534  assign dbg_calib_top = 256'd0;
535 
536  // Write Level and write calibration debug observation ports
537  assign dbg_wrlvl_start = wrlvl_start;
538  assign dbg_wrlvl_done = wrlvl_done;
539  assign dbg_wrlvl_err = wrlvl_err;
540 
541  // Read Level debug observation ports
542  assign dbg_rdlvl_start = {mpr_rdlvl_start, rdlvl_stg1_start};
543  assign dbg_rdlvl_done = {mpr_rdlvl_done, rdlvl_stg1_done};
544  assign dbg_rdlvl_err = {mpr_rdlvl_err, rdlvl_err};
545 
546  assign dbg_oclkdelay_calib_done = oclkdelay_calib_done;
547  assign dbg_oclkdelay_calib_start = oclkdelay_calib_start;
548 
549  //***************************************************************************
550  // Write leveling dependent signals
551  //***************************************************************************
552 
553  assign wrcal_resume_w = (WRLVL == "ON") ? wrcal_pat_resume : 1'b0;
554  assign wrlvl_done_w = (WRLVL == "ON") ? wrlvl_done : 1'b1;
555  assign ck_addr_cmd_delay_done = (WRLVL == "ON") ? po_ck_addr_cmd_delay_done :
556  (po_ck_addr_cmd_delay_done
557  && pi_fine_dly_dec_done) ;
558 
559  generate
560  genvar i;
561  for (i = 0; i <= 2; i = i+1) begin : bankwise_signal
562 
563  assign po_sel_stg2stg3[i] = ((~oclk_init_delay_done && ck_addr_cmd_delay_done &&
564  (DRAM_TYPE=="DDR3")) ? 1'b1 :
565  ~oclkdelay_calib_done ? po_stg23_sel : 1'b0
566  ) | dbg_po_f_stg23_sel_r;
567 
568  assign po_stg2_c_incdec[i] = cmd_po_stg2_c_incdec ||
569  cmd_po_stg2_incdec_ddr2_c ||
570  dqs_wl_po_stg2_c_incdec;
571 
572  assign po_en_stg2_c[i] = cmd_po_en_stg2_c ||
573  cmd_po_en_stg2_ddr2_c ||
574  dqs_wl_po_en_stg2_c;
575 
576  assign po_stg2_f_incdec[i] = dqs_po_stg2_f_incdec ||
577  cmd_po_stg2_f_incdec ||
578  po_stg3_incdec ||
579  ck_po_stg2_f_indec ||
580  po_stg23_incdec ||
581  dbg_po_f_inc_r;
582 
583  assign po_en_stg2_f[i] = dqs_po_en_stg2_f ||
584  cmd_po_en_stg2_f ||
585  po_en_stg3 ||
586  ck_po_stg2_f_en ||
587  po_en_stg23 ||
588  dbg_po_f_en_r;
589 
590  end
591  endgenerate
592 
593  assign pi_stg2_f_incdec = (dbg_pi_f_inc_r | rdlvl_pi_stg2_f_incdec | prbs_pi_stg2_f_incdec | tempmon_pi_f_inc_r);
594  assign pi_en_stg2_f = (dbg_pi_f_en_r | rdlvl_pi_stg2_f_en | prbs_pi_stg2_f_en | tempmon_pi_f_en_r);
595 
596  assign idelay_ce = idelay_ce_r2;
597  assign idelay_inc = idelay_inc_r2;
598 
599  assign po_counter_load_en = 1'b0;
600 
601 // Added single stage flop to meet timing
602  always @(posedge clk)
603  init_calib_complete <= calib_complete;
604 
605  assign calib_rd_data_offset_0 = rd_data_offset_ranks_mc_0;
606  assign calib_rd_data_offset_1 = rd_data_offset_ranks_mc_1;
607  assign calib_rd_data_offset_2 = rd_data_offset_ranks_mc_2;
608 
609  //***************************************************************************
610  // Hard PHY signals
611  //***************************************************************************
612 
613  assign pi_phase_locked_err = phase_locked_err;
614  assign pi_dqsfound_err = pi_dqs_found_err;
615  assign wrcal_err = wrcal_pat_err;
616  assign rst_tg_mc = 1'b0;
617 
618  always @(posedge clk)
619  phy_if_reset <= #TCQ (phy_if_reset_w | mpr_end_if_reset |
620  reset_if | wrlvl_final_if_rst);
621 
622  //***************************************************************************
623  // Phaser_IN inc dec control for debug
624  //***************************************************************************
625 
626  always @(posedge clk) begin
627  if (rst) begin
628  dbg_pi_f_inc_r <= #TCQ 1'b0;
629  dbg_pi_f_en_r <= #TCQ 1'b0;
630  dbg_sel_pi_incdec_r <= #TCQ 1'b0;
631  end else begin
632  dbg_pi_f_inc_r <= #TCQ dbg_pi_f_inc;
633  dbg_pi_f_en_r <= #TCQ (dbg_pi_f_inc | dbg_pi_f_dec);
634  dbg_sel_pi_incdec_r <= #TCQ dbg_sel_pi_incdec;
635  end
636  end
637 
638  //***************************************************************************
639  // Phaser_OUT inc dec control for debug
640  //***************************************************************************
641 
642  always @(posedge clk) begin
643  if (rst) begin
644  dbg_po_f_inc_r <= #TCQ 1'b0;
645  dbg_po_f_stg23_sel_r<= #TCQ 1'b0;
646  dbg_po_f_en_r <= #TCQ 1'b0;
647  dbg_sel_po_incdec_r <= #TCQ 1'b0;
648  end else begin
649  dbg_po_f_inc_r <= #TCQ dbg_po_f_inc;
650  dbg_po_f_stg23_sel_r<= #TCQ dbg_po_f_stg23_sel;
651  dbg_po_f_en_r <= #TCQ (dbg_po_f_inc | dbg_po_f_dec);
652  dbg_sel_po_incdec_r <= #TCQ dbg_sel_po_incdec;
653  end
654  end
655 
656  //***************************************************************************
657  // Phaser_IN inc dec control for temperature tracking
658  //***************************************************************************
659 
660  always @(posedge clk) begin
661  if (rst) begin
662  tempmon_pi_f_inc_r <= #TCQ 1'b0;
663  tempmon_pi_f_en_r <= #TCQ 1'b0;
664  tempmon_sel_pi_incdec_r <= #TCQ 1'b0;
665  end else begin
666  tempmon_pi_f_inc_r <= #TCQ tempmon_pi_f_inc;
667  tempmon_pi_f_en_r <= #TCQ (tempmon_pi_f_inc | tempmon_pi_f_dec);
668  tempmon_sel_pi_incdec_r <= #TCQ tempmon_sel_pi_incdec;
669  end
670  end
671 
672  //***************************************************************************
673  // OCLKDELAY calibration signals
674  //***************************************************************************
675 
676  // Minimum of 5 'clk' cycles required between assertion of po_sel_stg2stg3
677  // and increment/decrement of Phaser_Out stage 3 delay
678  always @(posedge clk) begin
679  ck_addr_cmd_delay_done_r1 <= #TCQ ck_addr_cmd_delay_done;
680  ck_addr_cmd_delay_done_r2 <= #TCQ ck_addr_cmd_delay_done_r1;
681  ck_addr_cmd_delay_done_r3 <= #TCQ ck_addr_cmd_delay_done_r2;
682  ck_addr_cmd_delay_done_r4 <= #TCQ ck_addr_cmd_delay_done_r3;
683  ck_addr_cmd_delay_done_r5 <= #TCQ ck_addr_cmd_delay_done_r4;
684  ck_addr_cmd_delay_done_r6 <= #TCQ ck_addr_cmd_delay_done_r5;
685  end
686 
687  assign oclk_init_delay_start = ck_addr_cmd_delay_done_r6 && (DRAM_TYPE=="DDR3"); // && (SIM_CAL_OPTION == "NONE")
688 
689 
690 
691  //***************************************************************************
692  // MUX select logic to select current byte undergoing calibration
693  // Use DQS_CAL_MAP to determine the correlation between the physical
694  // byte numbering, and the byte numbering within the hard PHY
695  //***************************************************************************
696 
697 generate
698  if (tCK > 2500) begin: gen_byte_sel_div2
699 
700  always @(posedge clk) begin
701  if (rst) begin
702  byte_sel_cnt <= #TCQ 'd0;
703  ctl_lane_sel <= #TCQ 'd0;
704  calib_in_common <= #TCQ 1'b0;
705  end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
706  byte_sel_cnt <= #TCQ 'd0;
707  calib_in_common <= #TCQ 1'b1;
708  end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin
709  byte_sel_cnt <= #TCQ 'd0;
710  ctl_lane_sel <= #TCQ 'd0;
711  calib_in_common <= #TCQ 1'b1;
712  end else if (~ck_addr_cmd_delay_done) begin
713  ctl_lane_sel <= #TCQ ctl_lane_cnt;
714  calib_in_common <= #TCQ 1'b0;
715  end else if (~fine_adjust_done && rd_data_offset_cal_done) begin
716  if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin
717  byte_sel_cnt <= #TCQ 'd0;
718  ctl_lane_sel <= #TCQ 'd0;
719  calib_in_common <= #TCQ 1'b1;
720  end else begin
721  byte_sel_cnt <= #TCQ 'd0;
722  ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;
723  calib_in_common <= #TCQ 1'b0;
724  end
725  end else if (~oclk_init_delay_done) begin
726  byte_sel_cnt <= #TCQ 'd0;
727  calib_in_common <= #TCQ 1'b1;
728  end else if (~pi_calib_done) begin
729  byte_sel_cnt <= #TCQ 'd0;
730  calib_in_common <= #TCQ 1'b1;
731  end else if (~pi_dqs_found_done) begin
732  byte_sel_cnt <= #TCQ 'd0;
733  calib_in_common <= #TCQ 1'b1;
734  end else if (~wrlvl_done_w) begin
735  if (SIM_CAL_OPTION != "FAST_CAL") begin
736  byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
737  calib_in_common <= #TCQ 1'b0;
738  end else begin
739  // Special case for FAST_CAL simulation only to ensure that
740  // calib_in_common isn't asserted too soon
741  if (!phy_ctl_rdy_dly) begin
742  byte_sel_cnt <= #TCQ 'd0;
743  calib_in_common <= #TCQ 1'b0;
744  end else begin
745  byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
746  calib_in_common <= #TCQ 1'b1;
747  end
748  end
749  end else if (~mpr_rdlvl_done) begin
750  byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
751  calib_in_common <= #TCQ 1'b0;
752  end else if (~oclkdelay_calib_done) begin
753  byte_sel_cnt <= #TCQ oclkdelay_calib_cnt;
754  calib_in_common <= #TCQ 1'b0;
755  end else if (~rdlvl_stg1_done && pi_calib_done) begin
756  if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin
757  byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
758  calib_in_common <= #TCQ 1'b1;
759  end else begin
760  byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
761  calib_in_common <= #TCQ 1'b0;
762  end
763  end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin
764  byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt;
765  calib_in_common <= #TCQ 1'b0;
766  end else if (~wrcal_done) begin
767  byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;
768  calib_in_common <= #TCQ 1'b0;
769  end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin
770  byte_sel_cnt <= #TCQ dbg_byte_sel;
771  calib_in_common <= #TCQ 1'b0;
772  end else if (tempmon_sel_pi_incdec) begin
773  byte_sel_cnt <= #TCQ 'd0;
774  calib_in_common <= #TCQ 1'b1;
775  end
776  end
777 
778  end else begin: gen_byte_sel_div1
779 
780  always @(posedge clk) begin
781  if (rst) begin
782  byte_sel_cnt <= #TCQ 'd0;
783  ctl_lane_sel <= #TCQ 'd0;
784  calib_in_common <= #TCQ 1'b0;
785  end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
786  byte_sel_cnt <= #TCQ 'd0;
787  calib_in_common <= #TCQ 1'b1;
788  end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin
789  byte_sel_cnt <= #TCQ 'd0;
790  ctl_lane_sel <= #TCQ 'd0;
791  calib_in_common <= #TCQ 1'b1;
792  end else if (~ck_addr_cmd_delay_done) begin
793  ctl_lane_sel <= #TCQ ctl_lane_cnt;
794  calib_in_common <= #TCQ 1'b0;
795  end else if (~fine_adjust_done && rd_data_offset_cal_done) begin
796  if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin
797  byte_sel_cnt <= #TCQ 'd0;
798  ctl_lane_sel <= #TCQ 'd0;
799  calib_in_common <= #TCQ 1'b1;
800  end else begin
801  byte_sel_cnt <= #TCQ 'd0;
802  ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;
803  calib_in_common <= #TCQ 1'b0;
804  end
805  end else if (~oclk_init_delay_done) begin
806  byte_sel_cnt <= #TCQ 'd0;
807  calib_in_common <= #TCQ 1'b1;
808  end else if (~pi_calib_done) begin
809  byte_sel_cnt <= #TCQ 'd0;
810  calib_in_common <= #TCQ 1'b1;
811  end else if (~pi_dqs_found_done) begin
812  byte_sel_cnt <= #TCQ 'd0;
813  calib_in_common <= #TCQ 1'b1;
814  end else if (~wrlvl_done_w) begin
815  if (SIM_CAL_OPTION != "FAST_CAL") begin
816  byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
817  calib_in_common <= #TCQ 1'b0;
818  end else begin
819  // Special case for FAST_CAL simulation only to ensure that
820  // calib_in_common isn't asserted too soon
821  if (!phy_ctl_rdy_dly) begin
822  byte_sel_cnt <= #TCQ 'd0;
823  calib_in_common <= #TCQ 1'b0;
824  end else begin
825  byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
826  calib_in_common <= #TCQ 1'b1;
827  end
828  end
829  end else if (~mpr_rdlvl_done) begin
830  byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
831  calib_in_common <= #TCQ 1'b0;
832  end else if (~oclkdelay_calib_done) begin
833  byte_sel_cnt <= #TCQ oclkdelay_calib_cnt;
834  calib_in_common <= #TCQ 1'b0;
835  end else if ((~wrcal_done)&& (DRAM_TYPE == "DDR3")) begin
836  byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;
837  calib_in_common <= #TCQ 1'b0;
838  end else if (~rdlvl_stg1_done && pi_calib_done) begin
839  if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin
840  byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
841  calib_in_common <= #TCQ 1'b1;
842  end else begin
843  byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
844  calib_in_common <= #TCQ 1'b0;
845  end
846  end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin
847  byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt;
848  calib_in_common <= #TCQ 1'b0;
849  end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin
850  byte_sel_cnt <= #TCQ dbg_byte_sel;
851  calib_in_common <= #TCQ 1'b0;
852  end else if (tempmon_sel_pi_incdec) begin
853  byte_sel_cnt <= #TCQ 'd0;
854  calib_in_common <= #TCQ 1'b1;
855  end
856  end
857 
858  end
859 endgenerate
860 
861 
862  always @(posedge clk) begin
863  if (rst || (calib_complete && ~ (dbg_sel_pi_incdec_r|dbg_sel_po_incdec_r|tempmon_sel_pi_incdec) )) begin
864  calib_sel <= #TCQ 6'b000100;
865  calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
866  calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
867  end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
868  calib_sel[2] <= #TCQ 1'b0;
869  calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
870  calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
871  calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
872  if (~dqs_po_dec_done && (WRLVL != "ON"))
873  //if (~dqs_po_dec_done && ((SIM_CAL_OPTION == "FAST_CAL") ||(WRLVL != "ON")))
874  calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};
875  else
876  calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
877  end else if (~ck_addr_cmd_delay_done || (~fine_adjust_done && rd_data_offset_cal_done)) begin
878  if(WRLVL =="ON") begin
879  calib_sel[2] <= #TCQ 1'b0;
880  calib_sel[1:0] <= #TCQ CTL_BYTE_LANE[(ctl_lane_sel*2)+:2];
881  calib_sel[5:3] <= #TCQ CTL_BANK;
882  if (|pi_rst_stg1_cal) begin
883  calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
884  end else begin
885  calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
886  calib_zero_inputs[1*CTL_BANK] <= #TCQ 1'b0;
887  end
888  calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
889  end else begin // if (WRLVL =="ON")
890  calib_sel[2] <= #TCQ 1'b0;
891  calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
892  calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
893  calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
894  if(~ck_addr_cmd_delay_done)
895  calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
896  else
897  calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};
898  end // else: !if(WRLVL =="ON")
899  end else if (~oclk_init_delay_done) begin
900  calib_sel[2] <= #TCQ 1'b0;
901  calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
902  calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
903  calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
904  calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
905  end else if ((~wrlvl_done_w) && (SIM_CAL_OPTION == "FAST_CAL")) begin
906  calib_sel[2] <= #TCQ 1'b0;
907  calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
908  calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
909  calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
910  calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
911  end else if (~rdlvl_stg1_done && (SIM_CAL_OPTION == "FAST_CAL") &&
912  rdlvl_assrt_common) begin
913  calib_sel[2] <= #TCQ 1'b0;
914  calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
915  calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
916  calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
917  calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
918  end else if (tempmon_sel_pi_incdec) begin
919  calib_sel[2] <= #TCQ 1'b0;
920  calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
921  calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
922  calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
923  calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
924  end else begin
925  calib_sel[2] <= #TCQ 1'b0;
926  calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
927  calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
928  calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
929  if (~calib_in_common) begin
930  calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
931  calib_zero_inputs[(1*DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3])] <= #TCQ 1'b0;
932  end else
933  calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
934  end
935  end
936 
937  // Logic to reset IN_FIFO flags to account for the possibility that
938  // one or more PHASER_IN's have not correctly found the DQS preamble
939  // If this happens, we can still complete read leveling, but the # of
940  // words written into the IN_FIFO's may be an odd #, so that if the
941  // IN_FIFO is used in 2:1 mode ("8:4 mode"), there may be a "half" word
942  // of data left that can only be flushed out by reseting the IN_FIFO
943  always @(posedge clk) begin
944  rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done;
945  prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done;
946  reset_if_r1 <= #TCQ reset_if;
947  reset_if_r2 <= #TCQ reset_if_r1;
948  reset_if_r3 <= #TCQ reset_if_r2;
949  reset_if_r4 <= #TCQ reset_if_r3;
950  reset_if_r5 <= #TCQ reset_if_r4;
951  reset_if_r6 <= #TCQ reset_if_r5;
952  reset_if_r7 <= #TCQ reset_if_r6;
953  reset_if_r8 <= #TCQ reset_if_r7;
954  reset_if_r9 <= #TCQ reset_if_r8;
955  end
956 
957  always @(posedge clk) begin
958  if (rst || reset_if_r9)
959  reset_if <= #TCQ 1'b0;
960  else if ((rdlvl_stg1_done && ~rdlvl_stg1_done_r1) ||
961  (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
962  reset_if <= #TCQ 1'b1;
963  end
964 
965  assign phy_if_empty_def = 1'b0;
966 
967  // DQ IDELAY tap inc and ce signals registered to control calib_in_common
968  // signal during read leveling in FAST_CAL mode. The calib_in_common signal
969  // is only asserted for IDELAY tap increments not Phaser_IN tap increments
970  // in FAST_CAL mode. For Phaser_IN tap increments the Phaser_IN counter load
971  // inputs are used.
972  always @(posedge clk) begin
973  if (rst) begin
974  idelay_ce_r1 <= #TCQ 1'b0;
975  idelay_ce_r2 <= #TCQ 1'b0;
976  idelay_inc_r1 <= #TCQ 1'b0;
977  idelay_inc_r2 <= #TCQ 1'b0;
978  end else begin
979  idelay_ce_r1 <= #TCQ idelay_ce_int;
980  idelay_ce_r2 <= #TCQ idelay_ce_r1;
981  idelay_inc_r1 <= #TCQ idelay_inc_int;
982  idelay_inc_r2 <= #TCQ idelay_inc_r1;
983  end
984  end
985 
986  //***************************************************************************
987  // Delay all Outputs using Phaser_Out fine taps
988  //***************************************************************************
989 
990  assign init_wrcal_complete = 1'b0;
991 
992  //***************************************************************************
993  // PRBS Generator for Read Leveling Stage 1 - read window detection and
994  // DQS Centering
995  //***************************************************************************
996 
997  // Assign initial seed (used for 1st data word in 8-burst sequence); use alternating 1/0 pat
998  assign prbs_seed = 64'h9966aa559966aa55;
999 
1000  // A single PRBS generator
1001  // writes 64-bits every 4to1 fabric clock cycle and
1002  // write 32-bits every 2to1 fabric clock cycle
1003  mig_7series_v1_9_ddr_prbs_gen #
1004  (
1005  .TCQ (TCQ),
1006  .PRBS_WIDTH (2*8*nCK_PER_CLK)
1007  )
1008  u_ddr_prbs_gen
1009  (
1010  .clk_i (clk),
1011  .clk_en_i (prbs_gen_clk_en),
1012  .rst_i (rst),
1013  .prbs_o (prbs_out),
1014  .prbs_seed_i (prbs_seed),
1015  .phy_if_empty (phy_if_empty),
1016  .prbs_rdlvl_start (prbs_rdlvl_start)
1017  );
1018 
1019 // PRBS data slice that decides the Rise0, Fall0, Rise1, Fall1,
1020 // Rise2, Fall2, Rise3, Fall3 data
1021  generate
1022  if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4
1023  assign prbs_rise0 = prbs_out[7:0];
1024  assign prbs_fall0 = prbs_out[15:8];
1025  assign prbs_rise1 = prbs_out[23:16];
1026  assign prbs_fall1 = prbs_out[31:24];
1027  assign prbs_rise2 = prbs_out[39:32];
1028  assign prbs_fall2 = prbs_out[47:40];
1029  assign prbs_rise3 = prbs_out[55:48];
1030  assign prbs_fall3 = prbs_out[63:56];
1031  assign prbs_o = {prbs_fall3, prbs_rise3, prbs_fall2, prbs_rise2,
1032  prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};
1033  end else begin :gen_ck_per_clk2
1034  assign prbs_rise0 = prbs_out[7:0];
1035  assign prbs_fall0 = prbs_out[15:8];
1036  assign prbs_rise1 = prbs_out[23:16];
1037  assign prbs_fall1 = prbs_out[31:24];
1038  assign prbs_o = {prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};
1039  end
1040  endgenerate
1041 
1042 
1043  //***************************************************************************
1044  // Initialization / Master PHY state logic (overall control during memory
1045  // init, timing leveling)
1046  //***************************************************************************
1047 
1048  mig_7series_v1_9_ddr_phy_init #
1049  (
1050  .TCQ (TCQ),
1051  .nCK_PER_CLK (nCK_PER_CLK),
1052  .CLK_PERIOD (CLK_PERIOD),
1053  .DRAM_TYPE (DRAM_TYPE),
1054  .PRBS_WIDTH (PRBS_WIDTH),
1055  .BANK_WIDTH (BANK_WIDTH),
1056  .CA_MIRROR (CA_MIRROR),
1057  .COL_WIDTH (COL_WIDTH),
1058  .nCS_PER_RANK (nCS_PER_RANK),
1059  .DQ_WIDTH (DQ_WIDTH),
1060  .DQS_WIDTH (DQS_WIDTH),
1061  .DQS_CNT_WIDTH (DQS_CNT_WIDTH),
1062  .ROW_WIDTH (ROW_WIDTH),
1063  .CS_WIDTH (CS_WIDTH),
1064  .RANKS (RANKS),
1065  .CKE_WIDTH (CKE_WIDTH),
1066  .CALIB_ROW_ADD (CALIB_ROW_ADD),
1067  .CALIB_COL_ADD (CALIB_COL_ADD),
1068  .CALIB_BA_ADD (CALIB_BA_ADD),
1069  .AL (AL),
1070  .BURST_MODE (BURST_MODE),
1071  .BURST_TYPE (BURST_TYPE),
1072  .nCL (nCL),
1073  .nCWL (nCWL),
1074  .tRFC (tRFC),
1075  .OUTPUT_DRV (OUTPUT_DRV),
1076  .REG_CTRL (REG_CTRL),
1077  .ADDR_CMD_MODE (ADDR_CMD_MODE),
1078  .RTT_NOM (RTT_NOM),
1079  .RTT_WR (RTT_WR),
1080  .WRLVL (WRLVL),
1081  .USE_ODT_PORT (USE_ODT_PORT),
1082  .DDR2_DQSN_ENABLE(DDR2_DQSN_ENABLE),
1083  .nSLOTS (nSLOTS),
1084  .SIM_INIT_OPTION (SIM_INIT_OPTION),
1085  .SIM_CAL_OPTION (SIM_CAL_OPTION),
1086  .CKE_ODT_AUX (CKE_ODT_AUX),
1087  .PRE_REV3ES (PRE_REV3ES),
1088  .TEST_AL (TEST_AL)
1089  )
1090  u_ddr_phy_init
1091  (
1092  .clk (clk),
1093  .rst (rst),
1094  .prbs_o (prbs_o),
1095  .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),
1096  .delay_incdec_done (ck_addr_cmd_delay_done & oclk_init_delay_done),
1097  .pi_phase_locked_all (pi_phase_locked_all),
1098  .pi_phaselock_start (pi_phaselock_start),
1099  .pi_phase_locked_err (phase_locked_err),
1100  .pi_calib_done (pi_calib_done),
1101  .phy_if_empty (phy_if_empty),
1102  .phy_ctl_ready (phy_ctl_ready),
1103  .phy_ctl_full (phy_ctl_full),
1104  .phy_cmd_full (phy_cmd_full),
1105  .phy_data_full (phy_data_full),
1106  .calib_ctl_wren (calib_ctl_wren),
1107  .calib_cmd_wren (calib_cmd_wren),
1108  .calib_wrdata_en (calib_wrdata_en),
1109  .calib_seq (calib_seq),
1110  .calib_aux_out (calib_aux_out),
1111  .calib_rank_cnt (calib_rank_cnt),
1112  .calib_cas_slot (calib_cas_slot),
1113  .calib_data_offset_0 (calib_data_offset_0),
1114  .calib_data_offset_1 (calib_data_offset_1),
1115  .calib_data_offset_2 (calib_data_offset_2),
1116  .calib_cmd (calib_cmd),
1117  .calib_cke (calib_cke),
1118  .calib_odt (calib_odt),
1119  .write_calib (write_calib),
1120  .read_calib (read_calib),
1121  .wrlvl_done (wrlvl_done),
1122  .wrlvl_rank_done (wrlvl_rank_done),
1123  .wrlvl_byte_done (wrlvl_byte_done),
1124  .wrlvl_byte_redo (wrlvl_byte_redo),
1125  .wrlvl_final (wrlvl_final),
1126  .wrlvl_final_if_rst (wrlvl_final_if_rst),
1127  .oclkdelay_calib_start (oclkdelay_calib_start),
1128  .oclkdelay_calib_done (oclkdelay_calib_done),
1129  .oclk_prech_req (oclk_prech_req),
1130  .oclk_calib_resume (oclk_calib_resume),
1131  .done_dqs_tap_inc (done_dqs_tap_inc),
1132  .wl_sm_start (wl_sm_start),
1133  .wr_lvl_start (wrlvl_start),
1134  .slot_0_present (slot_0_present),
1135  .slot_1_present (slot_1_present),
1136  .mpr_rdlvl_done (mpr_rdlvl_done),
1137  .mpr_rdlvl_start (mpr_rdlvl_start),
1138  .mpr_last_byte_done (mpr_last_byte_done),
1139  .mpr_rnk_done (mpr_rnk_done),
1140  .mpr_end_if_reset (mpr_end_if_reset),
1141  .rdlvl_stg1_done (rdlvl_stg1_done),
1142  .rdlvl_stg1_rank_done (rdlvl_stg1_rank_done),
1143  .rdlvl_stg1_start (rdlvl_stg1_start),
1144  .rdlvl_prech_req (rdlvl_prech_req),
1145  .rdlvl_last_byte_done (rdlvl_last_byte_done),
1146  .prbs_rdlvl_start (prbs_rdlvl_start),
1147  .prbs_rdlvl_done (prbs_rdlvl_done),
1148  .prbs_last_byte_done (prbs_last_byte_done),
1149  .prbs_rdlvl_prech_req (prbs_rdlvl_prech_req),
1150  .prbs_gen_clk_en (prbs_gen_clk_en),
1151  .pi_dqs_found_start (pi_dqs_found_start),
1152  .dqsfound_retry (dqsfound_retry),
1153  .dqs_found_prech_req (dqs_found_prech_req),
1154  .pi_dqs_found_rank_done(pi_dqs_found_rank_done),
1155  .pi_dqs_found_done (pi_dqs_found_done),
1156  .detect_pi_found_dqs (detect_pi_found_dqs),
1157  .rd_data_offset_0 (rd_data_offset_0),
1158  .rd_data_offset_1 (rd_data_offset_1),
1159  .rd_data_offset_2 (rd_data_offset_2),
1160  .rd_data_offset_ranks_0(rd_data_offset_ranks_0),
1161  .rd_data_offset_ranks_1(rd_data_offset_ranks_1),
1162  .rd_data_offset_ranks_2(rd_data_offset_ranks_2),
1163  .wrcal_start (wrcal_start),
1164  .wrcal_rd_wait (wrcal_rd_wait),
1165  .wrcal_prech_req (wrcal_prech_req),
1166  .wrcal_resume (wrcal_resume_w),
1167  .wrcal_read_req (wrcal_read_req),
1168  .wrcal_act_req (wrcal_act_req),
1169  .wrcal_sanity_chk (wrcal_sanity_chk),
1170  .temp_wrcal_done (temp_wrcal_done),
1171  .wrcal_sanity_chk_done (wrcal_sanity_chk_done),
1172  .tg_timer_done (tg_timer_done),
1173  .no_rst_tg_mc (no_rst_tg_mc),
1174  .wrcal_done (wrcal_done),
1175  .prech_done (prech_done),
1176  .calib_writes (calib_writes),
1177  .init_calib_complete (calib_complete),
1178  .phy_address (phy_address),
1179  .phy_bank (phy_bank),
1180  .phy_cas_n (phy_cas_n),
1181  .phy_cs_n (phy_cs_n),
1182  .phy_ras_n (phy_ras_n),
1183  .phy_reset_n (phy_reset_n),
1184  .phy_we_n (phy_we_n),
1185  .phy_wrdata (phy_wrdata),
1186  .phy_rddata_en (phy_rddata_en),
1187  .phy_rddata_valid (phy_rddata_valid),
1188  .dbg_phy_init (dbg_phy_init)
1189  );
1190 
1191 
1192  //*****************************************************************
1193  // Write Calibration
1194  //*****************************************************************
1195 
1196  mig_7series_v1_9_ddr_phy_wrcal #
1197  (
1198  .TCQ (TCQ),
1199  .nCK_PER_CLK (nCK_PER_CLK),
1200  .CLK_PERIOD (CLK_PERIOD),
1201  .DQ_WIDTH (DQ_WIDTH),
1202  .DQS_CNT_WIDTH (DQS_CNT_WIDTH),
1203  .DQS_WIDTH (DQS_WIDTH),
1204  .DRAM_WIDTH (DRAM_WIDTH),
1205  .SIM_CAL_OPTION (SIM_CAL_OPTION)
1206  )
1207  u_ddr_phy_wrcal
1208  (
1209  .clk (clk),
1210  .rst (rst),
1211  .wrcal_start (wrcal_start),
1212  .wrcal_rd_wait (wrcal_rd_wait),
1213  .wrcal_sanity_chk (wrcal_sanity_chk),
1214  .dqsfound_retry_done (pi_dqs_found_done),
1215  .dqsfound_retry (dqsfound_retry),
1216  .wrcal_read_req (wrcal_read_req),
1217  .wrcal_act_req (wrcal_act_req),
1218  .phy_rddata_en (phy_rddata_en),
1219  .wrcal_done (wrcal_done),
1220  .wrcal_pat_err (wrcal_pat_err),
1221  .wrcal_prech_req (wrcal_prech_req),
1222  .temp_wrcal_done (temp_wrcal_done),
1223  .wrcal_sanity_chk_done (wrcal_sanity_chk_done),
1224  .prech_done (prech_done),
1225  .rd_data (phy_rddata),
1226  .wrcal_pat_resume (wrcal_pat_resume),
1227  .po_stg2_wrcal_cnt (po_stg2_wrcal_cnt),
1228  .phy_if_reset (phy_if_reset_w),
1229  .wl_po_coarse_cnt (wl_po_coarse_cnt),
1230  .wl_po_fine_cnt (wl_po_fine_cnt),
1231  .wrlvl_byte_redo (wrlvl_byte_redo),
1232  .wrlvl_byte_done (wrlvl_byte_done),
1233  .early1_data (early1_data),
1234  .early2_data (early2_data),
1235  .idelay_ld (idelay_ld),
1236  .dbg_phy_wrcal (dbg_phy_wrcal),
1237  .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
1238  .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt)
1239  );
1240 
1241 
1242 
1243  //***************************************************************************
1244  // Write-leveling calibration logic
1245  //***************************************************************************
1246 
1247  generate
1248  if (WRLVL == "ON") begin: mb_wrlvl_inst
1249 
1250  mig_7series_v1_9_ddr_phy_wrlvl #
1251  (
1252  .TCQ (TCQ),
1253  .DQS_CNT_WIDTH (DQS_CNT_WIDTH),
1254  .DQ_WIDTH (DQ_WIDTH),
1255  .DQS_WIDTH (DQS_WIDTH),
1256  .DRAM_WIDTH (DRAM_WIDTH),
1257  .RANKS (1),
1258  .CLK_PERIOD (CLK_PERIOD),
1259  .nCK_PER_CLK (nCK_PER_CLK),
1260  .SIM_CAL_OPTION (SIM_CAL_OPTION)
1261  )
1262  u_ddr_phy_wrlvl
1263  (
1264  .clk (clk),
1265  .rst (rst),
1266  .phy_ctl_ready (phy_ctl_ready),
1267  .wr_level_start (wrlvl_start),
1268  .wl_sm_start (wl_sm_start),
1269  .wrlvl_byte_redo (wrlvl_byte_redo),
1270  .wrcal_cnt (po_stg2_wrcal_cnt),
1271  .early1_data (early1_data),
1272  .early2_data (early2_data),
1273  .wrlvl_final (wrlvl_final),
1274  .oclkdelay_calib_cnt (oclkdelay_calib_cnt),
1275  .wrlvl_byte_done (wrlvl_byte_done),
1276  .oclkdelay_calib_done (oclkdelay_calib_done),
1277  .rd_data_rise0 (phy_rddata[DQ_WIDTH-1:0]),
1278  .dqs_po_dec_done (dqs_po_dec_done),
1279  .phy_ctl_rdy_dly (phy_ctl_rdy_dly),
1280  .wr_level_done (wrlvl_done),
1281  .wrlvl_rank_done (wrlvl_rank_done),
1282  .done_dqs_tap_inc (done_dqs_tap_inc),
1283  .dqs_po_stg2_f_incdec (dqs_po_stg2_f_incdec),
1284  .dqs_po_en_stg2_f (dqs_po_en_stg2_f),
1285  .dqs_wl_po_stg2_c_incdec (dqs_wl_po_stg2_c_incdec),
1286  .dqs_wl_po_en_stg2_c (dqs_wl_po_en_stg2_c),
1287  .po_counter_read_val (po_counter_read_val),
1288  .po_stg2_wl_cnt (po_stg2_wl_cnt),
1289  .wrlvl_err (wrlvl_err),
1290  .wl_po_coarse_cnt (wl_po_coarse_cnt),
1291  .wl_po_fine_cnt (wl_po_fine_cnt),
1292  .dbg_wl_tap_cnt (dbg_tap_cnt_during_wrlvl),
1293  .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
1294  .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
1295  .dbg_dqs_count (),
1296  .dbg_wl_state (),
1297  .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
1298  .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
1299  .dbg_phy_wrlvl (dbg_phy_wrlvl)
1300  );
1301 
1302 
1303  mig_7series_v1_9_ddr_phy_ck_addr_cmd_delay #
1304  (
1305  .TCQ (TCQ),
1306  .tCK (tCK),
1307  .DQS_CNT_WIDTH (DQS_CNT_WIDTH),
1308  .N_CTL_LANES (N_CTL_LANES),
1309  .SIM_CAL_OPTION(SIM_CAL_OPTION)
1310  )
1311  u_ddr_phy_ck_addr_cmd_delay
1312  (
1313  .clk (clk),
1314  .rst (rst),
1315  .cmd_delay_start (dqs_po_dec_done & pi_fine_dly_dec_done),
1316  .ctl_lane_cnt (ctl_lane_cnt),
1317  .po_stg2_f_incdec (cmd_po_stg2_f_incdec),
1318  .po_en_stg2_f (cmd_po_en_stg2_f),
1319  .po_stg2_c_incdec (cmd_po_stg2_c_incdec),
1320  .po_en_stg2_c (cmd_po_en_stg2_c),
1321  .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done)
1322  );
1323 
1324  assign cmd_po_stg2_incdec_ddr2_c = 1'b0;
1325  assign cmd_po_en_stg2_ddr2_c = 1'b0;
1326 
1327  end else begin: mb_wrlvl_off
1328 
1329  mig_7series_v1_9_ddr_phy_wrlvl_off_delay #
1330  (
1331  .TCQ (TCQ),
1332  .tCK (tCK),
1333  .nCK_PER_CLK (nCK_PER_CLK),
1334  .CLK_PERIOD (CLK_PERIOD),
1335  .PO_INITIAL_DLY(60),
1336  .DQS_CNT_WIDTH (DQS_CNT_WIDTH),
1337  .DQS_WIDTH (DQS_WIDTH),
1338  .N_CTL_LANES (N_CTL_LANES)
1339  )
1340  u_phy_wrlvl_off_delay
1341  (
1342  .clk (clk),
1343  .rst (rst),
1344  .pi_fine_dly_dec_done (pi_fine_dly_dec_done),
1345  .cmd_delay_start (phy_ctl_ready),
1346  .ctl_lane_cnt (ctl_lane_cnt),
1347  .po_s2_incdec_f (cmd_po_stg2_f_incdec),
1348  .po_en_s2_f (cmd_po_en_stg2_f),
1349  .po_s2_incdec_c (cmd_po_stg2_incdec_ddr2_c),
1350  .po_en_s2_c (cmd_po_en_stg2_ddr2_c),
1351  .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done),
1352  .po_dec_done (dqs_po_dec_done),
1353  .phy_ctl_rdy_dly (phy_ctl_rdy_dly)
1354  );
1355 
1356  assign wrlvl_done = 1'b1;
1357  assign wrlvl_err = 1'b0;
1358  assign dqs_po_stg2_f_incdec = 1'b0;
1359  assign dqs_po_en_stg2_f = 1'b0;
1360  assign dqs_wl_po_en_stg2_c = 1'b0;
1361  assign cmd_po_stg2_c_incdec = 1'b0;
1362  assign dqs_wl_po_stg2_c_incdec = 1'b0;
1363  assign cmd_po_en_stg2_c = 1'b0;
1364 
1365  end
1366  endgenerate
1367 
1368  generate
1369  if(WRLVL == "ON") begin: oclk_calib
1370  mig_7series_v1_9_ddr_phy_oclkdelay_cal #
1371  (
1372  .TCQ (TCQ),
1373  .tCK (tCK),
1374  .nCK_PER_CLK (nCK_PER_CLK),
1375  .DRAM_TYPE (DRAM_TYPE),
1376  .DRAM_WIDTH (DRAM_WIDTH),
1377  .DQS_CNT_WIDTH (DQS_CNT_WIDTH),
1378  .DQS_WIDTH (DQS_WIDTH),
1379  .DQ_WIDTH (DQ_WIDTH),
1380  .SIM_CAL_OPTION (SIM_CAL_OPTION),
1381  .OCAL_EN (OCAL_EN)
1382  )
1383  u_ddr_phy_oclkdelay_cal
1384  (
1385  .clk (clk),
1386  .rst (rst),
1387  .oclk_init_delay_start (oclk_init_delay_start),
1388  .oclkdelay_calib_start (oclkdelay_calib_start),
1389  .oclkdelay_init_val (oclkdelay_init_val),
1390  .phy_rddata_en (phy_rddata_en),
1391  .rd_data (phy_rddata),
1392  .prech_done (prech_done),
1393  .wl_po_fine_cnt (wl_po_fine_cnt),
1394  .po_stg3_incdec (po_stg3_incdec),
1395  .po_en_stg3 (po_en_stg3),
1396  .po_stg23_sel (po_stg23_sel),
1397  .po_stg23_incdec (po_stg23_incdec),
1398  .po_en_stg23 (po_en_stg23),
1399  .wrlvl_final (wrlvl_final),
1400  .oclk_prech_req (oclk_prech_req),
1401  .oclk_calib_resume (oclk_calib_resume),
1402  .oclk_init_delay_done (oclk_init_delay_done),
1403  .oclkdelay_calib_cnt (oclkdelay_calib_cnt),
1404  .oclkdelay_calib_done (oclkdelay_calib_done),
1405  .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
1406  .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data)
1407  );
1408  end else begin : oclk_calib_disabled
1409 
1410  assign wrlvl_final = 'b0;
1411  assign po_stg3_incdec = 'b0;
1412  assign po_en_stg3 = 'b0;
1413  assign po_stg23_sel = 'b0;
1414  assign po_stg23_incdec = 'b0;
1415  assign po_en_stg23 = 'b0;
1416  assign oclk_init_delay_done = 1'b1;
1417  assign oclkdelay_calib_cnt = 'b0;
1418  assign oclk_prech_req = 'b0;
1419  assign oclk_calib_resume = 'b0;
1420  assign oclkdelay_calib_done = 1'b1;
1421 
1422  end
1423  endgenerate
1424 
1425 
1426  //***************************************************************************
1427  // Read data-offset calibration required for Phaser_In
1428  //***************************************************************************
1429 
1430  generate
1431  if(DQSFOUND_CAL == "RIGHT") begin: dqsfind_calib_right
1432  mig_7series_v1_9_ddr_phy_dqs_found_cal #
1433  (
1434  .TCQ (TCQ),
1435  .nCK_PER_CLK (nCK_PER_CLK),
1436  .nCL (nCL),
1437  .AL (AL),
1438  .nCWL (nCWL),
1439  //.RANKS (RANKS),
1440  .RANKS (1),
1441  .DQS_CNT_WIDTH (DQS_CNT_WIDTH),
1442  .DQS_WIDTH (DQS_WIDTH),
1443  .DRAM_WIDTH (DRAM_WIDTH),
1444  .REG_CTRL (REG_CTRL),
1445  .SIM_CAL_OPTION (SIM_CAL_OPTION),
1446  .DRAM_TYPE (DRAM_TYPE),
1447  .NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL),
1448  .N_CTL_LANES (DQS_FOUND_N_CTL_LANES),
1449  .HIGHEST_LANE (HIGHEST_LANE),
1450  .HIGHEST_BANK (HIGHEST_BANK),
1451  .BYTE_LANES_B0 (BYTE_LANES_B0),
1452  .BYTE_LANES_B1 (BYTE_LANES_B1),
1453  .BYTE_LANES_B2 (BYTE_LANES_B2),
1454  .BYTE_LANES_B3 (BYTE_LANES_B3),
1455  .BYTE_LANES_B4 (BYTE_LANES_B4),
1456  .DATA_CTL_B0 (DATA_CTL_B0),
1457  .DATA_CTL_B1 (DATA_CTL_B1),
1458  .DATA_CTL_B2 (DATA_CTL_B2),
1459  .DATA_CTL_B3 (DATA_CTL_B3),
1460  .DATA_CTL_B4 (DATA_CTL_B4)
1461  )
1462  u_ddr_phy_dqs_found_cal
1463  (
1464  .clk (clk),
1465  .rst (rst),
1466  .pi_dqs_found_start (pi_dqs_found_start),
1467  .dqsfound_retry (dqsfound_retry),
1468  .detect_pi_found_dqs (detect_pi_found_dqs),
1469  .prech_done (prech_done),
1470  .pi_dqs_found_lanes (pi_dqs_found_lanes),
1471  .pi_rst_stg1_cal (pi_rst_stg1_cal),
1472  .rd_data_offset_0 (rd_data_offset_0),
1473  .rd_data_offset_1 (rd_data_offset_1),
1474  .rd_data_offset_2 (rd_data_offset_2),
1475  .pi_dqs_found_rank_done (pi_dqs_found_rank_done),
1476  .pi_dqs_found_done (pi_dqs_found_done),
1477  .dqsfound_retry_done (dqsfound_retry_done),
1478  .dqs_found_prech_req (dqs_found_prech_req),
1479  .pi_dqs_found_err (pi_dqs_found_err),
1480  .rd_data_offset_ranks_0 (rd_data_offset_ranks_0),
1481  .rd_data_offset_ranks_1 (rd_data_offset_ranks_1),
1482  .rd_data_offset_ranks_2 (rd_data_offset_ranks_2),
1483  .rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0),
1484  .rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1),
1485  .rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2),
1486  .po_counter_read_val (po_counter_read_val),
1487  .rd_data_offset_cal_done (rd_data_offset_cal_done),
1488  .fine_adjust_done (fine_adjust_done),
1489  .fine_adjust_lane_cnt (fine_adjust_lane_cnt),
1490  .ck_po_stg2_f_indec (ck_po_stg2_f_indec),
1491  .ck_po_stg2_f_en (ck_po_stg2_f_en),
1492  .dbg_dqs_found_cal (dbg_dqs_found_cal)
1493  );
1494  end else begin: dqsfind_calib_left
1495  mig_7series_v1_9_ddr_phy_dqs_found_cal_hr #
1496  (
1497  .TCQ (TCQ),
1498  .nCK_PER_CLK (nCK_PER_CLK),
1499  .nCL (nCL),
1500  .AL (AL),
1501  .nCWL (nCWL),
1502  //.RANKS (RANKS),
1503  .RANKS (1),
1504  .DQS_CNT_WIDTH (DQS_CNT_WIDTH),
1505  .DQS_WIDTH (DQS_WIDTH),
1506  .DRAM_WIDTH (DRAM_WIDTH),
1507  .REG_CTRL (REG_CTRL),
1508  .SIM_CAL_OPTION (SIM_CAL_OPTION),
1509  .DRAM_TYPE (DRAM_TYPE),
1510  .NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL),
1511  .N_CTL_LANES (DQS_FOUND_N_CTL_LANES),
1512  .HIGHEST_LANE (HIGHEST_LANE),
1513  .HIGHEST_BANK (HIGHEST_BANK),
1514  .BYTE_LANES_B0 (BYTE_LANES_B0),
1515  .BYTE_LANES_B1 (BYTE_LANES_B1),
1516  .BYTE_LANES_B2 (BYTE_LANES_B2),
1517  .BYTE_LANES_B3 (BYTE_LANES_B3),
1518  .BYTE_LANES_B4 (BYTE_LANES_B4),
1519  .DATA_CTL_B0 (DATA_CTL_B0),
1520  .DATA_CTL_B1 (DATA_CTL_B1),
1521  .DATA_CTL_B2 (DATA_CTL_B2),
1522  .DATA_CTL_B3 (DATA_CTL_B3),
1523  .DATA_CTL_B4 (DATA_CTL_B4)
1524  )
1525  u_ddr_phy_dqs_found_cal_hr
1526  (
1527  .clk (clk),
1528  .rst (rst),
1529  .pi_dqs_found_start (pi_dqs_found_start),
1530  .dqsfound_retry (dqsfound_retry),
1531  .detect_pi_found_dqs (detect_pi_found_dqs),
1532  .prech_done (prech_done),
1533  .pi_dqs_found_lanes (pi_dqs_found_lanes),
1534  .pi_rst_stg1_cal (pi_rst_stg1_cal),
1535  .rd_data_offset_0 (rd_data_offset_0),
1536  .rd_data_offset_1 (rd_data_offset_1),
1537  .rd_data_offset_2 (rd_data_offset_2),
1538  .pi_dqs_found_rank_done (pi_dqs_found_rank_done),
1539  .pi_dqs_found_done (pi_dqs_found_done),
1540  .dqsfound_retry_done (dqsfound_retry_done),
1541  .dqs_found_prech_req (dqs_found_prech_req),
1542  .pi_dqs_found_err (pi_dqs_found_err),
1543  .rd_data_offset_ranks_0 (rd_data_offset_ranks_0),
1544  .rd_data_offset_ranks_1 (rd_data_offset_ranks_1),
1545  .rd_data_offset_ranks_2 (rd_data_offset_ranks_2),
1546  .rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0),
1547  .rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1),
1548  .rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2),
1549  .po_counter_read_val (po_counter_read_val),
1550  .rd_data_offset_cal_done (rd_data_offset_cal_done),
1551  .fine_adjust_done (fine_adjust_done),
1552  .fine_adjust_lane_cnt (fine_adjust_lane_cnt),
1553  .ck_po_stg2_f_indec (ck_po_stg2_f_indec),
1554  .ck_po_stg2_f_en (ck_po_stg2_f_en),
1555  .dbg_dqs_found_cal (dbg_dqs_found_cal)
1556  );
1557  end
1558  endgenerate
1559 
1560  //***************************************************************************
1561  // Read-leveling calibration logic
1562  //***************************************************************************
1563 
1564  mig_7series_v1_9_ddr_phy_rdlvl #
1565  (
1566  .TCQ (TCQ),
1567  .nCK_PER_CLK (nCK_PER_CLK),
1568  .CLK_PERIOD (CLK_PERIOD),
1569  .DQ_WIDTH (DQ_WIDTH),
1570  .DQS_CNT_WIDTH (DQS_CNT_WIDTH),
1571  .DQS_WIDTH (DQS_WIDTH),
1572  .DRAM_WIDTH (DRAM_WIDTH),
1573  .RANKS (1),
1574  .PER_BIT_DESKEW (PER_BIT_DESKEW),
1575  .SIM_CAL_OPTION (SIM_CAL_OPTION),
1576  .DEBUG_PORT (DEBUG_PORT),
1577  .DRAM_TYPE (DRAM_TYPE),
1578  .OCAL_EN (OCAL_EN)
1579  )
1580  u_ddr_phy_rdlvl
1581  (
1582  .clk (clk),
1583  .rst (rst),
1584  .mpr_rdlvl_done (mpr_rdlvl_done),
1585  .mpr_rdlvl_start (mpr_rdlvl_start),
1586  .mpr_last_byte_done (mpr_last_byte_done),
1587  .mpr_rnk_done (mpr_rnk_done),
1588  .rdlvl_stg1_start (rdlvl_stg1_start),
1589  .rdlvl_stg1_done (rdlvl_stg1_done),
1590  .rdlvl_stg1_rnk_done (rdlvl_stg1_rank_done),
1591  .rdlvl_stg1_err (rdlvl_stg1_err),
1592  .mpr_rdlvl_err (mpr_rdlvl_err),
1593  .rdlvl_err (rdlvl_err),
1594  .rdlvl_prech_req (rdlvl_prech_req),
1595  .rdlvl_last_byte_done (rdlvl_last_byte_done),
1596  .rdlvl_assrt_common (rdlvl_assrt_common),
1597  .prech_done (prech_done),
1598  .phy_if_empty (phy_if_empty),
1599  .idelaye2_init_val (idelaye2_init_val),
1600  .rd_data (phy_rddata),
1601  .pi_en_stg2_f (rdlvl_pi_stg2_f_en),
1602  .pi_stg2_f_incdec (rdlvl_pi_stg2_f_incdec),
1603  .pi_stg2_load (pi_stg2_load),
1604  .pi_stg2_reg_l (pi_stg2_reg_l),
1605  .dqs_po_dec_done (dqs_po_dec_done),
1606  .pi_counter_read_val (pi_counter_read_val),
1607  .pi_fine_dly_dec_done (pi_fine_dly_dec_done),
1608  .idelay_ce (idelay_ce_int),
1609  .idelay_inc (idelay_inc_int),
1610  .idelay_ld (idelay_ld),
1611  .wrcal_cnt (po_stg2_wrcal_cnt),
1612  .pi_stg2_rdlvl_cnt (pi_stg2_rdlvl_cnt),
1613  .dlyval_dq (dlyval_dq),
1614  .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
1615  .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
1616  .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
1617  .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
1618  .dbg_idel_up_all (dbg_idel_up_all),
1619  .dbg_idel_down_all (dbg_idel_down_all),
1620  .dbg_idel_up_cpt (dbg_idel_up_cpt),
1621  .dbg_idel_down_cpt (dbg_idel_down_cpt),
1622  .dbg_sel_idel_cpt (dbg_sel_idel_cpt),
1623  .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
1624  .dbg_phy_rdlvl (dbg_phy_rdlvl)
1625  );
1626 
1627 
1628 generate
1629 if(DRAM_TYPE == "DDR3") begin:ddr_phy_prbs_rdlvl_gen
1630  mig_7series_v1_9_ddr_phy_prbs_rdlvl #
1631  (
1632  .TCQ (TCQ),
1633  .nCK_PER_CLK (nCK_PER_CLK),
1634  .DQ_WIDTH (DQ_WIDTH),
1635  .DQS_CNT_WIDTH (DQS_CNT_WIDTH),
1636  .DQS_WIDTH (DQS_WIDTH),
1637  .DRAM_WIDTH (DRAM_WIDTH),
1638  .RANKS (1),
1639  .SIM_CAL_OPTION (SIM_CAL_OPTION),
1640  .PRBS_WIDTH (PRBS_WIDTH)
1641  )
1642  u_ddr_phy_prbs_rdlvl
1643  (
1644  .clk (clk),
1645  .rst (rst),
1646  .prbs_rdlvl_start (prbs_rdlvl_start),
1647  .prbs_rdlvl_done (prbs_rdlvl_done),
1648  .prbs_last_byte_done (prbs_last_byte_done),
1649  .prbs_rdlvl_prech_req (prbs_rdlvl_prech_req),
1650  .prech_done (prech_done),
1651  .phy_if_empty (phy_if_empty),
1652  .rd_data (phy_rddata),
1653  .compare_data (prbs_o),
1654  .pi_counter_read_val (pi_counter_read_val),
1655  .pi_en_stg2_f (prbs_pi_stg2_f_en),
1656  .pi_stg2_f_incdec (prbs_pi_stg2_f_incdec),
1657  .dbg_prbs_rdlvl (dbg_prbs_rdlvl),
1658  .pi_stg2_prbs_rdlvl_cnt (pi_stg2_prbs_rdlvl_cnt)
1659  );
1660 end else begin:ddr_phy_prbs_rdlvl_off
1661 
1662  assign prbs_rdlvl_done = rdlvl_stg1_done ;
1663  assign prbs_last_byte_done = rdlvl_stg1_rank_done ;
1664  assign prbs_rdlvl_prech_req = 1'b0 ;
1665  assign prbs_pi_stg2_f_en = 1'b0 ;
1666  assign prbs_pi_stg2_f_incdec = 1'b0 ;
1667  assign pi_stg2_prbs_rdlvl_cnt = 'b0 ;
1668 
1669 end
1670 endgenerate
1671 
1672  //***************************************************************************
1673  // Temperature induced PI tap adjustment logic
1674  //***************************************************************************
1675 
1676  mig_7series_v1_9_ddr_phy_tempmon #
1677  (
1678  .TCQ (TCQ)
1679  )
1680  ddr_phy_tempmon_0
1681  (
1682  .rst (rst),
1683  .clk (clk),
1684  .calib_complete (calib_complete),
1685  .tempmon_pi_f_inc (tempmon_pi_f_inc),
1686  .tempmon_pi_f_dec (tempmon_pi_f_dec),
1687  .tempmon_sel_pi_incdec (tempmon_sel_pi_incdec),
1688  .device_temp (device_temp),
1689  .tempmon_sample_en (tempmon_sample_en)
1690  );
1691 
1692 endmodule
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