AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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mig_7series_v1_9_ddr_byte_lane.v
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47 
48 //
49 //
50 // Owner: Gary Martin
51 // Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_lane.v#4 $
52 // $Author: gary $
53 // $DateTime: 2010/05/11 18:05:17 $
54 // $Change: 490882 $
55 // Description:
56 // This verilog file is a parameterizable single 10 or 12 bit byte lane.
57 //
58 // History:
59 // Date Engineer Description
60 // 04/01/2010 G. Martin Initial Checkin.
61 //
62 ////////////////////////////////////////////////////////////
63 ************************************************************/
64 
65 
66 `timescale 1ps/1ps
67 
68 //`include "phy.vh"
69 
70 module mig_7series_v1_9_ddr_byte_lane #(
71 // these are used to scale the index into phaser,calib,scan,mc vectors
72 // to access fields used in this instance
73  parameter ABCD = "A", // A,B,C, or D
74  parameter PO_DATA_CTL = "FALSE",
75  parameter BITLANES = 12'b1111_1111_1111,
76  parameter BITLANES_OUTONLY = 12'b1111_1111_1111,
77  parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010,
78  parameter RCLK_SELECT_LANE = "B",
79  parameter PC_CLK_RATIO = 4,
80  parameter USE_PRE_POST_FIFO = "FALSE",
81 //OUT_FIFO
82  parameter OF_ALMOST_EMPTY_VALUE = 1,
83  parameter OF_ALMOST_FULL_VALUE = 1,
84  parameter OF_ARRAY_MODE = "UNDECLARED",
85  parameter OF_OUTPUT_DISABLE = "FALSE",
86  parameter OF_SYNCHRONOUS_MODE = "TRUE",
87 //IN_FIFO
88  parameter IF_ALMOST_EMPTY_VALUE = 1,
89  parameter IF_ALMOST_FULL_VALUE = 1,
90  parameter IF_ARRAY_MODE = "UNDECLARED",
91  parameter IF_SYNCHRONOUS_MODE = "TRUE",
92 //PHASER_IN
93  parameter PI_BURST_MODE = "TRUE",
94  parameter PI_CLKOUT_DIV = 2,
95  parameter PI_FREQ_REF_DIV = "NONE",
96  parameter PI_FINE_DELAY = 1,
97  parameter PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF",
98  parameter PI_SEL_CLK_OFFSET = 0,
99 
100  parameter PI_SYNC_IN_DIV_RST = "FALSE",
101 //PHASER_OUT
102  parameter PO_CLKOUT_DIV = (PO_DATA_CTL == "FALSE") ? 4 : 2,
103  parameter PO_FINE_DELAY = 0,
104  parameter PO_COARSE_BYPASS = "FALSE",
105  parameter PO_COARSE_DELAY = 0,
106  parameter PO_OCLK_DELAY = 0,
107  parameter PO_OCLKDELAY_INV = "TRUE",
108  parameter PO_OUTPUT_CLK_SRC = "DELAYED_REF",
109  parameter PO_SYNC_IN_DIV_RST = "FALSE",
110 // OSERDES
111  parameter OSERDES_DATA_RATE = "DDR",
112  parameter OSERDES_DATA_WIDTH = 4,
113 
114 //IDELAY
115  parameter IDELAYE2_IDELAY_TYPE = "VARIABLE",
116  parameter IDELAYE2_IDELAY_VALUE = 00,
117  parameter IODELAY_GRP = "IODELAY_MIG",
118  parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
119  parameter real TCK = 0.00,
120  parameter SYNTHESIS = "FALSE",
121 
122 // local constants, do not pass in from above
123  parameter BUS_WIDTH = 12,
124  parameter MSB_BURST_PEND_PO = 3,
125  parameter MSB_BURST_PEND_PI = 7,
126  parameter MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8,
127  parameter PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1
128  ,parameter CKE_ODT_AUX = "FALSE"
129  )(
130  input rst,
131  input phy_clk,
132  input freq_refclk,
133  input mem_refclk,
134  input idelayctrl_refclk,
135  input sync_pulse,
136  output [BUS_WIDTH-1:0] mem_dq_out,
137  output [BUS_WIDTH-1:0] mem_dq_ts,
138  input [9:0] mem_dq_in,
139  output mem_dqs_out,
140  output mem_dqs_ts,
141  input mem_dqs_in,
142  output [11:0] ddr_ck_out,
143  output rclk,
144  input if_empty_def,
145  output if_a_empty,
146  output if_empty,
147  output if_a_full,
148  output if_full,
149  output of_a_empty,
150  output of_empty,
151  output of_a_full,
152  output of_full,
153  output pre_fifo_a_full,
154  output [79:0] phy_din,
155  input [79:0] phy_dout,
156  input phy_cmd_wr_en,
157  input phy_data_wr_en,
158  input phy_rd_en,
159  input [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus,
160  input idelay_inc,
161  input idelay_ce,
162  input idelay_ld,
163  input if_rst,
164  input [2:0] byte_rd_en_oth_lanes,
165  input [1:0] byte_rd_en_oth_banks,
166  output byte_rd_en,
167 
168  output po_coarse_overflow,
169  output po_fine_overflow,
170  output [8:0] po_counter_read_val,
171  input po_fine_enable,
172  input po_coarse_enable,
173  input [1:0] po_en_calib,
174  input po_fine_inc,
175  input po_coarse_inc,
176  input po_counter_load_en,
177  input po_counter_read_en,
178  input po_sel_fine_oclk_delay,
179  input [8:0] po_counter_load_val,
180 
181  input [1:0] pi_en_calib,
182  input pi_rst_dqs_find,
183  input pi_fine_enable,
184  input pi_fine_inc,
185  input pi_counter_load_en,
186  input pi_counter_read_en,
187  input [5:0] pi_counter_load_val,
188 
189  output wire pi_iserdes_rst,
190  output pi_phase_locked,
191  output pi_fine_overflow,
192  output [5:0] pi_counter_read_val,
193  output wire pi_dqs_found,
194  output dqs_out_of_range
195 );
196 
197 localparam PHASER_INDEX =
198  (ABCD=="B" ? 1 : (ABCD == "C") ? 2 : (ABCD == "D" ? 3 : 0));
199 localparam L_OF_ARRAY_MODE =
200  (OF_ARRAY_MODE != "UNDECLARED") ? OF_ARRAY_MODE :
201  (PO_DATA_CTL == "FALSE" || PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_8_X_4";
202 localparam L_IF_ARRAY_MODE = (IF_ARRAY_MODE != "UNDECLARED") ? IF_ARRAY_MODE :
203  (PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_4_X_8";
204 
205 localparam L_OSERDES_DATA_RATE = (OSERDES_DATA_RATE != "UNDECLARED") ? OSERDES_DATA_RATE : ((PO_DATA_CTL == "FALSE" && PC_CLK_RATIO == 4) ? "SDR" : "DDR") ;
206 localparam L_OSERDES_DATA_WIDTH = (OSERDES_DATA_WIDTH != "UNDECLARED") ? OSERDES_DATA_WIDTH : 4;
207 localparam real L_FREQ_REF_PERIOD_NS = TCK > 2500.0 ? (TCK/(PI_FREQ_REF_DIV == "DIV2" ? 2 : 1)/1000.0) : TCK/1000.0;
208 localparam real L_MEM_REF_PERIOD_NS = TCK/1000.0;
209 localparam real L_PHASE_REF_PERIOD_NS = TCK/1000.0;
210 localparam ODDR_CLK_EDGE = "SAME_EDGE";
211 localparam PO_DCD_CORRECTION = "ON";
212 localparam [2:0] PO_DCD_SETTING = (PO_DCD_CORRECTION == "ON") ? 3'b111 : 3'b000;
213 
214 localparam DQS_AUTO_RECAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK > 2500)) ? 1 : 0;
215 localparam DQS_FIND_PATTERN = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK > 2500)) ? "001" : "000";
216 
217 wire [1:0] oserdes_dqs;
218 wire [1:0] oserdes_dqs_ts;
219 wire [1:0] oserdes_dq_ts;
220 
221 wire [3:0] of_q9;
222 wire [3:0] of_q8;
223 wire [3:0] of_q7;
224 wire [7:0] of_q6;
225 wire [7:0] of_q5;
226 wire [3:0] of_q4;
227 wire [3:0] of_q3;
228 wire [3:0] of_q2;
229 wire [3:0] of_q1;
230 wire [3:0] of_q0;
231 wire [7:0] of_d9;
232 wire [7:0] of_d8;
233 wire [7:0] of_d7;
234 wire [7:0] of_d6;
235 wire [7:0] of_d5;
236 wire [7:0] of_d4;
237 wire [7:0] of_d3;
238 wire [7:0] of_d2;
239 wire [7:0] of_d1;
240 wire [7:0] of_d0;
241 
242 wire [7:0] if_q9;
243 wire [7:0] if_q8;
244 wire [7:0] if_q7;
245 wire [7:0] if_q6;
246 wire [7:0] if_q5;
247 wire [7:0] if_q4;
248 wire [7:0] if_q3;
249 wire [7:0] if_q2;
250 wire [7:0] if_q1;
251 wire [7:0] if_q0;
252 wire [3:0] if_d9;
253 wire [3:0] if_d8;
254 wire [3:0] if_d7;
255 wire [3:0] if_d6;
256 wire [3:0] if_d5;
257 wire [3:0] if_d4;
258 wire [3:0] if_d3;
259 wire [3:0] if_d2;
260 wire [3:0] if_d1;
261 wire [3:0] if_d0;
262 
263 wire [3:0] dummy_i5;
264 wire [3:0] dummy_i6;
265 
266 wire [48-1:0] of_dqbus;
267 wire [10*4-1:0] iserdes_dout;
268 
269 wire iserdes_clk;
270 wire iserdes_clkdiv;
271 wire ififo_wr_enable;
272 wire phy_rd_en_;
273 
274 
275 wire dqs_to_phaser;
276 wire phy_wr_en = ( PO_DATA_CTL == "FALSE" ) ? phy_cmd_wr_en : phy_data_wr_en;
277 wire if_empty_;
278 wire if_a_empty_;
279 wire if_full_;
280 wire if_a_full_;
281 wire po_oserdes_rst;
282 wire empty_post_fifo;
283 (* keep = "true", max_fanout = 3 *) reg [3:0] if_empty_r /* synthesis syn_maxfan = 3 **/;
284 wire [79:0] rd_data;
285 reg [79:0] rd_data_r;
286 /////////////////////////////////////////////////////////////////////////
287 ///This is a temporary fix until we get a proper fix for CR#638064///////
288 /////////////////////////////////////////////////////////////////////////
289 reg ififo_rst = 1'b1;
290 reg ofifo_rst = 1'b1;
291 /////////////////////////////////////////////////////////////////////////
292 
293 wire of_wren_pre;
294 wire [79:0] pre_fifo_dout;
295 wire pre_fifo_full;
296 wire pre_fifo_rden;
297 wire [5:0] ddr_ck_out_q;
298 (* keep = "true", max_fanout = 10 *) wire ififo_rd_en_in /* synthesis syn_maxfan = 10 **/;
299 
300 always @(posedge phy_clk) begin
301  ififo_rst <= #1 pi_rst_dqs_find | if_rst ;
302 // reset only data o-fifos on reset of dqs_found
303  ofifo_rst <= #1 (pi_rst_dqs_find & PO_DATA_CTL == "TRUE") | rst;
304 end
305 
306 // IN_FIFO EMPTY->RDEN TIMING FIX:
307 // Always read from IN_FIFO - it doesn't hurt to read from an empty FIFO
308 // since the IN_FIFO read pointers are not incr'ed when the FIFO is empty
309 assign #(25) phy_rd_en_ = 1'b1;
310 //assign #(25) phy_rd_en_ = phy_rd_en;
311 
312 generate
313 if ( PO_DATA_CTL == "FALSE" ) begin : if_empty_null
314  assign if_empty = 0;
315  assign if_a_empty = 0;
316  assign if_full = 0;
317  assign if_a_full = 0;
318 end
319 else begin : if_empty_gen
320  assign if_empty = empty_post_fifo;
321  assign if_a_empty = if_a_empty_;
322  assign if_full = if_full_;
323  assign if_a_full = if_a_full_;
324 end
325 endgenerate
326 
327 generate
328 if ( PO_DATA_CTL == "FALSE" ) begin : dq_gen_48
329  assign of_dqbus[48-1:0] = {of_q6[7:4], of_q5[7:4], of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};
330  assign phy_din = 80'h0;
331  assign byte_rd_en = 1'b1;
332 end
333 else begin : dq_gen_40
334 
335  assign of_dqbus[40-1:0] = {of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};
336  assign ififo_rd_en_in = !if_empty_def ? ((&byte_rd_en_oth_banks) && (&byte_rd_en_oth_lanes) && byte_rd_en) :
337  ((|byte_rd_en_oth_banks) || (|byte_rd_en_oth_lanes) || byte_rd_en);
338 
339  if (USE_PRE_POST_FIFO == "TRUE") begin : if_post_fifo_gen
340 
341  // IN_FIFO EMPTY->RDEN TIMING FIX:
342  assign rd_data = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0};
343 
344  always @(posedge phy_clk) begin
345  rd_data_r <= #(025) rd_data;
346  if_empty_r[0] <= #(025) if_empty_;
347  if_empty_r[1] <= #(025) if_empty_;
348  if_empty_r[2] <= #(025) if_empty_;
349  if_empty_r[3] <= #(025) if_empty_;
350  end
351 
352 
353  mig_7series_v1_9_ddr_if_post_fifo #
354  (
355  .TCQ (25), // simulation CK->Q delay
356  .DEPTH (4), //2 // depth - account for up to 2 cycles of skew
357  .WIDTH (80) // width
358  )
359  u_ddr_if_post_fifo
360  (
361  .clk (phy_clk),
362  .rst (ififo_rst),
363  .empty_in (if_empty_r),
364  .rd_en_in (ififo_rd_en_in),
365  .d_in (rd_data_r),
366  .empty_out (empty_post_fifo),
367  .byte_rd_en (byte_rd_en),
368  .d_out (phy_din)
369  );
370 
371  end
372  else begin : phy_din_gen
373  assign phy_din = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0};
374  assign empty_post_fifo = if_empty_;
375  end
376 
377 end
378 endgenerate
379 
380 
381 assign { if_d9, if_d8, if_d7, if_d6, if_d5, if_d4, if_d3, if_d2, if_d1, if_d0} = iserdes_dout;
382 
383 
384 wire [1:0] rank_sel_i = ((phaser_ctl_bus[MSB_RANK_SEL_I :MSB_RANK_SEL_I -7] >> (PHASER_INDEX << 1)) & 2'b11);
385 
386 
387 
388 
389 generate
390 
391 if ( USE_PRE_POST_FIFO == "TRUE" ) begin : of_pre_fifo_gen
392  assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = pre_fifo_dout;
393  mig_7series_v1_9_ddr_of_pre_fifo #
394  (
395  .TCQ (25), // simulation CK->Q delay
396  .DEPTH (9), // depth - set to 9 to accommodate flow control
397  .WIDTH (80) // width
398  )
399  u_ddr_of_pre_fifo
400  (
401  .clk (phy_clk),
402 /////////////////////////////////////////////////////////////////////////
403 ///This is a temporary fix until we get a proper fix for CR#638064///////
404 /////////////////////////////////////////////////////////////////////////
405  .rst (ofifo_rst),
406 /////////////////////////////////////////////////////////////////////////
407  .full_in (of_full),
408  .wr_en_in (phy_wr_en),
409  .d_in (phy_dout),
410  .wr_en_out (of_wren_pre),
411  .d_out (pre_fifo_dout),
412  .afull (pre_fifo_a_full)
413  );
414 end
415 else begin
416 // wire direct to ofifo
417  assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = phy_dout;
418  assign of_wren_pre = phy_wr_en;
419 end
420 
421 
422 endgenerate
423 
424 
425 
426 
427 generate
428 
429 if ( PO_DATA_CTL == "TRUE" || ((RCLK_SELECT_LANE==ABCD) && (CKE_ODT_AUX =="TRUE"))) begin : phaser_in_gen
430 
431 PHASER_IN_PHY #(
432  .BURST_MODE ( PI_BURST_MODE),
433  .CLKOUT_DIV ( PI_CLKOUT_DIV),
434  .DQS_AUTO_RECAL ( DQS_AUTO_RECAL),
435  .DQS_FIND_PATTERN ( DQS_FIND_PATTERN),
436  .SEL_CLK_OFFSET ( PI_SEL_CLK_OFFSET),
437  .FINE_DELAY ( PI_FINE_DELAY),
438  .FREQ_REF_DIV ( PI_FREQ_REF_DIV),
439  .OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC),
440  .SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST),
441  .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
442  .MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS),
443  .PHASEREFCLK_PERIOD ( L_PHASE_REF_PERIOD_NS)
444 ) phaser_in (
445  .DQSFOUND (pi_dqs_found),
446  .DQSOUTOFRANGE (dqs_out_of_range),
447  .FINEOVERFLOW (pi_fine_overflow),
448  .PHASELOCKED (pi_phase_locked),
449  .ISERDESRST (pi_iserdes_rst),
450  .ICLKDIV (iserdes_clkdiv),
451  .ICLK (iserdes_clk),
452  .COUNTERREADVAL (pi_counter_read_val),
453  .RCLK (rclk),
454  .WRENABLE (ififo_wr_enable),
455  .BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]),
456  .ENCALIBPHY (pi_en_calib),
457  .FINEENABLE (pi_fine_enable),
458  .FREQREFCLK (freq_refclk),
459  .MEMREFCLK (mem_refclk),
460  .RANKSELPHY (rank_sel_i),
461  .PHASEREFCLK (dqs_to_phaser),
462  .RSTDQSFIND (pi_rst_dqs_find),
463  .RST (rst),
464  .FINEINC (pi_fine_inc),
465  .COUNTERLOADEN (pi_counter_load_en),
466  .COUNTERREADEN (pi_counter_read_en),
467  .COUNTERLOADVAL (pi_counter_load_val),
468  .SYNCIN (sync_pulse),
469  .SYSCLK (phy_clk)
470 );
471 end
472 
473 else begin
474  assign pi_dqs_found = 1'b1;
475  assign pi_dqs_out_of_range = 1'b0;
476  assign pi_phase_locked = 1'b1;
477 end
478 
479 endgenerate
480 
481 wire #0 phase_ref = freq_refclk;
482 
483 wire oserdes_clk;
484 
485 
486 PHASER_OUT_PHY #(
487  .CLKOUT_DIV ( PO_CLKOUT_DIV),
488  .DATA_CTL_N ( PO_DATA_CTL ),
489  .FINE_DELAY ( PO_FINE_DELAY),
490  .COARSE_BYPASS ( PO_COARSE_BYPASS ),
491  .COARSE_DELAY ( PO_COARSE_DELAY),
492  .OCLK_DELAY ( PO_OCLK_DELAY),
493  .OCLKDELAY_INV ( PO_OCLKDELAY_INV),
494  .OUTPUT_CLK_SRC ( PO_OUTPUT_CLK_SRC),
495  .SYNC_IN_DIV_RST ( PO_SYNC_IN_DIV_RST),
496  .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
497  .PHASEREFCLK_PERIOD ( 1), // dummy, not used
498  .PO ( PO_DCD_SETTING ),
499  .MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS)
500 ) phaser_out (
501  .COARSEOVERFLOW (po_coarse_overflow),
502  .CTSBUS (oserdes_dqs_ts),
503  .DQSBUS (oserdes_dqs),
504  .DTSBUS (oserdes_dq_ts),
505  .FINEOVERFLOW (po_fine_overflow),
506  .OCLKDIV (oserdes_clkdiv),
507  .OCLK (oserdes_clk),
508  .OCLKDELAYED (oserdes_clk_delayed),
509  .COUNTERREADVAL (po_counter_read_val),
510  .BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PO -3 + PHASER_INDEX]),
511  .ENCALIBPHY (po_en_calib),
512  .RDENABLE (po_rd_enable),
513  .FREQREFCLK (freq_refclk),
514  .MEMREFCLK (mem_refclk),
515  .PHASEREFCLK (/*phase_ref**/),
516  .RST (rst),
517  .OSERDESRST (po_oserdes_rst),
518  .COARSEENABLE (po_coarse_enable),
519  .FINEENABLE (po_fine_enable),
520  .COARSEINC (po_coarse_inc),
521  .FINEINC (po_fine_inc),
522  .SELFINEOCLKDELAY (po_sel_fine_oclk_delay),
523  .COUNTERLOADEN (po_counter_load_en),
524  .COUNTERREADEN (po_counter_read_en),
525  .COUNTERLOADVAL (po_counter_load_val),
526  .SYNCIN (sync_pulse),
527  .SYSCLK (phy_clk)
528 );
529 
530 
531 generate
532 
533 if (PO_DATA_CTL == "TRUE") begin : in_fifo_gen
534 
535 IN_FIFO #(
536  .ALMOST_EMPTY_VALUE ( IF_ALMOST_EMPTY_VALUE ),
537  .ALMOST_FULL_VALUE ( IF_ALMOST_FULL_VALUE ),
538  .ARRAY_MODE ( L_IF_ARRAY_MODE),
539  .SYNCHRONOUS_MODE ( IF_SYNCHRONOUS_MODE)
540 ) in_fifo (
541  .ALMOSTEMPTY (if_a_empty_),
542  .ALMOSTFULL (if_a_full_),
543  .EMPTY (if_empty_),
544  .FULL (if_full_),
545  .Q0 (if_q0),
546  .Q1 (if_q1),
547  .Q2 (if_q2),
548  .Q3 (if_q3),
549  .Q4 (if_q4),
550  .Q5 (if_q5),
551  .Q6 (if_q6),
552  .Q7 (if_q7),
553  .Q8 (if_q8),
554  .Q9 (if_q9),
555 //===
556  .D0 (if_d0),
557  .D1 (if_d1),
558  .D2 (if_d2),
559  .D3 (if_d3),
560  .D4 (if_d4),
561  .D5 ({dummy_i5,if_d5}),
562  .D6 ({dummy_i6,if_d6}),
563  .D7 (if_d7),
564  .D8 (if_d8),
565  .D9 (if_d9),
566  .RDCLK (phy_clk),
567  .RDEN (phy_rd_en_),
568  .RESET (ififo_rst),
569  .WRCLK (iserdes_clkdiv),
570  .WREN (ififo_wr_enable)
571 );
572 end
573 
574 endgenerate
575 
576 
577 
578 OUT_FIFO #(
579  .ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
580  .ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
581  .ARRAY_MODE (L_OF_ARRAY_MODE),
582  .OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
583  .SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE)
584 ) out_fifo (
585  .ALMOSTEMPTY (of_a_empty),
586  .ALMOSTFULL (of_a_full),
587  .EMPTY (of_empty),
588  .FULL (of_full),
589  .Q0 (of_q0),
590  .Q1 (of_q1),
591  .Q2 (of_q2),
592  .Q3 (of_q3),
593  .Q4 (of_q4),
594  .Q5 (of_q5),
595  .Q6 (of_q6),
596  .Q7 (of_q7),
597  .Q8 (of_q8),
598  .Q9 (of_q9),
599  .D0 (of_d0),
600  .D1 (of_d1),
601  .D2 (of_d2),
602  .D3 (of_d3),
603  .D4 (of_d4),
604  .D5 (of_d5),
605  .D6 (of_d6),
606  .D7 (of_d7),
607  .D8 (of_d8),
608  .D9 (of_d9),
609  .RDCLK (oserdes_clkdiv),
610  .RDEN (po_rd_enable),
611  .RESET (ofifo_rst),
612  .WRCLK (phy_clk),
613  .WREN (of_wren_pre)
614 );
615 
616 
617 mig_7series_v1_9_ddr_byte_group_io #
618  (
619  .PO_DATA_CTL (PO_DATA_CTL),
620  .BITLANES (BITLANES),
621  .BITLANES_OUTONLY (BITLANES_OUTONLY),
622  .OSERDES_DATA_RATE (L_OSERDES_DATA_RATE),
623  .OSERDES_DATA_WIDTH (L_OSERDES_DATA_WIDTH),
624  .IODELAY_GRP (IODELAY_GRP),
625  .IDELAYE2_IDELAY_TYPE (IDELAYE2_IDELAY_TYPE),
626  .IDELAYE2_IDELAY_VALUE (IDELAYE2_IDELAY_VALUE),
627  .SYNTHESIS (SYNTHESIS)
628  )
629  ddr_byte_group_io
630  (
631  .mem_dq_out (mem_dq_out),
632  .mem_dq_ts (mem_dq_ts),
633  .mem_dq_in (mem_dq_in),
634  .mem_dqs_in (mem_dqs_in),
635  .mem_dqs_out (mem_dqs_out),
636  .mem_dqs_ts (mem_dqs_ts),
637  .rst (rst),
638  .oserdes_rst (po_oserdes_rst),
639  .iserdes_rst (pi_iserdes_rst ),
640  .iserdes_dout (iserdes_dout),
641  .dqs_to_phaser (dqs_to_phaser),
642  .phy_clk (phy_clk),
643  .iserdes_clk (iserdes_clk),
644  .iserdes_clkb (!iserdes_clk),
645  .iserdes_clkdiv (iserdes_clkdiv),
646  .idelay_inc (idelay_inc),
647  .idelay_ce (idelay_ce),
648  .idelay_ld (idelay_ld),
649  .idelayctrl_refclk (idelayctrl_refclk),
650  .oserdes_clk (oserdes_clk),
651  .oserdes_clk_delayed (oserdes_clk_delayed),
652  .oserdes_clkdiv (oserdes_clkdiv),
653  .oserdes_dqs ({oserdes_dqs[1], oserdes_dqs[0]}),
654  .oserdes_dqsts ({oserdes_dqs_ts[1], oserdes_dqs_ts[0]}),
655  .oserdes_dq (of_dqbus),
656  .oserdes_dqts ({oserdes_dq_ts[1], oserdes_dq_ts[0]})
657  );
658 
659 genvar i;
660 generate
661  for (i = 0; i <= 5; i = i+1) begin : ddr_ck_gen_loop
662  if (PO_DATA_CTL== "FALSE" && (BYTELANES_DDR_CK[i*4+PHASER_INDEX])) begin : ddr_ck_gen
663  ODDR #(.DDR_CLK_EDGE (ODDR_CLK_EDGE))
664  ddr_ck (
665  .C (oserdes_clk),
666  .R (1'b0),
667  .S (),
668  .D1 (1'b0),
669  .D2 (1'b1),
670  .CE (1'b1),
671  .Q (ddr_ck_out_q[i])
672  );
673  OBUFDS ddr_ck_obuf (.I(ddr_ck_out_q[i]), .O(ddr_ck_out[i*2]), .OB(ddr_ck_out[i*2+1]));
674  end // ddr_ck_gen
675  else begin : ddr_ck_null
676  assign ddr_ck_out[i*2+1:i*2] = 2'b0;
677  end
678  end // ddr_ck_gen_loop
679 endgenerate
680 
681 endmodule // byte_lane
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