AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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TTS_if.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 09:49:10 06/14/2012
6 -- Design Name:
7 -- Module Name: TTS_if - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 -- TTC Hamming encoding
20 -- hmg[0] = d[0]^d[1]^d[2]^d[3];
21 -- hmg[1] = d[0]^d[4]^d[5]^d[6];
22 -- hmg[2] = d[1]^d[2]^d[4]^d[5]^d[7];
23 -- hmg[3] = d[1]^d[3]^d[4]^d[6]^d[7];
24 -- hmg[4] = d[0]^d[2]^d[3]^d[5]^d[6]^d[7];
25 --
26 -- L1A trigger from CTR module takes the position of L1A in TTC
27 -- message format takes that of TTC broadcast message.(FMT = 0)
28 -- BcntRes uses brcst_data(0), TTS signals uses brcst_data(7 downto 4), brcst_data(3 downto 1) are reserved and are always 0
29 ----------------------------------------------------------------------------------
30 library IEEE;
31 use IEEE.STD_LOGIC_1164.ALL;
32 use IEEE.STD_LOGIC_ARITH.ALL;
33 use IEEE.STD_LOGIC_UNSIGNED.ALL;
34 use IEEE.std_logic_misc.all;
35 library UNISIM;
36 use UNISIM.VComponents.all;
37 Library UNIMACRO;
38 use UNIMACRO.vcomponents.all;
39 
40 
42 
55 
56 entity TTS_if is
57  Port ( sysclk : in STD_LOGIC;
58  TTS_clk : in STD_LOGIC;
59  reset : in STD_LOGIC;
60  local_TTC : in STD_LOGIC; --! Controls TCDS DDR or TTC clock output
61  TTS : in STD_LOGIC_VECTOR (3 downto 0);
62  TTS_out_p : out STD_LOGIC;
63  TTS_out_n : out STD_LOGIC);
64 end TTS_if;
65 
66 architecture Behavioral of TTS_if is
67  COMPONENT RAM32x6D
68  PORT(
69  wclk : IN std_logic;
70  rclk : IN std_logic;
71  di : IN std_logic_vector(5 downto 0);
72  we : IN std_logic;
73  wa : IN std_logic_vector(4 downto 0);
74  ra : IN std_logic_vector(4 downto 0);
75  ceReg : IN std_logic;
76  do : OUT std_logic_vector(5 downto 0)
77  );
78  END COMPONENT;
79  COMPONENT Gray5
80  PORT(
81  d_current : IN std_logic_vector(4 downto 0);
82  d_next : OUT std_logic_vector(4 downto 0)
83  );
84  END COMPONENT;
85 --COMPONENT enc_8b10b_wrapper
86 -- port
87 -- (
88 -- reset_i : in std_logic ; -- Global asynchronous reset (active high)
89 -- clk_i : in std_logic ; -- Master synchronous send byte clock
90 -- strobe_i : in std_logic ; -- Master synchronous send byte clock
91 -- k_i : in std_logic ; -- Control (K) input(active high)
92 -- data_i : in std_logic_vector(7 downto 0); -- Unencoded input data
93 -- data_o : out std_logic_vector(9 downto 0) -- Encoded out
94 -- );
95 --end COMPONENT;
96  signal TTS_out : std_logic := '0';
97  signal TTS_fifo_empty : std_logic := '1';
98  signal TTS_q : std_logic_vector(3 downto 0) := (others =>'0');
99  signal TTS_fifo_wa : std_logic_vector(4 downto 0) := (others =>'0');
100  signal TTS_fifo_ra : std_logic_vector(4 downto 0) := (others =>'0');
101  signal next_TTS_fifo_wa : std_logic_vector(4 downto 0) := (others =>'0');
102  signal next_TTS_fifo_ra : std_logic_vector(4 downto 0) := (others =>'0');
103  signal TTS_fifo_waSync : std_logic_vector(4 downto 0) := (others =>'0');
104  signal TTS_fifo_di : std_logic_vector(5 downto 0) := (others =>'0');
105  signal TTS_fifo_do : std_logic_vector(5 downto 0) := (others =>'0');
106  signal sr : std_logic_vector(9 downto 0) := (others =>'0');
107  signal TTS_fifo_we : std_logic := '0';
108  signal TTS_fifo_re : std_logic := '0';
109  signal NewTTS : std_logic := '0';
110  signal TTS_clk_div : std_logic_vector(2 downto 0) := (others =>'0');
111  signal SameTTS_cnt : std_logic_vector(1 downto 0) := (others =>'0');
112  signal IS_K : std_logic := '0';
113  signal enc_di : std_logic_vector(7 downto 0) := (others =>'0');
114  signal enc_do : std_logic_vector(9 downto 0) := (others =>'0');
115 begin
116  process(sysclk)
117  begin
118  if(sysclk'event and sysclk = '1')then
119  if(TTS_q = TTS)then
120  TTS_FIFO_we <= '0';
121  else
122  TTS_FIFO_we <= '1';
123  end if;
124  end if;
125  end process;
126  process(sysclk,reset)
127  begin
128  if(reset = '1')then
129  TTS_q <= (others =>'0');
130  TTS_fifo_wa <= (others =>'0');
131  elsif(sysclk'event and sysclk = '1')then
132  TTS_q <= TTS;
133  if(TTS_FIFO_we = '1')then
134  TTS_fifo_wa <= next_TTS_fifo_wa;
135  end if;
136  end if;
137  end process;
138  i_next_TTS_fifo_wa : Gray5 PORT MAP(
139  d_current => TTS_fifo_wa ,
140  d_next => next_TTS_fifo_wa
141  );
142  i_TTS_FIFO : RAM32X6D
143  port map (
144  wclk => sysclk,
145  rclk => TTS_clk,
146  di => TTS_FIFO_di,
147  we => TTS_FIFO_we,
148  wa => TTS_FIFO_wa,
149  ra => TTS_FIFO_ra,
150  ceReg => '1',
151  do => TTS_FIFO_do
152  );
153  TTS_FIFO_di(3 downto 0) <= TTS_q;
154  i_next_TTS_fifo_ra : Gray5 PORT MAP(
155  d_current => TTS_fifo_ra ,
156  d_next => next_TTS_fifo_ra
157  );
158  process(TTS_clk,reset)
159  begin
160  if(reset = '1')then
161  TTS_fifo_waSync <= (others =>'0');
162  TTS_FIFO_re <= '0';
163  NewTTS <= '1';
164  IS_K <= '1';
165  enc_di <= x"bc";
166  TTS_fifo_ra <= (others =>'0');
167  SameTTS_cnt <= "00";
168  elsif(TTS_clk'event and TTS_clk = '1')then
169  if(TTS_clk_div(2) = '1')then
170  TTS_fifo_waSync <= TTS_fifo_wa;
171  if(NewTTS = '1')then
172  SameTTS_cnt <= "00";
173  else
174  SameTTS_cnt <= SameTTS_cnt + 1;
175  end if;
176  if(NewTTS = '1' or SameTTS_cnt = "11")then
177  enc_di <= x"0" & TTS_FIFO_do(3 downto 0);
178  IS_K <= '0';
179  else
180  enc_di <= x"bc"; -- K28.5
181  IS_K <= '1';
182  end if;
183  end if;
184  if(TTS_fifo_waSync /= TTS_fifo_ra and TTS_clk_div(1 downto 0) = "01")then
185  TTS_FIFO_re <= '1';
186  else
187  TTS_FIFO_re <= '0';
188  end if;
189  if(TTS_FIFO_re = '1')then
190  TTS_fifo_ra <= next_TTS_fifo_ra;
191  end if;
192  if(TTS_FIFO_re = '1')then
193  NewTTS <= '1';
194  elsif(TTS_clk_div(2) = '1')then
195  NewTTS <= '0';
196  end if;
197  end if;
198  end process;
199 --i_8b10b_enc: enc_8b10b_wrapper
200 -- port map
201 -- (
202 -- reset_i => reset,
203 -- clk_i => TTS_clk,
204 -- strobe_i => TTS_clk_div(2),
205 -- k_i => IS_K,
206 -- data_i => enc_di,
207 -- data_o => enc_do
208 -- );
209  i_8b10b_enc : ENTITY work.encode_8b10b_lut_base
210  GENERIC MAP (
211  C_HAS_DISP_IN => 0,
212  C_HAS_FORCE_CODE => 0,
213  C_FORCE_CODE_VAL => "1010101010",
214  C_FORCE_CODE_DISP => 0,
215  C_HAS_ND => 0,
216  C_HAS_KERR => 1
217  )
218  PORT MAP (
219  DIN => enc_di,
220  KIN => IS_K,
221  FORCE_DISP => '0',
222  FORCE_CODE => '0',
223  DISP_IN => '0',
224  CE => TTS_clk_div(2),
225  CLK => TTS_clk,
226  DOUT => enc_do,
227  KERR => open,
228  DISP_OUT => open,
229  ND => open
230  );
231  process(TTS_clk)
232  begin
233  if(TTS_clk'event and TTS_clk = '1')then
234  -- 5 state counter for 10bit 8b10char in groups of two
235  if(TTS_clk_div(2) = '1')then
236  TTS_clk_div <= "000";
237  else
238  TTS_clk_div <= TTS_clk_div + 1;
239  end if;
240 
241  if(local_TTC = '1')then
242  sr(1) <= not sr(0);
243  sr(0) <= not sr(0);
244  elsif(TTS_clk_div(2) = '1')then
245  sr <= enc_do;
246  else
247  for i in 0 to 3 loop
248  sr(i*2+1 downto i*2) <= sr(i*2+3 downto i*2+2);
249  end loop;
250  end if;
251  end if;
252  end process;
253  i_TTS_out: OBUFDS generic map(IOSTANDARD => "LVDS_25") port map (O => TTS_out_p, OB => TTS_out_n , I => TTS_out);
254  ODDR_inst : ODDR
255  generic map(
256  DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
257  INIT => '0', -- Initial value for Q port ('1' or '0')
258  SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
259  port map (
260  Q => TTS_out, -- 1-bit DDR output
261  C => TTS_clk, -- 1-bit clock input
262  CE => '1', -- 1-bit clock enable input
263  D1 => sr(0), -- 1-bit data input (positive edge)
264  D2 => sr(1), -- 1-bit data input (negative edge)
265  R => '0', -- 1-bit reset input
266  S => '0' -- 1-bit set input
267  );
268 end Behavioral;
269 
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