AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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TTC_trigger.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 09:29:47 08/28/2015
6 -- Design Name:
7 -- Module Name: TTC_trigger - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 --use IEEE.NUMERIC_STD.ALL;
29 
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 library UNISIM;
33 use UNISIM.VComponents.all;
34 
35 entity TTC_trigger is
36  generic(simulation : boolean := false);
37  Port ( reset : in STD_LOGIC; -- async reset
38  UsrClk : in STD_LOGIC;
39  TTCclk : in STD_LOGIC;
40  HammingData_in : in STD_LOGIC_VECTOR (17 downto 0);
41  HammingDataValid : in STD_LOGIC;
42  BC0 : in STD_LOGIC;
43  BcntMm : out STD_LOGIC;
44  TTC_lock : out STD_LOGIC;
45  BC0_lock : out STD_LOGIC;
46  TrigData : out STD_LOGIC_VECTOR (7 downto 0));
47 end TTC_trigger;
48 
49 architecture Behavioral of TTC_trigger is
50 signal TTC_lock_i : std_logic := '0';
51 signal BC0_lock_i : std_logic := '0';
52 signal Toggle : std_logic := '0';
53 signal ToggleSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
54 signal TTC_edge : std_logic_vector(6 downto 0) := (others => '0');
55 signal HammingDataValid_dl3 : std_logic := '0';
56 signal chk_HammingData : std_logic := '0';
57 signal OutStrobe : std_logic := '0';
58 signal rd_enable : std_logic := '0';
59 signal rd_TTC_data : std_logic := '0';
60 signal BC0_l : std_logic := '0';
61 signal BcntMm_i : std_logic := '0';
62 signal BC0_matchCntr : std_logic_vector(8 downto 0) := (others => '0');
63 signal HammingData : std_logic_vector(17 downto 0) := (others => '0');
64 signal TTC_data_we : std_logic := '0';
65 signal TTC_data_in : std_logic_vector(8 downto 0) := (others => '0');
66 signal TTC_data : std_logic_vector(8 downto 0) := (others => '0');
67 signal TTC_data_a : std_logic_vector(2 downto 0) := (others => '1');
68 signal bcnt : std_logic_vector(11 downto 0) := (others => '0');
69 signal MmCntr : std_logic_vector(3 downto 0) := (others => '0');
70 signal GoodBcnt : std_logic_vector(3 downto 0) := (others => '0');
71 signal BC0_link : std_logic := '0';
72 signal BC0_offset : std_logic_vector(3 downto 0) := (others => '0');
73 signal ec_delta_BC0 : std_logic := '0';
74 signal delta_BC0 : std_logic_vector(3 downto 0) := (others => '0');
75 signal sel_TTC_edge : std_logic_vector(2 downto 0) := (others => '0');
76 type array6x9 is array(0 to 5) of std_logic_vector(8 downto 0);
77 signal MatchCntr : array6x9 := (others => (others => '0'));
78 begin
79 TTC_lock <= TTC_lock_i;
80 BC0_lock <= BC0_lock_i;
81 BcntMm <= BcntMm_i;
82 process(TTCclk)
83 begin
84  if(TTCclk'event and TTCclk = '1')then
85  Toggle <= not Toggle;
86  end if;
87 end process;
88 process(UsrClk,reset)
89 begin
90  if(reset = '1' or TTC_lock_i = '0')then
91  TTC_data_a <= (others => '1');
92  rd_enable <= '0';
93  rd_TTC_data <= '0';
94  elsif(UsrClk'event and UsrClk = '1')then
95  if(TTC_data_we = '1' and rd_TTC_data = '0')then
96  TTC_data_a <= TTC_data_a + 1;
97  elsif(TTC_data_we = '0' and rd_TTC_data = '1' and TTC_data_a /= "111")then
98  TTC_data_a <= TTC_data_a - 1;
99  end if;
100  if(TTC_data_a = "001")then
101  rd_enable <= '1';
102  end if;
103  if(TTC_edge(3) = '1' and rd_enable = '1')then
104  rd_TTC_data <= '1';
105  else
106  rd_TTC_data <= '0';
107  end if;
108  end if;
109 end process;
110 OutStrobe <= TTC_edge(4);
111 process(UsrClk)
112 variable reached256 : std_logic;
113 variable MatchCntr_MSB : std_logic_vector(5 downto 0);
114 begin
115  if(simulation)then
116  reached256 := MatchCntr(5)(4) or MatchCntr(4)(4) or MatchCntr(3)(4) or MatchCntr(2)(4) or MatchCntr(1)(4) or MatchCntr(0)(4);
117  MatchCntr_MSB := MatchCntr(5)(4) & MatchCntr(4)(4) & MatchCntr(3)(4) & MatchCntr(2)(4) & MatchCntr(1)(4) & MatchCntr(0)(4);
118  else
119  reached256 := MatchCntr(5)(8) or MatchCntr(4)(8) or MatchCntr(3)(8) or MatchCntr(2)(8) or MatchCntr(1)(8) or MatchCntr(0)(8);
120  MatchCntr_MSB := MatchCntr(5)(8) & MatchCntr(4)(8) & MatchCntr(3)(8) & MatchCntr(2)(8) & MatchCntr(1)(8) & MatchCntr(0)(8);
121  end if;
122  if(UsrClk'event and UsrClk = '1')then
123  ToggleSyncRegs <= ToggleSyncRegs(2 downto 0) & Toggle;
124  TTC_edge <= TTC_edge(5 downto 0) & (ToggleSyncRegs(3) xor ToggleSyncRegs(2));
125  if(TTC_lock_i = '0')then
126  chk_HammingData <= HammingDataValid_dl3;
127  else
128  chk_HammingData <= TTC_edge(conv_integer(sel_TTC_edge));
129  end if;
130  if((chk_HammingData = '1' and BC0_l = '1') or TTC_lock_i = '1')then
131  MatchCntr <= (others => (others => '0'));
132  elsif(chk_HammingData = '1' and reached256 = '0')then
133  for i in 0 to 5 loop
134  if(TTC_edge(i+1) = '1')then
135  MatchCntr(i) <= MatchCntr(i) + 1;
136  end if;
137  end loop;
138  end if;
139  if(chk_HammingData = '1' and BC0_l = '1' and TTC_lock_i = '0')then
140  sel_TTC_edge(2) <= MatchCntr_MSB(4) or MatchCntr_MSB(5);
141  sel_TTC_edge(1) <= not MatchCntr_MSB(5) and (MatchCntr_MSB(2) or MatchCntr_MSB(3));
142  sel_TTC_edge(0) <= MatchCntr_MSB(5) or (not MatchCntr_MSB(4) and (MatchCntr_MSB(3) or (not MatchCntr_MSB(2) and MatchCntr_MSB(1))));
143  end if;
144  if(chk_HammingData = '1')then
145  if(TTC_lock_i = '0' and HammingData(17 downto 16) = "11")then
146  bcnt <= x"001";
147  BC0_l <= '0';
148  elsif(simulation and bcnt = x"10f")then
149  bcnt <= x"cd0";
150  elsif(bcnt = x"deb")then
151  bcnt <= x"000";
152  BC0_l <= '1';
153  else
154  bcnt <= bcnt + 1;
155  BC0_l <= '0';
156  end if;
157  end if;
158  if(OutStrobe = '1')then
159  TrigData <= TTC_data(7 downto 0);
160  BC0_link <= TTC_data(8);
161  end if;
162  if(chk_HammingData = '1' and bcnt(3 downto 0) /= HammingData(15 downto 12))then
163  BcntMm_i <= '1';
164  else
165  BcntMm_i <= '0';
166  end if;
167  if(TTC_lock_i = '1')then
168  BC0_matchCntr <= (others => '0');
169  elsif(chk_HammingData = '1' and HammingData(17 downto 16) = "11")then
170  if(BC0_l = '0')then
171  BC0_matchCntr <= (others => '0');
172  else
173  BC0_matchCntr <= BC0_matchCntr + 1;
174  end if;
175  end if;
176  if(TTC_lock_i = '0')then
177  MmCntr <= (others => '0');
178  elsif(BcntMm_i = '1')then
179  MmCntr <= MmCntr + 1;
180  elsif(GoodBcnt(3) = '1')then
181  MmCntr <= MmCntr - 1;
182  end if;
183  if(or_reduce(MmCntr) = '0' or GoodBcnt(3) = '1' or BcntMm_i = '1')then
184  GoodBcnt <= (others => '0');
185  elsif(chk_HammingData = '1')then
186  GoodBcnt <= GoodBcnt + 1;
187  end if;
188  if(MmCntr(3) = '1')then
189  TTC_lock_i <= '0';
190  elsif(BC0_matchCntr(8) = '1' or (simulation and BC0_matchCntr(2) = '1'))then
191  TTC_lock_i <= '1';
192  end if;
193  if(HammingDataValid = '1')then
194  HammingData <= HammingData_in;
195  end if;
196  if(HammingData(17) = HammingData(16) and HammingData(17) = BC0_l and bcnt(3 downto 0) = HammingData(15 downto 12) and BC0_lock_i = '1')then
197  TTC_data_in <= BC0_l & HammingData(7 downto 0);
198  else
199  TTC_data_in <= BC0_l & x"00";
200  end if;
201  if(chk_HammingData = '1')then
202  TTC_data_we <= '1';
203  else
204  TTC_data_we <= '0';
205  end if;
206  end if;
207 end process;
208 i_HammingDataValid_dl3 : SRL16E
209  port map (
210  Q => HammingDataValid_dl3, -- SRL data output
211  A0 => '0', -- Select[0] input
212  A1 => '1', -- Select[1] input
213  A2 => '0', -- Select[2] input
214  A3 => '0', -- Select[3] input
215  CE => '1', -- Clock enable input
216  CLK => UsrClk, -- Clock input
217  D => HammingDataValid -- SRL data input
218  );
219 g_TTC_data : for i in 1 to 8 generate
220  i_TTC_data : SRL16E
221  port map (
222  Q => TTC_data(i), -- SRL data output
223  A0 => TTC_data_a(0), -- Select[0] input
224  A1 => TTC_data_a(1), -- Select[1] input
225  A2 => TTC_data_a(2), -- Select[2] input
226  A3 => '0', -- Select[3] input
227  CE => TTC_data_we, -- Clock enable input
228  CLK => UsrClk, -- Clock input
229  D => TTC_data_in(i) -- SRL data input
230  );
231 end generate;
232 process(TTCclk, reset, TTC_lock_i)
233 begin
234  if(reset = '1' or TTC_lock_i = '0')then
235  ec_delta_BC0 <= '0';
236  delta_BC0 <= (others => '0');
237  BC0_offset <= (others => '0');
238  BC0_lock_i <= '0';
239  elsif(TTCclk'event and TTCclk = '1')then
240  if(BC0_link = '1')then
241  ec_delta_BC0 <= '1';
242  elsif(BC0 = '1' or delta_BC0 = x"f")then
243  ec_delta_BC0 <= '0';
244  end if;
245  if(ec_delta_BC0 = '0')then
246  delta_BC0 <= (others => '0');
247  else
248  delta_BC0 <= delta_BC0 + 1;
249  end if;
250  if(BC0 = '1')then
251  if(ec_delta_BC0 = '1')then
252  BC0_offset <= delta_BC0;
253  BC0_lock_i <= '1';
254  else
255  BC0_offset <= (others => '0');
256  BC0_lock_i <= '0';
257  end if;
258  end if;
259  end if;
260 end process;
261 
262 end Behavioral;
263 
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