AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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TCPIP_if.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 14:07:47 10/07/2013
6 -- Design Name:
7 -- Module Name: TCPIP_if - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 use IEEE.numeric_std.all;
26 use work.amc13_pack.all;
27 
28 -- Uncomment the following library declaration if using
29 -- arithmetic functions with Signed or Unsigned values
30 --use IEEE.NUMERIC_STD.ALL;
31 
32 -- Uncomment the following library declaration if instantiating
33 -- any Xilinx primitives in this code.
34 library UNISIM;
35 use UNISIM.VComponents.all;
36 Library UNIMACRO;
37 use UNIMACRO.vcomponents.all;
38 
39 entity TCPIP_if is
40  generic (simulation : boolean := false; en_KEEPALIVE : std_logic := '0');
41  Port ( sysclk : in STD_LOGIC;
42  DRPclk : in STD_LOGIC;
43  reset : in STD_LOGIC;
44  TCPreset : in STD_LOGIC;
45  rstCntr : in STD_LOGIC;
46  test : in STD_LOGIC;
47  Dis_pd : in STD_LOGIC;
48  enSFP : IN std_logic_vector(3 downto 0);
49  SFP_down : OUT std_logic_vector(2 downto 0);
50  inc_ddr_pa : in STD_LOGIC;
51 -- event data in
52  evt_data_rdy : in std_logic_vector(2 downto 0);
53  EventData_in : in array3X67;
54  EventData_we : in std_logic_VECTOR(2 downto 0);
55  EventData_re : out std_logic_VECTOR(2 downto 0); --
56  evt_buf_full : out std_logic_vector(2 downto 0);
57  buf_rqst : in std_logic_vector(3 downto 0);
58  WaitMonBuf : IN std_logic;
59  MonBufOverWrite : in STD_LOGIC;
60  TCPBuf_avl : out STD_LOGIC;
61  MonBuf_avl : out STD_LOGIC;
62  MonBuf_empty : out STD_LOGIC;
63  MonBufOvfl : out STD_LOGIC;
64  mon_evt_cnt : out std_logic_vector(31 downto 0);
65  WrtMonBlkDone : in STD_LOGIC_VECTOR(2 downto 0);
66  WrtMonEvtDone : in STD_LOGIC_VECTOR(2 downto 0);
67  KiloByte_toggle : in STD_LOGIC_VECTOR(2 downto 0);
68  EoB_toggle : in STD_LOGIC_VECTOR(2 downto 0);
69 -- ddr wportA status
70  wport_rdy : in std_logic_vector(2 downto 0);
71  wport_FIFO_full : in std_logic_vector(2 downto 0);
72 -- signal to ddr_if, AMC_if to start moving data
73  EventBufAddr_we : out std_logic_VECTOR(2 downto 0);
74  EventBufAddr : out array3X14;
75 -- ddr wportB signals in sysclk domain
76  TCPclk : out STD_LOGIC;
77  TCP_dout : out std_logic_vector(31 downto 0); -- TCP data are written in unit of 32-bit words
78  TCP_channel : out std_logic_vector(1 downto 0); -- Each entry has four 32bit words, each address saves two entries. Addresses are kept in ddr_wportB
79  TCP_we : out STD_LOGIC;
80  TCP_wcount : in STD_LOGIC_VECTOR (2 downto 0);
81 -- ddr rport signals
82  TCP_raddr : out STD_LOGIC_VECTOR(28 downto 0); -- 28-26 encoded request source 25-0 address in 64 bit word
83  TCP_length : out STD_LOGIC_VECTOR(10 downto 0); -- in 64 bit word, actual length - 1
84  TCP_rrqst : out STD_LOGIC;
85  TCP_rack : in STD_LOGIC;
86  TCP_din_type : in STD_LOGIC_VECTOR(2 downto 0); -- TCP data destination
87  TCP_din : in STD_LOGIC_VECTOR(31 downto 0); -- TCP data are written in unit of 32-bit words
88  TCP_din_valid : in STD_LOGIC;
89  TCP_lastword : in STD_LOGIC;
90 -- SFP ports
91  SFP0_RXN : in STD_LOGIC;
92  SFP0_RXP : in STD_LOGIC;
93  SFP1_RXN : in STD_LOGIC;
94  SFP1_RXP : in STD_LOGIC;
95  SFP2_RXN : in STD_LOGIC;
96  SFP2_RXP : in STD_LOGIC;
97  SFP0_TXN : out STD_LOGIC;
98  SFP0_TXP : out STD_LOGIC;
99  SFP1_TXN : out STD_LOGIC;
100  SFP1_TXP : out STD_LOGIC;
101  SFP2_TXN : out STD_LOGIC;
102  SFP2_TXP : out STD_LOGIC;
103  SFP_REFCLK_N : in STD_LOGIC;
104  SFP_REFCLK_P : in STD_LOGIC;
105  cs_out : out std_logic_vector(511 downto 0);
106 -- ipbus signals
107  ipb_clk : in STD_LOGIC;
108  ipb_write : in STD_LOGIC;
109  ipb_strobe : in STD_LOGIC;
110  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
111  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
112  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0)
113  );
114 end TCPIP_if;
115 
116 architecture Behavioral of TCPIP_if is
117 COMPONENT TCPIP
118  generic (simulation : boolean := false; en_KEEPALIVE : std_logic := '0');
119  PORT(
120  reset : IN std_logic;
121  rstCntr : in STD_LOGIC;
122  sysclk : IN std_logic;
123  clk2x : IN std_logic;
124  clk : IN std_logic;
125  strobe_us : IN std_logic;
126  strobe_ms : IN std_logic;
127  en_LINK : IN std_logic;
128 -- IP_ID : IN std_logic_vector(15 downto 0);
129  MY_PORT : IN std_logic_vector(15 downto 0);
130  MY_IP : IN std_logic_vector(31 downto 0);
131  MY_ETH : IN std_logic_vector(47 downto 0);
132  CWND_max : IN std_logic_vector(31 downto 0);
133  TSclock : IN std_logic_vector(31 downto 0);
134  EVENTdata : IN std_logic_vector(66 downto 0);
135  EventBufAddr : IN std_logic_vector(13 downto 0);
136  EventBufAddr_we : IN std_logic;
137  AddrBuf_full : OUT std_logic;
138  EVENTdata_avl : IN std_logic;
139  DDR2TCPdata : IN std_logic_vector(32 downto 0);
140  RETXdata_we : IN std_logic_vector(1 downto 0);
141  RETXdata_chksum : IN std_logic_vector(15 downto 0);
142  re_RETX_ddr_wq : IN std_logic;
143  RETX_ddr_data_we : IN std_logic;
144  RETXdataACK : IN std_logic;
145  KiloByte_toggle : in STD_LOGIC;
146  EoB_toggle : in STD_LOGIC;
147  TCP_wcount : in STD_LOGIC;
148  PhyEmacRxC : IN std_logic_vector(3 downto 0);
149  PhyEmacRxD : IN std_logic_vector(31 downto 0);
150  LINK_down : OUT std_logic;
151  EVENTdata_re : OUT std_logic;
152  RETX_ddr_out : OUT std_logic_vector(31 downto 0);
153  RETX_ddr_wrqst : OUT std_logic;
154  RETX_ddr_LEN_max : IN std_logic_vector(4 downto 0);
155  RETX_ddr_LEN : OUT std_logic_vector(4 downto 0);
156  RETX_ddr_rrqst : OUT std_logic;
157  RETXdataRqst : OUT std_logic;
158  RETXdataAddr : OUT std_logic_vector(25 downto 0);
159  RETXdataLEN : OUT std_logic_vector(10 downto 0);
160  UNA_MonBuf : OUT std_logic_vector(10 downto 0);
161  UNA_TCPBuf : OUT std_logic_vector(10 downto 0);
162  EmacPhyTxC : OUT std_logic_vector(3 downto 0);
163  EmacPhyTxD : OUT std_logic_vector(31 downto 0);
164  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
165  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
166  cs_out : OUT std_logic_vector(511 downto 0)
167  );
168 END COMPONENT;
169 COMPONENT XGbEPCS32
170  PORT(
171  reset : IN std_logic;
172  clk2x : IN std_logic;
173  clk : IN std_logic;
174  TXUSRCLK : IN std_logic;
175  TX_high : IN std_logic;
176  RXUSRCLK : IN std_logic;
177  RXRESETDONE : IN std_logic;
178  inh_TX : IN std_logic;
179  RESET_TXSync : IN std_logic;
180  GTX_TXD : OUT std_logic_vector(31 downto 0);
181  GTX_TXHEADER : OUT std_logic_vector(1 downto 0);
182  GTX_TX_PAUSE : IN std_logic;
183  GTX_RXD : IN std_logic_vector(31 downto 0);
184  GTX_RXDVLD : IN std_logic;
185  GTX_RXHEADER : IN std_logic_vector(1 downto 0);
186  GTX_RXHEADERVLD : IN std_logic;
187  GTX_RXGOOD : OUT std_logic;
188  GTX_RXGEARBOXSLIP_OUT : OUT std_logic;
189  EmacPhyTxC : IN std_logic_vector(3 downto 0);
190  EmacPhyTxD : IN std_logic_vector(31 downto 0);
191  PhyEmacRxC : OUT std_logic_vector(3 downto 0);
192  PhyEmacRxD : OUT std_logic_vector(31 downto 0)
193  );
194 END COMPONENT;
195 COMPONENT FIFO_RESET_7S
196  PORT(
197  reset : IN std_logic;
198  clk : IN std_logic;
199  fifo_rst : OUT std_logic;
200  fifo_en : OUT std_logic
201  );
202 END COMPONENT;
203 component SFP3_v2_7_init
204 generic
205 (
206  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
207  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
208  STABLE_CLOCK_PERIOD : integer := 20; --Period of the stable clock driving this state-machine, unit is [ns]
209  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
210 
211 );
212 port
213 (
214  SYSCLK_IN : in std_logic;
215  SOFT_RESET_IN : in std_logic;
216  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
217  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
218  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
219  GT0_DATA_VALID_IN : in std_logic;
220  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
221  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
222  GT1_DATA_VALID_IN : in std_logic;
223  GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
224  GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
225  GT2_DATA_VALID_IN : in std_logic;
226 
227  --_________________________________________________________________________
228  --GT0 (X1Y12)
229  --____________________________CHANNEL PORTS________________________________
230  ---------------------------- Channel - DRP Ports --------------------------
231  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
232  GT0_DRPCLK_IN : in std_logic;
233  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
234  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
235  GT0_DRPEN_IN : in std_logic;
236  GT0_DRPRDY_OUT : out std_logic;
237  GT0_DRPWE_IN : in std_logic;
238  ------------------------------- Loopback Ports -----------------------------
239  GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
240  ------------------------------ Power-Down Ports ----------------------------
241  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
242  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
243  --------------------- RX Initialization and Reset Ports --------------------
244  GT0_RXUSERRDY_IN : in std_logic;
245  -------------------------- RX Margin Analysis Ports ------------------------
246  GT0_EYESCANDATAERROR_OUT : out std_logic;
247  ------------------------- Receive Ports - CDR Ports ------------------------
248  GT0_RXCDRLOCK_OUT : out std_logic;
249  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
250  GT0_RXUSRCLK_IN : in std_logic;
251  GT0_RXUSRCLK2_IN : in std_logic;
252  ------------------ Receive Ports - FPGA RX interface Ports -----------------
253  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
254  ------------------- Receive Ports - Pattern Checker Ports ------------------
255  GT0_RXPRBSERR_OUT : out std_logic;
256  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
257  ------------------- Receive Ports - Pattern Checker ports ------------------
258  GT0_RXPRBSCNTRESET_IN : in std_logic;
259  --------------------------- Receive Ports - RX AFE -------------------------
260  GT0_GTXRXP_IN : in std_logic;
261  ------------------------ Receive Ports - RX AFE Ports ----------------------
262  GT0_GTXRXN_IN : in std_logic;
263  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
264  GT0_RXBUFRESET_IN : in std_logic;
265  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
266  --------------- Receive Ports - RX Fabric Output Control Ports -------------
267  GT0_RXOUTCLK_OUT : out std_logic;
268  ---------------------- Receive Ports - RX Gearbox Ports --------------------
269  GT0_RXDATAVALID_OUT : out std_logic;
270  GT0_RXHEADER_OUT : out std_logic_vector(1 downto 0);
271  GT0_RXHEADERVALID_OUT : out std_logic;
272  --------------------- Receive Ports - RX Gearbox Ports --------------------
273  GT0_RXGEARBOXSLIP_IN : in std_logic;
274  ------------- Receive Ports - RX Initialization and Reset Ports ------------
275  GT0_GTRXRESET_IN : in std_logic;
276  GT0_RXPMARESET_IN : in std_logic;
277  ------------------ Receive Ports - RX Margin Analysis ports ----------------
278  GT0_RXLPMEN_IN : in std_logic;
279  -------------- Receive Ports -RX Initialization and Reset Ports ------------
280  GT0_RXRESETDONE_OUT : out std_logic;
281  --------------------- TX Initialization and Reset Ports --------------------
282  GT0_GTTXRESET_IN : in std_logic;
283  GT0_TXUSERRDY_IN : in std_logic;
284  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
285  GT0_TXUSRCLK_IN : in std_logic;
286  GT0_TXUSRCLK2_IN : in std_logic;
287  --------------- Transmit Ports - TX Configurable Driver Ports --------------
288  GT0_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
289  GT0_TXINHIBIT_IN : in std_logic;
290  GT0_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
291  ------------------ Transmit Ports - TX Data Path interface -----------------
292  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
293  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
294  GT0_GTXTXN_OUT : out std_logic;
295  GT0_GTXTXP_OUT : out std_logic;
296  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
297  GT0_TXOUTCLK_OUT : out std_logic;
298  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
299  GT0_TXOUTCLKPCS_OUT : out std_logic;
300  --------------------- Transmit Ports - TX Gearbox Ports --------------------
301  GT0_TXHEADER_IN : in std_logic_vector(1 downto 0);
302  GT0_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
303  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
304  GT0_TXRESETDONE_OUT : out std_logic;
305  ------------------ Transmit Ports - pattern Generator Ports ----------------
306  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
307 
308  --GT1 (X1Y13)
309  --____________________________CHANNEL PORTS________________________________
310  ---------------------------- Channel - DRP Ports --------------------------
311  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
312  GT1_DRPCLK_IN : in std_logic;
313  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
314  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
315  GT1_DRPEN_IN : in std_logic;
316  GT1_DRPRDY_OUT : out std_logic;
317  GT1_DRPWE_IN : in std_logic;
318  ------------------------------- Loopback Ports -----------------------------
319  GT1_LOOPBACK_IN : in std_logic_vector(2 downto 0);
320  ------------------------------ Power-Down Ports ----------------------------
321  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
322  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
323  --------------------- RX Initialization and Reset Ports --------------------
324  GT1_RXUSERRDY_IN : in std_logic;
325  -------------------------- RX Margin Analysis Ports ------------------------
326  GT1_EYESCANDATAERROR_OUT : out std_logic;
327  ------------------------- Receive Ports - CDR Ports ------------------------
328  GT1_RXCDRLOCK_OUT : out std_logic;
329  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
330  GT1_RXUSRCLK_IN : in std_logic;
331  GT1_RXUSRCLK2_IN : in std_logic;
332  ------------------ Receive Ports - FPGA RX interface Ports -----------------
333  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
334  ------------------- Receive Ports - Pattern Checker Ports ------------------
335  GT1_RXPRBSERR_OUT : out std_logic;
336  GT1_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
337  ------------------- Receive Ports - Pattern Checker ports ------------------
338  GT1_RXPRBSCNTRESET_IN : in std_logic;
339  --------------------------- Receive Ports - RX AFE -------------------------
340  GT1_GTXRXP_IN : in std_logic;
341  ------------------------ Receive Ports - RX AFE Ports ----------------------
342  GT1_GTXRXN_IN : in std_logic;
343  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
344  GT1_RXBUFRESET_IN : in std_logic;
345  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
346  --------------- Receive Ports - RX Fabric Output Control Ports -------------
347  GT1_RXOUTCLK_OUT : out std_logic;
348  ---------------------- Receive Ports - RX Gearbox Ports --------------------
349  GT1_RXDATAVALID_OUT : out std_logic;
350  GT1_RXHEADER_OUT : out std_logic_vector(1 downto 0);
351  GT1_RXHEADERVALID_OUT : out std_logic;
352  --------------------- Receive Ports - RX Gearbox Ports --------------------
353  GT1_RXGEARBOXSLIP_IN : in std_logic;
354  ------------- Receive Ports - RX Initialization and Reset Ports ------------
355  GT1_GTRXRESET_IN : in std_logic;
356  GT1_RXPMARESET_IN : in std_logic;
357  ------------------ Receive Ports - RX Margin Analysis ports ----------------
358  GT1_RXLPMEN_IN : in std_logic;
359  -------------- Receive Ports -RX Initialization and Reset Ports ------------
360  GT1_RXRESETDONE_OUT : out std_logic;
361  --------------------- TX Initialization and Reset Ports --------------------
362  GT1_GTTXRESET_IN : in std_logic;
363  GT1_TXUSERRDY_IN : in std_logic;
364  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
365  GT1_TXUSRCLK_IN : in std_logic;
366  GT1_TXUSRCLK2_IN : in std_logic;
367  --------------- Transmit Ports - TX Configurable Driver Ports --------------
368  GT1_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
369  GT1_TXINHIBIT_IN : in std_logic;
370  GT1_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
371  ------------------ Transmit Ports - TX Data Path interface -----------------
372  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
373  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
374  GT1_GTXTXN_OUT : out std_logic;
375  GT1_GTXTXP_OUT : out std_logic;
376  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
377  GT1_TXOUTCLK_OUT : out std_logic;
378  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
379  GT1_TXOUTCLKPCS_OUT : out std_logic;
380  --------------------- Transmit Ports - TX Gearbox Ports --------------------
381  GT1_TXHEADER_IN : in std_logic_vector(1 downto 0);
382  GT1_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
383  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
384  GT1_TXRESETDONE_OUT : out std_logic;
385  ------------------ Transmit Ports - pattern Generator Ports ----------------
386  GT1_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
387 
388  --GT2 (X1Y14)
389  --____________________________CHANNEL PORTS________________________________
390  ---------------------------- Channel - DRP Ports --------------------------
391  GT2_DRPADDR_IN : in std_logic_vector(8 downto 0);
392  GT2_DRPCLK_IN : in std_logic;
393  GT2_DRPDI_IN : in std_logic_vector(15 downto 0);
394  GT2_DRPDO_OUT : out std_logic_vector(15 downto 0);
395  GT2_DRPEN_IN : in std_logic;
396  GT2_DRPRDY_OUT : out std_logic;
397  GT2_DRPWE_IN : in std_logic;
398  ------------------------------- Loopback Ports -----------------------------
399  GT2_LOOPBACK_IN : in std_logic_vector(2 downto 0);
400  ------------------------------ Power-Down Ports ----------------------------
401  GT2_RXPD_IN : in std_logic_vector(1 downto 0);
402  GT2_TXPD_IN : in std_logic_vector(1 downto 0);
403  --------------------- RX Initialization and Reset Ports --------------------
404  GT2_RXUSERRDY_IN : in std_logic;
405  -------------------------- RX Margin Analysis Ports ------------------------
406  GT2_EYESCANDATAERROR_OUT : out std_logic;
407  ------------------------- Receive Ports - CDR Ports ------------------------
408  GT2_RXCDRLOCK_OUT : out std_logic;
409  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
410  GT2_RXUSRCLK_IN : in std_logic;
411  GT2_RXUSRCLK2_IN : in std_logic;
412  ------------------ Receive Ports - FPGA RX interface Ports -----------------
413  GT2_RXDATA_OUT : out std_logic_vector(31 downto 0);
414  ------------------- Receive Ports - Pattern Checker Ports ------------------
415  GT2_RXPRBSERR_OUT : out std_logic;
416  GT2_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
417  ------------------- Receive Ports - Pattern Checker ports ------------------
418  GT2_RXPRBSCNTRESET_IN : in std_logic;
419  --------------------------- Receive Ports - RX AFE -------------------------
420  GT2_GTXRXP_IN : in std_logic;
421  ------------------------ Receive Ports - RX AFE Ports ----------------------
422  GT2_GTXRXN_IN : in std_logic;
423  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
424  GT2_RXBUFRESET_IN : in std_logic;
425  GT2_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
426  --------------- Receive Ports - RX Fabric Output Control Ports -------------
427  GT2_RXOUTCLK_OUT : out std_logic;
428  ---------------------- Receive Ports - RX Gearbox Ports --------------------
429  GT2_RXDATAVALID_OUT : out std_logic;
430  GT2_RXHEADER_OUT : out std_logic_vector(1 downto 0);
431  GT2_RXHEADERVALID_OUT : out std_logic;
432  --------------------- Receive Ports - RX Gearbox Ports --------------------
433  GT2_RXGEARBOXSLIP_IN : in std_logic;
434  ------------- Receive Ports - RX Initialization and Reset Ports ------------
435  GT2_GTRXRESET_IN : in std_logic;
436  GT2_RXPMARESET_IN : in std_logic;
437  ------------------ Receive Ports - RX Margin Analysis ports ----------------
438  GT2_RXLPMEN_IN : in std_logic;
439  -------------- Receive Ports -RX Initialization and Reset Ports ------------
440  GT2_RXRESETDONE_OUT : out std_logic;
441  --------------------- TX Initialization and Reset Ports --------------------
442  GT2_GTTXRESET_IN : in std_logic;
443  GT2_TXUSERRDY_IN : in std_logic;
444  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
445  GT2_TXUSRCLK_IN : in std_logic;
446  GT2_TXUSRCLK2_IN : in std_logic;
447  --------------- Transmit Ports - TX Configurable Driver Ports --------------
448  GT2_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
449  GT2_TXINHIBIT_IN : in std_logic;
450  GT2_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
451  ------------------ Transmit Ports - TX Data Path interface -----------------
452  GT2_TXDATA_IN : in std_logic_vector(31 downto 0);
453  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
454  GT2_GTXTXN_OUT : out std_logic;
455  GT2_GTXTXP_OUT : out std_logic;
456  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
457  GT2_TXOUTCLK_OUT : out std_logic;
458  GT2_TXOUTCLKFABRIC_OUT : out std_logic;
459  GT2_TXOUTCLKPCS_OUT : out std_logic;
460  --------------------- Transmit Ports - TX Gearbox Ports --------------------
461  GT2_TXHEADER_IN : in std_logic_vector(1 downto 0);
462  GT2_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
463  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
464  GT2_TXRESETDONE_OUT : out std_logic;
465  ------------------ Transmit Ports - pattern Generator Ports ----------------
466  GT2_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
467 
468 
469  --____________________________COMMON PORTS________________________________
470  ---------------------- Common Block - Ref Clock Ports ---------------------
471  GT0_GTREFCLK0_COMMON_IN : in std_logic;
472  ------------------------- Common Block - QPLL Ports ------------------------
473  GT0_QPLLLOCK_OUT : out std_logic;
474  GT0_QPLLLOCKDETCLK_IN : in std_logic;
475  GT0_QPLLRESET_IN : in std_logic
476 
477 
478 );
479 end component;
480 COMPONENT RETXdata_chksum
481  PORT(
482  c : IN std_logic;
483  r : IN std_logic;
484  ce : IN std_logic;
485  d : IN std_logic_vector(31 downto 0);
486  s : OUT std_logic_vector(15 downto 0)
487  );
488 END COMPONENT;
489 COMPONENT check_event
490  PORT(
491  clk : IN std_logic;
492  reset : IN std_logic;
493  en_stop : IN std_logic_vector(4 downto 0);
494  cmsCRC_err : IN std_logic_vector(2 downto 0);
495  EventData_in : IN array3X67;
496  EventData_we : IN std_logic_vector(2 downto 0);
497  inc_err : OUT array3X5;
498  stop : OUT std_logic
499  );
500 END COMPONENT;
501 COMPONENT RAM32x6D
502  PORT(
503  wclk : IN std_logic;
504  rclk : IN std_logic;
505  di : IN std_logic_vector(5 downto 0);
506  we : IN std_logic;
507  wa : IN std_logic_vector(4 downto 0);
508  ra : IN std_logic_vector(4 downto 0);
509  ceReg : IN std_logic;
510  do : OUT std_logic_vector(5 downto 0)
511  );
512 END COMPONENT;
513 COMPONENT RAM32x6Db
514  PORT(
515  wclk : IN std_logic;
516  di : IN std_logic_vector(5 downto 0);
517  we : IN std_logic;
518  wa : IN std_logic_vector(4 downto 0);
519  ra : IN std_logic_vector(4 downto 0);
520  do : OUT std_logic_vector(5 downto 0)
521  );
522 END COMPONENT;
523 COMPONENT cmsCRC64
524  PORT(
525  clk : IN std_logic;
526  reset : IN std_logic;
527  crc_init : IN std_logic;
528  trailer : IN std_logic;
529  crc_d : IN std_logic_vector(63 downto 0);
530  crc_ce : IN std_logic;
531  crc : OUT std_logic_vector(15 downto 0);
532  crc_err : OUT std_logic;
533  dout : OUT std_logic_vector(63 downto 0);
534  dout_vld : OUT std_logic
535  );
536 END COMPONENT;
537 signal resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
538 signal ClientClk2XresetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
539 signal refclk : std_logic := '0';
540 signal REFCLK2XPLLRST : std_logic := '0';
541 signal refclk2x_in : std_logic := '0';
542 signal ClientClk2x_dcm : std_logic := '0';
543 signal ClientClk2x : std_logic := '0';
544 signal ClientClk_dcm : std_logic := '0';
545 signal ClientClk : std_logic := '0';
546 signal ClientClk_lock : std_logic := '0';
547 signal ClientClkToggle : std_logic := '0';
548 signal ClientClkToggle_q : std_logic := '0';
549 signal FIFO_rst : std_logic := '0';
550 --signal reset_dl : std_logic := '0';
551 signal FIFO_en : std_logic := '0';
552 signal TX_high : std_logic := '0';
553 signal us_cntr : std_logic_vector(9 downto 0) := (others => '0');
554 signal ms_cntr : std_logic_vector(10 downto 0) := (others => '0');
555 signal strobe_us : std_logic := '0';
556 signal strobe_ms : std_logic := '0';
557 signal TSclock : std_logic_vector(31 downto 0) := (others => '0');
558 signal evt_FIFO_full : std_logic_vector(2 downto 0) := (others => '0');
559 signal evt_FIFO_empty : std_logic_vector(2 downto 0) := (others => '0');
560 signal evt_FIFO_we : std_logic_vector(2 downto 0) := (others => '0');
561 signal evt_FIFO_re : std_logic_vector(2 downto 0) := (others => '0');
562 signal evt_FIFO_rep : std_logic_vector(2 downto 0) := (others => '0');
563 signal evt_FIFO_data_avl : std_logic_vector(2 downto 0) := (others => '0');
564 signal evt_FIFO_di : array3X67 := (others => (others => '0'));
565 signal evt_FIFO_do : array3X67 := (others => (others => '0'));
566 signal evt_FIFO_RDCOUNT : array3X9 := (others => (others => '0'));
567 signal evt_FIFO_WRCOUNT : array3X9 := (others => (others => '0'));
568 signal EVENTdata_avl : std_logic_vector(2 downto 0) := (others => '0');
569 signal EVENTdata_addr : array3X13 := (others => (others => '0'));
570 signal re_RETX_ddr_wq : std_logic_vector(2 downto 0) := (others => '0');
571 signal RETX_ddr_data_we : std_logic_vector(2 downto 0) := (others => '0');
572 signal RETX_ddr_wrqst : std_logic_vector(2 downto 0) := (others => '0');
573 signal RETX_ddr_rrqst : std_logic_vector(2 downto 0) := (others => '0');
574 signal RETX_ddr_out : array3X32 := (others => (others => '0'));
575 signal RETX_ddr_LEN_max : array3X5 := (others => (others => '0'));
576 signal RETX_ddr_LEN : array3X5 := (others => (others => '0'));
577 signal RETXdata_we : array3X2 := (others => (others => '0'));
578 signal DDR2TCPdata : std_logic_vector(32 downto 0) := (others => '0');
579 signal rst_RETXdata_chksum : std_logic := '0';
580 signal RETXdata_chksum_out : std_logic_vector(15 downto 0) := (others => '0');
581 signal RETXdata_checksum : array3x16 := (others => (others => '0'));
582 signal RETXdataLEN : array3X11 := (others => (others => '0'));
583 signal RETXdataAddr : array3X26 := (others => (others => '0'));
584 signal RETXdata_space : std_logic_vector(2 downto 0) := (others => '0');
585 signal RETXdataRqst : std_logic_vector(2 downto 0) := (others => '0');
586 signal RETXdataACK : std_logic_vector(2 downto 0) := (others => '0');
587 signal ReleaseLen : array3X11 := (others => (others => '0'));
588 signal Release_space : std_logic_vector(2 downto 0) := (others => '0');
589 signal ReleaseBuffer : std_logic_vector(2 downto 0) := (others => '0');
590 signal Release_rqst: std_logic_vector(2 downto 0) := (others => '0');
591 signal rrqstMask : std_logic_vector(5 downto 0) := (others => '0');
592 signal TCP_rrqst_i : std_logic_vector(2 downto 0) := (others => '0');
593 signal odd : std_logic := '0';
594 signal rst_odd : std_logic := '0';
595 --signal DDR2TCPdata_vld : std_logic := '0';
596 signal TCP_rFIFO_do_vld : std_logic := '0';
597 signal ld_RETXdata_chksum : std_logic_vector(2 downto 0) := (others => '0');
598 signal ld_RETXdata_chksum_r : std_logic_vector(2 downto 0) := (others => '0');
599 signal ld_RETXdata_chksum_r2 : std_logic_vector(2 downto 0) := (others => '0');
600 signal TCP_rFIFO_wa0SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
601 signal TCP_rFIFO_wa1SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
602 signal TCP_rFIFO_wa2SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
603 signal TCP_rFIFO_di : std_logic_vector(35 downto 0) := (others => '0');
604 signal TCP_rFIFO_do : std_logic_vector(35 downto 0) := (others => '0');
605 signal TCP_rFIFO_wa : std_logic_vector(4 downto 0) := (others => '0');
606 signal TCP_rFIFO_ra : std_logic_vector(4 downto 0) := (others => '0');
607 signal RETX_ddr_rp_rst : std_logic := '0';
608 signal RETX_ddr_rp_we : std_logic := '0';
609 signal RETX_ddr_rp_di : std_logic_vector(17 downto 0) := (others => '0');
610 signal RETX_ddr_rp_do : std_logic_vector(17 downto 0) := (others => '0');
611 signal RETX_ddr_rp_a : std_logic_vector(4 downto 0) := (others => '0');
612 signal TCP_length_i : std_logic_vector(20 downto 0) := (others => '0');
613 signal TCP_raddr_i : std_logic_vector(28 downto 0) := (others => '0');
614 signal TCP_rlength : std_logic_vector(10 downto 0) := (others => '0');
615 --signal rdDDRqueue_we : std_logic := '0';
616 --signal rdDDRqueue_re : std_logic := '0';
617 --signal rdDDRqueue_a : std_logic_vector(2 downto 0) := (others => '0');
618 --signal rdDDRqueue_di : std_logic_vector(2 downto 0) := (others => '0');
619 --signal rdDDRqueue_do : std_logic_vector(2 downto 0) := (others => '0');
620 --signal rdDDRqueue_dout : std_logic_vector(2 downto 0) := (others => '0');
621 --signal rdDDRqueue_dout_vld : std_logic := '0';
622 signal TCP_wFIFO_re : std_logic := '0';
623 signal TCP_w_busy : std_logic := '0';
624 signal TCP_wFIFO_we : std_logic := '0';
625 signal TCP_w_sel : std_logic_vector(1 downto 0) := (others => '0');
626 signal TCP_w_wc : std_logic_vector(3 downto 0) := (others => '0');
627 signal TCP_wFIFO_DI : std_logic_vector(33 downto 0) := (others => '0');
628 signal TCP_wFIFO_DO : std_logic_vector(33 downto 0) := (others => '0');
629 signal TCP_wFIFO_RDCOUNT : std_logic_vector(8 downto 0) := (others => '0');
630 signal TCP_wFIFO_WRCOUNT : std_logic_vector(8 downto 0) := (others => '0');
631 signal inh_TX : std_logic_vector(2 downto 0) := (others => '0');
632 signal inh_TX_q : std_logic_vector(2 downto 0) := (others => '0');
633 signal reset_TXSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
634 signal SFP_TXOUTCLK : std_logic_vector(2 downto 0) := (others => '0');
635 signal txusrclk : std_logic := '0';
636 signal qplllock : std_logic := '0';
637 signal qpllreset : std_logic := '0';
638 signal GTX_TX_READ : std_logic := '0';
639 signal LINK_down : std_logic_vector(2 downto 0) := (others => '0');
640 signal EnTCPIP : std_logic_vector(2 downto 0) := (others => '0');
641 signal SFP_rxoutclk : std_logic_vector(2 downto 0) := (others => '0');
642 signal SFP_rxusrclk : std_logic_vector(2 downto 0) := (others => '0');
643 signal SFP_txresetdone : std_logic_vector(2 downto 0) := (others => '0');
644 signal SFP_gttxreset : std_logic_vector(2 downto 0) := (others => '0');
645 signal SFP_txuserrdy : std_logic_vector(2 downto 0) := (others => '0');
646 signal SFP_rxresetdone : std_logic_vector(2 downto 0) := (others => '0');
647 signal SFP_gtrxreset : std_logic_vector(2 downto 0) := (others => '0');
648 signal SFP_rxuserrdy : std_logic_vector(2 downto 0) := (others => '0');
649 signal SFP_drprdy : std_logic_vector(2 downto 0) := (others => '0');
650 signal SFP_drpen : std_logic_vector(2 downto 0) := (others => '0');
651 signal SFP_drpwe : std_logic_vector(2 downto 0) := (others => '0');
652 signal SFP_rxdfeagchold : std_logic_vector(2 downto 0) := (others => '0');
653 signal SFP_adapt_done : std_logic_vector(2 downto 0) := (others => '0');
654 signal SFP_rxmonitor : array3X7 := (others => (others => '0'));
655 signal SFP_drpdo : array3X16 := (others => (others => '0'));
656 signal SFP_rxmonitorsel : array3X2 := (others => (others => '0'));
657 signal SFP_drpaddr : array3X9 := (others => (others => '0'));
658 signal SFP_drpdi : array3X16 := (others => (others => '0'));
659 signal SFP_RX_FSM_RESET_DONE : std_logic_vector(2 downto 0) := (others => '0');
660 signal SFP_TX_FSM_RESET_DONE : std_logic_vector(2 downto 0) := (others => '0');
661 signal SFP_RXDVLD : std_logic_vector(2 downto 0) := (others => '0');
662 signal SFP_RXHEADERVLD : std_logic_vector(2 downto 0) := (others => '0');
663 signal SFP_RXGEARBOXSLIP : std_logic_vector(2 downto 0) := (others => '0');
664 signal SFP_RXGOOD : std_logic_vector(2 downto 0) := (others => '0');
665 signal SFP_TXD : array3X32 := (others => (others => '0'));
666 signal SFP_TXD_inv : array3X32 := (others => (others => '0'));
667 signal SFP_TXHEADER : array3X2 := (others => (others => '0'));
668 signal SFP_RXD : array3X32 := (others => (others => '0'));
669 signal SFP_RXD_inv : array3X32 := (others => (others => '0'));
670 signal SFP_RXHEADER : array3X2 := (others => (others => '0'));
671 signal SFP_EmacPhyTxD : array3X32 := (others => (others => '0'));
672 signal SFP_EmacPhyTxC : array3X4 := (others => (others => '0'));
673 signal SFP_PhyEmacRxD : array3X32 := (others => (others => '0'));
674 signal SFP_PhyEmacRxC : array3X4 := (others => (others => '0'));
675 signal EmacPhyTxD : array3X32 := (others => (others => '0'));
676 signal EmacPhyTxC : array3X4 := (others => (others => '0'));
677 signal PhyEmacRxD : array3X32 := (others => (others => '0'));
678 signal PhyEmacRxC : array3X4 := (others => (others => '0'));
679 signal TCPIP2SFP_sel : array3X2 := (others => (others => '0'));
680 signal SFP2TCPIP : array3X2 := (others => (others => '0'));
681 signal IPADDR : array3X32 := (others => (others => '0'));
682 signal SFP_IPADDR : array3X32 := (x"c0a80120",x"c0a80121",x"c0a80122");
683 signal CWND_max : std_logic_vector(31 downto 0) := x"0fffffff";
684 signal MACADDR : array3X48 := (others => (others => '0'));
685 signal GTX_TX_PAUSE : std_logic := '0';
686 signal TXSEQ_cntr : std_logic_vector(6 downto 0) := (others => '0');
687 signal SFP_TXSEQUENCE : array3X7 := (others => (others => '0'));
688 signal SFP_LOOPBACK_IN : array3X3 := (others => (others => '0'));
689 signal SFP_RXPRBSERR_OUT : std_logic_vector(2 downto 0) := (others => '0');
690 signal SFP_RXPRBSSEL_IN : array3X3 := (others => (others => '0'));
691 signal SFP_TXPRBSSEL_IN : array3X3 := (others => (others => '0'));
692 signal SFP_EYESCANDATAERROR_OUT : std_logic_vector(2 downto 0) := (others => '0');
693 signal got_eofToggle : std_logic_vector(2 downto 0) := (others => '0');
694 signal EventBufAddr_we_i : std_logic_vector(2 downto 0) := (others => '0');
695 signal EventData_re_i : std_logic_vector(2 downto 0) := (others => '0');
696 signal EventBufAddr_i : array3X14 := (others => (others => '0'));
697 signal ReadBusy : std_logic_vector(2 downto 0) := (others => '0');
698 signal UNA_MonBufMatch : std_logic_vector(3 downto 0) := (others => '0');
699 signal UNA_TCPBufMatch : std_logic_vector(2 downto 0) := (others => '0');
700 signal UNA_MonBufSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
701 signal UNA_TCPBufSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
702 signal inc_ddr_paSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
703 signal sysDIV2 : std_logic := '0';
704 signal evt_FIFO_sel : std_logic := '0';
705 signal ReleaseMonBuf : std_logic := '0';
706 signal ReleaseTCPBuf : std_logic := '0';
707 signal WrtMonBufAllDone_i : std_logic := '0';
708 --signal TCPBufCnt : std_logic_vector(12 downto 0) := (others => '0');
709 --signal MonBufCnt : std_logic_vector(12 downto 0) := (others => '0');
710 signal NXT_TCPBuf : array3X12 := (others => (others => '0'));
711 signal UNA_MonBuf : array5X11 := (others => (others => '0'));
712 signal UNA_TCPBuf : array4X11 := (others => (others => '0'));
713 signal AddrOffset : array3X10 := (others => (others => '0'));
714 signal SFPresetSyncRegs : array3X3 := (others => (others => '0'));
715 signal TCPresetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
716 signal got_eofToggle0SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
717 signal reset_TCPIP : std_logic_vector(2 downto 0) := (others => '0');
718 signal got_eofToggle1SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
719 signal got_eofToggle2SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
720 signal TCPIP_rdata : array3X32 := (others => (others => '0'));
721 signal AddrBuf_full : std_logic_vector(2 downto 0) := (others => '0');
722 signal mon_evt_cnt_i : std_logic_vector(10 downto 0) := (others => '0');
723 signal MonBufUsed : std_logic_vector(9 downto 0) := (others => '0');
724 signal MonBuf_full : std_logic := '0';
725 signal chk_MonBuf_avl : std_logic := '0';
726 signal FirstBlkAddrDo : array2x3x12 := (others => (others => (others => '0')));
727 signal FirstBlkAddr_ra : array2x3x5 := (others => (others => (others => '0')));
728 signal FirstBlkAddr_re : array2X3 := (others => (others => '0'));
729 signal WrtMonEvtDone_l : std_logic_vector(2 downto 0) := (others => '0');
730 signal MonEvtQueued : std_logic_vector(2 downto 0) := (others => '0');
731 signal FirstBlkAddrDoValid : array2X3 := (others => (others => '0'));
732 signal FirstBlkAddr_wa : std_logic_vector(4 downto 0) := (others => '0');
733 signal FirstBlkAddrDi : std_logic_vector(11 downto 0) := (others => '0');
734 signal FirstBlkAddr_we : std_logic := '0';
735 signal MonBuf_wa : std_logic_vector(10 downto 0) := (others => '0');
736 signal MonBuf_ra : std_logic_vector(10 downto 0) := (others => '0');
737 signal NXT_MonBuf : array3X11 := (others => (others => '0'));
738 signal Written_MonBuf : array4X11 := (others => (others => '0'));
739 signal Written_MonBufMatch : std_logic_vector(2 downto 0) := (others => '0');
740 signal SFP_pd : array3X2 := (others => (others => '0'));
741 signal EventData_reCntr : array3X32 := (others => (others => '0'));
742 signal EventData_weCntr : array3X32 := (others => (others => '0'));
743 signal EventBufAddr_weCntr : array3X32 := (others => (others => '0'));
744 signal cmsCRC_initp : std_logic_vector(2 downto 0) := (others => '0');
745 signal cmsCRC_init : std_logic_vector(2 downto 0) := (others => '0');
746 signal cmsCRC_ce : std_logic_vector(2 downto 0) := (others => '0');
747 signal cmsCRC_err : std_logic_vector(2 downto 0) := (others => '0');
748 signal cmsCRC_errCntr : array3X32 := (others => (others => '0'));
749 signal SFP_we : std_logic_vector(2 downto 0) := (others => '0');
750 signal EoB : std_logic_vector(2 downto 0) := (others => '0');
751 signal EoE : std_logic_vector(2 downto 0) := (others => '0');
752 signal SFP_evt_cntr : array3X32 := (others => (others => '0'));
753 signal SFP_blk_cntr : array3X32 := (others => (others => '0'));
754 signal SFP_word_cntr : array3X32 := (others => (others => '0'));
755 --signal EvtLength_err : std_logic_vector(2 downto 0) := (others => '0');
756 signal TotalEvtLengthCntr24q : std_logic_vector(2 downto 0) := (others => '0');
757 signal EvtLengthCntr : array3X24 := (others => (others => '0'));
758 signal EvtLength_errCntr : array3X32 := (others => (others => '0'));
759 signal AMClength_errCntr : array3X32 := (others => (others => '0'));
760 signal AMCvalid_errCntr : array3X32 := (others => (others => '0'));
761 signal AMCcrc_errCntr : array3X32 := (others => (others => '0'));
762 signal TotalEvtLengthCntr : array3X56 := (others => (others => '0'));
763 signal SFP_down_i : std_logic_vector(2 downto 0) := (others => '0');
764 signal StopOverWrite : std_logic := '0';
765 signal StopOnCMScrc_err : std_logic := '0';
766 signal en_stop : std_logic_vector(4 downto 0) := (others => '1');
767 signal stop : std_logic := '0';
768 signal inc_err : array3x5 := (others => (others => '0'));
769 COMPONENT chipscope
770  generic (N : integer := 5);
771  PORT(
772  clka : IN std_logic;
773  clkb : IN std_logic;
774  ina : IN std_logic_vector(135 downto 0);
775  inb : IN std_logic_vector(135 downto 0)
776  );
777 END COMPONENT;
778 COMPONENT chipscope1
779  generic (N : integer := 5);
780  PORT(
781  clk : IN std_logic;
782  Din : IN std_logic_vector(303 downto 0)
783  );
784 END COMPONENT;
785 COMPONENT chipscope1b
786  generic (USER2 : boolean := false);
787  PORT(
788  clk : IN std_logic;
789  Din : IN std_logic_vector(303 downto 0)
790  );
791 END COMPONENT;
792 
793 type array3x512 is array(0 to 2) of std_logic_vector(511 downto 0);
794 signal TCPIP_cs : array3x512;
795 signal cs_din : std_logic_vector(303 downto 0) := (others => '0');
796 signal waitcntr : std_logic_vector(11 downto 0) := (others => '0');
797 begin
798 SFP_down(2) <= SFP_down_i(2) and not enSFP(3) and enSFP(2);
799 SFP_down(1) <= SFP_down_i(1) and not enSFP(3) and enSFP(1);
800 SFP_down(0) <= SFP_down_i(0) and not enSFP(3) and enSFP(0);
801 TCPclk <= ClientClk2X;
802 --MonBuf_avl <= MonBuf_avl_i;
803 MonBufOvfl <= '0';
804 EventBufAddr_we <= EventBufAddr_we_i;
805 EventData_re <= EventData_re_i;
806 mon_evt_cnt(31 downto 11) <= (others => '0');
807 mon_evt_cnt(10 downto 0) <= mon_evt_cnt_i;
808 EventBufAddr <= EventBufAddr_i;
809 TCP_rrqst <= TCP_rrqst_i(2);
810 TCP_raddr <= TCP_raddr_i;
811 --TCP_length <= TCP_rlength(9 downto 0);
812 TCP_length <= TCP_rlength;
813 process(sysclk,reset,ClientClk_lock)
814 begin
815  if(reset = '1' or ClientClk_lock = '0')then
816  resetSyncRegs <= (others => '1');
817  elsif(sysclk'event and sysclk = '1')then
818  resetSyncRegs <= resetSyncRegs(1 downto 0) & '0';
819  end if;
820 end process;
821 process(ClientClk2X,SFP_TX_FSM_RESET_DONE,SFP_RX_FSM_RESET_DONE)
822 begin
823  for i in 0 to 2 loop
824  if(SFP_TX_FSM_RESET_DONE(i) = '0' or SFP_RX_FSM_RESET_DONE(i) = '0')then
825  SFPresetSyncRegs(i) <= (others => '1');
826  elsif(ClientClk2X'event and ClientClk2X = '1')then
827  SFPresetSyncRegs(i) <= SFPresetSyncRegs(i)(1 downto 0) & '0';
828  end if;
829  end loop;
830 end process;
831 process(ClientClk2X,reset,ClientClk_lock)
832 begin
833  if(reset = '1' or ClientClk_lock = '0')then
834  ClientClk2XresetSyncRegs <= (others => '1');
835  elsif(ClientClk2X'event and ClientClk2X = '1')then
836  ClientClk2XresetSyncRegs <= ClientClk2XresetSyncRegs(1 downto 0) & '0';
837  end if;
838 end process;
839 process(ClientClk,TCPreset,ClientClk_lock)
840 begin
841  if(TCPreset = '1' or ClientClk_lock = '0')then
842  TCPresetSyncRegs <= (others => '1');
843  elsif(ClientClk'event and ClientClk = '1')then
844  TCPresetSyncRegs <= TCPresetSyncRegs(1 downto 0) & '0';
845  end if;
846 end process;
847 process(ClientClk)
848 begin
849  if(ClientClk'event and ClientClk = '1')then
850  ClientClkToggle <= not ClientClkToggle;
851  end if;
852 end process;
853 process(ClientClk2X)
854 begin
855  if(ClientClk2X'event and ClientClk2X = '1')then
856  ClientClkToggle_q <= ClientClkToggle;
857  TX_high <= ClientClkToggle_q xnor ClientClkToggle;
858  if(us_cntr(9) = '1')then
859  us_cntr <= "00" & x"c9";
860  TSclock <= TSclock + 1;
861  else
862  us_cntr <= us_cntr + 1;
863  end if;
864  if(us_cntr(9) = '1')then
865  if(ms_cntr(10) = '1')then
866  ms_cntr <= x"03" & "000";
867  else
868  ms_cntr <= ms_cntr + 1;
869  end if;
870  end if;
871  strobe_ms <= us_cntr(9) and ms_cntr(10);
872  end if;
873 end process;
874 strobe_us <= us_cntr(9);
875 process(txusrclk)
876 begin
877  if(txusrclk'event and txusrclk = '1')then
878  if(TXSEQ_cntr = "1000001")then
879  TXSEQ_cntr <= (others => '0');
880  else
881  TXSEQ_cntr <= TXSEQ_cntr + 1;
882  end if;
883  if(TXSEQ_cntr(0) = '1')then
884  GTX_TX_PAUSE <= and_reduce(TXSEQ_cntr(5 downto 1));
885  end if;
886  if(inh_TX(0) = '1')then
887  SFP_TXSEQUENCE(0) <= (others => '0');
888  elsif(TXSEQ_cntr(0) = '1')then
889  SFP_TXSEQUENCE(0) <= '0' & TXSEQ_cntr(6 downto 1);
890  end if;
891  if(inh_TX(1) = '1')then
892  SFP_TXSEQUENCE(1) <= (others => '0');
893  elsif(TXSEQ_cntr(0) = '1')then
894  SFP_TXSEQUENCE(1) <= '0' & TXSEQ_cntr(6 downto 1);
895  end if;
896  if(inh_TX(2) = '1')then
897  SFP_TXSEQUENCE(2) <= (others => '0');
898  elsif(TXSEQ_cntr(0) = '1')then
899  SFP_TXSEQUENCE(2) <= '0' & TXSEQ_cntr(6 downto 1);
900  end if;
901  end if;
902 end process;
903 process(TXUSRCLK,TCPreset)
904 begin
905  if(TCPreset = '1')then
906  reset_TXSyncRegs <= (others => '1');
907  elsif(TXUSRCLK'event and TXUSRCLK = '1')then
908  reset_TXSyncRegs <= reset_TXSyncRegs(1 downto 0) & '0';
909  end if;
910 end process;
911 process(TXUSRCLK,SFP_TX_FSM_RESET_DONE(0))
912 begin
913  if(SFP_TX_FSM_RESET_DONE(0) = '0')then
914  inh_TX(0) <= '1';
915  inh_TX_q(0) <= '1';
916  elsif(TXUSRCLK'event and TXUSRCLK = '1')then
917  if(TXSEQ_cntr(0) = '1' and TXSEQ_cntr(6) = '1')then
918  inh_TX(0) <= '0';
919  end if;
920  inh_TX_q(0) <= inh_TX(0);
921  end if;
922 end process;
923 process(TXUSRCLK,SFP_TX_FSM_RESET_DONE(1))
924 begin
925  if(SFP_TX_FSM_RESET_DONE(1) = '0')then
926  inh_TX(1) <= '1';
927  inh_TX_q(1) <= '1';
928  elsif(TXUSRCLK'event and TXUSRCLK = '1')then
929  if(TXSEQ_cntr(0) = '1' and TXSEQ_cntr(6) = '1')then
930  inh_TX(1) <= '0';
931  end if;
932  inh_TX_q(1) <= inh_TX(1);
933  end if;
934 end process;
935 process(TXUSRCLK,SFP_TX_FSM_RESET_DONE(2))
936 begin
937  if(SFP_TX_FSM_RESET_DONE(2) = '0')then
938  inh_TX(2) <= '1';
939  inh_TX_q(2) <= '1';
940  elsif(TXUSRCLK'event and TXUSRCLK = '1')then
941  if(TXSEQ_cntr(0) = '1' and TXSEQ_cntr(6) = '1')then
942  inh_TX(2) <= '0';
943  end if;
944  inh_TX_q(2) <= inh_TX(2);
945  end if;
946 end process;
947 process(sysclk)
948 begin
949  if(sysclk'event and sysclk = '1')then
950  TCPBuf_avl <= not or_reduce(enTCPIP);
951  evt_buf_full <= evt_FIFO_full or wport_FIFO_full;
952  end if;
953 end process;
954 g_FirstBlkAddr: for j in 0 to 1 generate
955  g1_FirstBlkAddr: for i in 0 to 5 generate
956  i_FirstBlkAddr : RAM32M
957  port map (
958  DOA => FirstBlkAddrDo(j)(0)(i*2+1 downto i*2), -- Read port A 2-bit output
959  DOB => FirstBlkAddrDo(j)(1)(i*2+1 downto i*2), -- Read port B 2-bit output
960  DOC => FirstBlkAddrDo(j)(2)(i*2+1 downto i*2), -- Read port C 2-bit output
961  DOD => open, -- Read/Write port D 2-bit output
962  ADDRA => FirstBlkAddr_ra(j)(0), -- Read port A 5-bit address input
963  ADDRB => FirstBlkAddr_ra(j)(1), -- Read port B 5-bit address input
964  ADDRC => FirstBlkAddr_ra(j)(2), -- Read port C 5-bit address input
965  ADDRD => FirstBlkAddr_wa, -- Read/Write port D 5-bit address input
966  DIA => FirstBlkAddrDi(i*2+1 downto i*2), -- RAM 2-bit data write input addressed by ADDRD,
967  -- read addressed by ADDRA
968  DIB => FirstBlkAddrDi(i*2+1 downto i*2), -- RAM 2-bit data write input addressed by ADDRD,
969  -- read addressed by ADDRB
970  DIC => FirstBlkAddrDi(i*2+1 downto i*2), -- RAM 2-bit data write input addressed by ADDRD,
971  -- read addressed by ADDRC
972  DID => "00", -- RAM 2-bit data write input addressed by ADDRD,
973  -- read addressed by ADDRD
974  WCLK => sysclk, -- Write clock input
975  WE => FirstBlkAddr_we -- Write enable input
976  );
977  end generate;
978 end generate;
979 FirstBlkAddrDi <= '0' & MonBuf_wa;
980 process(sysclk)
981 begin
982  if(sysclk'event and sysclk = '1')then
983  sysDIV2 <= not sysDIV2;
984  if(resetSyncRegs(2) = '1')then
985  chk_MonBuf_avl <= '1';
986  elsif(buf_rqst(0) = '1')then
987  chk_MonBuf_avl <= buf_rqst(3);
988  end if;
989  if(resetSyncRegs(2) = '1')then
990  MonBuf_avl <= '1';
991  elsif(WaitMonBuf = '1' or MonBufOverWrite = '1' or enTCPIP /= "000")then
992  if((MonBuf_wa(10) /= MonBuf_ra(10) and MonBuf_wa(9 downto 0) = MonBuf_ra(9 downto 0)))then
993  MonBuf_avl <= '0';
994  else
995  MonBuf_avl <= '1';
996  end if;
997  elsif(chk_MonBuf_avl = '1')then
998  if(MonBufUsed(9 downto 8) = "11")then
999  MonBuf_avl <= '0';
1000  else
1001  MonBuf_avl <= '1';
1002  end if;
1003  end if;
1004  if(enTCPIP /= "000")then
1005  mon_evt_cnt_i <= (others => '0');
1006  elsif(MonBufOverWrite = '1')then
1007  mon_evt_cnt_i <= '0' & Written_MonBuf(3)(9 downto 0);
1008  else
1009  mon_evt_cnt_i <= Written_MonBuf(3) - MonBuf_ra;
1010  end if;
1011  if(enTCPIP /= "000")then
1012  MonBuf_empty <= '1';
1013  elsif(MonBufOverWrite = '0')then
1014  MonBuf_empty <= not or_reduce(mon_evt_cnt_i);
1015  elsif(Written_MonBuf(3) /= MonBuf_ra or MonBuf_full = '1')then
1016  MonBuf_empty <= '0';
1017  else
1018  MonBuf_empty <= '1';
1019  end if;
1020  if(EnSFP(2 downto 1) = "00")then
1021  SFP_we(0) <= EventData_we(0);
1022  EoB(0) <= EventData_in(0)(64);
1023  EoE(0) <= EventData_in(0)(65);
1024  else
1025  SFP_we(0) <= EventData_we(1) and EnSFP(0);
1026  EoB(0) <= EventData_in(1)(64);
1027  EoE(0) <= EventData_in(1)(65);
1028  end if;
1029  if(EnSFP(2 downto 0) = "110")then
1030  SFP_we(1) <= EventData_we(1);
1031  EoB(1) <= EventData_in(1)(64);
1032  EoE(1) <= EventData_in(1)(65);
1033  else
1034  SFP_we(1) <= EventData_we(0) and EnSFP(1);
1035  EoB(1) <= EventData_in(0)(64);
1036  EoE(1) <= EventData_in(0)(65);
1037  end if;
1038  if(EnSFP(2 downto 0) = "111")then
1039  SFP_we(2) <= EventData_we(2);
1040  EoB(2) <= EventData_in(2)(64);
1041  EoE(2) <= EventData_in(2)(65);
1042  else
1043  SFP_we(2) <= EventData_we(0) and EnSFP(2);
1044  EoB(2) <= EventData_in(0)(64);
1045  EoE(2) <= EventData_in(0)(65);
1046  end if;
1047  if(resetSyncRegs(2) = '1')then
1048  ReadBusy <= (others => '0');
1049  EventData_re_i <= (others => '0');
1050  EventBufAddr_we_i <= (others => '0');
1051  UNA_MonBufSyncRegs <= (others => '0');
1052  UNA_TCPBufSyncRegs <= (others => '0');
1053  ReleaseMonBuf <= '0';
1054  ReleaseTCPBuf <= '0';
1055  MonBuf_wa <= (others => '0');
1056  MonBuf_ra <= (others => '0');
1057  Written_MonBufMatch <= (others => '1');
1058  Written_MonBuf <= (others => (others => '0'));
1059  NXT_MonBuf <= (others => (others => '0'));
1060  NXT_TCPBuf <= (others => (others => '0'));
1061  FirstBlkAddr_we <= '0';
1062  FirstBlkAddr_re <= (others => (others => '0'));
1063  FirstBlkAddrDoValid <= (others => (others => '0'));
1064  WrtMonEvtDone_l <= (others => '0');
1065  MonEvtQueued <= (others => '0');
1066  FirstBlkAddr_wa <= (others => '0');
1067  FirstBlkAddr_ra <= (others => (others => (others => '0')));
1068  MonBuf_full <= '0';
1069  EventData_reCntr <= (others => (others => '0'));
1070  EventData_weCntr <= (others => (others => '0'));
1071  EventBufAddr_weCntr <= (others => (others => '0'));
1072  EvtLengthCntr <= (others => x"000001");
1073  TotalEvtLengthCntr <= (others => (others => '0'));
1074  TotalEvtLengthCntr24q <= "000";
1075  SFP_blk_cntr <= (others => (others => '0'));
1076  SFP_evt_cntr <= (others => (others => '0'));
1077  SFP_word_cntr <= (others => (others => '0'));
1078  else
1079  for i in 0 to 2 loop
1080  if(EVENTdata_in(i)(64) = '1' and EVENTdata_we(i) = '1')then
1081  ReadBusy(i) <= '0';
1082  elsif(evt_data_rdy(i) = '1' and wport_rdy(i) = '1' and AddrBuf_full(i) = '0')then
1083  ReadBusy(i) <= '1';
1084  end if;
1085  EventData_re_i(i) <= evt_data_rdy(i) and wport_rdy(i) and not ReadBusy(i) and not AddrBuf_full(i);
1086  if(EventData_re_i(i) = '1')then
1087  EventData_reCntr(i) <= EventData_reCntr(i) + 1;
1088  end if;
1089  if(EventData_we(i) = '1')then
1090  EventData_weCntr(i) <= EventData_weCntr(i) + 1;
1091  end if;
1092  if(EventData_in(i)(66) = '0')then
1093  EventBufAddr_we_i(i) <= evt_data_rdy(i) and wport_rdy(i) and not ReadBusy(i) and not AddrBuf_full(i);
1094  else
1095  EventBufAddr_we_i(i) <= '0';
1096  end if;
1097  if(EventBufAddr_we_i(i) = '1')then
1098  EventBufAddr_weCntr(i) <= EventBufAddr_weCntr(i) + 1;
1099  end if;
1100  if(EventData_we(i) = '1')then
1101  if(EventData_in(i)(65) = '1')then
1102  EvtLengthCntr(i) <= x"000001";
1103  TotalEvtLengthCntr(i)(24 downto 0) <= TotalEvtLengthCntr(i)(24 downto 0) + ('0' & EventData_in(i)(55 downto 32));
1104  else
1105  EvtLengthCntr(i) <= EvtLengthCntr(i) + 1;
1106  end if;
1107  end if;
1108  TotalEvtLengthCntr24q(i) <= TotalEvtLengthCntr(i)(24);
1109  if(TotalEvtLengthCntr24q(i) = '1' and TotalEvtLengthCntr(i)(24) = '0')then
1110  TotalEvtLengthCntr(i)(55 downto 25) <= TotalEvtLengthCntr(i)(55 downto 25) + 1;
1111  end if;
1112  end loop;
1113  if(MonBufOverWrite = '1' and Written_MonBuf(3)(10) = '1')then
1114  MonBuf_full <= '1';
1115  end if;
1116  for j in 0 to 1 loop
1117  for i in 0 to 2 loop
1118  if(FirstBlkAddr_re(j)(i) = '1')then
1119  FirstBlkAddr_ra(j)(i) <= FirstBlkAddr_ra(j)(i) + 1;
1120  end if;
1121  if(FirstBlkAddr_ra(j)(i) = FirstBlkAddr_wa)then
1122  FirstBlkAddrDoValid(j)(i) <= '0';
1123  else
1124  FirstBlkAddrDoValid(j)(i) <= '1';
1125  end if;
1126  end loop;
1127  end loop;
1128  if(FirstBlkAddr_we = '1')then
1129  FirstBlkAddr_wa <= FirstBlkAddr_wa + 1;
1130  end if;
1131  for i in 0 to 2 loop
1132  if(WrtMonEvtDone(i) = '1' and enTCPIP = "000")then
1133  WrtMonEvtDone_l(i) <= '1';
1134  elsif(FirstBlkAddrDoValid(0)(i) = '1')then
1135  WrtMonEvtDone_l(i) <= '0';
1136  end if;
1137  FirstBlkAddr_re(0)(i) <= FirstBlkAddrDoValid(0)(i) and WrtMonEvtDone_l(i);
1138  if(EventData_we(i) = '1' and EventData_in(i)(66 downto 65) = "01" and enTCPIP = "000")then
1139  MonEvtQueued(i) <= '1';
1140  elsif(FirstBlkAddrDoValid(1)(i) = '1')then
1141  MonEvtQueued(i) <= '0';
1142  end if;
1143  FirstBlkAddr_re(1)(i) <= FirstBlkAddrDoValid(1)(i) and MonEvtQueued(i);
1144  end loop;
1145  FirstBlkAddr_we <= buf_rqst(3) and buf_rqst(0) and not or_reduce(enTCPIP);
1146  if(buf_rqst(0) = '1')then
1147  MonBuf_wa <= MonBuf_wa + 1;
1148  end if;
1149  MonBufUsed <= MonBuf_wa(9 downto 0) - MonBuf_ra(9 downto 0);
1150  if(ReleaseMonBuf = '1' or (MonBufOverWrite = '1' and StopOverWrite = '0' and and_reduce(MonBufUsed) = '1' and buf_rqst(0) = '1'))then
1151  MonBuf_ra <= MonBuf_ra + 1;
1152  end if;
1153  if(Written_MonBuf(0) = Written_MonBuf(3) and WrtMonEvtDone_l(0) = '0')then
1154  Written_MonBufMatch(0) <= '1';
1155  else
1156  Written_MonBufMatch(0) <= '0';
1157  end if;
1158  if((EnSFP(2 downto 0) = "111" or EnSFP(2 downto 0) = "011" or EnSFP(2 downto 0) = "110" or EnSFP(2 downto 0) = "101") and Written_MonBuf(1) = Written_MonBuf(3) and WrtMonEvtDone_l(1) = '0')then
1159  Written_MonBufMatch(1) <= '1';
1160  else
1161  Written_MonBufMatch(1) <= '0';
1162  end if;
1163  if(EnSFP(2 downto 0) = "111" and Written_MonBuf(2) = Written_MonBuf(3) and WrtMonEvtDone_l(2) = '0')then
1164  Written_MonBufMatch(2) <= '1';
1165  else
1166  Written_MonBufMatch(2) <= '0';
1167  end if;
1168  if(Written_MonBufMatch = "000" and sysDIV2 = '0')then
1169  Written_MonBuf(3) <= Written_MonBuf(3) + 1;
1170  end if;
1171  UNA_MonBufSyncRegs <= UNA_MonBufSyncRegs(2 downto 0) & UNA_MonBuf(4)(0);
1172  UNA_TCPBufSyncRegs <= UNA_TCPBufSyncRegs(2 downto 0) & UNA_TCPBuf(3)(0);
1173  ReleaseMonBuf <= UNA_MonBufSyncRegs(3) xor UNA_MonBufSyncRegs(2);
1174  ReleaseTCPBuf <= UNA_TCPBufSyncRegs(3) xor UNA_TCPBufSyncRegs(2);
1175  for i in 0 to 2 loop
1176  if(FirstBlkAddr_re(0)(i) = '1')then
1177  Written_MonBuf(i) <= FirstBlkAddrDo(0)(i)(10 downto 0);
1178  elsif(WrtMonBlkDone(i) = '1')then
1179  Written_MonBuf(i) <= Written_MonBuf(i) + 1;
1180  end if;
1181  if(FirstBlkAddr_re(1)(i) = '1')then
1182  NXT_MonBuf(i) <= FirstBlkAddrDo(1)(i)(10 downto 0);
1183  elsif(EventBufAddr_we_i(i) = '1' and EventData_in(i)(66) = '0')then
1184  NXT_MonBuf(i) <= NXT_MonBuf(i) + 1;
1185  end if;
1186  if(EventBufAddr_we_i(i) = '1' and EventData_in(i)(66) = '1')then
1187  NXT_TCPBuf(i) <= NXT_TCPBuf(i) + 1;
1188  end if;
1189  if(SFP_we(i) = '1' and EoB(i) = '1')then
1190  SFP_blk_cntr(i) <= SFP_blk_cntr(i) + 1;
1191  end if;
1192  if(SFP_we(i) = '1' and EoE(i) = '1')then
1193  SFP_evt_cntr(i) <= SFP_evt_cntr(i) + 1;
1194  end if;
1195  if(SFP_we(i) = '1')then
1196  SFP_word_cntr(i) <= SFP_word_cntr(i) + 1;
1197  end if;
1198  end loop;
1199  end if;
1200  for i in 0 to 2 loop
1201  if(EventData_in(i)(66) = '0')then
1202  EventBufAddr_i(i) <= NXT_MonBuf(i)(9 downto 0) & AddrOffset(i)(9 downto 6);
1203  else
1204  EventBufAddr_i(i) <= NXT_TCPBuf(i)(9 downto 0) & AddrOffset(i)(9 downto 6);
1205  end if;
1206  end loop;
1207  end if;
1208 end process;
1209 process(ClientClk2X)
1210 begin
1211  if(ClientClk2X'event and ClientClk2X = '1')then
1212  if(ClientClk2XresetSyncRegs(2) = '1')then
1213  inc_ddr_paSyncRegs <= (others => '0');
1214  UNA_MonBufMatch <= (others => '1');
1215  UNA_TCPBufMatch <= (others => '1');
1216  UNA_MonBuf(4) <= (others => '0');
1217  UNA_MonBuf(3) <= (others => '0');
1218  UNA_TCPBuf(3) <= (others => '0');
1219  else
1220  inc_ddr_paSyncRegs <= inc_ddr_paSyncRegs(2 downto 0) & inc_ddr_pa;
1221  if(inc_ddr_paSyncRegs(3 downto 2) = "10")then
1222  UNA_MonBuf(3) <= UNA_MonBuf(3) + 1;
1223  end if;
1224  for i in 0 to 2 loop
1225  if(enTCPIP(i) = '1' and UNA_MonBuf(i) = UNA_MonBuf(4))then
1226  UNA_MonBufMatch(i) <= '1';
1227  else
1228  UNA_MonBufMatch(i) <= '0';
1229  end if;
1230  if(enTCPIP(i) = '1' and UNA_TCPBuf(i) = UNA_TCPBuf(3))then
1231  UNA_TCPBufMatch(i) <= '1';
1232  else
1233  UNA_TCPBufMatch(i) <= '0';
1234  end if;
1235  end loop;
1236  if(EnTCPIP = "000" and UNA_MonBuf(3) = UNA_MonBuf(4))then
1237  UNA_MonBufMatch(3) <= '1';
1238  else
1239  UNA_MonBufMatch(3) <= '0';
1240  end if;
1241  if(UNA_MonBufMatch = x"0" and us_cntr(0) = '1')then
1242  UNA_MonBuf(4) <= UNA_MonBuf(4) + 1;
1243  end if;
1244  if(UNA_TCPBufMatch = "000" and enSFP(2 downto 0) /= "000" and us_cntr(0) = '1')then
1245  UNA_TCPBuf(3) <= UNA_TCPBuf(3) + 1;
1246  end if;
1247  end if;
1248  case EnSFP(2 downto 0) is
1249  when "011" | "101" | "110" => AddrOffset(0)(9 downto 6) <= x"8";
1250  when "111" => AddrOffset(0)(9 downto 6) <= x"5";
1251  when others => AddrOffset(0)(9 downto 6) <= x"0";
1252  end case;
1253  AddrOffset(1)(9 downto 6) <= x"0";
1254  AddrOffset(2)(9 downto 6) <= x"a";
1255  if(EnSFP(3) = '0' and or_reduce(EnSFP(2 downto 0)) = '1')then
1256  EnTCPIP(0) <= '1';
1257  else
1258  EnTCPIP(0) <= '0';
1259  end if;
1260  if(EnSFP(3) = '0' and (EnSFP(2 downto 0) = "011" or EnSFP(2 downto 0) = "101" or EnSFP(2 downto 0) = "110" or EnSFP(2 downto 0) = "111"))then
1261  EnTCPIP(1) <= '1';
1262  else
1263  EnTCPIP(1) <= '0';
1264  end if;
1265  if(EnSFP = x"7")then
1266  EnTCPIP(2) <= '1';
1267  else
1268  EnTCPIP(2) <= '0';
1269  end if;
1270  end if;
1271 end process;
1272 process(sysclk,rstCntr)
1273 begin
1274  if(rstCntr = '1')then
1275  EvtLength_errCntr <= (others => (others => '0'));
1276  AMCLength_errCntr <= (others => (others => '0'));
1277  AMCvalid_errCntr <= (others => (others => '0'));
1278  AMCcrc_errCntr <= (others => (others => '0'));
1279  elsif(sysclk'event and sysclk = '1')then
1280  for i in 0 to 2 loop
1281  if(inc_err(i)(1) = '1')then
1282  EvtLength_errCntr(i) <= EvtLength_errCntr(i) + 1;
1283  end if;
1284  if(inc_err(i)(2) = '1')then
1285  AMClength_errCntr(i) <= AMClength_errCntr(i) + 1;
1286  end if;
1287  if(inc_err(i)(3) = '1')then
1288  AMCvalid_errCntr(i) <= AMCvalid_errCntr(i) + 1;
1289  end if;
1290  if(inc_err(i)(4) = '1')then
1291  AMCcrc_errCntr(i) <= AMCcrc_errCntr(i) + 1;
1292  end if;
1293  end loop;
1294  end if;
1295 end process;
1296 i_check_event: check_event PORT MAP(
1297  clk => sysclk ,
1298  reset => resetSyncRegs(2),
1299  en_stop => en_stop,
1300  cmsCRC_err => "000",
1301  EventData_in => EventData_in ,
1302  EventData_we => EventData_we ,
1303  inc_err => inc_err,
1304  stop => stop
1305  );
1306 process(sysclk,rstCntr)
1307 begin
1308  if(rstCntr = '1')then
1309  StopOverWrite <= '0';
1310  elsif(StopOnCMScrc_err = '1')then
1311  StopOverWrite <= '1';
1312  elsif(sysclk'event and sysclk = '1')then
1313  if(stop = '1')then
1314  StopOverWrite <= '1';
1315  end if;
1316  end if;
1317 end process;
1318 i_FIFO_RESET_7S: FIFO_RESET_7S PORT MAP(
1319  reset => resetSyncRegs(2),
1320  clk => sysclk ,
1321  fifo_rst => fifo_rst,
1322  fifo_en => fifo_en
1323  );
1324 process(sysclk)
1325 begin
1326  if(sysclk'event and sysclk = '1')then
1327  for i in 0 to 2 loop
1328  if(resetSyncRegs(2) = '1' or EventBufAddr_we_i(i) = '1')then
1329  evt_FIFO_di(i)(65) <= '1';
1330  elsif(evt_FIFO_we(i) = '1')then
1331  evt_FIFO_di(i)(65) <= '0';
1332  end if;
1333  end loop;
1334  end if;
1335 end process;
1336 g_evt_FIFO: for i in 0 to 2 generate
1337  i_evt_fifo : FIFO_DUALCLOCK_MACRO
1338  generic map (
1339  DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"
1340  ALMOST_FULL_OFFSET => X"0004", -- Sets almost full threshold
1341  ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold
1342  DATA_WIDTH => 67, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
1343  FIFO_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
1344  FIRST_WORD_FALL_THROUGH => TRUE) -- Sets the FIFO FWFT to TRUE or FALSE
1345  port map (
1346  ALMOSTEMPTY => open, -- 1-bit output almost empty
1347  ALMOSTFULL => evt_FIFO_full(i), -- 1-bit output almost full
1348  DO => evt_FIFO_do(i), -- Output data, width defined by DATA_WIDTH parameter
1349  EMPTY => evt_FIFO_empty(i), -- 1-bit output empty
1350  FULL => open, -- 1-bit output full
1351  RDCOUNT => evt_FIFO_RDCOUNT (i), -- Output read count, width determined by FIFO depth
1352  RDERR => open, -- 1-bit output read error
1353  WRCOUNT => evt_FIFO_WRCOUNT (i), -- Output write count, width determined by FIFO depth
1354  WRERR => open, -- 1-bit output write error
1355  DI => evt_FIFO_di(i), -- Input data, width defined by DATA_WIDTH parameter
1356  RDCLK => ClientClk2X, -- 1-bit input read clock
1357  RDEN => evt_FIFO_re(i), -- 1-bit input read enable
1358  RST => fifo_rst, -- 1-bit input reset
1359  WRCLK => sysclk, -- 1-bit input write clock
1360  WREN => evt_FIFO_we(i) -- 1-bit input write enable
1361  );
1362 end generate;
1363 evt_FIFO_di(0)(64 downto 0) <= EVENTdata_in(0)(64 downto 0);
1364 evt_FIFO_di(1)(64 downto 0) <= EVENTdata_in(1)(64 downto 0);
1365 evt_FIFO_di(2)(64 downto 0) <= EVENTdata_in(2)(64 downto 0);
1366 evt_FIFO_di(0)(66) <= EVENTdata_in(0)(65);
1367 evt_FIFO_di(1)(66) <= EVENTdata_in(1)(65);
1368 evt_FIFO_di(2)(66) <= EVENTdata_in(2)(65);
1369 evt_FIFO_we <= "000" when EnSFP(3) = '1' or fifo_en = '0' else EVENTdata_we;
1370 evt_FIFO_re <= "000" when fifo_en = '0' else evt_FIFO_rep;
1371 EVENTdata_avl <= not evt_FIFO_empty;
1372 g_cmsCRC : for i in 0 to 2 generate
1373  i_cmsCRC: cmsCRC64 PORT MAP(
1374  clk => ClientClk2X ,
1375  reset => '0',
1376  crc_init => cmsCRC_init(i),
1377  trailer => evt_FIFO_do(i)(66),
1378  crc_d => evt_FIFO_do(i)(63 downto 0),
1379  crc_ce => cmsCRC_ce(i),
1380  crc => open,
1381  crc_err => cmsCRC_err(i),
1382  dout => open,
1383  dout_vld => open
1384  );
1385 end generate;
1386 cmsCRC_ce <= evt_FIFO_rep and EVENTdata_avl;
1387 process(ClientClk2X)
1388 begin
1389  if(ClientClk2X'event and ClientClk2X = '1')then
1390  if(ClientClk2XresetSyncRegs(2) = '1')then
1391  cmsCRC_initp <= "000";
1392  cmsCRC_init <= "111";
1393  cmsCRC_errCntr <= (others => (others => '0'));
1394  StopOnCMScrc_err <= '0';
1395  else
1396  for i in 0 to 2 loop
1397  cmsCRC_initp(i) <= evt_FIFO_do(i)(66) and cmsCRC_ce(i);
1398  if(cmsCRC_err(i) = '1' and cmsCRC_init(i) = '1')then
1399  cmsCRC_errCntr(i) <= cmsCRC_errCntr(i) + 1;
1400  end if;
1401  end loop;
1402  cmsCRC_init <= cmsCRC_initp;
1403  if(en_stop(0) = '1' and or_reduce(cmsCRC_err and cmsCRC_init) = '1')then
1404  StopOnCMScrc_err <= '1';
1405  else
1406  StopOnCMScrc_err <= '0';
1407  end if;
1408  end if;
1409  end if;
1410 end process;
1411 g_TCPIP: for i in 0 to 2 generate
1412  i_TCPIP: TCPIP PORT MAP(
1413  reset => reset_TCPIP(i),
1414  rstCntr => rstCntr,
1415  sysclk => sysclk,
1416  clk2x => ClientClk2X,
1417  clk => ClientClk ,
1418  strobe_us => strobe_us,
1419  strobe_ms => strobe_ms,
1420  en_LINK => enTCPIP(i),
1421  LINK_down => LINK_down(i),
1422  MY_PORT => x"1234",
1423  MY_IP => IPADDR (i),
1424  MY_ETH => MACADDR(i),
1425  TSclock => TSclock,
1426  CWND_max => CWND_max,
1427  EVENTdata => evt_FIFO_do(i),
1428  EVENTdata_avl => EVENTdata_avl (i),
1429  EVENTdata_re => evt_FIFO_rep (i),
1430  DDR2TCPdata => DDR2TCPdata ,
1431  RETXdata_chksum => RETXdata_checksum (i),
1432  RETXdata_we => RETXdata_we (i),
1433  RETX_ddr_out => RETX_ddr_out (i),
1434  re_RETX_ddr_wq => re_RETX_ddr_wq (i),
1435  RETX_ddr_wrqst => RETX_ddr_wrqst (i),
1436  RETX_ddr_data_we => RETX_ddr_data_we (i),
1437  RETX_ddr_rrqst => RETX_ddr_rrqst (i),
1438  RETX_ddr_LEN_max => RETX_ddr_LEN_max (i),
1439  RETX_ddr_LEN => RETX_ddr_LEN (i),
1440  RETXdataACK => RETXdataACK (i),
1441  RETXdataRqst => RETXdataRqst (i),
1442  RETXdataAddr => RETXdataAddr (i),
1443  RETXdataLEN => RETXdataLEN (i),
1444  KiloByte_toggle => KiloByte_toggle (i),
1445  EoB_toggle => EoB_toggle(i),
1446  TCP_wcount => TCP_wcount(i),
1447  EventBufAddr => EventBufAddr_i (i),
1448  EventBufAddr_we => EventBufAddr_we_i (i),
1449  AddrBuf_full => AddrBuf_full (i),
1450  UNA_MonBuf => UNA_MonBuf(i),
1451  UNA_TCPBuf => UNA_TCPBuf(i),
1452  EmacPhyTxC => EmacPhyTxc(i),
1453  EmacPhyTxD => EmacPhyTxd(i),
1454  PhyEmacRxC => PhyEmacRxC(i),
1455  PhyEmacRxD => PhyEmacRxD(i),
1456  ipb_addr => ipb_addr,
1457  ipb_rdata => TCPIP_rdata(i),
1458  cs_out => TCPIP_cs(i)
1459  );
1460 end generate;
1461 i_RETXdata_chksum: RETXdata_chksum PORT MAP(
1462  c => ClientClk2X,
1463  r => rst_RETXdata_chksum,
1464  ce => TCP_din_valid,
1465  d => TCP_din ,
1466  s => RETXdata_chksum_out
1467  );
1468 process(ClientClk2X)
1469 begin
1470  if(ClientClk2X'event and ClientClk2X = '1')then
1471  if(TCP_lastword = '1' and TCP_din_valid = '1' and TCP_din_type = "100")then
1472  ld_RETXdata_chksum(0) <= '1';
1473  else
1474  ld_RETXdata_chksum(0) <= '0';
1475  end if;
1476  if(TCP_lastword = '1' and TCP_din_valid = '1' and TCP_din_type = "101")then
1477  ld_RETXdata_chksum(1) <= '1';
1478  else
1479  ld_RETXdata_chksum(1) <= '0';
1480  end if;
1481  if(TCP_lastword = '1' and TCP_din_valid = '1' and TCP_din_type = "110")then
1482  ld_RETXdata_chksum(2) <= '1';
1483  else
1484  ld_RETXdata_chksum(2) <= '0';
1485  end if;
1486  ld_RETXdata_chksum_r <= ld_RETXdata_chksum;
1487  ld_RETXdata_chksum_r2 <= ld_RETXdata_chksum_r;
1488  if(ld_RETXdata_chksum_r2(0) = '1')then
1489  RETXdata_checksum(0) <= RETXdata_chksum_out;
1490  end if;
1491  if(ld_RETXdata_chksum_r2(1) = '1')then
1492  RETXdata_checksum(1) <= RETXdata_chksum_out;
1493  end if;
1494  if(ld_RETXdata_chksum_r2(2) = '1')then
1495  RETXdata_checksum(2) <= RETXdata_chksum_out;
1496  end if;
1497  if(ClientClk2XresetSyncRegs(2) = '1')then
1498  rst_RETXdata_chksum <= '1';
1499  else
1500  rst_RETXdata_chksum <= TCP_lastword and TCP_din_valid;
1501  end if;
1502  DDR2TCPdata <= TCP_lastword & TCP_din;
1503  if(FIFO_en = '1' and TCP_din_valid = '1' and TCP_din_type = "000")then
1504  RETX_ddr_data_we(0) <= '1';
1505  else
1506  RETX_ddr_data_we(0) <= '0';
1507  end if;
1508  if(FIFO_en = '1' and TCP_din_valid = '1' and TCP_din_type = "001")then
1509  RETX_ddr_data_we(1) <= '1';
1510  else
1511  RETX_ddr_data_we(1) <= '0';
1512  end if;
1513  if(FIFO_en = '1' and TCP_din_valid = '1' and TCP_din_type = "010")then
1514  RETX_ddr_data_we(2) <= '1';
1515  else
1516  RETX_ddr_data_we(2) <= '0';
1517  end if;
1518  rst_odd <= TCP_lastword and TCP_din_valid;
1519  if(ClientClk2XresetSyncRegs(2) = '1' or rst_odd = '1')then
1520  odd <= '0';
1521  elsif(TCP_din_valid = '1')then
1522  odd <= not odd;
1523  end if;
1524  if(TCP_din_valid = '1' and TCP_din_type = "100")then
1525  RETXdata_we(0) <= odd & not odd;
1526  else
1527  RETXdata_we(0) <= "00";
1528  end if;
1529  if(TCP_din_valid = '1' and TCP_din_type = "101")then
1530  RETXdata_we(1) <= odd & not odd;
1531  else
1532  RETXdata_we(1) <= "00";
1533  end if;
1534  if(TCP_din_valid = '1' and TCP_din_type = "110")then
1535  RETXdata_we(2) <= odd & not odd;
1536  else
1537  RETXdata_we(2) <= "00";
1538  end if;
1539  if(RETX_ddr_rp_rst = '1')then
1540  RETX_ddr_rp_di <= (others => '0');
1541  RETX_ddr_rp_we <= '1';
1542  else
1543  RETX_ddr_rp_di(16 downto 0) <= RETX_ddr_rp_do(16 downto 0) + TCP_length_i(20 downto 4);
1544  RETX_ddr_rp_we <= TCP_rack and not TCP_raddr_i(28);
1545  end if;
1546  if(ClientClk2XresetSyncRegs(2) = '1')then
1547  ReTx_ddr_LEN_max <= (others => "10000");
1548  elsif(RETX_ddr_rp_we = '1')then
1549  if(and_reduce(RETX_ddr_rp_di(8 downto 4)) = '0')then -- ReTx_ddr_LEN_max insures the readout does not go into event data area
1550  ReTx_ddr_LEN_max(conv_integer(RETX_ddr_rp_a)) <= "10000";
1551  else
1552  ReTx_ddr_LEN_max(conv_integer(RETX_ddr_rp_a)) <= "10000" - ('0' & RETX_ddr_rp_di(3 downto 0));
1553  end if;
1554  end if;
1555  if(ClientClk2XresetSyncRegs(2) = '1')then
1556  RETX_ddr_rp_rst <= '1';
1557  RETX_ddr_rp_a <= (others => '0');
1558  TCP_rrqst_i <= "000";
1559  rrqstMask <= (others => '1');
1560  else
1561  if(RETX_ddr_rp_a(1) = '1')then
1562  RETX_ddr_rp_rst <= '0';
1563  end if;
1564  if(RETX_ddr_rp_rst = '1')then
1565  RETX_ddr_rp_a(1 downto 0) <= RETX_ddr_rp_a(1 downto 0) + 1;
1566  elsif(TCP_rrqst_i(0) = '0')then
1567  if(or_reduce(rrqstMask(5 downto 3) and RETXdataRqst) = '1')then
1568  RETX_ddr_rp_a(1 downto 0) <= "11";
1569  elsif(rrqstMask(0) = '1' and RETX_ddr_rrqst(0) = '1')then
1570  RETX_ddr_rp_a(1 downto 0) <= "00";
1571  elsif(rrqstMask(1) = '1' and RETX_ddr_rrqst(1) = '1')then
1572  RETX_ddr_rp_a(1 downto 0) <= "01";
1573  else
1574  RETX_ddr_rp_a(1 downto 0) <= "10";
1575  end if;
1576  end if;
1577  if(TCP_rack = '1')then
1578  TCP_rrqst_i <= "000";
1579  else
1580  if(or_reduce(rrqstMask(2 downto 0) and RETX_ddr_rrqst) = '1' or or_reduce(rrqstMask(5 downto 3) and RETXdataRqst) = '1')then
1581  TCP_rrqst_i(0) <= '1';
1582  end if;
1583  TCP_rrqst_i(2 downto 1) <= TCP_rrqst_i(1 downto 0);
1584  end if;
1585  for i in 0 to 2 loop
1586  if(TCP_rrqst_i(0) = '1' and TCP_raddr_i(28) = '0' and i = conv_integer(TCP_raddr_i(27 downto 26)))then
1587  rrqstMask(i) <= '0';
1588  elsif(rst_RETXdata_chksum = '1' and TCP_din_type(2) = '0' and i = conv_integer(TCP_din_type(1 downto 0)))then
1589  rrqstMask(i) <= '1';
1590  end if;
1591  if(TCP_rrqst_i(0) = '1' and TCP_raddr_i(28) = '1' and i = conv_integer(TCP_raddr_i(27 downto 26)))then
1592  rrqstMask(i+3) <= '0';
1593  elsif(rst_RETXdata_chksum = '1' and TCP_din_type(2) = '1' and i = conv_integer(TCP_din_type(1 downto 0)))then
1594  rrqstMask(i+3) <= '1';
1595  end if;
1596  end loop;
1597  end if;
1598  if(TCP_rrqst_i(0) = '0')then
1599  RETXdataAck <= (others => '0');
1600  elsif(TCP_raddr_i(28) = '1')then
1601  case TCP_raddr_i(27 downto 26) is
1602  when "00" => RETXdataAck <= "001";
1603  when "01" => RETXdataAck <= "010";
1604  when "10" => RETXdataAck <= "100";
1605  when others => RETXdataAck <= "000";
1606  end case;
1607  end if;
1608  if(TCP_rrqst_i(0) = '0')then
1609  if(or_reduce(rrqstMask(5 downto 3) and RETXdataRqst) = '1')then
1610  TCP_raddr_i(28) <= '1';
1611  if(rrqstMask(3) = '1' and RETXdataRqst(0) = '1')then
1612  TCP_raddr_i(27 downto 26) <= "00";
1613  elsif(rrqstMask(4) = '1' and RETXdataRqst(1) = '1')then
1614  TCP_raddr_i(27 downto 26) <= "01";
1615  else
1616  TCP_raddr_i(27 downto 26) <= "10";
1617  end if;
1618  else
1619  TCP_raddr_i(28) <= '0';
1620  if(rrqstMask(0) = '1' and RETX_ddr_rrqst(0) = '1')then
1621  TCP_raddr_i(27 downto 26) <= "00";
1622  elsif(rrqstMask(1) = '1' and RETX_ddr_rrqst(1) = '1')then
1623  TCP_raddr_i(27 downto 26) <= "01";
1624  else
1625  TCP_raddr_i(27 downto 26) <= "10";
1626  end if;
1627  end if;
1628  end if;
1629  case TCP_raddr_i(28 downto 26) is
1630  when "100" => TCP_raddr_i(25 downto 0) <= RETXdataAddr(0);
1631  when "101" => TCP_raddr_i(25 downto 0) <= RETXdataAddr(1);
1632  when "110" => TCP_raddr_i(25 downto 0) <= RETXdataAddr(2);
1633  when others => TCP_raddr_i(25 downto 0) <= TCP_raddr_i(27 downto 26)(1 downto 0) & RETX_ddr_rp_do(16 downto 9) & x"f" & RETX_ddr_rp_do(8 downto 0) & "000";
1634  end case;
1635  TCP_rlength <= TCP_length_i(11 downto 1) - 1;
1636  case TCP_raddr_i(28 downto 26) is
1637  when "000" => TCP_length_i(11 downto 0) <= "000" & RETX_ddr_LEN(0) & x"0";
1638  when "001" => TCP_length_i(11 downto 0) <= "000" & RETX_ddr_LEN(1) & x"0";
1639  when "010" => TCP_length_i(11 downto 0) <= "000" & RETX_ddr_LEN(2) & x"0";
1640  when "100" => TCP_length_i(11 downto 0) <= RETXdataLEN(0) & '0';
1641  when "101" => TCP_length_i(11 downto 0) <= RETXdataLEN(1) & '0';
1642  when "110" => TCP_length_i(11 downto 0) <= RETXdataLEN(2) & '0';
1643  when others => TCP_length_i(11 downto 0) <= x"000";
1644  end case;
1645  end if;
1646 end process;
1647 g_RETX_ddr_rp : for i in 0 to 2 generate
1648  i_RETX_ddr_rp : RAM32x6Db PORT MAP(
1649  wclk => ClientClk2X ,
1650  di => RETX_ddr_rp_di(i*6+5 downto i*6),
1651  we => RETX_ddr_rp_we,
1652  wa => RETX_ddr_rp_a,
1653  ra => RETX_ddr_rp_a,
1654  do => RETX_ddr_rp_do(i*6+5 downto i*6)
1655  );
1656 end generate;
1657 TCP_we <= TCP_wFIFO_we;
1658 i_TCP_wFIFO_we : SRL16E
1659  port map (
1660  Q => TCP_wFIFO_we, -- SRL data output
1661  A0 => '0', -- Select[0] input
1662  A1 => '1', -- Select[1] input
1663  A2 => '0', -- Select[2] input
1664  A3 => '0', -- Select[3] input
1665  CE => '1', -- Clock enable input
1666  CLK => ClientClk2X, -- Clock input
1667  D => TCP_w_busy -- SRL data input
1668  );
1669 TCP_channel <= TCP_wFIFO_DI(33 downto 32);
1670 TCP_dout <= TCP_wFIFO_DI(31 downto 0);
1671 process(ClientClk2X, TCP_w_sel, RETX_ddr_wrqst)
1672 variable s : std_logic_vector(4 downto 0);
1673 begin
1674  s := TCP_w_sel & RETX_ddr_wrqst;
1675  if(ClientClk2X'event and ClientClk2X = '1')then
1676  if(FIFO_en = '0' or ClientClk2XresetSyncRegs(2) = '1')then
1677  TCP_w_sel <= "00";
1678  elsif(TCP_w_busy = '0')then
1679  case s is
1680  when "00001" | "01001" | "01011" | "10001" | "10011" | "10101" | "10111" =>
1681  TCP_w_sel <= "00";
1682  when "00010" | "00011" | "00110" | "00111" | "01010" | "10010" | "10110" =>
1683  TCP_w_sel <= "01";
1684  when "00100" | "00101" | "01100" | "01101" | "01110" | "01111" | "10100" =>
1685  TCP_w_sel <= "10";
1686  when others => null;
1687  end case;
1688  end if;
1689  if(FIFO_en = '0' or ClientClk2XresetSyncRegs(2) = '1')then
1690  TCP_w_busy <= '0';
1691  elsif(TCP_w_wc = x"f")then
1692  TCP_w_busy <= '0';
1693  elsif(RETX_ddr_wrqst /= "000")then
1694  TCP_w_busy <= '1';
1695  end if;
1696  if(ClientClk2XresetSyncRegs(2) = '1')then
1697  TCP_w_wc <= x"0";
1698  elsif(TCP_w_busy = '1')then
1699  TCP_w_wc <= TCP_w_wc + 1;
1700  end if;
1701  if(FIFO_en = '0' or ClientClk2XresetSyncRegs(2) = '1')then
1702  re_RETX_ddr_wq <= "000";
1703  else
1704  case TCP_w_sel is
1705  when "00" => re_RETX_ddr_wq(0) <= TCP_w_busy;
1706  when "01" => re_RETX_ddr_wq(1) <= TCP_w_busy;
1707  when others => re_RETX_ddr_wq(2) <= TCP_w_busy;
1708  end case;
1709  end if;
1710  case TCP_w_sel is
1711  when "00" => TCP_wFIFO_DI <= "00" & RETX_ddr_out(0);
1712  when "01" => TCP_wFIFO_DI <= "01" & RETX_ddr_out(1);
1713  when others => TCP_wFIFO_DI <= "10" & RETX_ddr_out(2);
1714  end case;
1715  end if;
1716 end process;
1717 process(ClientClk2X)
1718 begin
1719  if(ClientClk2X'event and ClientClk2X = '1')then
1720  case EnSFP(2 downto 0) is
1721  when "010" | "011" | "101" | "111" => TCPIP2SFP_sel(0) <= "01";
1722  when "100" | "110" => TCPIP2SFP_sel(0) <= "10";
1723  when others => TCPIP2SFP_sel(0) <= "00";
1724  end case;
1725  case EnSFP(2 downto 0) is
1726  when "010" | "011" | "111" => TCPIP2SFP_sel(1) <= "00";
1727  when "101" => TCPIP2SFP_sel(1) <= "10";
1728  when others => TCPIP2SFP_sel(1) <= "01";
1729  end case;
1730  case EnSFP(2 downto 0) is
1731  when "100" | "101" | "110" => TCPIP2SFP_sel(2) <= "00";
1732  when others => TCPIP2SFP_sel(2) <= "10";
1733  end case;
1734  for i in 0 to 1 loop
1735  SFP_EmacPhyTxc(i) <= EmacPhyTxc(conv_integer(TCPIP2SFP_sel(i)));
1736  SFP_EmacPhyTxD(i) <= EmacPhyTxD(conv_integer(TCPIP2SFP_sel(i)));
1737  SFP_down_i(i) <= LINK_down(conv_integer(TCPIP2SFP_sel(i)));
1738  end loop;
1739  if(TCPIP2SFP_sel(2)(1) = '0')then
1740  SFP_EmacPhyTxc(2) <= EmacPhyTxc(0);
1741  SFP_EmacPhyTxD(2) <= EmacPhyTxD(0);
1742  SFP_down_i(2) <= LINK_down(0);
1743  else
1744  SFP_EmacPhyTxc(2) <= EmacPhyTxc(2);
1745  SFP_EmacPhyTxD(2) <= EmacPhyTxD(2);
1746  SFP_down_i(2) <= LINK_down(2);
1747  end if;
1748  case EnSFP(2 downto 0) is
1749  when "010" | "011" | "111" => SFP2TCPIP(0) <= "01";
1750  when "100" | "101" | "110" => SFP2TCPIP(0) <= "10";
1751  when others => SFP2TCPIP(0) <= "00";
1752  end case;
1753  case EnSFP(2 downto 0) is
1754  when "010" | "011" | "101" | "111" => SFP2TCPIP(1) <= "00";
1755  when others => SFP2TCPIP(1) <= "01";
1756  end case;
1757  case EnSFP(2 downto 0) is
1758  when "100" | "110" => SFP2TCPIP(2) <= "00";
1759  when "101" => SFP2TCPIP(2) <= "01";
1760  when others => SFP2TCPIP(2) <= "10";
1761  end case;
1762  PhyEmacRxc(0) <= SFP_PhyEmacRxc(conv_integer(SFP2TCPIP(0)));
1763  PhyEmacRxD(0) <= SFP_PhyEmacRxD(conv_integer(SFP2TCPIP(0)));
1764  if(SFP2TCPIP(1)(0) = '0')then
1765  PhyEmacRxc(1) <= SFP_PhyEmacRxc(0);
1766  PhyEmacRxD(1) <= SFP_PhyEmacRxD(0);
1767  else
1768  PhyEmacRxc(1) <= SFP_PhyEmacRxc(1);
1769  PhyEmacRxD(1) <= SFP_PhyEmacRxD(1);
1770  end if;
1771  PhyEmacRxc(2) <= SFP_PhyEmacRxc(conv_integer(SFP2TCPIP(2)));
1772  PhyEmacRxD(2) <= SFP_PhyEmacRxD(conv_integer(SFP2TCPIP(2)));
1773  IPADDR(0) <= SFP_IPADDR(conv_integer(SFP2TCPIP(0)));
1774  IPADDR(1) <= SFP_IPADDR(conv_integer(SFP2TCPIP(1)));
1775  IPADDR(2) <= SFP_IPADDR(conv_integer(SFP2TCPIP(2)));
1776  MACADDR(0) <= x"00ac1234568" & "10" & SFP2TCPIP(0);
1777  MACADDR(1) <= x"00ac1234568" & "100" & SFP2TCPIP(1)(0);
1778  MACADDR(2) <= x"00ac1234568" & "10" & SFP2TCPIP(2);
1779  reset_TCPIP(0) <= SFPresetSyncRegs(conv_integer(SFP2TCPIP(0)))(2);
1780  if(SFP2TCPIP(1)(0) = '0')then
1781  reset_TCPIP(1) <= SFPresetSyncRegs(conv_integer(SFP2TCPIP(0)))(2);
1782  else
1783  reset_TCPIP(1) <= SFPresetSyncRegs(conv_integer(SFP2TCPIP(1)))(2);
1784  end if;
1785  reset_TCPIP(2) <= SFPresetSyncRegs(conv_integer(SFP2TCPIP(2)))(2);
1786  end if;
1787 end process;
1788 g_XGbEPCS : for i in 0 to 2 generate
1789  i_XGbEPCS: XGbEPCS32 PORT MAP (
1790  reset => TCPresetSyncRegs (2),
1791  clk2x => ClientClk2X,
1792  clk => ClientClk ,
1793  TXUSRCLK => txusrclk,
1794  TX_high => TX_high,
1795  RXUSRCLK => SFP_RXUSRCLK(i),
1796  RXRESETDONE => SFP_RXRESETDONE (i),
1797  inh_TX => inh_TX(i),
1798  RESET_TXSync => reset_TXSyncRegs (2),
1799  GTX_RXGEARBOXSLIP_OUT => SFP_RXGEARBOXSLIP (i),
1800  GTX_TXD => SFP_TXD(i),
1801  GTX_TXHEADER => SFP_TXHEADER (i),
1802  GTX_TX_PAUSE => GTX_TX_PAUSE ,
1803  GTX_RXD => SFP_RXD(i),
1804  GTX_RXDVLD => SFP_RXDVLD(i),
1805  GTX_RXHEADER => SFP_RXHEADER (i),
1806  GTX_RXHEADERVLD => SFP_RXHEADERVLD (i),
1807  GTX_RXGOOD => SFP_RXGOOD(i),
1808  EmacPhyTxC => SFP_EmacPhyTxc(i),
1809  EmacPhyTxD => SFP_EmacPhyTxd(i),
1810  PhyEmacRxC => SFP_PhyEmacRxC(i),
1811  PhyEmacRxD => SFP_PhyEmacRxD(i)
1812  );
1813 end generate;
1814 SFP_pd(0) <= "00" when Dis_pd = '1' else "11" when enSFP(3) = '1' or enSFP(0) = '0' else "00";
1815 SFP_pd(1) <= "00" when Dis_pd = '1' else "11" when enSFP(3) = '1' or enSFP(1) = '0' else "00";
1816 SFP_pd(2) <= "00" when Dis_pd = '1' else "11" when enSFP(3) = '1' or enSFP(2) = '0' else "00";
1817 SFP_gttxreset <= "111" when TCPreset = '1' else "000";
1818 SFP_gtrxreset <= "111" when TCPreset = '1' else "000";
1819 i_SFP3_init : SFP3_v2_7_init
1820  port map
1821  (
1822  SYSCLK_IN => DRPclk,
1823  SOFT_RESET_IN => '0',
1824  DONT_RESET_ON_DATA_ERROR_IN => '0',
1825  GT0_TX_FSM_RESET_DONE_OUT => SFP_TX_FSM_RESET_DONE (0),
1826  GT0_RX_FSM_RESET_DONE_OUT => SFP_RX_FSM_RESET_DONE (0),
1827  GT0_DATA_VALID_IN => SFP_RXGOOD(0),
1828  GT1_TX_FSM_RESET_DONE_OUT => SFP_TX_FSM_RESET_DONE (1),
1829  GT1_RX_FSM_RESET_DONE_OUT => SFP_RX_FSM_RESET_DONE (1),
1830  GT1_DATA_VALID_IN => SFP_RXGOOD(1),
1831  GT2_TX_FSM_RESET_DONE_OUT => SFP_TX_FSM_RESET_DONE (2),
1832  GT2_RX_FSM_RESET_DONE_OUT => SFP_RX_FSM_RESET_DONE (2),
1833  GT2_DATA_VALID_IN => SFP_RXGOOD(2),
1834 
1835 
1836 
1837 
1838 
1839  --_____________________________________________________________________
1840  --_____________________________________________________________________
1841  --GT0 (X1Y12)
1842 
1843  ---------------------------- Channel - DRP Ports --------------------------
1844  GT0_DRPADDR_IN => SFP_drpaddr(0),
1845  GT0_DRPCLK_IN => DRPclk,
1846  GT0_DRPDI_IN => SFP_drpdi(0),
1847  GT0_DRPDO_OUT => SFP_drpdo(0),
1848  GT0_DRPEN_IN => SFP_drpen(0),
1849  GT0_DRPRDY_OUT => SFP_drprdy(0),
1850  GT0_DRPWE_IN => SFP_drpwe(0),
1851  ------------------------------- Loopback Ports -----------------------------
1852  GT0_LOOPBACK_IN => SFP_LOOPBACK_IN (0),
1853  ------------------------------ Power-Down Ports ----------------------------
1854  GT0_RXPD_IN => SFP_pd(0),
1855  GT0_TXPD_IN => SFP_pd(0),
1856  --------------------- RX Initialization and Reset Ports --------------------
1857  GT0_RXUSERRDY_IN => SFP_rxuserrdy(0),
1858  -------------------------- RX Margin Analysis Ports ------------------------
1859  GT0_EYESCANDATAERROR_OUT => SFP_EYESCANDATAERROR_OUT (0),
1860  ------------------------- Receive Ports - CDR Ports ------------------------
1861  GT0_RXCDRLOCK_OUT => open,
1862  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1863  GT0_RXUSRCLK_IN => SFP_RXUSRCLK(0),
1864  GT0_RXUSRCLK2_IN => SFP_RXUSRCLK(0),
1865  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1866  GT0_RXDATA_OUT => SFP_RXD_inv(0),
1867  ------------------- Receive Ports - Pattern Checker Ports ------------------
1868  GT0_RXPRBSERR_OUT => SFP_RXPRBSERR_OUT (0),
1869  GT0_RXPRBSSEL_IN => SFP_RXPRBSSEL_IN (0),
1870  ------------------- Receive Ports - Pattern Checker ports ------------------
1871  GT0_RXPRBSCNTRESET_IN => '0',
1872  --------------------------- Receive Ports - RX AFE -------------------------
1873  GT0_GTXRXP_IN => SFP0_RXP,
1874  ------------------------ Receive Ports - RX AFE Ports ----------------------
1875  GT0_GTXRXN_IN => SFP0_RXN,
1876  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1877  GT0_RXBUFRESET_IN => '0',
1878  GT0_RXBUFSTATUS_OUT => open,
1879  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1880  GT0_RXOUTCLK_OUT => SFP_rxoutclk(0),
1881  ---------------------- Receive Ports - RX Gearbox Ports --------------------
1882  GT0_RXDATAVALID_OUT => SFP_RXDVLD(0),
1883  GT0_RXHEADER_OUT => SFP_RXHEADER(0),
1884  GT0_RXHEADERVALID_OUT => SFP_RXHEADERVLD(0),
1885  --------------------- Receive Ports - RX Gearbox Ports --------------------
1886  GT0_RXGEARBOXSLIP_IN => SFP_RXGEARBOXSLIP (0),
1887  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1888  GT0_GTRXRESET_IN => SFP_gtrxreset(0),
1889  GT0_RXPMARESET_IN => '0',
1890  ------------------ Receive Ports - RX Margin Analysis ports ----------------
1891  GT0_RXLPMEN_IN => '0',
1892  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1893  GT0_RXRESETDONE_OUT => SFP_rxresetdone(0),
1894  --------------------- TX Initialization and Reset Ports --------------------
1895  GT0_GTTXRESET_IN => SFP_gttxreset(0),
1896  GT0_TXUSERRDY_IN => SFP_txuserrdy(0),
1897  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1898  GT0_TXUSRCLK_IN => txusrclk,
1899  GT0_TXUSRCLK2_IN => txusrclk,
1900  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1901  GT0_TXDIFFCTRL_IN => "1110",
1902  GT0_TXINHIBIT_IN => '0',
1903  GT0_TXMAINCURSOR_IN => (others => '0'),
1904  ------------------ Transmit Ports - TX Data Path interface -----------------
1905  GT0_TXDATA_IN => SFP_TXD_inv(0),
1906  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1907  GT0_GTXTXN_OUT => SFP0_TXN,
1908  GT0_GTXTXP_OUT => SFP0_TXP,
1909  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1910  GT0_TXOUTCLK_OUT => SFP_TXOUTCLK(0),
1911  GT0_TXOUTCLKFABRIC_OUT => open,
1912  GT0_TXOUTCLKPCS_OUT => open,
1913  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1914  GT0_TXHEADER_IN => SFP_TXHEADER(0),
1915  GT0_TXSEQUENCE_IN => SFP_TXSEQUENCE(0),
1916  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1917  GT0_TXRESETDONE_OUT => SFP_txresetdone(0),
1918  ------------------ Transmit Ports - pattern Generator Ports ----------------
1919  GT0_TXPRBSSEL_IN => SFP_TXPRBSSEL_IN (0),
1920 
1921 
1922 
1923 
1924 
1925 
1926  --_____________________________________________________________________
1927  --_____________________________________________________________________
1928  --GT1 (X1Y13)
1929 
1930  ---------------------------- Channel - DRP Ports --------------------------
1931  GT1_DRPADDR_IN => SFP_drpaddr(1),
1932  GT1_DRPCLK_IN => DRPclk,
1933  GT1_DRPDI_IN => SFP_drpdi(1),
1934  GT1_DRPDO_OUT => SFP_drpdo(1),
1935  GT1_DRPEN_IN => SFP_drpen(1),
1936  GT1_DRPRDY_OUT => SFP_drprdy(1),
1937  GT1_DRPWE_IN => SFP_drpwe(1),
1938  ------------------------------- Loopback Ports -----------------------------
1939  GT1_LOOPBACK_IN => SFP_LOOPBACK_IN (1),
1940  ------------------------------ Power-Down Ports ----------------------------
1941  GT1_RXPD_IN => SFP_pd(1),
1942  GT1_TXPD_IN => SFP_pd(1),
1943  --------------------- RX Initialization and Reset Ports --------------------
1944  GT1_RXUSERRDY_IN => SFP_rxuserrdy(1),
1945  -------------------------- RX Margin Analysis Ports ------------------------
1946  GT1_EYESCANDATAERROR_OUT => SFP_EYESCANDATAERROR_OUT (1),
1947  ------------------------- Receive Ports - CDR Ports ------------------------
1948  GT1_RXCDRLOCK_OUT => open,
1949  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1950  GT1_RXUSRCLK_IN => SFP_RXUSRCLK(1),
1951  GT1_RXUSRCLK2_IN => SFP_RXUSRCLK(1),
1952  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1953  GT1_RXDATA_OUT => SFP_RXD_inv(1),
1954  ------------------- Receive Ports - Pattern Checker Ports ------------------
1955  GT1_RXPRBSERR_OUT => SFP_RXPRBSERR_OUT (1),
1956  GT1_RXPRBSSEL_IN => SFP_RXPRBSSEL_IN (1),
1957  ------------------- Receive Ports - Pattern Checker ports ------------------
1958  GT1_RXPRBSCNTRESET_IN => '0',
1959  --------------------------- Receive Ports - RX AFE -------------------------
1960  GT1_GTXRXP_IN => SFP1_RXP,
1961  ------------------------ Receive Ports - RX AFE Ports ----------------------
1962  GT1_GTXRXN_IN => SFP1_RXN,
1963  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1964  GT1_RXBUFRESET_IN => '0',
1965  GT1_RXBUFSTATUS_OUT => open,
1966  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1967  GT1_RXOUTCLK_OUT => SFP_rxoutclk(1),
1968  ---------------------- Receive Ports - RX Gearbox Ports --------------------
1969  GT1_RXDATAVALID_OUT => SFP_RXDVLD(1),
1970  GT1_RXHEADER_OUT => SFP_RXHEADER(1),
1971  GT1_RXHEADERVALID_OUT => SFP_RXHEADERVLD(1),
1972  --------------------- Receive Ports - RX Gearbox Ports --------------------
1973  GT1_RXGEARBOXSLIP_IN => SFP_RXGEARBOXSLIP (1),
1974  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1975  GT1_GTRXRESET_IN => SFP_gtrxreset(1),
1976  GT1_RXPMARESET_IN => '0',
1977  ------------------ Receive Ports - RX Margin Analysis ports ----------------
1978  GT1_RXLPMEN_IN => '0',
1979  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1980  GT1_RXRESETDONE_OUT => SFP_rxresetdone(1),
1981  --------------------- TX Initialization and Reset Ports --------------------
1982  GT1_GTTXRESET_IN => SFP_gttxreset(1),
1983  GT1_TXUSERRDY_IN => SFP_txuserrdy(1),
1984  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1985  GT1_TXUSRCLK_IN => txusrclk,
1986  GT1_TXUSRCLK2_IN => txusrclk,
1987  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1988  GT1_TXDIFFCTRL_IN => "1110",
1989  GT1_TXINHIBIT_IN => '0',
1990  GT1_TXMAINCURSOR_IN => (others => '0'),
1991  ------------------ Transmit Ports - TX Data Path interface -----------------
1992  GT1_TXDATA_IN => SFP_TXD_inv(1),
1993  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1994  GT1_GTXTXN_OUT => SFP1_TXN,
1995  GT1_GTXTXP_OUT => SFP1_TXP,
1996  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1997  GT1_TXOUTCLK_OUT => open,
1998  GT1_TXOUTCLKFABRIC_OUT => open,
1999  GT1_TXOUTCLKPCS_OUT => open,
2000  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2001  GT1_TXHEADER_IN => SFP_TXHEADER(1),
2002  GT1_TXSEQUENCE_IN => SFP_TXSEQUENCE(1),
2003  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2004  GT1_TXRESETDONE_OUT => SFP_txresetdone(1),
2005  ------------------ Transmit Ports - pattern Generator Ports ----------------
2006  GT1_TXPRBSSEL_IN => SFP_TXPRBSSEL_IN (1),
2007 
2008 
2009  --_____________________________________________________________________
2010  --_____________________________________________________________________
2011  --GT2 (X1Y14)
2012 
2013  ---------------------------- Channel - DRP Ports --------------------------
2014  GT2_DRPADDR_IN => SFP_drpaddr(2),
2015  GT2_DRPCLK_IN => DRPclk,
2016  GT2_DRPDI_IN => SFP_drpdi(2),
2017  GT2_DRPDO_OUT => SFP_drpdo(2),
2018  GT2_DRPEN_IN => SFP_drpen(2),
2019  GT2_DRPRDY_OUT => SFP_drprdy(2),
2020  GT2_DRPWE_IN => SFP_drpwe(2),
2021  ------------------------------- Loopback Ports -----------------------------
2022  GT2_LOOPBACK_IN => SFP_LOOPBACK_IN (2),
2023  ------------------------------ Power-Down Ports ----------------------------
2024  GT2_RXPD_IN => SFP_pd(2),
2025  GT2_TXPD_IN => SFP_pd(2),
2026  --------------------- RX Initialization and Reset Ports --------------------
2027  GT2_RXUSERRDY_IN => SFP_rxuserrdy(2),
2028  -------------------------- RX Margin Analysis Ports ------------------------
2029  GT2_EYESCANDATAERROR_OUT => SFP_EYESCANDATAERROR_OUT (2),
2030  ------------------------- Receive Ports - CDR Ports ------------------------
2031  GT2_RXCDRLOCK_OUT => open,
2032  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2033  GT2_RXUSRCLK_IN => SFP_RXUSRCLK(2),
2034  GT2_RXUSRCLK2_IN => SFP_RXUSRCLK(2),
2035  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2036  GT2_RXDATA_OUT => SFP_RXD_inv(2),
2037  ------------------- Receive Ports - Pattern Checker Ports ------------------
2038  GT2_RXPRBSERR_OUT => SFP_RXPRBSERR_OUT (2),
2039  GT2_RXPRBSSEL_IN => SFP_RXPRBSSEL_IN (2),
2040  ------------------- Receive Ports - Pattern Checker ports ------------------
2041  GT2_RXPRBSCNTRESET_IN => '0',
2042  --------------------------- Receive Ports - RX AFE -------------------------
2043  GT2_GTXRXP_IN => SFP2_RXP,
2044  ------------------------ Receive Ports - RX AFE Ports ----------------------
2045  GT2_GTXRXN_IN => SFP2_RXN,
2046  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
2047  GT2_RXBUFRESET_IN => '0',
2048  GT2_RXBUFSTATUS_OUT => open,
2049  --------------- Receive Ports - RX Fabric Output Control Ports -------------
2050  GT2_RXOUTCLK_OUT => SFP_rxoutclk(2),
2051  ---------------------- Receive Ports - RX Gearbox Ports --------------------
2052  GT2_RXDATAVALID_OUT => SFP_RXDVLD(2),
2053  GT2_RXHEADER_OUT => SFP_RXHEADER(2),
2054  GT2_RXHEADERVALID_OUT => SFP_RXHEADERVLD(2),
2055  --------------------- Receive Ports - RX Gearbox Ports --------------------
2056  GT2_RXGEARBOXSLIP_IN => SFP_RXGEARBOXSLIP (2),
2057  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2058  GT2_GTRXRESET_IN => SFP_gtrxreset(2),
2059  GT2_RXPMARESET_IN => '0',
2060  ------------------ Receive Ports - RX Margin Analysis ports ----------------
2061  GT2_RXLPMEN_IN => '0',
2062  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2063  GT2_RXRESETDONE_OUT => SFP_rxresetdone(2),
2064  --------------------- TX Initialization and Reset Ports --------------------
2065  GT2_GTTXRESET_IN => SFP_gttxreset(2),
2066  GT2_TXUSERRDY_IN => SFP_txuserrdy(2),
2067  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2068  GT2_TXUSRCLK_IN => txusrclk,
2069  GT2_TXUSRCLK2_IN => txusrclk,
2070  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2071  GT2_TXDIFFCTRL_IN => "1110",
2072  GT2_TXINHIBIT_IN => '0',
2073  GT2_TXMAINCURSOR_IN => (others => '0'),
2074  ------------------ Transmit Ports - TX Data Path interface -----------------
2075  GT2_TXDATA_IN => SFP_TXD_inv(2),
2076  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2077  GT2_GTXTXN_OUT => SFP2_TXN,
2078  GT2_GTXTXP_OUT => SFP2_TXP,
2079  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2080  GT2_TXOUTCLK_OUT => open,
2081  GT2_TXOUTCLKFABRIC_OUT => open,
2082  GT2_TXOUTCLKPCS_OUT => open,
2083  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2084  GT2_TXHEADER_IN => SFP_TXHEADER(2),
2085  GT2_TXSEQUENCE_IN => SFP_TXSEQUENCE(2),
2086  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2087  GT2_TXRESETDONE_OUT => SFP_txresetdone(2),
2088  ------------------ Transmit Ports - pattern Generator Ports ----------------
2089  GT2_TXPRBSSEL_IN => SFP_TXPRBSSEL_IN (2),
2090 
2091 
2092  --____________________________COMMON PORTS________________________________
2093  ---------------------- Common Block - Ref Clock Ports ---------------------
2094  GT0_GTREFCLK0_COMMON_IN => REFCLK,
2095  ------------------------- Common Block - QPLL Ports ------------------------
2096  GT0_QPLLLOCK_OUT => qplllock,
2097  GT0_QPLLLOCKDETCLK_IN => DRPclk,
2098  GT0_QPLLRESET_IN => qpllreset
2099 
2100  );
2101 process(SFP_TXD,SFP_RXD,SFP_RXD_inv)
2102  begin
2103  for j in 0 to 2 loop
2104  for i in 0 to 31 loop
2105  SFP_TXD_inv(j)(i) <= SFP_TXD(j)(31-i);
2106  SFP_RXD(j)(i) <= SFP_RXD_inv(j)(31-i);
2107  end loop;
2108  end loop;
2109 end process;
2110 i_REFCLK : IBUFDS_GTE2 port map(O => REFCLK, ODIV2 => open, CEB => '0', I => SFP_REFCLK_P, IB => SFP_REFCLK_N);
2111 i_txusrclk : BUFG port map (I => SFP_TXOUTCLK(0), O => txusrclk);
2112 g_SFP_rxusrclk : for i in 0 to 2 generate
2113  i_SFP_rxusrclk : BUFG port map (I => SFP_RXOUTCLK(i), O => SFP_rxusrclk(i));
2114 end generate;
2115 i_REFCLK2X_in: bufg port map(i => REFCLK, o => REFCLK2X_in);
2116 i_ClientClk2X : BUFG port map (I => ClientClk2X_dcm, O => ClientClk2X);
2117 i_ClientClk : BUFG port map (I => ClientClk_dcm, O => ClientClk);
2118 i_REFCLK2XPLLRST : SRL16 generic map(INIT => x"ffff" )
2119  port map (
2120  Q => REFCLK2XPLLRST, -- SRL data output
2121  A0 => '1', -- Select[0] input
2122  A1 => '1', -- Select[1] input
2123  A2 => '1', -- Select[2] input
2124  A3 => '1', -- Select[3] input
2125  CLK => REFCLK2X_in, -- Clock input
2126  D => '0' -- SRL data input
2127  );
2128 i_REFCLK2XPLL : PLLE2_BASE
2129  generic map (
2130  BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
2131  CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
2132  CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
2133  CLKIN1_PERIOD => 6.4, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
2134  -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
2135  CLKOUT0_DIVIDE => 4,
2136  DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
2137  REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
2138  STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
2139  )
2140  port map (
2141  -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
2142  CLKOUT0 => ClientClk2X_dcm ,
2143  -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
2144  CLKFBOUT => ClientClk_dcm, -- 1-bit output: Feedback clock
2145  -- Status Port: 1-bit (each) output: PLL status ports
2146  LOCKED => ClientClk_lock, -- 1-bit output: LOCK
2147  -- Clock Input: 1-bit (each) input: Clock input
2148  CLKIN1 => REFCLK2X_in, -- 1-bit input: Input clock
2149  -- Control Ports: 1-bit (each) input: PLL control ports
2150  PWRDWN => '0', -- 1-bit input: Power-down
2151  RST => REFCLK2XPLLRST, -- 1-bit input: Reset
2152  -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
2153  CLKFBIN => ClientClk -- 1-bit input: Feedback clock
2154  );
2155 process(ipb_clk)
2156 begin
2157  if(ipb_clk'event and ipb_clk = '1')then
2158  if(ipb_addr(15 downto 0) = x"1c20" and ipb_write = '1' and ipb_strobe = '1')then
2159  en_stop <= ipb_wdata(4 downto 0);
2160  end if;
2161  end if;
2162 end process;
2163 process(ipb_addr)
2164 variable s : std_logic_vector(1 downto 0);
2165 begin
2166  case ipb_addr(11 downto 10) is
2167  when "00" =>
2168  case enSFP(2 downto 0) is
2169  when "010" | "011" | "101" | "111" => s := "01";
2170  when "110" => s := "10";
2171  when others => s := "00";
2172  end case;
2173  when "01" =>
2174  case enSFP(2 downto 0) is
2175  when "010" | "011" | "111" => s := "00";
2176  when "101" => s := "10";
2177  when others => s := "01";
2178  end case;
2179  when "10" =>
2180  case enSFP(2 downto 0) is
2181  when "100" | "101" | "110" => s := "00";
2182  when others => s := "10";
2183  end case;
2184  when others => s := "11";
2185  end case;
2186  if(ipb_addr(15 downto 12) = x"1")then
2187  case s is
2188  when "00" =>
2189  if(ipb_addr(9 downto 8) = "11")then
2190  case ipb_addr(3 downto 0) is
2191  when x"0" => ipb_rdata <= TotalEvtLengthCntr(0)(31 downto 0);
2192  when x"1" => ipb_rdata <= x"00" & TotalEvtLengthCntr(0)(55 downto 32);
2193  when x"2" => ipb_rdata <= EvtLength_errCntr(0);
2194  when x"3" => ipb_rdata <= AMClength_errCntr(0);
2195  when x"4" => ipb_rdata <= AMCvalid_errCntr(0);
2196  when x"5" => ipb_rdata <= AMCcrc_errCntr(0);
2197  when others => ipb_rdata <= (others => '0');
2198  end case;
2199  else
2200  ipb_rdata <= TCPIP_rdata(0);
2201  end if;
2202  when "01" =>
2203  if(ipb_addr(9 downto 8) = "11")then
2204  case ipb_addr(3 downto 0) is
2205  when x"0" => ipb_rdata <= TotalEvtLengthCntr(1)(31 downto 0);
2206  when x"1" => ipb_rdata <= x"00" & TotalEvtLengthCntr(1)(55 downto 32);
2207  when x"2" => ipb_rdata <= EvtLength_errCntr(1);
2208  when x"3" => ipb_rdata <= AMClength_errCntr(1);
2209  when x"4" => ipb_rdata <= AMCvalid_errCntr(1);
2210  when x"5" => ipb_rdata <= AMCcrc_errCntr(1);
2211  when others => ipb_rdata <= (others => '0');
2212  end case;
2213  else
2214  ipb_rdata <= TCPIP_rdata(0);
2215  end if;
2216  when "10" =>
2217  if(ipb_addr(9 downto 8) = "11")then
2218  case ipb_addr(3 downto 0) is
2219  when x"0" => ipb_rdata <= TotalEvtLengthCntr(2)(31 downto 0);
2220  when x"1" => ipb_rdata <= x"00" & TotalEvtLengthCntr(2)(55 downto 32);
2221  when x"2" => ipb_rdata <= EvtLength_errCntr(2);
2222  when x"3" => ipb_rdata <= AMClength_errCntr(2);
2223  when x"4" => ipb_rdata <= AMCvalid_errCntr(2);
2224  when x"5" => ipb_rdata <= AMCcrc_errCntr(2);
2225  when others => ipb_rdata <= (others => '0');
2226  end case;
2227  else
2228  ipb_rdata <= TCPIP_rdata(0);
2229  end if;
2230  when others =>
2231  case ipb_addr(5 downto 4) is
2232  when "00" =>
2233  case ipb_addr(3 downto 0) is
2234  when x"0" => ipb_rdata <= "00000" & NXT_MonBuf(1) & "00000" & NXT_MonBuf(0);
2235  when x"1" => ipb_rdata <= x"0000" & "00000" & NXT_MonBuf(2);
2236  when x"2" => ipb_rdata <= "00000" & UNA_MonBuf(1) & "00000" & UNA_MonBuf(0);
2237  when x"3" => ipb_rdata <= "00000" & UNA_MonBuf(3) & "00000" & UNA_MonBuf(2);
2238  when x"4" => ipb_rdata <= x"0000" & "00000" & UNA_MonBuf(4);
2239  when x"5" => ipb_rdata <= x"0" & NXT_TCPBuf(1) & x"0" & NXT_TCPBuf(0);
2240  when x"6" => ipb_rdata <= x"00000" & NXT_TCPBuf(2);
2241  when x"7" => ipb_rdata <= "00000" & UNA_TCPBuf(1) & "00000" & UNA_TCPBuf(0);
2242  when x"8" => ipb_rdata <= "00000" & UNA_TCPBuf(3) & "00000" & UNA_TCPBuf(2);
2243  when x"9" => ipb_rdata <= "00000" & Written_MonBuf(1) & "00000" & Written_MonBuf(0);
2244  when x"a" => ipb_rdata <= "00000" & Written_MonBuf(3) & "00000" & Written_MonBuf(2);
2245  when x"b" => ipb_rdata <= '0' & ReadBusy & x"000" & "00" & sfp_pd(2) & sfp_pd(1) & sfp_pd(0) & '0' & SFP_TX_FSM_RESET_DONE & '0' & SFP_RX_FSM_RESET_DONE;
2246  when x"c" => ipb_rdata <= x"000" & SFP2TCPIP(2) & SFP2TCPIP(1) & SFP2TCPIP(0) & TCPIP2SFP_sel(2) & TCPIP2SFP_sel(1) & TCPIP2SFP_sel(0) & '0' & EnTCPIP & '0' & LINK_down;
2247  when x"d" => ipb_rdata <= cmsCRC_errCntr(0);
2248  when x"e" => ipb_rdata <= cmsCRC_errCntr(1);
2249  when others => ipb_rdata <= cmsCRC_errCntr(2);
2250  end case;
2251  when "01" =>
2252  case ipb_addr(3 downto 0) is
2253  when x"0" => ipb_rdata <= '0' & RETX_ddr_rrqst & '0' & RETX_ddr_wrqst & '0' & EVENTdata_avl & '0' & AddrBuf_full & '0' & evt_FIFO_full & '0' & wport_FIFO_full & '0' & wport_rdy & '0' & evt_data_rdy;
2254  when x"1" => ipb_rdata <= TCP_rrqst_i & TCP_rFIFO_ra & "000" & TCP_rFIFO_wa & "00" & rrqstMask & '0' & RETXdataAck & '0' & RETXdataRqst;
2255  when x"2" => ipb_rdata <= "00000" & MonBuf_wa & "00000" & MonBuf_ra;
2256  when x"3" => ipb_rdata <= EventData_reCntr(0);
2257  when x"4" => ipb_rdata <= EventData_reCntr(1);
2258  when x"5" => ipb_rdata <= EventData_reCntr(2);
2259  when x"6" => ipb_rdata <= EventBufAddr_weCntr(0);
2260  when x"7" => ipb_rdata <= EventBufAddr_weCntr(1);
2261  when x"8" => ipb_rdata <= EventBufAddr_weCntr(2);
2262  when x"9" => ipb_rdata <= EventData_weCntr(0);
2263  when x"a" => ipb_rdata <= EventData_weCntr(1);
2264  when x"b" => ipb_rdata <= EventData_weCntr(2);
2265  when x"c" => ipb_rdata <= SFP_IPADDR(0);
2266  when x"d" => ipb_rdata <= SFP_IPADDR(1);
2267  when x"e" => ipb_rdata <= SFP_IPADDR(2);
2268  when others => ipb_rdata <= CWND_max;
2269  end case;
2270  when "10" =>
2271  case ipb_addr(3 downto 0) is
2272  when x"0" => ipb_rdata <= x"000000" & "000" & en_stop;
2273  when x"4" => ipb_rdata <= SFP_evt_cntr(0);
2274  when x"5" => ipb_rdata <= SFP_evt_cntr(1);
2275  when x"6" => ipb_rdata <= SFP_evt_cntr(2);
2276  when x"8" => ipb_rdata <= SFP_word_cntr(0);
2277  when x"9" => ipb_rdata <= SFP_word_cntr(1);
2278  when x"a" => ipb_rdata <= SFP_word_cntr(2);
2279  when x"c" => ipb_rdata <= SFP_blk_cntr(0);
2280  when x"d" => ipb_rdata <= SFP_blk_cntr(1);
2281  when x"e" => ipb_rdata <= SFP_blk_cntr(2);
2282  when others => ipb_rdata <= (others => '0');
2283  end case;
2284  when others => ipb_rdata <= (others => '0');
2285  end case;
2286  end case;
2287  else
2288  ipb_rdata <= (others => '0');
2289  end if;
2290 end process;
2291 process(ipb_clk)
2292 begin
2293  if(ipb_clk'event and ipb_clk = '1')then
2294  if(ipb_addr(27) = '0' and ipb_addr(15 downto 2) = "00011100000111" and ipb_strobe = '1' and ipb_write = '1')then
2295  if(ipb_addr(1 downto 0) = "11")then
2296  CWND_max <= x"0" & ipb_wdata(27 downto 0);
2297  else
2298  SFP_IPADDR(conv_integer(ipb_addr(1 downto 0))) <= ipb_wdata;
2299  end if;
2300  end if;
2301  end if;
2302 end process;
2303 end Behavioral;
2304 
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