AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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XGbEPCS32.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 09:16:59 11/24/2012
6 -- Design Name:
7 -- Module Name: EMAC_GXPCS - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 --use IEEE.NUMERIC_STD.ALL;
29 
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 library UNISIM;
33 use UNISIM.VComponents.all;
34 
35 entity XGbEPCS32 is
36  Port (
37  reset : IN std_logic;
38  clk2x : IN std_logic; -- 2xSFP_REFCLK 312.5MHz norminal
39  clk : IN std_logic;
40  TXUSRCLK : IN std_logic;
41  TX_high : IN std_logic; -- in clk2x domain, TX_high = clk
42  RXUSRCLK : IN std_logic;
43  RXRESETDONE : IN std_logic;
44  RESET_TXSync : IN std_logic;
45  inh_TX : IN std_logic;
46  GTX_TXD : out STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
47  GTX_TXHEADER : out STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
48  GTX_TX_PAUSE : IN std_logic; -- sequence counter = "011111"
49  GTX_RXD : in STD_LOGIC_VECTOR (31 downto 0);
50  GTX_RXDVLD : in STD_LOGIC;
51  GTX_RXHEADER : in STD_LOGIC_VECTOR (1 downto 0);
52  GTX_RXHEADERVLD : in STD_LOGIC;
53  GTX_RXGOOD : out STD_LOGIC;
54  GTX_RXGEARBOXSLIP_OUT : out STD_LOGIC := '0';
55  EmacPhyTxC : in STD_LOGIC_VECTOR (3 downto 0);
56  EmacPhyTxD : in STD_LOGIC_VECTOR (31 downto 0);
57  PhyEmacRxC : out STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
58  PhyEmacRxD : out STD_LOGIC_VECTOR (31 downto 0) := (others => '0')
59  );
60 end XGbEPCS32;
61 
62 architecture Behavioral of XGbEPCS32 is
63 COMPONENT BLOCK_SYNC_SM
64  PORT(
65  RXHEADER_IN : IN std_logic_vector(2 downto 0);
66  RXHEADERVALID_IN : IN std_logic;
67  USER_CLK : IN std_logic;
68  SYSTEM_RESET : IN std_logic;
69  BLOCKSYNC_OUT : OUT std_logic;
70  RXGEARBOXSLIP_OUT : OUT std_logic
71  );
72 END COMPONENT;
73 COMPONENT SCRAMBLER
74 generic
75 (
76  TX_DATA_WIDTH : integer := 32
77 );
78  PORT(
79  UNSCRAMBLED_DATA_IN : IN std_logic_vector((TX_DATA_WIDTH-1) downto 0);
80  DATA_VALID_IN : IN std_logic;
81  USER_CLK : IN std_logic;
82  SYSTEM_RESET : IN std_logic;
83  SCRAMBLED_DATA_OUT : OUT std_logic_vector((TX_DATA_WIDTH-1) downto 0)
84  );
85 END COMPONENT;
86 COMPONENT DESCRAMBLER
87 generic
88 (
89  RX_DATA_WIDTH : integer := 32
90 );
91  PORT(
92  SCRAMBLED_DATA_IN : IN std_logic_vector((RX_DATA_WIDTH-1) downto 0);
93  DATA_VALID_IN : IN std_logic;
94  USER_CLK : IN std_logic;
95  SYSTEM_RESET : IN std_logic;
96  UNSCRAMBLED_DATA_OUT : OUT std_logic_vector((RX_DATA_WIDTH-1) downto 0)
97  );
98 END COMPONENT;
99 constant EBLOCK : std_logic_vector(63 downto 0) := x"1e1e1e1e1e1e1e1e";
100 constant LBLOCK : std_logic_vector(63 downto 0) := x"0100000001000055";
101 constant R_FAULT : std_logic_vector(31 downto 0) := x"0200009c";
102 constant LBLOCK_R : std_logic_vector(71 downto 0) := x"0100009c10100009c1";
103 constant EBLOCK_R : std_logic_vector(71 downto 0) := x"fefefefeffefefefef";
104 type array37x32 is array(0 to 36) of bit_vector(31 downto 0);
105 constant RxIdle : array37x32 := (x"ffff0000",x"ffff0000",x"ffff0000",x"ffff0000",
106  x"ffff0000",x"ffff0000",x"ffff0000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
107  x"ffff0000",x"ffff0000",x"ffff0000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
108  x"ffff0000",x"ffff0000",x"ffff0000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
109  x"ffff0000",x"ffff0000",x"ffff0000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
110  x"00000000");
111 type state is (TX_INIT, TX_C, TX_D, TX_T, TX_E);
112 signal T_state : state := TX_INIT;
113 signal EmacPhyTxC_q : std_logic_vector(3 downto 0) := (others => '0');
114 signal EmacPhyTxD_q : std_logic_vector(31 downto 0) := (others => '0');
115 signal TxC : std_logic_vector(7 downto 0) := (others => '0');
116 signal TxD : std_logic_vector(63 downto 0) := (others => '0');
117 signal TxD_q : std_logic_vector(63 downto 0) := (others => '0');
118 signal c_coded : std_logic_vector(55 downto 0) := (others => '0');
119 signal tx_coded : std_logic_vector(65 downto 0) := (others => '0');
120 signal T_TYPE_C : std_logic := '0';
121 signal T_TYPE_D : std_logic := '0';
122 signal T_TYPE_S : std_logic := '0';
123 signal T_TYPE_T : std_logic := '0';
124 signal T_IS_D : std_logic := '0';
125 signal T_IS_O : std_logic_vector(1 downto 0) := (others => '0');
126 signal T_IS_S : std_logic_vector(1 downto 0) := (others => '0');
127 signal T_IS_C : std_logic_vector(7 downto 0) := (others => '0');
128 signal T_IS_E : std_logic_vector(7 downto 0) := (others => '0');
129 signal T_IS_T : std_logic_vector(7 downto 0) := (others => '0');
130 signal GTX_TX_PAUSE_q : std_logic := '0';
131 signal TX_FIFO_DI : std_logic_vector(33 downto 0) := (others => '0');
132 signal TX_FIFO_DO : std_logic_vector(33 downto 0) := (others => '0');
133 signal TX_FIFO_wa : std_logic_vector(3 downto 0) := (others => '0');
134 signal TX_FIFO_ra : std_logic_vector(3 downto 0) := (others => '0');
135 signal GTX_RXHEADER_IN : std_logic_vector(2 downto 0) := (others => '0');
136 signal BLOCK_LOCK : std_logic := '0';
137 signal BLOCK_SYNC_SM_RESET : std_logic := '0';
138 signal BLOCK_NOT_LOCK : std_logic := '0';
139 signal GTX_RXHEADERVLD_dl : std_logic_vector(1 downto 0) := (others => '0');
140 signal GTX_RXHEADER_dl0 : std_logic_vector(1 downto 0) := (others => '0');
141 signal TX_UNSCRAMBLED_DATA : std_logic_vector(65 downto 0) := (others => '0');
142 signal TX_UNSCRAMBLED_DATA_MUX : std_logic_vector(33 downto 0) := (others => '0');
143 signal RX_UNSCRAMBLED_DATA : std_logic_vector(63 downto 0) := (others => '0');
144 signal RX_UNSCRAMBLED_DATA_OUT : std_logic_vector(31 downto 0) := (others => '0');
145 signal RXHEADER : std_logic_vector(1 downto 0) := (others => '0');
146 type Rstate is (RX_INIT, RX_C, RX_D, RX_T, RX_E);
147 signal R_state : Rstate := RX_INIT;
148 signal RxC : std_logic_vector(7 downto 0) := (others => '0');
149 signal RxD : std_logic_vector(63 downto 0) := (others => '0');
150 signal c_raw : std_logic_vector(63 downto 0) := (others => '0');
151 signal rx_raw : std_logic_vector(71 downto 0) := (others => '0');
152 signal rx_raw_ps2 : std_logic_vector(71 downto 0) := (others => '0');
153 signal rx_raw_ps3 : std_logic_vector(71 downto 0) := (others => '0');
154 signal rx_raw_mux : std_logic_vector(35 downto 0) := (others => '0');
155 signal R_TYPE_C : std_logic := '0';
156 signal R_TYPE_D : std_logic := '0';
157 signal R_TYPE_S : std_logic := '0';
158 signal R_TYPE_T : std_logic := '0';
159 signal NEXT_TYPE_C : std_logic := '0';
160 signal NEXT_TYPE_D : std_logic := '0';
161 signal NEXT_TYPE_S : std_logic := '0';
162 signal NEXT_TYPE_T : std_logic := '0';
163 signal R_IS_D : std_logic := '0';
164 signal R_IS_T : std_logic := '0';
165 signal Legal_O : std_logic_vector(1 downto 0) := (others => '0');
166 signal R_IS_O : std_logic_vector(1 downto 0) := (others => '0');
167 signal R_IS_S : std_logic_vector(1 downto 0) := (others => '0');
168 signal R_IS_C : std_logic_vector(7 downto 0) := (others => '0');
169 signal R_IS_E : std_logic_vector(7 downto 0) := (others => '0');
170 signal RX_FIFO_DI : std_logic_vector(36 downto 0) := (others => '0');
171 signal RX_FIFO_DO : std_logic_vector(36 downto 0) := (others => '0');
172 signal RX_FIFO_WA : std_logic_vector(3 downto 0) := (others => '0');
173 signal RX_FIFO_RA : std_logic_vector(3 downto 0) := (others => '0');
174 signal RX_FIFO_RA_G : std_logic_vector(3 downto 0) := (others => '0');
175 signal RX_FIFO_RA_P : std_logic_vector(3 downto 0) := (others => '0');
176 signal RX_FIFO_WA_RA_D : std_logic_vector(3 downto 0) := (others => '0');
177 signal RX_FIFO_RA_G0SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
178 signal RX_FIFO_RA_G1SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
179 signal RX_FIFO_RA_G2SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
180 signal RX_FIFO_RA_G3SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
181 signal RX_FIFO_WE : std_logic := '0';
182 signal GTX_RXDVLD_q : std_logic := '0';
183 signal skip_RX_FIFO_WE : std_logic := '0';
184 signal ec_RX_FIFO_RAn : std_logic := '0';
185 signal insert_IDLE : std_logic := '0';
186 signal delete_IDLE : std_logic := '0';
187 signal insert_IDLE_l : std_logic := '0';
188 signal delete_IDLE_l : std_logic := '0';
189 signal R_IS_RF : std_logic_vector(6 downto 0) := (others => '0');
190 signal R_IS_LF : std_logic_vector(6 downto 0) := (others => '0');
191 signal R_IS_IDLE : std_logic_vector(5 downto 0) := (others => '0');
192 signal en_DI : std_logic := '0';
193 signal en_II : std_logic := '0';
194 signal T4567 : std_logic := '0';
195 signal inh : std_logic := '0';
196 signal inh_cntr : std_logic_vector(3 downto 0) := (others => '0');
197 signal reset_RXSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
198 signal RXGOOD_cntr : std_logic_vector(4 downto 0) := (others => '0');
199 signal RXRESETDONE_SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
200 begin
201 process(clk2x)
202 begin
203  if(clk2x'event and clk2x = '1')then
204  if(TX_high = '0')then
205  EmacPhyTxC_q <= EmacPhyTxC;
206  EmacPhyTxD_q <= EmacPhyTxD;
207  else
208  TxC <= EmacPhyTxC & EmacPhyTxC_q;
209  TxD <= EmacPhyTxD & EmacPhyTxD_q;
210  end if;
211  if(TX_high = '1')then
212  TX_UNSCRAMBLED_DATA_MUX <= '1' & TX_UNSCRAMBLED_DATA(64) & TX_UNSCRAMBLED_DATA(31 downto 0);
213  else
214  TX_UNSCRAMBLED_DATA_MUX <= '0' & TX_UNSCRAMBLED_DATA(64 downto 32);
215  end if;
216  TX_FIFO_DI(33 downto 32) <= TX_UNSCRAMBLED_DATA_MUX(33 downto 32);
217  end if;
218 end process;
219 process(clk)
220 begin
221  if(clk'event and clk = '1')then
222  if(TxC(3 downto 0) = x"1" and TxD(31 downto 0) = R_FAULT)then
223  T_IS_O(0) <= '1';
224  else
225  T_IS_O(0) <= '0';
226  end if;
227  if(TxC(7 downto 4) = x"1" and TxD(63 downto 32) = R_FAULT)then
228  T_IS_O(1) <= '1';
229  else
230  T_IS_O(1) <= '0';
231  end if;
232  if(TxC = x"01" and TxD(7 downto 0) = x"fb")then
233  T_IS_S(0) <= '1';
234  else
235  T_IS_S(0) <= '0';
236  end if;
237  if(TxC(7 downto 4) = x"1" and TxD(39 downto 32) = x"fb")then
238  T_IS_S(1) <= '1';
239  else
240  T_IS_S(1) <= '0';
241  end if;
242  for i in 0 to 7 loop
243  if(TxC(i) = '1' and TxD(i*8+7 downto i*8) = x"07")then
244  T_IS_C(i) <= '1';
245  else
246  T_IS_C(i) <= '0';
247  end if;
248  if(TxC(i) = '1' and TxD(i*8+7 downto i*8) = x"fe")then
249  T_IS_E(i) <= '1';
250  c_coded(I*7+6 downto i*7) <= "0011110";
251  else
252  T_IS_E(i) <= '0';
253  c_coded(I*7+6 downto i*7) <= "0000000";
254  end if;
255  end loop;
256  if(TxC(0) = '1' and TxD(7 downto 0) = x"fd")then
257  T_IS_T(0) <= '1';
258  else
259  T_IS_T(0) <= '0';
260  end if;
261  if(TxC(1 downto 0) = "10" and TxD(15 downto 8) = x"fd")then
262  T_IS_T(1) <= '1';
263  else
264  T_IS_T(1) <= '0';
265  end if;
266  if(TxC(2 downto 0) = "100" and TxD(23 downto 16) = x"fd")then
267  T_IS_T(2) <= '1';
268  else
269  T_IS_T(2) <= '0';
270  end if;
271  if(TxC(3 downto 0) = "1000" and TxD(31 downto 24) = x"fd")then
272  T_IS_T(3) <= '1';
273  else
274  T_IS_T(3) <= '0';
275  end if;
276  if(TxC(4 downto 0) = "10000" and TxD(39 downto 32) = x"fd")then
277  T_IS_T(4) <= '1';
278  else
279  T_IS_T(4) <= '0';
280  end if;
281  if(TxC(5 downto 0) = "100000" and TxD(47 downto 40) = x"fd")then
282  T_IS_T(5) <= '1';
283  else
284  T_IS_T(5) <= '0';
285  end if;
286  if(TxC(6 downto 0) = "1000000" and TxD(55 downto 48) = x"fd")then
287  T_IS_T(6) <= '1';
288  else
289  T_IS_T(6) <= '0';
290  end if;
291  if(TxC(7 downto 0) = "10000000" and TxD(63 downto 56) = x"fd")then
292  T_IS_T(7) <= '1';
293  else
294  T_IS_T(7) <= '0';
295  end if;
296  T_IS_D <= not or_reduce(TxC);
297  if(and_reduce(T_IS_C) = '1' or (T_IS_O(0) = '1' and T_IS_C(7 downto 4) = not T_IS_E(7 downto 4)) or (T_IS_O(1) = '1' and T_IS_C(3 downto 0) = not T_IS_E(3 downto 0)) or T_IS_O = "11")then
298  T_TYPE_C <= '1';
299  else
300  T_TYPE_C <= '0';
301  end if;
302  if(T_IS_S(0) = '1' or (T_IS_S(1) = '1' and (T_IS_C(3 downto 0) = not T_IS_E(3 downto 0) or T_IS_O(0) = '1')))then
303  T_TYPE_S <= '1';
304  else
305  T_TYPE_S <= '0';
306  end if;
307  T_TYPE_D <= T_IS_D;
308  T_TYPE_T <= '0';
309  if(T_IS_T(0) = '1' and T_IS_C(7 downto 1) = not T_IS_E(7 downto 1))then
310  T_TYPE_T <= '1';
311  end if;
312  if(T_IS_T(1) = '1' and T_IS_C(7 downto 2) = not T_IS_E(7 downto 2))then
313  T_TYPE_T <= '1';
314  end if;
315  if(T_IS_T(2) = '1' and T_IS_C(7 downto 3) = not T_IS_E(7 downto 3))then
316  T_TYPE_T <= '1';
317  end if;
318  if(T_IS_T(3) = '1' and T_IS_C(7 downto 4) = not T_IS_E(7 downto 4))then
319  T_TYPE_T <= '1';
320  end if;
321  if(T_IS_T(4) = '1' and T_IS_C(7 downto 5) = not T_IS_E(7 downto 5))then
322  T_TYPE_T <= '1';
323  end if;
324  if(T_IS_T(5) = '1' and T_IS_C(7 downto 6) = not T_IS_E(7 downto 6))then
325  T_TYPE_T <= '1';
326  end if;
327  if(T_IS_T(6) = '1' and T_IS_C(7) = not T_IS_E(7))then
328  T_TYPE_T <= '1';
329  end if;
330  if(T_IS_T(7) = '1')then
331  T_TYPE_T <= '1';
332  end if;
333  TxD_q <= TxD;
334  if(T_IS_C = x"ff")then
335  tx_coded(63 downto 0) <= x"000000000000001e";
336  end if;
337  if(T_IS_O(1) = '1' and T_IS_C(3 downto 0) = not T_IS_E(3 downto 0))then
338  tx_coded(63 downto 0) <= TxD_q(63 downto 40) & x"0" & c_coded(27 downto 0) & x"2d";
339  end if;
340  if(T_IS_S(1) = '1' and T_IS_C(3 downto 0) = not T_IS_E(3 downto 0))then
341  tx_coded(63 downto 0) <= TxD_q(63 downto 40) & x"0" & c_coded(27 downto 0) & x"33";
342  end if;
343  if(T_IS_O(0) = '1' and T_IS_C(7 downto 4) = not T_IS_E(7 downto 4))then
344  tx_coded(63 downto 0) <= c_coded(55 downto 28) & x"0" & TxD_q(31 downto 8) & x"4b";
345  end if;
346  if(T_IS_O = "11")then
347  tx_coded(63 downto 0) <= TxD_q(63 downto 40) & x"00" & TxD_q(31 downto 8) & x"55";
348  end if;
349  if(T_IS_S(1) = '1' and T_IS_O(0) = '1')then
350  tx_coded(63 downto 0) <= TxD_q(63 downto 40) & TxD_q(31 downto 0) & x"66";
351  end if;
352  if(T_IS_S(0) = '1')then
353  tx_coded(63 downto 0) <= TxD_q(63 downto 8) & x"78";
354  end if;
355  if(T_IS_T(0) = '1')then
356  tx_coded(63 downto 0) <= c_coded(55 downto 7) & "0000000" & x"87";
357  end if;
358  if(T_IS_T(1) = '1')then
359  tx_coded(63 downto 0) <= c_coded(55 downto 14) & "000000" & TxD_q(7 downto 0) & x"99";
360  end if;
361  if(T_IS_T(2) = '1')then
362  tx_coded(63 downto 0) <= c_coded(55 downto 21) & "00000" & TxD_q(15 downto 0) & x"aa";
363  end if;
364  if(T_IS_T(3) = '1')then
365  tx_coded(63 downto 0) <= c_coded(55 downto 28) & "0000" & TxD_q(23 downto 0) & x"b4";
366  end if;
367  if(T_IS_T(4) = '1')then
368  tx_coded(63 downto 0) <= c_coded(55 downto 35) & "000" & TxD_q(31 downto 0) & x"cc";
369  end if;
370  if(T_IS_T(5) = '1')then
371  tx_coded(63 downto 0) <= c_coded(55 downto 42) & "00" & TxD_q(39 downto 0) & x"d2";
372  end if;
373  if(T_IS_T(6) = '1')then
374  tx_coded(63 downto 0) <= c_coded(55 downto 49) & '0' & TxD_q(47 downto 0) & x"e1";
375  end if;
376  if(T_IS_T(7) = '1')then
377  tx_coded(63 downto 0) <= TxD_q(55 downto 0) & x"ff";
378  end if;
379  if(T_IS_D = '1')then
380  tx_coded(63 downto 0) <= TxD_q;
381  end if;
382  if(T_IS_D = '1')then
383  tx_coded(65 downto 64) <= "01";
384  else
385  tx_coded(65 downto 64) <= "10";
386  end if;
387  if(reset = '1')then
388  T_state <= TX_INIT;
389  TX_UNSCRAMBLED_DATA <= "10" & LBLOCK;
390  else
391  case T_state is
392  when TX_INIT =>
393  TX_UNSCRAMBLED_DATA <= tx_coded;
394  if(T_TYPE_C = '1')then
395  T_state <= TX_C;
396  elsif(T_TYPE_S = '1')then
397  T_state <= TX_D;
398  else
399  T_state <= TX_E;
400  TX_UNSCRAMBLED_DATA <= "10" & EBLOCK;
401  end if;
402  when TX_C =>
403  TX_UNSCRAMBLED_DATA <= tx_coded;
404  if(T_TYPE_S = '1')then
405  T_state <= TX_D;
406  elsif(T_TYPE_C = '0')then
407  T_state <= TX_E;
408  TX_UNSCRAMBLED_DATA <= "10" & EBLOCK;
409  end if;
410  when TX_D =>
411  TX_UNSCRAMBLED_DATA <= tx_coded;
412  if(T_TYPE_T = '1')then
413  T_state <= TX_T;
414  elsif(T_TYPE_D = '0')then
415  T_state <= TX_E;
416  TX_UNSCRAMBLED_DATA <= "10" & EBLOCK;
417  end if;
418  when TX_T =>
419  TX_UNSCRAMBLED_DATA <= tx_coded;
420  if(T_TYPE_C = '1')then
421  T_state <= TX_C;
422  elsif(T_TYPE_S = '1')then
423  T_state <= TX_D;
424  else
425  T_state <= TX_E;
426  TX_UNSCRAMBLED_DATA <= "10" & EBLOCK;
427  end if;
428  when others =>
429  TX_UNSCRAMBLED_DATA <= tx_coded;
430  if(T_TYPE_C = '1')then
431  T_state <= TX_C;
432  elsif(T_TYPE_D = '1')then
433  T_state <= TX_D;
434  elsif(T_TYPE_T = '1')then
435  T_state <= TX_T;
436  else
437  TX_UNSCRAMBLED_DATA <= "10" & EBLOCK;
438  end if;
439  end case;
440  end if;
441  end if;
442 end process;
443 process(clk2x,reset_TXSync)
444 begin
445  if(reset_TXSync = '1')then
446  TX_FIFO_WA <= x"8";
447  elsif(clk2x'event and clk2x = '1')then
448  TX_FIFO_WA <= TX_FIFO_WA + 1;
449  end if;
450 end process;
451 g_TX_FIFO: for i in 0 to 33 generate
452  i_TX_FIFO : RAM32X1D
453  port map (
454  DPO => TX_FIFO_DO(i), -- Read-only 1-bit data output
455  SPO => open, -- R/W 1-bit data output
456  A0 => TX_FIFO_WA(0), -- R/W address[0] input bit
457  A1 => TX_FIFO_WA(1), -- R/W address[1] input bit
458  A2 => TX_FIFO_WA(2), -- R/W address[2] input bit
459  A3 => TX_FIFO_WA(3), -- R/W address[3] input bit
460  A4 => '0', -- R/W address[4] input bit
461  D => TX_FIFO_DI(i), -- Write 1-bit data input
462  DPRA0 => TX_FIFO_RA(0), -- Read-only address[0] input bit
463  DPRA1 => TX_FIFO_RA(1), -- Read-only address[1] input bit
464  DPRA2 => TX_FIFO_RA(2), -- Read-only address[2] input bit
465  DPRA3 => TX_FIFO_RA(3), -- Read-only address[3] input bit
466  DPRA4 => '0', -- Read-only address[4] input bit
467  WCLK => clk2x, -- Write clock input
468  WE => '1' -- Write enable input
469  );
470 end generate;
471 process(TXUSRCLK)
472 begin
473  if(TXUSRCLK'event and TXUSRCLK = '1')then
474  if(reset_TXSync = '1')then
475  TX_FIFO_RA <= (others => '0');
476  elsif(GTX_TX_PAUSE = '0' or (TX_FIFO_DO(33) = '1' and GTX_TX_PAUSE_q = '0'))then
477  TX_FIFO_RA <= TX_FIFO_RA + 1;
478  end if;
479  if(inh_TX = '1')then
480  GTX_TXHEADER <= "00";
481  else
482  GTX_TXHEADER <= not TX_FIFO_DO(32) & TX_FIFO_DO(32);
483  end if;
484  GTX_TX_PAUSE_q <= GTX_TX_PAUSE;
485  if(inh_TX = '1')then
486  GTX_TXD <= (others => '0');
487  else
488  GTX_TXD <= TX_FIFO_DO(31 downto 0);
489  end if;
490  end if;
491 end process;
492 process(RXUSRCLK,RXRESETDONE)
493 begin
494  if(RXRESETDONE = '0')then
495  RXRESETDONE_SyncRegs <= (others => '0');
496  elsif(RXUSRCLK'event and RXUSRCLK = '1')then
497  RXRESETDONE_SyncRegs <= RXRESETDONE_SyncRegs(2 downto 0) & '1';
498  end if;
499 end process;
500 i_BLOCK_SYNC_SM: BLOCK_SYNC_SM PORT MAP(
501  BLOCKSYNC_OUT => BLOCK_LOCK,
502  RXGEARBOXSLIP_OUT => GTX_RXGEARBOXSLIP_OUT ,
503  RXHEADER_IN => GTX_RXHEADER_IN ,
504  RXHEADERVALID_IN => GTX_RXHEADERVLD,
505  USER_CLK => RXUSRCLK,
506  SYSTEM_RESET => BLOCK_SYNC_SM_RESET
507  );
508 BLOCK_SYNC_SM_RESET <= not RXRESETDONE_SyncRegs(3);
509 GTX_RXHEADER_IN <= '0' & GTX_RXHEADER;
510 BLOCK_NOT_LOCK <= not BLOCK_LOCK;
511 i_SCRAMBLER: SCRAMBLER PORT MAP(
512  UNSCRAMBLED_DATA_IN => TX_UNSCRAMBLED_DATA_MUX (31 downto 0),
513  SCRAMBLED_DATA_OUT => TX_FIFO_DI(31 downto 0),
514  DATA_VALID_IN => '1',
515  USER_CLK => clk2x,
516  SYSTEM_RESET => RESET_TXSync
517  );
518 -- Rx code follows
519 i_DESCRAMBLER: DESCRAMBLER PORT MAP(
520  SCRAMBLED_DATA_IN => GTX_RXD,
521  UNSCRAMBLED_DATA_OUT => RX_UNSCRAMBLED_DATA_OUT ,
522  DATA_VALID_IN => GTX_RXDVLD,
523  USER_CLK => RXUSRCLK,
524  SYSTEM_RESET => BLOCK_NOT_LOCK
525  );
526 process(RXUSRCLK)
527 begin
528  if(RXUSRCLK'event and RXUSRCLK = '1')then
529  GTX_RXHEADERVLD_dl <= GTX_RXHEADERVLD_dl(0) & GTX_RXHEADERVLD;
530  if(GTX_RXHEADERVLD = '1')then
531  GTX_RXHEADER_dl0 <= GTX_RXHEADER;
532  end if;
533  if(GTX_RXHEADERVLD_dl(0) = '1')then
534  RX_UNSCRAMBLED_DATA(31 downto 0) <= RX_UNSCRAMBLED_DATA_OUT;
535  end if;
536  if(GTX_RXHEADERVLD_dl(1) = '1')then
537  RX_UNSCRAMBLED_DATA(63 downto 32) <= RX_UNSCRAMBLED_DATA_OUT;
538  end if;
539  if(GTX_RXHEADERVLD_dl(0) = '1')then
540  if(reset_RXSyncRegs(2) = '1' or R_state = RX_E)then
541  GTX_RXGOOD <= '0';
542  elsif(RXGOOD_cntr(4) = '1')then
543  GTX_RXGOOD <= '1';
544  end if;
545  if(reset_RXSyncRegs(2) = '1' or R_state = RX_E)then
546  RXGOOD_cntr <= (others => '0');
547  elsif(RXGOOD_cntr(4) = '0')then
548  RXGOOD_cntr <= RXGOOD_cntr + 1;
549  end if;
550 -- pipeline stage 1
551  RXHEADER <= GTX_RXHEADER_dl0;
552  case RX_UNSCRAMBLED_DATA(3 downto 0) is
553  when x"1" => RxC <= x"c0";
554  when x"2" => RxC <= x"e0";
555  when x"3" | x"d" => RxC <= x"1f";
556  when x"4" => RxC <= x"f8";
557  when x"5" | x"6" => RxC <= x"11";
558  when x"7" | x"e" => RxC <= x"ff";
559  when x"8" => RxC <= x"01";
560  when x"9" => RxC <= x"fe";
561  when x"a" => RxC <= x"fc";
562  when x"b" => RxC <= x"f1";
563  when x"c" => RxC <= x"f0";
564  when x"f" => RxC <= x"80";
565  when others => RxC <= x"00";
566  end case;
567  RxD <= RX_UNSCRAMBLED_DATA;
568  for i in 0 to 7 loop
569  if(RX_UNSCRAMBLED_DATA(i*7+14 downto i*7+8) = "0000000")then
570  R_IS_C(i) <= '1';
571  else
572  R_IS_C(i) <= '0';
573  end if;
574  if(RX_UNSCRAMBLED_DATA(i*7+14 downto i*7+8) = "0011110")then
575  R_IS_E(i) <= '1';
576  c_raw(I*8+7 downto i*8) <= x"fe";
577  else
578  R_IS_E(i) <= '0';
579  c_raw(I*8+7 downto i*8) <= x"07";
580  end if;
581  end loop;
582  if(RX_UNSCRAMBLED_DATA(35 downto 8) = x"0010000" or RX_UNSCRAMBLED_DATA(35 downto 8) = x"0020000")then
583  Legal_O(0) <= '1';
584  else
585  Legal_O(0) <= '0';
586  end if;
587  if(RX_UNSCRAMBLED_DATA(63 downto 36) = x"0100000" or RX_UNSCRAMBLED_DATA(63 downto 36) = x"0200000")then
588  Legal_O(1) <= '1';
589  else
590  Legal_O(1) <= '0';
591  end if;
592  if(RX_UNSCRAMBLED_DATA(7 downto 4) = x"4" or RX_UNSCRAMBLED_DATA(7 downto 4) = x"5" or RX_UNSCRAMBLED_DATA(7 downto 4) = x"6")then
593  R_IS_O(0) <= '1';
594  else
595  R_IS_O(0) <= '0';
596  end if;
597  if(RX_UNSCRAMBLED_DATA(7 downto 4) = x"2" or RX_UNSCRAMBLED_DATA(7 downto 4) = x"5")then
598  R_IS_O(1) <= '1';
599  else
600  R_IS_O(1) <= '0';
601  end if;
602  if(RX_UNSCRAMBLED_DATA(7 downto 4) = x"7")then
603  R_IS_S(0) <= '1';
604  else
605  R_IS_S(0) <= '0';
606  end if;
607  if(RX_UNSCRAMBLED_DATA(7 downto 4) = x"3" or RX_UNSCRAMBLED_DATA(7 downto 4) = x"6")then
608  R_IS_S(1) <= '1';
609  else
610  R_IS_S(1) <= '0';
611  end if;
612  if(RXHEADER = "01")then
613  R_IS_D <= '1';
614  else
615  R_IS_D <= '0';
616  end if;
617  if(RX_UNSCRAMBLED_DATA(7) = '1')then
618  case RX_UNSCRAMBLED_DATA(6 downto 4) is
619  when "000" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(14 downto 8));
620  when "001" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(21 downto 16));
621  when "010" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(28 downto 24));
622  when "011" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(35 downto 32));
623  when "100" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(42 downto 40));
624  when "101" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(49 downto 48));
625  when "110" => R_IS_T <= not RX_UNSCRAMBLED_DATA(56);
626  when others => R_IS_T <= '1';
627  end case;
628  else
629  R_IS_T <= '0';
630  end if;
631 -- pipeline stage 2
632  if(R_IS_D = '1')then
633  NEXT_TYPE_D <= '1';
634  NEXT_TYPE_C <= '0';
635  NEXT_TYPE_S <= '0';
636  NEXT_TYPE_T <= '0';
637  rx_raw_ps2 <= x"00" & RxD;
638  R_IS_IDLE(1 downto 0) <= "00";
639  R_IS_RF(1 downto 0) <= "00";
640  R_IS_LF(1 downto 0) <= "00";
641  else
642  R_IS_IDLE(0) <= and_reduce(RxC(3 downto 0)) and and_reduce(R_IS_C(3 downto 0)) and (not NEXT_TYPE_T or not T4567) and not R_IS_T;
643  R_IS_IDLE(1) <= and_reduce(RxC(7 downto 4)) and and_reduce(R_IS_C(7 downto 4)) and not R_IS_T;
644  R_IS_RF(0) <= R_IS_O(0) and Legal_O(0) and not RxD(24);
645  R_IS_RF(1) <= R_IS_O(1) and Legal_O(1) and not RxD(56);
646  R_IS_LF(0) <= R_IS_O(0) and Legal_O(0) and RxD(24);
647  R_IS_LF(1) <= R_IS_O(1) and Legal_O(1) and RxD(56);
648  NEXT_TYPE_D <= '0';
649  rx_raw_ps2(71 downto 64) <= RxC;
650  if(RxC = x"ff" and R_IS_C = x"ff" and R_IS_T = '0')then
651  NEXT_TYPE_C <= '1';
652  rx_raw_ps2(63 downto 0) <= c_raw;
653  elsif(Legal_O(0) = '1' and R_IS_O(0) = '1' and R_IS_C(7 downto 4) = not R_IS_E(7 downto 4) and RxC(7 downto 4) = x"f")then
654  NEXT_TYPE_C <= '1';
655  rx_raw_ps2(63 downto 0) <= c_raw(63 downto 32) & RxD(31 downto 8) & x"9c";
656  elsif(Legal_O(1) = '1' and R_IS_O(1) = '1' and R_IS_C(3 downto 0) = not R_IS_E(3 downto 0) and RxC(3 downto 0) = x"f")then
657  NEXT_TYPE_C <= '1';
658  rx_raw_ps2(63 downto 0) <= RxD(63 downto 40) & x"9c" & c_raw(31 downto 0);
659  elsif(Legal_O = "11" and R_IS_O = "11")then
660  NEXT_TYPE_C <= '1';
661  rx_raw_ps2(63 downto 0) <= RxD(63 downto 40) & x"9c" & RxD(31 downto 8) & x"9c";
662  else
663  NEXT_TYPE_C <= '0';
664  end if;
665  if(R_IS_S(0) = '1')then
666  NEXT_TYPE_S <= '1';
667  rx_raw_ps2(63 downto 0) <= RxD(63 downto 8) & x"fb";
668  elsif(R_IS_S(1) = '1' and R_IS_C(3 downto 0) = not R_IS_E(3 downto 0) and RxC(3 downto 0) = x"f")then
669  NEXT_TYPE_S <= '1';
670  rx_raw_ps2(63 downto 0) <= RxD(63 downto 40) & x"fb" & c_raw(31 downto 0);
671  elsif(R_IS_S(1) = '1' and Legal_O(1) = '1' and R_IS_O(1) = '1')then
672  NEXT_TYPE_S <= '1';
673  rx_raw_ps2(63 downto 0) <= RxD(63 downto 40) & x"fb" & RxD(31 downto 8) & x"9c";
674  else
675  NEXT_TYPE_S <= '0';
676  end if;
677  if(R_IS_T = '1')then
678  case RxD(6 downto 4) is
679  when "000" =>
680  if(R_IS_C(7 downto 1) = not R_IS_E(7 downto 1))then
681  NEXT_TYPE_T <= '1';
682  else
683  NEXT_TYPE_T <= '0';
684  end if;
685  rx_raw_ps2(63 downto 0) <= c_raw(63 downto 8) & x"fd";
686  when "001" =>
687  if(R_IS_C(7 downto 2) = not R_IS_E(7 downto 2))then
688  NEXT_TYPE_T <= '1';
689  else
690  NEXT_TYPE_T <= '0';
691  end if;
692  rx_raw_ps2(63 downto 0) <= c_raw(63 downto 16) & x"fd" & RxD(15 downto 8);
693  when "010" =>
694  if(R_IS_C(7 downto 3) = not R_IS_E(7 downto 3))then
695  NEXT_TYPE_T <= '1';
696  else
697  NEXT_TYPE_T <= '0';
698  end if;
699  rx_raw_ps2(63 downto 0) <= c_raw(63 downto 24) & x"fd" & RxD(23 downto 8);
700  when "011" =>
701  if(R_IS_C(7 downto 4) = not R_IS_E(7 downto 4))then
702  NEXT_TYPE_T <= '1';
703  else
704  NEXT_TYPE_T <= '0';
705  end if;
706  rx_raw_ps2(63 downto 0) <= c_raw(63 downto 32) & x"fd" & RxD(31 downto 8);
707  when "100" =>
708  if(R_IS_C(7 downto 5) = not R_IS_E(7 downto 5))then
709  NEXT_TYPE_T <= '1';
710  else
711  NEXT_TYPE_T <= '0';
712  end if;
713  rx_raw_ps2(63 downto 0) <= c_raw(63 downto 40) & x"fd" & RxD(39 downto 8);
714  when "101" =>
715  if(R_IS_C(7 downto 6) = not R_IS_E(7 downto 6))then
716  NEXT_TYPE_T <= '1';
717  else
718  NEXT_TYPE_T <= '0';
719  end if;
720  rx_raw_ps2(63 downto 0) <= c_raw(63 downto 48) & x"fd" & RxD(47 downto 8);
721  when "110" =>
722  if(R_IS_C(7) = not R_IS_E(7))then
723  NEXT_TYPE_T <= '1';
724  else
725  NEXT_TYPE_T <= '0';
726  end if;
727  rx_raw_ps2(63 downto 0) <= c_raw(63 downto 56) & x"fd" & RxD(55 downto 8);
728  when others =>
729  NEXT_TYPE_T <= '1';
730  rx_raw_ps2(63 downto 0) <= x"fd" & RxD(63 downto 8);
731  end case;
732  else
733  NEXT_TYPE_T <= '0';
734  end if;
735  end if;
736  T4567 <= RxD(6);
737 -- pipeline stage 3
738  R_TYPE_C <= NEXT_TYPE_C;
739  R_TYPE_D <= NEXT_TYPE_D;
740  R_TYPE_S <= NEXT_TYPE_S;
741  R_TYPE_T <= NEXT_TYPE_T;
742  rx_raw_ps3 <= rx_raw_ps2(63 downto 32) & rx_raw_ps2(71 downto 68) & rx_raw_ps2(31 downto 0) & rx_raw_ps2(67 downto 64);
743  R_IS_IDLE(3 downto 2) <= R_IS_IDLE(1 downto 0);
744  R_IS_RF(3 downto 2) <= R_IS_RF(1 downto 0);
745  R_IS_LF(3 downto 2) <= R_IS_LF(1 downto 0);
746  end if;
747 -- pipeline stage 4
748  if(reset = '1' or BLOCK_LOCK = '0')then
749  R_state <= RX_INIT;
750  rx_raw <= LBLOCK_R;
751  R_IS_LF(5 downto 4) <= "11";
752  R_IS_RF(5 downto 4) <= "00";
753  R_IS_IDLE(5 downto 4) <= "00";
754  elsif(GTX_RXHEADERVLD_dl(0) = '1')then
755  case R_state is
756  when RX_INIT =>
757  rx_raw <= rx_raw_ps3;
758  R_IS_LF(5 downto 4) <= "11";
759  R_IS_RF(5 downto 4) <= "00";
760  R_IS_IDLE(5 downto 4) <= "00";
761  if(R_TYPE_C = '1')then
762  R_state <= RX_C;
763  elsif(R_TYPE_S = '1')then
764  R_state <= RX_D;
765  else
766  R_state <= RX_E;
767  rx_raw <= EBLOCK_R;
768  end if;
769  when RX_C =>
770  R_IS_LF(5 downto 4) <= R_IS_LF(3 downto 2);
771  R_IS_RF(5 downto 4) <= R_IS_RF(3 downto 2);
772  R_IS_IDLE(5 downto 4) <= R_IS_IDLE(3 downto 2);
773  rx_raw <= rx_raw_ps3;
774  if(R_TYPE_S = '1')then
775  R_state <= RX_D;
776  elsif(R_TYPE_C = '0')then
777  R_state <= RX_E;
778  rx_raw <= EBLOCK_R;
779  end if;
780  when RX_D =>
781  R_IS_LF(5 downto 4) <= R_IS_LF(3 downto 2);
782  R_IS_RF(5 downto 4) <= R_IS_RF(3 downto 2);
783  R_IS_IDLE(5 downto 4) <= R_IS_IDLE(3 downto 2);
784  rx_raw <= rx_raw_ps3;
785  if(R_TYPE_T = '1' and (NEXT_TYPE_C = '1' or NEXT_TYPE_S = '1'))then
786  R_state <= RX_T;
787  elsif(R_TYPE_D = '0')then
788  R_state <= RX_E;
789  rx_raw <= EBLOCK_R;
790  end if;
791  when RX_T =>
792  R_IS_LF(5 downto 4) <= R_IS_LF(3 downto 2);
793  R_IS_RF(5 downto 4) <= R_IS_RF(3 downto 2);
794  R_IS_IDLE(5 downto 4) <= R_IS_IDLE(3 downto 2);
795  rx_raw <= rx_raw_ps3;
796  if(R_TYPE_S = '1')then
797  R_state <= RX_D;
798  else
799  R_state <= RX_C;
800  end if;
801  when others =>
802  rx_raw <= rx_raw_ps3;
803  R_IS_LF(5 downto 4) <= "00";
804  R_IS_RF(5 downto 4) <= "00";
805  R_IS_IDLE(5 downto 4) <= "00";
806  if(R_TYPE_C = '1')then
807  R_state <= RX_C;
808  elsif(R_TYPE_D = '1')then
809  R_state <= RX_D;
810  elsif(R_TYPE_T = '1' and (NEXT_TYPE_C = '1' or NEXT_TYPE_S = '1'))then
811  R_state <= RX_T;
812  else
813  rx_raw <= EBLOCK_R;
814  end if;
815  end case;
816  end if;
817  end if;
818 end process;
819 process(RXUSRCLK,reset)
820 begin
821  if(reset = '1')then
822  reset_RXSyncRegs <= (others => '1');
823  en_II <= '1';
824  elsif(RXUSRCLK'event and RXUSRCLK = '1')then
825  reset_RXSyncRegs <= reset_RXSyncRegs(1 downto 0) & '0';
826  if(BLOCK_LOCK = '0')then
827  en_II <= '1';
828  elsif((GTX_RXHEADERVLD_dl(0) = '0' and and_reduce(rx_raw(3 downto 0)) = '0') or (GTX_RXHEADERVLD_dl(0) = '1' and and_reduce(rx_raw(39 downto 36)) = '0'))then
829  en_II <= '0';
830  elsif((GTX_RXHEADERVLD_dl(0) = '0' and or_reduce(rx_raw(3 downto 0)) = '1') or (GTX_RXHEADERVLD_dl(0) = '1' and or_reduce(rx_raw(39 downto 36)) = '1'))then
831  en_II <= '1';
832  end if;
833  end if;
834 end process;
835 process(RXUSRCLK)
836 begin
837  if(RXUSRCLK'event and RXUSRCLK = '1')then
838  GTX_RXDVLD_q <= GTX_RXDVLD;
839  RX_FIFO_WE <= GTX_RXHEADERVLD_dl(1) or GTX_RXHEADERVLD_dl(0);
840  if(GTX_RXHEADERVLD_dl(0) = '0')then
841  rx_raw_mux <= rx_raw(35 downto 0);
842  R_IS_LF(6) <= R_IS_LF(4);
843  R_IS_RF(6) <= R_IS_RF(4);
844  if(R_IS_IDLE(4) = '1' or (R_IS_RF(6) = '1' and R_IS_RF(4) = '1') or (R_IS_LF(6) = '1' and R_IS_LF(4) = '1'))then
845  en_DI <= '1';
846  else
847  en_DI <= '0';
848  end if;
849  else
850  rx_raw_mux <= rx_raw(71 downto 36);
851  R_IS_LF(6) <= R_IS_LF(5);
852  R_IS_RF(6) <= R_IS_RF(5);
853  if(R_IS_IDLE(5) = '1' or (R_IS_RF(6) = '1' and R_IS_RF(5) = '1') or (R_IS_LF(6) = '1' and R_IS_LF(5) = '1'))then
854  en_DI <= '1';
855  else
856  en_DI <= '0';
857  end if;
858  end if;
859  RX_FIFO_DI(36) <= en_II and insert_IDLE_l and not(RX_FIFO_DI(36) and RX_FIFO_WE);
860  RX_FIFO_DI(35 downto 0) <= rx_raw_mux;
861  skip_RX_FIFO_WE <= not (RX_FIFO_WE and skip_RX_FIFO_WE) and en_DI and delete_IDLE_l;
862  if(inh = '1' or (RX_FIFO_WE = '1' and skip_RX_FIFO_WE = '1'))then
863  delete_IDLE_l <= '0';
864  elsif(GTX_RXDVLD_q = '1' and GTX_RXDVLD = '0')then
865  delete_IDLE_l <= delete_IDLE;
866  end if;
867  if(inh = '1' or (RX_FIFO_WE = '1' and RX_FIFO_DI(36) = '1'))then
868  insert_IDLE_l <= '0';
869  elsif(GTX_RXDVLD_q = '1' and GTX_RXDVLD = '0')then
870  insert_IDLE_l <= insert_IDLE;
871  end if;
872  end if;
873 end process;
874 process(RXUSRCLK,reset)
875 begin
876  if(reset = '1')then
877  RX_FIFO_WA <= x"8";
878  RX_FIFO_RA_G0SyncRegs <= (others => '0');
879  RX_FIFO_RA_G1SyncRegs <= (others => '0');
880  RX_FIFO_RA_G2SyncRegs <= (others => '0');
881  RX_FIFO_RA_G3SyncRegs <= (others => '0');
882  RX_FIFO_RA_P <= (others => '0');
883  RX_FIFO_WA_RA_D <= (others => '0');
884  inh <= '0';
885  elsif(RXUSRCLK'event and RXUSRCLK = '1')then
886  if(RX_FIFO_WE = '1' and skip_RX_FIFO_WE = '0')then
887  RX_FIFO_WA <= RX_FIFO_WA + 1;
888  end if;
889  RX_FIFO_RA_G0SyncRegs <= RX_FIFO_RA_G0SyncRegs(1 downto 0) & RX_FIFO_RA_G(0);
890  RX_FIFO_RA_G1SyncRegs <= RX_FIFO_RA_G1SyncRegs(1 downto 0) & RX_FIFO_RA_G(1);
891  RX_FIFO_RA_G2SyncRegs <= RX_FIFO_RA_G2SyncRegs(1 downto 0) & RX_FIFO_RA_G(2);
892  RX_FIFO_RA_G3SyncRegs <= RX_FIFO_RA_G3SyncRegs(1 downto 0) & RX_FIFO_RA_G(3);
893  RX_FIFO_RA_P(3) <= RX_FIFO_RA_G3SyncRegs(2);
894  RX_FIFO_RA_P(2) <= RX_FIFO_RA_G3SyncRegs(2) xor RX_FIFO_RA_G2SyncRegs(2);
895  RX_FIFO_RA_P(1) <= RX_FIFO_RA_G3SyncRegs(2) xor RX_FIFO_RA_G2SyncRegs(2) xor RX_FIFO_RA_G1SyncRegs(2);
896  RX_FIFO_RA_P(0) <= RX_FIFO_RA_G3SyncRegs(2) xor RX_FIFO_RA_G2SyncRegs(2) xor RX_FIFO_RA_G1SyncRegs(2) xor RX_FIFO_RA_G0SyncRegs(2);
897  RX_FIFO_WA_RA_D <= RX_FIFO_WA - RX_FIFO_RA_P;
898  if(RX_FIFO_WE = '1' and (skip_RX_FIFO_WE = '1' or RX_FIFO_DI(36) = '1'))then
899  inh <= '1';
900  elsif(inh_cntr(3) = '1')then
901  inh <= '0';
902  end if;
903  if(inh = '0')then
904  inh_cntr <= (others => '0');
905  elsif(GTX_RXHEADERVLD_dl(0) = '1')then
906  inh_cntr <= inh_cntr + 1;
907  end if;
908  end if;
909 end process;
910 i_delete_IDLE : ROM32X1
911  generic map (
912  INIT => X"0000c01f")
913  port map (
914  O => delete_IDLE, -- ROM output
915  A0 => RX_FIFO_WA_RA_D(0), -- ROM address[0]
916  A1 => RX_FIFO_WA_RA_D(1), -- ROM address[1]
917  A2 => RX_FIFO_WA_RA_D(2), -- ROM address[2]
918  A3 => RX_FIFO_WA_RA_D(3), -- ROM address[3]
919  A4 => '0' -- ROM address[4]
920  );
921 i_insert_IDLE : ROM32X1
922  generic map (
923  INIT => X"00000fe0")
924  port map (
925  O => insert_IDLE, -- ROM output
926  A0 => RX_FIFO_WA_RA_D(0), -- ROM address[0]
927  A1 => RX_FIFO_WA_RA_D(1), -- ROM address[1]
928  A2 => RX_FIFO_WA_RA_D(2), -- ROM address[2]
929  A3 => RX_FIFO_WA_RA_D(3), -- ROM address[3]
930  A4 => '0' -- ROM address[4]
931  );
932 g_RX_FIFO: for i in 0 to 36 generate
933  i_RX_FIFO : RAM32X1D
934  generic map (
935  INIT => RxIdle(i)) -- Initial contents of RAM
936  port map (
937  DPO => RX_FIFO_DO(i), -- Read-only 1-bit data output
938  SPO => open, -- R/W 1-bit data output
939  A0 => RX_FIFO_WA(0), -- R/W address[0] input bit
940  A1 => RX_FIFO_WA(1), -- R/W address[1] input bit
941  A2 => RX_FIFO_WA(2), -- R/W address[2] input bit
942  A3 => RX_FIFO_WA(3), -- R/W address[3] input bit
943  A4 => '0', -- R/W address[4] input bit
944  D => RX_FIFO_DI(i), -- Write 1-bit data input
945  DPRA0 => RX_FIFO_RA(0), -- Read-only address[0] input bit
946  DPRA1 => RX_FIFO_RA(1), -- Read-only address[1] input bit
947  DPRA2 => RX_FIFO_RA(2), -- Read-only address[2] input bit
948  DPRA3 => RX_FIFO_RA(3), -- Read-only address[3] input bit
949  DPRA4 => ec_RX_FIFO_RAn, -- Read-only address[4] input bit
950  WCLK => RXUSRCLK, -- Write clock input
951  WE => RX_FIFO_WE -- Write enable input
952  );
953 end generate;
954 -- add or remove idle(Ordered set) will be decided at the RX_FIFO write side
955 process(clk2x)
956 begin
957  if(clk2x'event and clk2x = '1')then
958  ec_RX_FIFO_RAn <= RX_FIFO_DO(36);
959  if(reset = '1')then
960  RX_FIFO_RA <= (others => '0');
961  RX_FIFO_RA_G <= (others => '0');
962  else
963  if(ec_RX_FIFO_RAn = '0')then
964  RX_FIFO_RA <= RX_FIFO_RA +1;
965  end if;
966  RX_FIFO_RA_G(3) <= RX_FIFO_RA(3);
967  RX_FIFO_RA_G(2) <= RX_FIFO_RA(3) xor RX_FIFO_RA(2);
968  RX_FIFO_RA_G(1) <= RX_FIFO_RA(2) xor RX_FIFO_RA(1);
969  RX_FIFO_RA_G(0) <= RX_FIFO_RA(1) xor RX_FIFO_RA(0);
970  end if;
971  PhyEmacRxC <= RX_FIFO_DO(3 downto 0);
972  PhyEmacRxD <= RX_FIFO_DO(35 downto 4);
973  end if;
974 end process;
975 end Behavioral;
976 
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