AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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sfp3_v2_7.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : sfp3_v2_7.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module SFP3_v2_7 (a GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 library UNISIM;
68 use UNISIM.VCOMPONENTS.ALL;
69 
70 
71 --***************************** Entity Declaration ****************************
72 
73 entity SFP3_v2_7 is
74 generic
75 (
76  QPLL_FBDIV_TOP : integer := 66;
77 
78  -- Simulation attributes
79  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
80  RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
81  PMA_RSV_IN : bit_vector := x"001E7080"
82 
83 );
84 port
85 (
86  --_________________________________________________________________________
87  --_________________________________________________________________________
88  --GT0 (X0Y12)
89  --____________________________CHANNEL PORTS________________________________
90  ---------------------------- Channel - DRP Ports --------------------------
91  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
92  GT0_DRPCLK_IN : in std_logic;
93  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
94  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
95  GT0_DRPEN_IN : in std_logic;
96  GT0_DRPRDY_OUT : out std_logic;
97  GT0_DRPWE_IN : in std_logic;
98  ------------------------------- Loopback Ports -----------------------------
99  GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
100  ------------------------------ Power-Down Ports ----------------------------
101  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
102  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
103  --------------------- RX Initialization and Reset Ports --------------------
104  GT0_RXUSERRDY_IN : in std_logic;
105  -------------------------- RX Margin Analysis Ports ------------------------
106  GT0_EYESCANDATAERROR_OUT : out std_logic;
107  ------------------------- Receive Ports - CDR Ports ------------------------
108  GT0_RXCDRLOCK_OUT : out std_logic;
109  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
110  GT0_RXUSRCLK_IN : in std_logic;
111  GT0_RXUSRCLK2_IN : in std_logic;
112  ------------------ Receive Ports - FPGA RX interface Ports -----------------
113  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
114  ------------------- Receive Ports - Pattern Checker Ports ------------------
115  GT0_RXPRBSERR_OUT : out std_logic;
116  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
117  ------------------- Receive Ports - Pattern Checker ports ------------------
118  GT0_RXPRBSCNTRESET_IN : in std_logic;
119  --------------------------- Receive Ports - RX AFE -------------------------
120  GT0_GTXRXP_IN : in std_logic;
121  ------------------------ Receive Ports - RX AFE Ports ----------------------
122  GT0_GTXRXN_IN : in std_logic;
123  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
124  GT0_RXBUFRESET_IN : in std_logic;
125  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
126  --------------------- Receive Ports - RX Equalizer Ports -------------------
127  GT0_RXDFEAGCHOLD_IN : in std_logic;
128  GT0_RXDFELFHOLD_IN : in std_logic;
129  --------------- Receive Ports - RX Fabric Output Control Ports -------------
130  GT0_RXOUTCLK_OUT : out std_logic;
131  ---------------------- Receive Ports - RX Gearbox Ports --------------------
132  GT0_RXDATAVALID_OUT : out std_logic;
133  GT0_RXHEADER_OUT : out std_logic_vector(1 downto 0);
134  GT0_RXHEADERVALID_OUT : out std_logic;
135  --------------------- Receive Ports - RX Gearbox Ports --------------------
136  GT0_RXGEARBOXSLIP_IN : in std_logic;
137  ------------- Receive Ports - RX Initialization and Reset Ports ------------
138  GT0_GTRXRESET_IN : in std_logic;
139  GT0_RXPCSRESET_IN : in std_logic;
140  GT0_RXPMARESET_IN : in std_logic;
141  ------------------ Receive Ports - RX Margin Analysis ports ----------------
142  GT0_RXLPMEN_IN : in std_logic;
143  -------------- Receive Ports -RX Initialization and Reset Ports ------------
144  GT0_RXRESETDONE_OUT : out std_logic;
145  --------------------- TX Initialization and Reset Ports --------------------
146  GT0_GTTXRESET_IN : in std_logic;
147  GT0_TXUSERRDY_IN : in std_logic;
148  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
149  GT0_TXUSRCLK_IN : in std_logic;
150  GT0_TXUSRCLK2_IN : in std_logic;
151  --------------- Transmit Ports - TX Configurable Driver Ports --------------
152  GT0_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
153  GT0_TXINHIBIT_IN : in std_logic;
154  GT0_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
155  ------------------ Transmit Ports - TX Data Path interface -----------------
156  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
157  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
158  GT0_GTXTXN_OUT : out std_logic;
159  GT0_GTXTXP_OUT : out std_logic;
160  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
161  GT0_TXOUTCLK_OUT : out std_logic;
162  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
163  GT0_TXOUTCLKPCS_OUT : out std_logic;
164  --------------------- Transmit Ports - TX Gearbox Ports --------------------
165  GT0_TXHEADER_IN : in std_logic_vector(1 downto 0);
166  GT0_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
167  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
168  GT0_TXPCSRESET_IN : in std_logic;
169  GT0_TXRESETDONE_OUT : out std_logic;
170  ------------------ Transmit Ports - pattern Generator Ports ----------------
171  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
172 
173  --GT1 (X0Y13)
174  --____________________________CHANNEL PORTS________________________________
175  ---------------------------- Channel - DRP Ports --------------------------
176  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
177  GT1_DRPCLK_IN : in std_logic;
178  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
179  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
180  GT1_DRPEN_IN : in std_logic;
181  GT1_DRPRDY_OUT : out std_logic;
182  GT1_DRPWE_IN : in std_logic;
183  ------------------------------- Loopback Ports -----------------------------
184  GT1_LOOPBACK_IN : in std_logic_vector(2 downto 0);
185  ------------------------------ Power-Down Ports ----------------------------
186  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
187  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
188  --------------------- RX Initialization and Reset Ports --------------------
189  GT1_RXUSERRDY_IN : in std_logic;
190  -------------------------- RX Margin Analysis Ports ------------------------
191  GT1_EYESCANDATAERROR_OUT : out std_logic;
192  ------------------------- Receive Ports - CDR Ports ------------------------
193  GT1_RXCDRLOCK_OUT : out std_logic;
194  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
195  GT1_RXUSRCLK_IN : in std_logic;
196  GT1_RXUSRCLK2_IN : in std_logic;
197  ------------------ Receive Ports - FPGA RX interface Ports -----------------
198  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
199  ------------------- Receive Ports - Pattern Checker Ports ------------------
200  GT1_RXPRBSERR_OUT : out std_logic;
201  GT1_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
202  ------------------- Receive Ports - Pattern Checker ports ------------------
203  GT1_RXPRBSCNTRESET_IN : in std_logic;
204  --------------------------- Receive Ports - RX AFE -------------------------
205  GT1_GTXRXP_IN : in std_logic;
206  ------------------------ Receive Ports - RX AFE Ports ----------------------
207  GT1_GTXRXN_IN : in std_logic;
208  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
209  GT1_RXBUFRESET_IN : in std_logic;
210  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
211  --------------------- Receive Ports - RX Equalizer Ports -------------------
212  GT1_RXDFEAGCHOLD_IN : in std_logic;
213  GT1_RXDFELFHOLD_IN : in std_logic;
214  --------------- Receive Ports - RX Fabric Output Control Ports -------------
215  GT1_RXOUTCLK_OUT : out std_logic;
216  ---------------------- Receive Ports - RX Gearbox Ports --------------------
217  GT1_RXDATAVALID_OUT : out std_logic;
218  GT1_RXHEADER_OUT : out std_logic_vector(1 downto 0);
219  GT1_RXHEADERVALID_OUT : out std_logic;
220  --------------------- Receive Ports - RX Gearbox Ports --------------------
221  GT1_RXGEARBOXSLIP_IN : in std_logic;
222  ------------- Receive Ports - RX Initialization and Reset Ports ------------
223  GT1_GTRXRESET_IN : in std_logic;
224  GT1_RXPCSRESET_IN : in std_logic;
225  GT1_RXPMARESET_IN : in std_logic;
226  ------------------ Receive Ports - RX Margin Analysis ports ----------------
227  GT1_RXLPMEN_IN : in std_logic;
228  -------------- Receive Ports -RX Initialization and Reset Ports ------------
229  GT1_RXRESETDONE_OUT : out std_logic;
230  --------------------- TX Initialization and Reset Ports --------------------
231  GT1_GTTXRESET_IN : in std_logic;
232  GT1_TXUSERRDY_IN : in std_logic;
233  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
234  GT1_TXUSRCLK_IN : in std_logic;
235  GT1_TXUSRCLK2_IN : in std_logic;
236  --------------- Transmit Ports - TX Configurable Driver Ports --------------
237  GT1_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
238  GT1_TXINHIBIT_IN : in std_logic;
239  GT1_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
240  ------------------ Transmit Ports - TX Data Path interface -----------------
241  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
242  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
243  GT1_GTXTXN_OUT : out std_logic;
244  GT1_GTXTXP_OUT : out std_logic;
245  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
246  GT1_TXOUTCLK_OUT : out std_logic;
247  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
248  GT1_TXOUTCLKPCS_OUT : out std_logic;
249  --------------------- Transmit Ports - TX Gearbox Ports --------------------
250  GT1_TXHEADER_IN : in std_logic_vector(1 downto 0);
251  GT1_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
252  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
253  GT1_TXPCSRESET_IN : in std_logic;
254  GT1_TXRESETDONE_OUT : out std_logic;
255  ------------------ Transmit Ports - pattern Generator Ports ----------------
256  GT1_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
257 
258  --GT2 (X0Y14)
259  --____________________________CHANNEL PORTS________________________________
260  ---------------------------- Channel - DRP Ports --------------------------
261  GT2_DRPADDR_IN : in std_logic_vector(8 downto 0);
262  GT2_DRPCLK_IN : in std_logic;
263  GT2_DRPDI_IN : in std_logic_vector(15 downto 0);
264  GT2_DRPDO_OUT : out std_logic_vector(15 downto 0);
265  GT2_DRPEN_IN : in std_logic;
266  GT2_DRPRDY_OUT : out std_logic;
267  GT2_DRPWE_IN : in std_logic;
268  ------------------------------- Loopback Ports -----------------------------
269  GT2_LOOPBACK_IN : in std_logic_vector(2 downto 0);
270  ------------------------------ Power-Down Ports ----------------------------
271  GT2_RXPD_IN : in std_logic_vector(1 downto 0);
272  GT2_TXPD_IN : in std_logic_vector(1 downto 0);
273  --------------------- RX Initialization and Reset Ports --------------------
274  GT2_RXUSERRDY_IN : in std_logic;
275  -------------------------- RX Margin Analysis Ports ------------------------
276  GT2_EYESCANDATAERROR_OUT : out std_logic;
277  ------------------------- Receive Ports - CDR Ports ------------------------
278  GT2_RXCDRLOCK_OUT : out std_logic;
279  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
280  GT2_RXUSRCLK_IN : in std_logic;
281  GT2_RXUSRCLK2_IN : in std_logic;
282  ------------------ Receive Ports - FPGA RX interface Ports -----------------
283  GT2_RXDATA_OUT : out std_logic_vector(31 downto 0);
284  ------------------- Receive Ports - Pattern Checker Ports ------------------
285  GT2_RXPRBSERR_OUT : out std_logic;
286  GT2_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
287  ------------------- Receive Ports - Pattern Checker ports ------------------
288  GT2_RXPRBSCNTRESET_IN : in std_logic;
289  --------------------------- Receive Ports - RX AFE -------------------------
290  GT2_GTXRXP_IN : in std_logic;
291  ------------------------ Receive Ports - RX AFE Ports ----------------------
292  GT2_GTXRXN_IN : in std_logic;
293  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
294  GT2_RXBUFRESET_IN : in std_logic;
295  GT2_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
296  --------------------- Receive Ports - RX Equalizer Ports -------------------
297  GT2_RXDFEAGCHOLD_IN : in std_logic;
298  GT2_RXDFELFHOLD_IN : in std_logic;
299  --------------- Receive Ports - RX Fabric Output Control Ports -------------
300  GT2_RXOUTCLK_OUT : out std_logic;
301  ---------------------- Receive Ports - RX Gearbox Ports --------------------
302  GT2_RXDATAVALID_OUT : out std_logic;
303  GT2_RXHEADER_OUT : out std_logic_vector(1 downto 0);
304  GT2_RXHEADERVALID_OUT : out std_logic;
305  --------------------- Receive Ports - RX Gearbox Ports --------------------
306  GT2_RXGEARBOXSLIP_IN : in std_logic;
307  ------------- Receive Ports - RX Initialization and Reset Ports ------------
308  GT2_GTRXRESET_IN : in std_logic;
309  GT2_RXPCSRESET_IN : in std_logic;
310  GT2_RXPMARESET_IN : in std_logic;
311  ------------------ Receive Ports - RX Margin Analysis ports ----------------
312  GT2_RXLPMEN_IN : in std_logic;
313  -------------- Receive Ports -RX Initialization and Reset Ports ------------
314  GT2_RXRESETDONE_OUT : out std_logic;
315  --------------------- TX Initialization and Reset Ports --------------------
316  GT2_GTTXRESET_IN : in std_logic;
317  GT2_TXUSERRDY_IN : in std_logic;
318  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
319  GT2_TXUSRCLK_IN : in std_logic;
320  GT2_TXUSRCLK2_IN : in std_logic;
321  --------------- Transmit Ports - TX Configurable Driver Ports --------------
322  GT2_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
323  GT2_TXINHIBIT_IN : in std_logic;
324  GT2_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
325  ------------------ Transmit Ports - TX Data Path interface -----------------
326  GT2_TXDATA_IN : in std_logic_vector(31 downto 0);
327  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
328  GT2_GTXTXN_OUT : out std_logic;
329  GT2_GTXTXP_OUT : out std_logic;
330  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
331  GT2_TXOUTCLK_OUT : out std_logic;
332  GT2_TXOUTCLKFABRIC_OUT : out std_logic;
333  GT2_TXOUTCLKPCS_OUT : out std_logic;
334  --------------------- Transmit Ports - TX Gearbox Ports --------------------
335  GT2_TXHEADER_IN : in std_logic_vector(1 downto 0);
336  GT2_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
337  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
338  GT2_TXPCSRESET_IN : in std_logic;
339  GT2_TXRESETDONE_OUT : out std_logic;
340  ------------------ Transmit Ports - pattern Generator Ports ----------------
341  GT2_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
342 
343 
344  --____________________________COMMON PORTS________________________________
345  ---------------------- Common Block - Ref Clock Ports ---------------------
346  GT0_GTREFCLK0_COMMON_IN : in std_logic;
347  ------------------------- Common Block - QPLL Ports ------------------------
348  GT0_QPLLLOCK_OUT : out std_logic;
349  GT0_QPLLLOCKDETCLK_IN : in std_logic;
350  GT0_QPLLREFCLKLOST_OUT : out std_logic;
351  GT0_QPLLRESET_IN : in std_logic
352 
353 
354 );
355 
356 
357 end SFP3_v2_7;
358 
359 architecture RTL of SFP3_v2_7 is
360 
361  attribute CORE_GENERATION_INFO : string;
362  attribute CORE_GENERATION_INFO of RTL : architecture is "SFP3_v2_7,gtwizard_v2_7,{protocol_file=10GBASE-R}";
363 
364 
365 --***********************************Parameter Declarations********************
366 
367  constant DLY : time := 1 ns;
368 
369 --***************************** Signal Declarations *****************************
370 
371  -- ground and tied_to_vcc_i signals
372  signal tied_to_ground_i : std_logic;
373  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
374  signal tied_to_vcc_i : std_logic;
375  signal gt0_qplloutclk_i : std_logic;
376  signal gt0_qplloutrefclk_i : std_logic;
377 
378 
379  signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0);
380  signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0);
381 
382  signal gt1_mgtrefclktx_i : std_logic_vector(1 downto 0);
383  signal gt1_mgtrefclkrx_i : std_logic_vector(1 downto 0);
384 
385  signal gt2_mgtrefclktx_i : std_logic_vector(1 downto 0);
386  signal gt2_mgtrefclkrx_i : std_logic_vector(1 downto 0);
387 
388 
389  signal gt0_qpllclk_i : std_logic;
390  signal gt0_qpllrefclk_i : std_logic;
391  signal gt1_qpllclk_i : std_logic;
392  signal gt1_qpllrefclk_i : std_logic;
393  signal gt2_qpllclk_i : std_logic;
394  signal gt2_qpllrefclk_i : std_logic;
395 
396 
397 --*************************** Component Declarations **************************
398 component SFP3_v2_7_GT
399 generic
400 (
401  -- Simulation attributes
402  GT_SIM_GTRESET_SPEEDUP : string := "FALSE";
403  RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
404  PMA_RSV_IN : bit_vector := X"00000000";
405  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
406 );
407 port
408 (
409  ---------------------------- Channel - DRP Ports --------------------------
410  DRPADDR_IN : in std_logic_vector(8 downto 0);
411  DRPCLK_IN : in std_logic;
412  DRPDI_IN : in std_logic_vector(15 downto 0);
413  DRPDO_OUT : out std_logic_vector(15 downto 0);
414  DRPEN_IN : in std_logic;
415  DRPRDY_OUT : out std_logic;
416  DRPWE_IN : in std_logic;
417  ------------------------------- Clocking Ports -----------------------------
418  QPLLCLK_IN : in std_logic;
419  QPLLREFCLK_IN : in std_logic;
420  ------------------------------- Loopback Ports -----------------------------
421  LOOPBACK_IN : in std_logic_vector(2 downto 0);
422  ------------------------------ Power-Down Ports ----------------------------
423  RXPD_IN : in std_logic_vector(1 downto 0);
424  TXPD_IN : in std_logic_vector(1 downto 0);
425  --------------------- RX Initialization and Reset Ports --------------------
426  RXUSERRDY_IN : in std_logic;
427  -------------------------- RX Margin Analysis Ports ------------------------
428  EYESCANDATAERROR_OUT : out std_logic;
429  ------------------------- Receive Ports - CDR Ports ------------------------
430  RXCDRLOCK_OUT : out std_logic;
431  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
432  RXUSRCLK_IN : in std_logic;
433  RXUSRCLK2_IN : in std_logic;
434  ------------------ Receive Ports - FPGA RX interface Ports -----------------
435  RXDATA_OUT : out std_logic_vector(31 downto 0);
436  ------------------- Receive Ports - Pattern Checker Ports ------------------
437  RXPRBSERR_OUT : out std_logic;
438  RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
439  ------------------- Receive Ports - Pattern Checker ports ------------------
440  RXPRBSCNTRESET_IN : in std_logic;
441  --------------------------- Receive Ports - RX AFE -------------------------
442  GTXRXP_IN : in std_logic;
443  ------------------------ Receive Ports - RX AFE Ports ----------------------
444  GTXRXN_IN : in std_logic;
445  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
446  RXBUFRESET_IN : in std_logic;
447  RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
448  --------------------- Receive Ports - RX Equalizer Ports -------------------
449  RXDFEAGCHOLD_IN : in std_logic;
450  RXDFELFHOLD_IN : in std_logic;
451  --------------- Receive Ports - RX Fabric Output Control Ports -------------
452  RXOUTCLK_OUT : out std_logic;
453  ---------------------- Receive Ports - RX Gearbox Ports --------------------
454  RXDATAVALID_OUT : out std_logic;
455  RXHEADER_OUT : out std_logic_vector(1 downto 0);
456  RXHEADERVALID_OUT : out std_logic;
457  --------------------- Receive Ports - RX Gearbox Ports --------------------
458  RXGEARBOXSLIP_IN : in std_logic;
459  ------------- Receive Ports - RX Initialization and Reset Ports ------------
460  GTRXRESET_IN : in std_logic;
461  RXPCSRESET_IN : in std_logic;
462  RXPMARESET_IN : in std_logic;
463  ------------------ Receive Ports - RX Margin Analysis ports ----------------
464  RXLPMEN_IN : in std_logic;
465  -------------- Receive Ports -RX Initialization and Reset Ports ------------
466  RXRESETDONE_OUT : out std_logic;
467  --------------------- TX Initialization and Reset Ports --------------------
468  GTTXRESET_IN : in std_logic;
469  TXUSERRDY_IN : in std_logic;
470  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
471  TXUSRCLK_IN : in std_logic;
472  TXUSRCLK2_IN : in std_logic;
473  --------------- Transmit Ports - TX Configurable Driver Ports --------------
474  TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
475  TXINHIBIT_IN : in std_logic;
476  TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
477  ------------------ Transmit Ports - TX Data Path interface -----------------
478  TXDATA_IN : in std_logic_vector(31 downto 0);
479  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
480  GTXTXN_OUT : out std_logic;
481  GTXTXP_OUT : out std_logic;
482  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
483  TXOUTCLK_OUT : out std_logic;
484  TXOUTCLKFABRIC_OUT : out std_logic;
485  TXOUTCLKPCS_OUT : out std_logic;
486  --------------------- Transmit Ports - TX Gearbox Ports --------------------
487  TXHEADER_IN : in std_logic_vector(1 downto 0);
488  TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
489  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
490  TXPCSRESET_IN : in std_logic;
491  TXRESETDONE_OUT : out std_logic;
492  ------------------ Transmit Ports - pattern Generator Ports ----------------
493  TXPRBSSEL_IN : in std_logic_vector(2 downto 0)
494 
495 
496 );
497 end component;
498 
499 
500 
501 --*************************Logic to set Attribute QPLL_FB_DIV*****************************
502  impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
503  begin
504  if (qpllfbdiv_top = 16) then
505  return "0000100000";
506  elsif (qpllfbdiv_top = 20) then
507  return "0000110000" ;
508  elsif (qpllfbdiv_top = 32) then
509  return "0001100000" ;
510  elsif (qpllfbdiv_top = 40) then
511  return "0010000000" ;
512  elsif (qpllfbdiv_top = 64) then
513  return "0011100000" ;
514  elsif (qpllfbdiv_top = 66) then
515  return "0101000000" ;
516  elsif (qpllfbdiv_top = 80) then
517  return "0100100000" ;
518  elsif (qpllfbdiv_top = 100) then
519  return "0101110000" ;
520  else
521  return "0000000000" ;
522  end if;
523  end function;
524 
525  impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
526  begin
527  if (qpllfbdiv_top = 16) then
528  return '1';
529  elsif (qpllfbdiv_top = 20) then
530  return '1' ;
531  elsif (qpllfbdiv_top = 32) then
532  return '1' ;
533  elsif (qpllfbdiv_top = 40) then
534  return '1' ;
535  elsif (qpllfbdiv_top = 64) then
536  return '1' ;
537  elsif (qpllfbdiv_top = 66) then
538  return '0' ;
539  elsif (qpllfbdiv_top = 80) then
540  return '1' ;
541  elsif (qpllfbdiv_top = 100) then
542  return '1' ;
543  else
544  return '1' ;
545  end if;
546  end function;
547 
548  constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
549  constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
550 
551 --********************************* Main Body of Code**************************
552 
553 begin
554 
555  tied_to_ground_i <= '0';
556  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
557  tied_to_vcc_i <= '1';
558  gt0_qpllclk_i <= gt0_qplloutclk_i;
559  gt0_qpllrefclk_i <= gt0_qplloutrefclk_i;
560 
561  gt1_qpllclk_i <= gt0_qplloutclk_i;
562  gt1_qpllrefclk_i <= gt0_qplloutrefclk_i;
563 
564  gt2_qpllclk_i <= gt0_qplloutclk_i;
565  gt2_qpllrefclk_i <= gt0_qplloutrefclk_i;
566 
567 
568 
569  --------------------------- GT Instances -------------------------------
570 
571  --_________________________________________________________________________
572  --_________________________________________________________________________
573  --GT0 (X0Y12)
574 
575  gt0_SFP3_v2_7_i : SFP3_v2_7_GT
576  generic map
577  (
578  -- Simulation attributes
579  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
580  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
581  PMA_RSV_IN => PMA_RSV_IN,
582  PCS_RSVD_ATTR_IN => X"000000000000"
583  )
584  port map
585  (
586  ---------------------------- Channel - DRP Ports --------------------------
587  DRPADDR_IN => GT0_DRPADDR_IN,
588  DRPCLK_IN => GT0_DRPCLK_IN,
589  DRPDI_IN => GT0_DRPDI_IN ,
590  DRPDO_OUT => GT0_DRPDO_OUT,
591  DRPEN_IN => GT0_DRPEN_IN ,
592  DRPRDY_OUT => GT0_DRPRDY_OUT,
593  DRPWE_IN => GT0_DRPWE_IN ,
594  ------------------------------- Clocking Ports -----------------------------
595  QPLLCLK_IN => gt0_qpllclk_i,
596  QPLLREFCLK_IN => gt0_qpllrefclk_i,
597  ------------------------------- Loopback Ports -----------------------------
598  LOOPBACK_IN => GT0_LOOPBACK_IN,
599  ------------------------------ Power-Down Ports ----------------------------
600  RXPD_IN => GT0_RXPD_IN ,
601  TXPD_IN => GT0_TXPD_IN ,
602  --------------------- RX Initialization and Reset Ports --------------------
603  RXUSERRDY_IN => GT0_RXUSERRDY_IN,
604  -------------------------- RX Margin Analysis Ports ------------------------
605  EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
606  ------------------------- Receive Ports - CDR Ports ------------------------
607  RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
608  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
609  RXUSRCLK_IN => GT0_RXUSRCLK_IN,
610  RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
611  ------------------ Receive Ports - FPGA RX interface Ports -----------------
612  RXDATA_OUT => GT0_RXDATA_OUT,
613  ------------------- Receive Ports - Pattern Checker Ports ------------------
614  RXPRBSERR_OUT => GT0_RXPRBSERR_OUT,
615  RXPRBSSEL_IN => GT0_RXPRBSSEL_IN,
616  ------------------- Receive Ports - Pattern Checker ports ------------------
617  RXPRBSCNTRESET_IN => GT0_RXPRBSCNTRESET_IN ,
618  --------------------------- Receive Ports - RX AFE -------------------------
619  GTXRXP_IN => GT0_GTXRXP_IN,
620  ------------------------ Receive Ports - RX AFE Ports ----------------------
621  GTXRXN_IN => GT0_GTXRXN_IN,
622  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
623  RXBUFRESET_IN => GT0_RXBUFRESET_IN,
624  RXBUFSTATUS_OUT => GT0_RXBUFSTATUS_OUT ,
625  --------------------- Receive Ports - RX Equalizer Ports -------------------
626  RXDFEAGCHOLD_IN => GT0_RXDFEAGCHOLD_IN ,
627  RXDFELFHOLD_IN => GT0_RXDFELFHOLD_IN,
628  --------------- Receive Ports - RX Fabric Output Control Ports -------------
629  RXOUTCLK_OUT => GT0_RXOUTCLK_OUT,
630  ---------------------- Receive Ports - RX Gearbox Ports --------------------
631  RXDATAVALID_OUT => GT0_RXDATAVALID_OUT ,
632  RXHEADER_OUT => GT0_RXHEADER_OUT,
633  RXHEADERVALID_OUT => GT0_RXHEADERVALID_OUT ,
634  --------------------- Receive Ports - RX Gearbox Ports --------------------
635  RXGEARBOXSLIP_IN => GT0_RXGEARBOXSLIP_IN ,
636  ------------- Receive Ports - RX Initialization and Reset Ports ------------
637  GTRXRESET_IN => GT0_GTRXRESET_IN,
638  RXPCSRESET_IN => GT0_RXPCSRESET_IN,
639  RXPMARESET_IN => GT0_RXPMARESET_IN,
640  ------------------ Receive Ports - RX Margin Analysis ports ----------------
641  RXLPMEN_IN => GT0_RXLPMEN_IN,
642  -------------- Receive Ports -RX Initialization and Reset Ports ------------
643  RXRESETDONE_OUT => GT0_RXRESETDONE_OUT ,
644  --------------------- TX Initialization and Reset Ports --------------------
645  GTTXRESET_IN => GT0_GTTXRESET_IN,
646  TXUSERRDY_IN => GT0_TXUSERRDY_IN,
647  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
648  TXUSRCLK_IN => GT0_TXUSRCLK_IN,
649  TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
650  --------------- Transmit Ports - TX Configurable Driver Ports --------------
651  TXDIFFCTRL_IN => GT0_TXDIFFCTRL_IN,
652  TXINHIBIT_IN => GT0_TXINHIBIT_IN,
653  TXMAINCURSOR_IN => GT0_TXMAINCURSOR_IN ,
654  ------------------ Transmit Ports - TX Data Path interface -----------------
655  TXDATA_IN => GT0_TXDATA_IN,
656  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
657  GTXTXN_OUT => GT0_GTXTXN_OUT,
658  GTXTXP_OUT => GT0_GTXTXP_OUT,
659  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
660  TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
661  TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT ,
662  TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT ,
663  --------------------- Transmit Ports - TX Gearbox Ports --------------------
664  TXHEADER_IN => GT0_TXHEADER_IN,
665  TXSEQUENCE_IN => GT0_TXSEQUENCE_IN,
666  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
667  TXPCSRESET_IN => GT0_TXPCSRESET_IN,
668  TXRESETDONE_OUT => GT0_TXRESETDONE_OUT ,
669  ------------------ Transmit Ports - pattern Generator Ports ----------------
670  TXPRBSSEL_IN => GT0_TXPRBSSEL_IN
671 
672  );
673 
674  --_________________________________________________________________________
675  --_________________________________________________________________________
676  --GT1 (X0Y13)
677 
678  gt1_SFP3_v2_7_i : SFP3_v2_7_GT
679  generic map
680  (
681  -- Simulation attributes
682  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
683  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
684  PMA_RSV_IN => PMA_RSV_IN,
685  PCS_RSVD_ATTR_IN => X"000000000000"
686  )
687  port map
688  (
689  ---------------------------- Channel - DRP Ports --------------------------
690  DRPADDR_IN => GT1_DRPADDR_IN,
691  DRPCLK_IN => GT1_DRPCLK_IN,
692  DRPDI_IN => GT1_DRPDI_IN ,
693  DRPDO_OUT => GT1_DRPDO_OUT,
694  DRPEN_IN => GT1_DRPEN_IN ,
695  DRPRDY_OUT => GT1_DRPRDY_OUT,
696  DRPWE_IN => GT1_DRPWE_IN ,
697  ------------------------------- Clocking Ports -----------------------------
698  QPLLCLK_IN => gt1_qpllclk_i,
699  QPLLREFCLK_IN => gt1_qpllrefclk_i,
700  ------------------------------- Loopback Ports -----------------------------
701  LOOPBACK_IN => GT1_LOOPBACK_IN,
702  ------------------------------ Power-Down Ports ----------------------------
703  RXPD_IN => GT1_RXPD_IN ,
704  TXPD_IN => GT1_TXPD_IN ,
705  --------------------- RX Initialization and Reset Ports --------------------
706  RXUSERRDY_IN => GT1_RXUSERRDY_IN,
707  -------------------------- RX Margin Analysis Ports ------------------------
708  EYESCANDATAERROR_OUT => GT1_EYESCANDATAERROR_OUT,
709  ------------------------- Receive Ports - CDR Ports ------------------------
710  RXCDRLOCK_OUT => GT1_RXCDRLOCK_OUT,
711  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
712  RXUSRCLK_IN => GT1_RXUSRCLK_IN,
713  RXUSRCLK2_IN => GT1_RXUSRCLK2_IN,
714  ------------------ Receive Ports - FPGA RX interface Ports -----------------
715  RXDATA_OUT => GT1_RXDATA_OUT,
716  ------------------- Receive Ports - Pattern Checker Ports ------------------
717  RXPRBSERR_OUT => GT1_RXPRBSERR_OUT,
718  RXPRBSSEL_IN => GT1_RXPRBSSEL_IN,
719  ------------------- Receive Ports - Pattern Checker ports ------------------
720  RXPRBSCNTRESET_IN => GT1_RXPRBSCNTRESET_IN ,
721  --------------------------- Receive Ports - RX AFE -------------------------
722  GTXRXP_IN => GT1_GTXRXP_IN,
723  ------------------------ Receive Ports - RX AFE Ports ----------------------
724  GTXRXN_IN => GT1_GTXRXN_IN,
725  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
726  RXBUFRESET_IN => GT1_RXBUFRESET_IN,
727  RXBUFSTATUS_OUT => GT1_RXBUFSTATUS_OUT ,
728  --------------------- Receive Ports - RX Equalizer Ports -------------------
729  RXDFEAGCHOLD_IN => GT1_RXDFEAGCHOLD_IN ,
730  RXDFELFHOLD_IN => GT1_RXDFELFHOLD_IN,
731  --------------- Receive Ports - RX Fabric Output Control Ports -------------
732  RXOUTCLK_OUT => GT1_RXOUTCLK_OUT,
733  ---------------------- Receive Ports - RX Gearbox Ports --------------------
734  RXDATAVALID_OUT => GT1_RXDATAVALID_OUT ,
735  RXHEADER_OUT => GT1_RXHEADER_OUT,
736  RXHEADERVALID_OUT => GT1_RXHEADERVALID_OUT ,
737  --------------------- Receive Ports - RX Gearbox Ports --------------------
738  RXGEARBOXSLIP_IN => GT1_RXGEARBOXSLIP_IN ,
739  ------------- Receive Ports - RX Initialization and Reset Ports ------------
740  GTRXRESET_IN => GT1_GTRXRESET_IN,
741  RXPCSRESET_IN => GT1_RXPCSRESET_IN,
742  RXPMARESET_IN => GT1_RXPMARESET_IN,
743  ------------------ Receive Ports - RX Margin Analysis ports ----------------
744  RXLPMEN_IN => GT1_RXLPMEN_IN,
745  -------------- Receive Ports -RX Initialization and Reset Ports ------------
746  RXRESETDONE_OUT => GT1_RXRESETDONE_OUT ,
747  --------------------- TX Initialization and Reset Ports --------------------
748  GTTXRESET_IN => GT1_GTTXRESET_IN,
749  TXUSERRDY_IN => GT1_TXUSERRDY_IN,
750  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
751  TXUSRCLK_IN => GT1_TXUSRCLK_IN,
752  TXUSRCLK2_IN => GT1_TXUSRCLK2_IN,
753  --------------- Transmit Ports - TX Configurable Driver Ports --------------
754  TXDIFFCTRL_IN => GT1_TXDIFFCTRL_IN,
755  TXINHIBIT_IN => GT1_TXINHIBIT_IN,
756  TXMAINCURSOR_IN => GT1_TXMAINCURSOR_IN ,
757  ------------------ Transmit Ports - TX Data Path interface -----------------
758  TXDATA_IN => GT1_TXDATA_IN,
759  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
760  GTXTXN_OUT => GT1_GTXTXN_OUT,
761  GTXTXP_OUT => GT1_GTXTXP_OUT,
762  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
763  TXOUTCLK_OUT => GT1_TXOUTCLK_OUT,
764  TXOUTCLKFABRIC_OUT => GT1_TXOUTCLKFABRIC_OUT ,
765  TXOUTCLKPCS_OUT => GT1_TXOUTCLKPCS_OUT ,
766  --------------------- Transmit Ports - TX Gearbox Ports --------------------
767  TXHEADER_IN => GT1_TXHEADER_IN,
768  TXSEQUENCE_IN => GT1_TXSEQUENCE_IN,
769  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
770  TXPCSRESET_IN => GT1_TXPCSRESET_IN,
771  TXRESETDONE_OUT => GT1_TXRESETDONE_OUT ,
772  ------------------ Transmit Ports - pattern Generator Ports ----------------
773  TXPRBSSEL_IN => GT1_TXPRBSSEL_IN
774 
775  );
776 
777  --_________________________________________________________________________
778  --_________________________________________________________________________
779  --GT2 (X0Y14)
780 
781  gt2_SFP3_v2_7_i : SFP3_v2_7_GT
782  generic map
783  (
784  -- Simulation attributes
785  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
786  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
787  PMA_RSV_IN => PMA_RSV_IN,
788  PCS_RSVD_ATTR_IN => X"000000000000"
789  )
790  port map
791  (
792  ---------------------------- Channel - DRP Ports --------------------------
793  DRPADDR_IN => GT2_DRPADDR_IN,
794  DRPCLK_IN => GT2_DRPCLK_IN,
795  DRPDI_IN => GT2_DRPDI_IN ,
796  DRPDO_OUT => GT2_DRPDO_OUT,
797  DRPEN_IN => GT2_DRPEN_IN ,
798  DRPRDY_OUT => GT2_DRPRDY_OUT,
799  DRPWE_IN => GT2_DRPWE_IN ,
800  ------------------------------- Clocking Ports -----------------------------
801  QPLLCLK_IN => gt2_qpllclk_i,
802  QPLLREFCLK_IN => gt2_qpllrefclk_i,
803  ------------------------------- Loopback Ports -----------------------------
804  LOOPBACK_IN => GT2_LOOPBACK_IN,
805  ------------------------------ Power-Down Ports ----------------------------
806  RXPD_IN => GT2_RXPD_IN ,
807  TXPD_IN => GT2_TXPD_IN ,
808  --------------------- RX Initialization and Reset Ports --------------------
809  RXUSERRDY_IN => GT2_RXUSERRDY_IN,
810  -------------------------- RX Margin Analysis Ports ------------------------
811  EYESCANDATAERROR_OUT => GT2_EYESCANDATAERROR_OUT,
812  ------------------------- Receive Ports - CDR Ports ------------------------
813  RXCDRLOCK_OUT => GT2_RXCDRLOCK_OUT,
814  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
815  RXUSRCLK_IN => GT2_RXUSRCLK_IN,
816  RXUSRCLK2_IN => GT2_RXUSRCLK2_IN,
817  ------------------ Receive Ports - FPGA RX interface Ports -----------------
818  RXDATA_OUT => GT2_RXDATA_OUT,
819  ------------------- Receive Ports - Pattern Checker Ports ------------------
820  RXPRBSERR_OUT => GT2_RXPRBSERR_OUT,
821  RXPRBSSEL_IN => GT2_RXPRBSSEL_IN,
822  ------------------- Receive Ports - Pattern Checker ports ------------------
823  RXPRBSCNTRESET_IN => GT2_RXPRBSCNTRESET_IN ,
824  --------------------------- Receive Ports - RX AFE -------------------------
825  GTXRXP_IN => GT2_GTXRXP_IN,
826  ------------------------ Receive Ports - RX AFE Ports ----------------------
827  GTXRXN_IN => GT2_GTXRXN_IN,
828  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
829  RXBUFRESET_IN => GT2_RXBUFRESET_IN,
830  RXBUFSTATUS_OUT => GT2_RXBUFSTATUS_OUT ,
831  --------------------- Receive Ports - RX Equalizer Ports -------------------
832  RXDFEAGCHOLD_IN => GT2_RXDFEAGCHOLD_IN ,
833  RXDFELFHOLD_IN => GT2_RXDFELFHOLD_IN,
834  --------------- Receive Ports - RX Fabric Output Control Ports -------------
835  RXOUTCLK_OUT => GT2_RXOUTCLK_OUT,
836  ---------------------- Receive Ports - RX Gearbox Ports --------------------
837  RXDATAVALID_OUT => GT2_RXDATAVALID_OUT ,
838  RXHEADER_OUT => GT2_RXHEADER_OUT,
839  RXHEADERVALID_OUT => GT2_RXHEADERVALID_OUT ,
840  --------------------- Receive Ports - RX Gearbox Ports --------------------
841  RXGEARBOXSLIP_IN => GT2_RXGEARBOXSLIP_IN ,
842  ------------- Receive Ports - RX Initialization and Reset Ports ------------
843  GTRXRESET_IN => GT2_GTRXRESET_IN,
844  RXPCSRESET_IN => GT2_RXPCSRESET_IN,
845  RXPMARESET_IN => GT2_RXPMARESET_IN,
846  ------------------ Receive Ports - RX Margin Analysis ports ----------------
847  RXLPMEN_IN => GT2_RXLPMEN_IN,
848  -------------- Receive Ports -RX Initialization and Reset Ports ------------
849  RXRESETDONE_OUT => GT2_RXRESETDONE_OUT ,
850  --------------------- TX Initialization and Reset Ports --------------------
851  GTTXRESET_IN => GT2_GTTXRESET_IN,
852  TXUSERRDY_IN => GT2_TXUSERRDY_IN,
853  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
854  TXUSRCLK_IN => GT2_TXUSRCLK_IN,
855  TXUSRCLK2_IN => GT2_TXUSRCLK2_IN,
856  --------------- Transmit Ports - TX Configurable Driver Ports --------------
857  TXDIFFCTRL_IN => GT2_TXDIFFCTRL_IN,
858  TXINHIBIT_IN => GT2_TXINHIBIT_IN,
859  TXMAINCURSOR_IN => GT2_TXMAINCURSOR_IN ,
860  ------------------ Transmit Ports - TX Data Path interface -----------------
861  TXDATA_IN => GT2_TXDATA_IN,
862  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
863  GTXTXN_OUT => GT2_GTXTXN_OUT,
864  GTXTXP_OUT => GT2_GTXTXP_OUT,
865  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
866  TXOUTCLK_OUT => GT2_TXOUTCLK_OUT,
867  TXOUTCLKFABRIC_OUT => GT2_TXOUTCLKFABRIC_OUT ,
868  TXOUTCLKPCS_OUT => GT2_TXOUTCLKPCS_OUT ,
869  --------------------- Transmit Ports - TX Gearbox Ports --------------------
870  TXHEADER_IN => GT2_TXHEADER_IN,
871  TXSEQUENCE_IN => GT2_TXSEQUENCE_IN,
872  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
873  TXPCSRESET_IN => GT2_TXPCSRESET_IN,
874  TXRESETDONE_OUT => GT2_TXRESETDONE_OUT ,
875  ------------------ Transmit Ports - pattern Generator Ports ----------------
876  TXPRBSSEL_IN => GT2_TXPRBSSEL_IN
877 
878  );
879 
880  --_________________________________________________________________________
881  --_________________________________________________________________________
882  --_________________________GTXE2_COMMON____________________________________
883 
884  gtxe2_common_0_i : GTXE2_COMMON
885  generic map
886  (
887  -- Simulation attributes
888  SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
889  SIM_QPLLREFCLK_SEL => ("001"),
890  SIM_VERSION => "4.0",
891 
892 
893  ------------------COMMON BLOCK Attributes---------------
894  BIAS_CFG => (x"0000040000001000"),
895  COMMON_CFG => (x"00000000"),
896  QPLL_CFG => (x"0680181"),
897  QPLL_CLKOUT_CFG => ("0000"),
898  QPLL_COARSE_FREQ_OVRD => ("010000"),
899  QPLL_COARSE_FREQ_OVRD_EN => ('0'),
900  QPLL_CP => ("0000011111"),
901  QPLL_CP_MONITOR_EN => ('0'),
902  QPLL_DMONITOR_SEL => ('0'),
903  QPLL_FBDIV => (QPLL_FBDIV_IN),
904  QPLL_FBDIV_MONITOR_EN => ('0'),
905  QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
906  QPLL_INIT_CFG => (x"000006"),
907  QPLL_LOCK_CFG => (x"21E8"),
908  QPLL_LPF => ("1111"),
909  QPLL_REFCLK_DIV => (1)
910 
911 
912  )
913  port map
914  (
915  ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
916  DRPADDR => tied_to_ground_vec_i (7 downto 0),
917  DRPCLK => tied_to_ground_i,
918  DRPDI => tied_to_ground_vec_i (15 downto 0),
919  DRPDO => open,
920  DRPEN => tied_to_ground_i,
921  DRPRDY => open,
922  DRPWE => tied_to_ground_i,
923  ---------------------- Common Block - Ref Clock Ports ---------------------
924  GTGREFCLK => tied_to_ground_i,
925  GTNORTHREFCLK0 => tied_to_ground_i,
926  GTNORTHREFCLK1 => tied_to_ground_i,
927  GTREFCLK0 => GT0_GTREFCLK0_COMMON_IN ,
928  GTREFCLK1 => tied_to_ground_i,
929  GTSOUTHREFCLK0 => tied_to_ground_i,
930  GTSOUTHREFCLK1 => tied_to_ground_i,
931  ------------------------- Common Block - QPLL Ports -----------------------
932  QPLLDMONITOR => open,
933  ----------------------- Common Block - Clocking Ports ----------------------
934  QPLLOUTCLK => gt0_qplloutclk_i,
935  QPLLOUTREFCLK => gt0_qplloutrefclk_i ,
936  REFCLKOUTMONITOR => open,
937  ------------------------- Common Block - QPLL Ports ------------------------
938  QPLLFBCLKLOST => open,
939  QPLLLOCK => GT0_QPLLLOCK_OUT,
940  QPLLLOCKDETCLK => GT0_QPLLLOCKDETCLK_IN ,
941  QPLLLOCKEN => tied_to_vcc_i,
942  QPLLOUTRESET => tied_to_ground_i,
943  QPLLPD => tied_to_ground_i,
944  QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_OUT ,
945  QPLLREFCLKSEL => "001",
946  QPLLRESET => GT0_QPLLRESET_IN,
947  QPLLRSVD1 => "0000000000000000",
948  QPLLRSVD2 => "11111",
949  --------------------------------- QPLL Ports -------------------------------
950  BGBYPASSB => tied_to_vcc_i,
951  BGMONITORENB => tied_to_vcc_i,
952  BGPDB => tied_to_vcc_i,
953  BGRCALOVRD => "00000",
954  PMARSVD => "00000000",
955  RCALENB => tied_to_vcc_i
956 
957  );
958 
959 
960 
961 end RTL;
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