AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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HCAL_trig.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 11:06:56 07/09/2014
6 -- Design Name:
7 -- Module Name: HCAL_trig - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 -- Byte
19 -- 0 Comma character (0xBC k-char)
20 -- 1 BX0 [7] VER[6:4]=1 BX ID [11:8]
21 -- 2 Bx ID [7:0]
22 -- 3 local trigger word
23 --
24 ----------------------------------------------------------------------------------
25 library IEEE;
26 use IEEE.STD_LOGIC_1164.ALL;
27 use IEEE.STD_LOGIC_ARITH.ALL;
28 use IEEE.STD_LOGIC_UNSIGNED.ALL;
29 use IEEE.std_logic_misc.all;
30 use work.amc13_pack.all;
31 
32 -- Uncomment the following library declaration if using
33 -- arithmetic functions with Signed or Unsigned values
34 --use IEEE.NUMERIC_STD.ALL;
35 
36 -- Uncomment the following library declaration if instantiating
37 -- any Xilinx primitives in this code.
38 library UNISIM;
39 use UNISIM.VComponents.all;
40 
41 entity HCAL_trig is
42  Port ( TTC_clk : in STD_LOGIC;
43  DRPCLK : in STD_LOGIC;
44  reset : in STD_LOGIC;
45  en_HCAL_trig : in STD_LOGIC;
46  BC0 : in STD_LOGIC;
47  triggerOut : out STD_LOGIC;
48  Trigdata : in array12x8;
49 -- ipbus signals
50  ipb_clk : in STD_LOGIC;
51  ipb_write : in STD_LOGIC;
52  ipb_strobe : in STD_LOGIC;
53  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
54  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
55  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
56  GTX_REFCLKp : in STD_LOGIC;
57  GTX_REFCLKn : in STD_LOGIC;
58  GTX_RXp : in STD_LOGIC;
59  GTX_RXn : in STD_LOGIC;
60  GTX_TXp : out STD_LOGIC;
61  GTX_TXn : out STD_LOGIC);
62 end HCAL_trig;
63 
64 architecture Behavioral of HCAL_trig is
65 COMPONENT RAM32x6Db
66  PORT(
67  wclk : IN std_logic;
68  di : IN std_logic_vector(5 downto 0);
69  we : IN std_logic;
70  wa : IN std_logic_vector(4 downto 0);
71  ra : IN std_logic_vector(4 downto 0);
72  do : OUT std_logic_vector(5 downto 0)
73  );
74 END COMPONENT;
75 component uHTR_trig_init
76 generic
77 (
78  -- Simulation attributes
79  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to 1 to speed up sim reset
80  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
81  STABLE_CLOCK_PERIOD : integer := 20; --Period of the stable clock driving this state-machine, unit is [ns]
82  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
83 
84 );
85 port
86 (
87  SYSCLK_IN : in std_logic;
88  SOFT_RESET_IN : in std_logic;
89  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
90  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
91  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
92  GT0_DATA_VALID_IN : in std_logic;
93 
94  --_________________________________________________________________________
95  --GT0 (X1Y12)
96  --____________________________CHANNEL PORTS________________________________
97  --------------------------------- CPLL Ports -------------------------------
98  GT0_CPLLFBCLKLOST_OUT : out std_logic;
99  GT0_CPLLLOCK_OUT : out std_logic;
100  GT0_CPLLLOCKDETCLK_IN : in std_logic;
101  GT0_CPLLRESET_IN : in std_logic;
102  -------------------------- Channel - Clocking Ports ------------------------
103  GT0_GTREFCLK0_IN : in std_logic;
104  ---------------------------- Channel - DRP Ports --------------------------
105  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
106  GT0_DRPCLK_IN : in std_logic;
107  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
108  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
109  GT0_DRPEN_IN : in std_logic;
110  GT0_DRPRDY_OUT : out std_logic;
111  GT0_DRPWE_IN : in std_logic;
112  --------------------- RX Initialization and Reset Ports --------------------
113  GT0_RXUSERRDY_IN : in std_logic;
114  -------------------------- RX Margin Analysis Ports ------------------------
115  GT0_EYESCANDATAERROR_OUT : out std_logic;
116  ------------------------- Receive Ports - CDR Ports ------------------------
117  GT0_RXCDRLOCK_OUT : out std_logic;
118  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
119  GT0_RXUSRCLK_IN : in std_logic;
120  GT0_RXUSRCLK2_IN : in std_logic;
121  ------------------ Receive Ports - FPGA RX interface Ports -----------------
122  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
123  ------------------- Receive Ports - Pattern Checker Ports ------------------
124  GT0_RXPRBSERR_OUT : out std_logic;
125  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
126  ------------------- Receive Ports - Pattern Checker ports ------------------
127  GT0_RXPRBSCNTRESET_IN : in std_logic;
128  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
129  GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
130  GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
131  --------------------------- Receive Ports - RX AFE -------------------------
132  GT0_GTXRXP_IN : in std_logic;
133  ------------------------ Receive Ports - RX AFE Ports ----------------------
134  GT0_GTXRXN_IN : in std_logic;
135  ------------- Receive Ports - RX Initialization and Reset Ports ------------
136  GT0_GTRXRESET_IN : in std_logic;
137  GT0_RXPMARESET_IN : in std_logic;
138  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
139  GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
140  -------------- Receive Ports -RX Initialization and Reset Ports ------------
141  GT0_RXRESETDONE_OUT : out std_logic;
142  --------------------- TX Initialization and Reset Ports --------------------
143  GT0_GTTXRESET_IN : in std_logic;
144  GT0_TXUSERRDY_IN : in std_logic;
145  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
146  GT0_TXUSRCLK_IN : in std_logic;
147  GT0_TXUSRCLK2_IN : in std_logic;
148  ------------------ Transmit Ports - TX Data Path interface -----------------
149  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
150  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
151  GT0_GTXTXN_OUT : out std_logic;
152  GT0_GTXTXP_OUT : out std_logic;
153  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
154  GT0_TXOUTCLK_OUT : out std_logic;
155  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
156  GT0_TXOUTCLKPCS_OUT : out std_logic;
157  --------------------- Transmit Ports - TX Gearbox Ports --------------------
158  GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
159  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
160  GT0_TXRESETDONE_OUT : out std_logic;
161  ------------------ Transmit Ports - pattern Generator Ports ----------------
162  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
163 
164 
165  --____________________________COMMON PORTS________________________________
166  ---------------------- Common Block - Ref Clock Ports ---------------------
167  GT0_GTREFCLK0_COMMON_IN : in std_logic;
168  ------------------------- Common Block - QPLL Ports ------------------------
169  GT0_QPLLLOCK_OUT : out std_logic;
170  GT0_QPLLLOCKDETCLK_IN : in std_logic;
171  GT0_QPLLRESET_IN : in std_logic
172 
173 
174 );
175 end component;
176 signal version : std_logic_vector(2 downto 0) := "001";
177 signal MaskedTrigdata : array24x32 := (others => (others => '0'));
178 signal mask : array24x32 := (others => (others => '0'));
179 signal threshold : array8x4 := (others => (others => '0'));
180 signal NonZeroByteCnt : array16x4 := (others => (others => '0'));
181 signal NonZeroByte : std_logic_vector(95 downto 0) := (others => '0');
182 signal TrigDataOut : std_logic_vector(7 downto 0) := (others => '0');
183 signal RXDATA : std_logic_vector(31 downto 0) := (others => '0');
184 signal TXDATA : std_logic_vector(31 downto 0) := (others => '0');
185 signal Sample : std_logic := '0';
186 signal SampleSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
187 signal RXBUF_we : std_logic := '0';
188 signal RXBUF_wa : std_logic_vector(4 downto 0) := (others => '0');
189 signal RXBUF_di : std_logic_vector(29 downto 0) := (others => '0');
190 signal RXBUF : std_logic_vector(29 downto 0) := (others => '0');
191 signal PRBSSEL : std_logic_vector(2 downto 0) := (others => '0');
192 signal PRBSERR_cnt : std_logic_vector(7 downto 0) := (others => '0');
193 signal RXCHARISK : std_logic_vector(3 downto 0) := (others => '0');
194 signal txfsmresetdone : std_logic := '0';
195 signal DATA_VALID : std_logic := '0';
196 signal CPLLLOCK : std_logic := '0';
197 signal CPLLRESET : std_logic := '0';
198 signal REFCLK : std_logic := '0';
199 signal PRBSERR : std_logic := '0';
200 signal GTRXRESET : std_logic := '0';
201 signal RXRESETDONE : std_logic := '0';
202 signal GTTXRESET : std_logic := '0';
203 signal bcnt : std_logic_vector(11 downto 0) := (others => '0');
204 signal trigmask : std_logic_vector(7 downto 0) := (others => '0');
205 --signal : std_logic_vector(31 downto 0) := (others => '0');
206 --signal : std_logic_vector(31 downto 0) := (others => '0');
207 --signal : std_logic_vector(31 downto 0) := (others => '0');
208 signal en_BC0_dl : std_logic := '0';
209 signal got_BC0 : std_logic := '0';
210 signal catchBC0 : std_logic := '0';
211 signal BC0_gated : std_logic := '0';
212 signal BC0_dl : std_logic := '0';
213 begin
214 process(TTC_Clk)
215 begin
216  if(TTC_Clk'event and TTC_Clk = '1')then
217  if(BC0 = '1')then
218  bcnt <= x"001";
219  elsif(bcnt = x"deb")then
220  bcnt <= x"000";
221  else
222  bcnt <= bcnt + 1;
223  end if;
224  for i in 0 to 7 loop
225  if(en_HCAL_trig = '1' and (NonZeroByteCnt(i*2) + NonZeroByteCnt(i*2+1)) > threshold(i))then
226  TrigDataOut(i) <= '1';
227  else
228  TrigDataOut(i) <= '0';
229  end if;
230  end loop;
231  DATA_VALID <= not RXBUF_di(24);
232  if(PRBSSEL = "000")then
233  PRBSERR_cnt <= (others => '0');
234  elsif(PRBSERR = '1')then
235  PRBSERR_cnt <= PRBSERR_cnt + 1;
236  end if;
237  triggerOut <= or_reduce(trigmask and TrigDataOut);
238  SampleSyncRegs <= SampleSyncRegs(2 downto 0) & Sample;
239  if(SampleSyncRegs(3) /= SampleSyncRegs(2))then
240  RXBUF_we <= '1';
241  elsif((CatchBC0 = '0' and and_reduce(RXBUF_wa) = '1') or BC0_dl = '1')then
242  RXBUF_we <= '0';
243  end if;
244  if(RXBUF_we = '0')then
245  RXBUF_wa <= "00010";
246  elsif(and_reduce(RXBUF_wa) = '1')then
247  RXBUF_wa <= "00010";
248  else
249  RXBUF_wa <= RXBUF_wa + 1;
250  end if;
251  if(got_BC0 = '1' or RXBUF_we = '0')then
252  en_BC0_dl <= '0';
253  elsif(RXBUF_wa(4) = '1')then
254  en_BC0_dl <= '1';
255  end if;
256  if(RXBUF_we = '0')then
257  got_BC0 <= '0';
258  elsif(BC0_gated = '1')then
259  got_BC0 <= '1';
260  end if;
261  BC0_gated <= RXDATA(15) and en_BC0_dl;
262  end if;
263 end process;
264 i_BC0_dl : SRL16E
265  port map (
266  Q => BC0_dl , -- SRL data output
267  A0 => '0', -- Select[0] input
268  A1 => '1', -- Select[1] input
269  A2 => '1', -- Select[2] input
270  A3 => '1', -- Select[3] input
271  CE => '1', -- Clock enable input
272  CLK => TTC_Clk, -- Clock input
273  D => BC0_gated -- SRL data input
274  );
275 g_RXBUF : for i in 0 to 4 generate
276  i_ipbus_rbuf : RAM32x6Db PORT MAP(
277  wclk => TTC_Clk ,
278  di => RXBUF_di (i*6+5 downto i*6),
279  we => RXBUF_we ,
280  wa => RXBUF_wa ,
281  ra => ipb_addr (4 downto 0),
282  do => RXBUF(i*6+5 downto i*6)
283  );
284 end generate;
285 TXDATA <= TrigDataOut & bcnt(7 downto 0) & BC0 & version & bcnt(11 downto 8) & x"bc";
286 RXBUF_di(24) <= '0' when RXDATA(7 downto 0) = x"bc" and RXCHARISK = x"1" else '1';
287 RXBUF_di(23 downto 0) <= RXDATA(31 downto 24) & RXDATA(15 downto 8) & RXDATA(23 downto 16);
288 process(ipb_clk)
289 begin
290  if(ipb_clk'event and ipb_clk = '1')then
291  if(ipb_addr(27) = '0' and ipb_addr(15 downto 4) = x"100" and ipb_write = '1' and ipb_strobe = '1')then
292  mask(conv_integer(ipb_addr(3 downto 0))) <= ipb_wdata;
293  end if;
294  if(ipb_addr(27) = '0' and ipb_addr(15 downto 4) = x"101" and ipb_write = '1' and ipb_strobe = '1')then
295  if(ipb_addr(3) = '0')then
296  mask(16+conv_integer(ipb_addr(2 downto 0))) <= ipb_wdata;
297  else
298  threshold(conv_integer(ipb_addr(2 downto 0))) <= ipb_wdata(3 downto 0);
299  end if;
300  end if;
301  if(ipb_addr(27) = '0' and ipb_addr(15 downto 0) = x"1020" and ipb_write = '1' and ipb_strobe = '1')then
302  PRBSSEL <= ipb_wdata(2 downto 0);
303  end if;
304  if(ipb_addr(27) = '0' and ipb_addr(15 downto 0) = x"1021" and ipb_write = '1' and ipb_strobe = '1')then
305  Sample <= Sample xor ipb_wdata(0);
306  CatchBC0 <= ipb_wdata(1);
307  end if;
308  if(ipb_addr(27) = '0' and ipb_addr(15 downto 0) = x"1040" and ipb_write = '1' and ipb_strobe = '1')then
309  trigmask <= ipb_wdata(7 downto 0);
310  end if;
311  end if;
312 end process;
313 process(ipb_addr, mask, threshold)
314 begin
315  if(ipb_addr(15 downto 7) = "000100000")then
316  if(ipb_addr(6 downto 0) = "1000000")then
317  ipb_rdata <= x"000000" & trigmask;
318  elsif(ipb_addr(5 downto 4) = "00")then
319  ipb_rdata <= mask(conv_integer(ipb_addr(3 downto 0)));
320  elsif(ipb_addr(5 downto 3) = "010")then
321  ipb_rdata <= mask(16+conv_integer(ipb_addr(2 downto 0)));
322  elsif(ipb_addr(5 downto 3) = "011")then
323  ipb_rdata <= x"0000000" & threshold(conv_integer(ipb_addr(2 downto 0)));
324  elsif(ipb_addr(5 downto 0) = "100000")then
325  ipb_rdata <= x"0000000" & '0' & PRBSSEL;
326  elsif(ipb_addr(5 downto 0) = "100001")then
327  ipb_rdata <= x"000000" & PRBSERR_cnt;
328  elsif(ipb_addr(5) = '1')then
329  ipb_rdata <= RXBUF(24) & "0000000" & RXBUF(23 downto 0);
330  else
331  ipb_rdata <= (others => '0');
332  end if;
333  else
334  ipb_rdata <= (others => '0');
335  end if;
336 end process;
337 g_MaskedTrigdata : for i in 0 to 7 generate
338  g_MaskedTrigdataJ : for j in 0 to 2 generate
339  g_MaskedTrigdataK : for k in 0 to 3 generate
340  MaskedTrigdata(i*3+j)(k*8+7 downto k*8) <= not mask(i*3+j)(k*8+7 downto k*8) and Trigdata(j*4+k);
341  end generate;
342  end generate;
343 end generate;
344 g_NonZeroByte : for i in 0 to 23 generate
345  g_NonZeroByteJ : for j in 0 to 3 generate
346  NonZeroByte(i*4+j) <= '0' when MaskedTrigdata(i)(j*8+7 downto j*8) = x"00" else '1';
347  end generate;
348 end generate;
349 g_NonZeroByteCnt_i : for i in 0 to 1 generate
350  g_NonZeroByteCnt_j : for j in 0 to 7 generate
351  i_bitcount0 : ROM64X1
352  generic map (
353  INIT => X"6996966996696996") -- bit 0
354  port map (
355  O => NonZeroByteCnt(j*2+i)(0), -- ROM output
356  A0 => NonZeroByte(i*6+j*12), -- ROM address[0]
357  A1 => NonZeroByte(i*6+1+j*12), -- ROM address[1]
358  A2 => NonZeroByte(i*6+2+j*12), -- ROM address[2]
359  A3 => NonZeroByte(i*6+3+j*12), -- ROM address[3]
360  A4 => NonZeroByte(i*6+4+j*12), -- ROM address[4]
361  A5 => NonZeroByte(i*6+5+j*12) -- ROM address[5]
362  );
363  i_bitcount1 : ROM64X1
364  generic map (
365  INIT => X"8117177e177e7ee8") -- bit 1
366  port map (
367  O => NonZeroByteCnt(j*2+i)(1), -- ROM output
368  A0 => NonZeroByte(i*6+j*12), -- ROM address[0]
369  A1 => NonZeroByte(i*6+1+j*12), -- ROM address[1]
370  A2 => NonZeroByte(i*6+2+j*12), -- ROM address[2]
371  A3 => NonZeroByte(i*6+3+j*12), -- ROM address[3]
372  A4 => NonZeroByte(i*6+4+j*12), -- ROM address[4]
373  A5 => NonZeroByte(i*6+5+j*12) -- ROM address[5]
374  );
375  i_bitcount2 : ROM64X1
376  generic map (
377  INIT => X"fee8e880e8808000") -- bit 2
378  port map (
379  O => NonZeroByteCnt(j*2+i)(2), -- ROM output
380  A0 => NonZeroByte(i*6+j*12), -- ROM address[0]
381  A1 => NonZeroByte(i*6+1+j*12), -- ROM address[1]
382  A2 => NonZeroByte(i*6+2+j*12), -- ROM address[2]
383  A3 => NonZeroByte(i*6+3+j*12), -- ROM address[3]
384  A4 => NonZeroByte(i*6+4+j*12), -- ROM address[4]
385  A5 => NonZeroByte(i*6+5+j*12) -- ROM address[5]
386  );
387  end generate;
388 end generate;
389 uHTR_trig_init_i : uHTR_trig_init
390  generic map
391  (
392  EXAMPLE_SIM_GTRESET_SPEEDUP => "TRUE",
393  EXAMPLE_SIMULATION => 0,
394  STABLE_CLOCK_PERIOD => 20,
395  EXAMPLE_USE_CHIPSCOPE => 0
396  )
397  port map
398  (
399  SYSCLK_IN => DRPCLK,
400  SOFT_RESET_IN => '0',
401  DONT_RESET_ON_DATA_ERROR_IN => '0',
402  GT0_TX_FSM_RESET_DONE_OUT => txfsmresetdone,
403  GT0_RX_FSM_RESET_DONE_OUT => open,
404  GT0_DATA_VALID_IN => DATA_VALID,
405 
406 
407 
408 
409 
410  --_____________________________________________________________________
411  --_____________________________________________________________________
412  --GT0 (X1Y12)
413 
414  --------------------------------- CPLL Ports -------------------------------
415  GT0_CPLLFBCLKLOST_OUT => open,
416  GT0_CPLLLOCK_OUT => CPLLLOCK,
417  GT0_CPLLLOCKDETCLK_IN => DRPCLK,
418  GT0_CPLLRESET_IN => CPLLRESET,
419  -------------------------- Channel - Clocking Ports ------------------------
420  GT0_GTREFCLK0_IN => REFCLK,
421  ---------------------------- Channel - DRP Ports --------------------------
422  GT0_DRPADDR_IN => (others => '0'),
423  GT0_DRPCLK_IN => DRPCLK,
424  GT0_DRPDI_IN => (others => '0'),
425  GT0_DRPDO_OUT => open,
426  GT0_DRPEN_IN => '0',
427  GT0_DRPRDY_OUT => open,
428  GT0_DRPWE_IN => '0',
429  --------------------- RX Initialization and Reset Ports --------------------
430  GT0_RXUSERRDY_IN => '0',
431  -------------------------- RX Margin Analysis Ports ------------------------
432  GT0_EYESCANDATAERROR_OUT => open,
433  ------------------------- Receive Ports - CDR Ports ------------------------
434  GT0_RXCDRLOCK_OUT => open,
435  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
436  GT0_RXUSRCLK_IN => TTC_clk,
437  GT0_RXUSRCLK2_IN => TTC_clk,
438  ------------------ Receive Ports - FPGA RX interface Ports -----------------
439  GT0_RXDATA_OUT => RXDATA,
440  ------------------- Receive Ports - Pattern Checker Ports ------------------
441  GT0_RXPRBSERR_OUT => PRBSERR,
442  GT0_RXPRBSSEL_IN => PRBSSEL,
443  ------------------- Receive Ports - Pattern Checker ports ------------------
444  GT0_RXPRBSCNTRESET_IN => '0',
445  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
446  GT0_RXDISPERR_OUT => open,
447  GT0_RXNOTINTABLE_OUT => open,
448  --------------------------- Receive Ports - RX AFE -------------------------
449  GT0_GTXRXP_IN => GTX_RXp,
450  ------------------------ Receive Ports - RX AFE Ports ----------------------
451  GT0_GTXRXN_IN => GTX_RXn,
452  ------------- Receive Ports - RX Initialization and Reset Ports ------------
453  GT0_GTRXRESET_IN => GTRXRESET,
454  GT0_RXPMARESET_IN => '0',
455  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
456  GT0_RXCHARISK_OUT => RXCHARISK,
457  -------------- Receive Ports -RX Initialization and Reset Ports ------------
458  GT0_RXRESETDONE_OUT => RXRESETDONE ,
459  --------------------- TX Initialization and Reset Ports --------------------
460  GT0_GTTXRESET_IN => GTTXRESET,
461  GT0_TXUSERRDY_IN => '0',
462  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
463  GT0_TXUSRCLK_IN => TTC_Clk,
464  GT0_TXUSRCLK2_IN => TTC_Clk,
465  ------------------ Transmit Ports - TX Data Path interface -----------------
466  GT0_TXDATA_IN => TXDATA,
467  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
468  GT0_GTXTXN_OUT => GTX_TXn,
469  GT0_GTXTXP_OUT => GTX_TXp,
470  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
471  GT0_TXOUTCLK_OUT => open,
472  GT0_TXOUTCLKFABRIC_OUT => open,
473  GT0_TXOUTCLKPCS_OUT => open,
474  --------------------- Transmit Ports - TX Gearbox Ports --------------------
475  GT0_TXCHARISK_IN => x"1",
476  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
477  GT0_TXRESETDONE_OUT => open,
478  ------------------ Transmit Ports - pattern Generator Ports ----------------
479  GT0_TXPRBSSEL_IN => PRBSSEL,
480 
481 
482 
483 
484  --____________________________COMMON PORTS________________________________
485  ---------------------- Common Block - Ref Clock Ports ---------------------
486  GT0_GTREFCLK0_COMMON_IN => '0',
487  ------------------------- Common Block - QPLL Ports ------------------------
488  GT0_QPLLLOCK_OUT => open,
489  GT0_QPLLLOCKDETCLK_IN => '0',
490  GT0_QPLLRESET_IN => '0'
491 
492  );
493 
494 GTTXRESET <= not CPLLLOCK;
495 GTRXRESET <= not CPLLLOCK;
496 
497 i_REFCLK : IBUFDS_GTE2
498  port map
499  (
500  O => REFCLK,
501  ODIV2 => open,
502  CEB => '0',
503  I => GTX_REFCLKp,
504  IB => GTX_REFCLKn
505  );
506 end Behavioral;
507 
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