AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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sfp2_v2_7.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : sfp2_v2_7.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module SFP2_v2_7 (a GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 library UNISIM;
68 use UNISIM.VCOMPONENTS.ALL;
69 
70 
71 --***************************** Entity Declaration ****************************
72 
73 entity SFP2_v2_7 is
74 generic
75 (
76  QPLL_FBDIV_TOP : integer := 66;
77 
78  -- Simulation attributes
79  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
80  RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
81  PMA_RSV_IN : bit_vector := x"001E7080"
82 
83 );
84 port
85 (
86  --_________________________________________________________________________
87  --_________________________________________________________________________
88  --GT0 (X0Y12)
89  --____________________________CHANNEL PORTS________________________________
90  ---------------------------- Channel - DRP Ports --------------------------
91  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
92  GT0_DRPCLK_IN : in std_logic;
93  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
94  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
95  GT0_DRPEN_IN : in std_logic;
96  GT0_DRPRDY_OUT : out std_logic;
97  GT0_DRPWE_IN : in std_logic;
98  ------------------------------- Loopback Ports -----------------------------
99  GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
100  ------------------------------ Power-Down Ports ----------------------------
101  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
102  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
103  --------------------- RX Initialization and Reset Ports --------------------
104  GT0_RXUSERRDY_IN : in std_logic;
105  -------------------------- RX Margin Analysis Ports ------------------------
106  GT0_EYESCANDATAERROR_OUT : out std_logic;
107  ------------------------- Receive Ports - CDR Ports ------------------------
108  GT0_RXCDRLOCK_OUT : out std_logic;
109  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
110  GT0_RXUSRCLK_IN : in std_logic;
111  GT0_RXUSRCLK2_IN : in std_logic;
112  ------------------ Receive Ports - FPGA RX interface Ports -----------------
113  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
114  ------------------- Receive Ports - Pattern Checker Ports ------------------
115  GT0_RXPRBSERR_OUT : out std_logic;
116  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
117  ------------------- Receive Ports - Pattern Checker ports ------------------
118  GT0_RXPRBSCNTRESET_IN : in std_logic;
119  --------------------------- Receive Ports - RX AFE -------------------------
120  GT0_GTXRXP_IN : in std_logic;
121  ------------------------ Receive Ports - RX AFE Ports ----------------------
122  GT0_GTXRXN_IN : in std_logic;
123  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
124  GT0_RXBUFRESET_IN : in std_logic;
125  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
126  --------------------- Receive Ports - RX Equalizer Ports -------------------
127  GT0_RXDFEAGCHOLD_IN : in std_logic;
128  GT0_RXDFELFHOLD_IN : in std_logic;
129  --------------- Receive Ports - RX Fabric Output Control Ports -------------
130  GT0_RXOUTCLK_OUT : out std_logic;
131  ---------------------- Receive Ports - RX Gearbox Ports --------------------
132  GT0_RXDATAVALID_OUT : out std_logic;
133  GT0_RXHEADER_OUT : out std_logic_vector(1 downto 0);
134  GT0_RXHEADERVALID_OUT : out std_logic;
135  --------------------- Receive Ports - RX Gearbox Ports --------------------
136  GT0_RXGEARBOXSLIP_IN : in std_logic;
137  ------------- Receive Ports - RX Initialization and Reset Ports ------------
138  GT0_GTRXRESET_IN : in std_logic;
139  GT0_RXPCSRESET_IN : in std_logic;
140  GT0_RXPMARESET_IN : in std_logic;
141  ------------------ Receive Ports - RX Margin Analysis ports ----------------
142  GT0_RXLPMEN_IN : in std_logic;
143  -------------- Receive Ports -RX Initialization and Reset Ports ------------
144  GT0_RXRESETDONE_OUT : out std_logic;
145  --------------------- TX Initialization and Reset Ports --------------------
146  GT0_GTTXRESET_IN : in std_logic;
147  GT0_TXUSERRDY_IN : in std_logic;
148  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
149  GT0_TXUSRCLK_IN : in std_logic;
150  GT0_TXUSRCLK2_IN : in std_logic;
151  --------------- Transmit Ports - TX Configurable Driver Ports --------------
152  GT0_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
153  GT0_TXINHIBIT_IN : in std_logic;
154  GT0_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
155  ------------------ Transmit Ports - TX Data Path interface -----------------
156  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
157  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
158  GT0_GTXTXN_OUT : out std_logic;
159  GT0_GTXTXP_OUT : out std_logic;
160  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
161  GT0_TXOUTCLK_OUT : out std_logic;
162  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
163  GT0_TXOUTCLKPCS_OUT : out std_logic;
164  --------------------- Transmit Ports - TX Gearbox Ports --------------------
165  GT0_TXHEADER_IN : in std_logic_vector(1 downto 0);
166  GT0_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
167  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
168  GT0_TXPCSRESET_IN : in std_logic;
169  GT0_TXRESETDONE_OUT : out std_logic;
170  ------------------ Transmit Ports - pattern Generator Ports ----------------
171  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
172 
173  --GT1 (X0Y14)
174  --____________________________CHANNEL PORTS________________________________
175  ---------------------------- Channel - DRP Ports --------------------------
176  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
177  GT1_DRPCLK_IN : in std_logic;
178  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
179  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
180  GT1_DRPEN_IN : in std_logic;
181  GT1_DRPRDY_OUT : out std_logic;
182  GT1_DRPWE_IN : in std_logic;
183  ------------------------------- Loopback Ports -----------------------------
184  GT1_LOOPBACK_IN : in std_logic_vector(2 downto 0);
185  ------------------------------ Power-Down Ports ----------------------------
186  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
187  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
188  --------------------- RX Initialization and Reset Ports --------------------
189  GT1_RXUSERRDY_IN : in std_logic;
190  -------------------------- RX Margin Analysis Ports ------------------------
191  GT1_EYESCANDATAERROR_OUT : out std_logic;
192  ------------------------- Receive Ports - CDR Ports ------------------------
193  GT1_RXCDRLOCK_OUT : out std_logic;
194  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
195  GT1_RXUSRCLK_IN : in std_logic;
196  GT1_RXUSRCLK2_IN : in std_logic;
197  ------------------ Receive Ports - FPGA RX interface Ports -----------------
198  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
199  ------------------- Receive Ports - Pattern Checker Ports ------------------
200  GT1_RXPRBSERR_OUT : out std_logic;
201  GT1_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
202  ------------------- Receive Ports - Pattern Checker ports ------------------
203  GT1_RXPRBSCNTRESET_IN : in std_logic;
204  --------------------------- Receive Ports - RX AFE -------------------------
205  GT1_GTXRXP_IN : in std_logic;
206  ------------------------ Receive Ports - RX AFE Ports ----------------------
207  GT1_GTXRXN_IN : in std_logic;
208  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
209  GT1_RXBUFRESET_IN : in std_logic;
210  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
211  --------------------- Receive Ports - RX Equalizer Ports -------------------
212  GT1_RXDFEAGCHOLD_IN : in std_logic;
213  GT1_RXDFELFHOLD_IN : in std_logic;
214  --------------- Receive Ports - RX Fabric Output Control Ports -------------
215  GT1_RXOUTCLK_OUT : out std_logic;
216  ---------------------- Receive Ports - RX Gearbox Ports --------------------
217  GT1_RXDATAVALID_OUT : out std_logic;
218  GT1_RXHEADER_OUT : out std_logic_vector(1 downto 0);
219  GT1_RXHEADERVALID_OUT : out std_logic;
220  --------------------- Receive Ports - RX Gearbox Ports --------------------
221  GT1_RXGEARBOXSLIP_IN : in std_logic;
222  ------------- Receive Ports - RX Initialization and Reset Ports ------------
223  GT1_GTRXRESET_IN : in std_logic;
224  GT1_RXPCSRESET_IN : in std_logic;
225  GT1_RXPMARESET_IN : in std_logic;
226  ------------------ Receive Ports - RX Margin Analysis ports ----------------
227  GT1_RXLPMEN_IN : in std_logic;
228  -------------- Receive Ports -RX Initialization and Reset Ports ------------
229  GT1_RXRESETDONE_OUT : out std_logic;
230  --------------------- TX Initialization and Reset Ports --------------------
231  GT1_GTTXRESET_IN : in std_logic;
232  GT1_TXUSERRDY_IN : in std_logic;
233  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
234  GT1_TXUSRCLK_IN : in std_logic;
235  GT1_TXUSRCLK2_IN : in std_logic;
236  --------------- Transmit Ports - TX Configurable Driver Ports --------------
237  GT1_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
238  GT1_TXINHIBIT_IN : in std_logic;
239  GT1_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
240  ------------------ Transmit Ports - TX Data Path interface -----------------
241  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
242  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
243  GT1_GTXTXN_OUT : out std_logic;
244  GT1_GTXTXP_OUT : out std_logic;
245  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
246  GT1_TXOUTCLK_OUT : out std_logic;
247  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
248  GT1_TXOUTCLKPCS_OUT : out std_logic;
249  --------------------- Transmit Ports - TX Gearbox Ports --------------------
250  GT1_TXHEADER_IN : in std_logic_vector(1 downto 0);
251  GT1_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
252  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
253  GT1_TXPCSRESET_IN : in std_logic;
254  GT1_TXRESETDONE_OUT : out std_logic;
255  ------------------ Transmit Ports - pattern Generator Ports ----------------
256  GT1_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
257 
258 
259  --____________________________COMMON PORTS________________________________
260  ---------------------- Common Block - Ref Clock Ports ---------------------
261  GT0_GTREFCLK0_COMMON_IN : in std_logic;
262  ------------------------- Common Block - QPLL Ports ------------------------
263  GT0_QPLLLOCK_OUT : out std_logic;
264  GT0_QPLLLOCKDETCLK_IN : in std_logic;
265  GT0_QPLLREFCLKLOST_OUT : out std_logic;
266  GT0_QPLLRESET_IN : in std_logic
267 
268 
269 );
270 
271 
272 end SFP2_v2_7;
273 
274 architecture RTL of SFP2_v2_7 is
275 
276  attribute CORE_GENERATION_INFO : string;
277  attribute CORE_GENERATION_INFO of RTL : architecture is "SFP2_v2_7,gtwizard_v2_7,{protocol_file=10GBASE-R}";
278 
279 
280 --***********************************Parameter Declarations********************
281 
282  constant DLY : time := 1 ns;
283 
284 --***************************** Signal Declarations *****************************
285 
286  -- ground and tied_to_vcc_i signals
287  signal tied_to_ground_i : std_logic;
288  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
289  signal tied_to_vcc_i : std_logic;
290  signal gt0_qplloutclk_i : std_logic;
291  signal gt0_qplloutrefclk_i : std_logic;
292 
293 
294  signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0);
295  signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0);
296 
297  signal gt1_mgtrefclktx_i : std_logic_vector(1 downto 0);
298  signal gt1_mgtrefclkrx_i : std_logic_vector(1 downto 0);
299 
300 
301  signal gt0_qpllclk_i : std_logic;
302  signal gt0_qpllrefclk_i : std_logic;
303  signal gt1_qpllclk_i : std_logic;
304  signal gt1_qpllrefclk_i : std_logic;
305 
306 
307 --*************************** Component Declarations **************************
308 component SFP2_v2_7_GT
309 generic
310 (
311  -- Simulation attributes
312  GT_SIM_GTRESET_SPEEDUP : string := "FALSE";
313  RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
314  PMA_RSV_IN : bit_vector := X"00000000";
315  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
316 );
317 port
318 (
319  ---------------------------- Channel - DRP Ports --------------------------
320  DRPADDR_IN : in std_logic_vector(8 downto 0);
321  DRPCLK_IN : in std_logic;
322  DRPDI_IN : in std_logic_vector(15 downto 0);
323  DRPDO_OUT : out std_logic_vector(15 downto 0);
324  DRPEN_IN : in std_logic;
325  DRPRDY_OUT : out std_logic;
326  DRPWE_IN : in std_logic;
327  ------------------------------- Clocking Ports -----------------------------
328  QPLLCLK_IN : in std_logic;
329  QPLLREFCLK_IN : in std_logic;
330  ------------------------------- Loopback Ports -----------------------------
331  LOOPBACK_IN : in std_logic_vector(2 downto 0);
332  ------------------------------ Power-Down Ports ----------------------------
333  RXPD_IN : in std_logic_vector(1 downto 0);
334  TXPD_IN : in std_logic_vector(1 downto 0);
335  --------------------- RX Initialization and Reset Ports --------------------
336  RXUSERRDY_IN : in std_logic;
337  -------------------------- RX Margin Analysis Ports ------------------------
338  EYESCANDATAERROR_OUT : out std_logic;
339  ------------------------- Receive Ports - CDR Ports ------------------------
340  RXCDRLOCK_OUT : out std_logic;
341  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
342  RXUSRCLK_IN : in std_logic;
343  RXUSRCLK2_IN : in std_logic;
344  ------------------ Receive Ports - FPGA RX interface Ports -----------------
345  RXDATA_OUT : out std_logic_vector(31 downto 0);
346  ------------------- Receive Ports - Pattern Checker Ports ------------------
347  RXPRBSERR_OUT : out std_logic;
348  RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
349  ------------------- Receive Ports - Pattern Checker ports ------------------
350  RXPRBSCNTRESET_IN : in std_logic;
351  --------------------------- Receive Ports - RX AFE -------------------------
352  GTXRXP_IN : in std_logic;
353  ------------------------ Receive Ports - RX AFE Ports ----------------------
354  GTXRXN_IN : in std_logic;
355  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
356  RXBUFRESET_IN : in std_logic;
357  RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
358  --------------------- Receive Ports - RX Equalizer Ports -------------------
359  RXDFEAGCHOLD_IN : in std_logic;
360  RXDFELFHOLD_IN : in std_logic;
361  --------------- Receive Ports - RX Fabric Output Control Ports -------------
362  RXOUTCLK_OUT : out std_logic;
363  ---------------------- Receive Ports - RX Gearbox Ports --------------------
364  RXDATAVALID_OUT : out std_logic;
365  RXHEADER_OUT : out std_logic_vector(1 downto 0);
366  RXHEADERVALID_OUT : out std_logic;
367  --------------------- Receive Ports - RX Gearbox Ports --------------------
368  RXGEARBOXSLIP_IN : in std_logic;
369  ------------- Receive Ports - RX Initialization and Reset Ports ------------
370  GTRXRESET_IN : in std_logic;
371  RXPCSRESET_IN : in std_logic;
372  RXPMARESET_IN : in std_logic;
373  ------------------ Receive Ports - RX Margin Analysis ports ----------------
374  RXLPMEN_IN : in std_logic;
375  -------------- Receive Ports -RX Initialization and Reset Ports ------------
376  RXRESETDONE_OUT : out std_logic;
377  --------------------- TX Initialization and Reset Ports --------------------
378  GTTXRESET_IN : in std_logic;
379  TXUSERRDY_IN : in std_logic;
380  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
381  TXUSRCLK_IN : in std_logic;
382  TXUSRCLK2_IN : in std_logic;
383  --------------- Transmit Ports - TX Configurable Driver Ports --------------
384  TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
385  TXINHIBIT_IN : in std_logic;
386  TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
387  ------------------ Transmit Ports - TX Data Path interface -----------------
388  TXDATA_IN : in std_logic_vector(31 downto 0);
389  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
390  GTXTXN_OUT : out std_logic;
391  GTXTXP_OUT : out std_logic;
392  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
393  TXOUTCLK_OUT : out std_logic;
394  TXOUTCLKFABRIC_OUT : out std_logic;
395  TXOUTCLKPCS_OUT : out std_logic;
396  --------------------- Transmit Ports - TX Gearbox Ports --------------------
397  TXHEADER_IN : in std_logic_vector(1 downto 0);
398  TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
399  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
400  TXPCSRESET_IN : in std_logic;
401  TXRESETDONE_OUT : out std_logic;
402  ------------------ Transmit Ports - pattern Generator Ports ----------------
403  TXPRBSSEL_IN : in std_logic_vector(2 downto 0)
404 
405 
406 );
407 end component;
408 
409 
410 
411 --*************************Logic to set Attribute QPLL_FB_DIV*****************************
412  impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
413  begin
414  if (qpllfbdiv_top = 16) then
415  return "0000100000";
416  elsif (qpllfbdiv_top = 20) then
417  return "0000110000" ;
418  elsif (qpllfbdiv_top = 32) then
419  return "0001100000" ;
420  elsif (qpllfbdiv_top = 40) then
421  return "0010000000" ;
422  elsif (qpllfbdiv_top = 64) then
423  return "0011100000" ;
424  elsif (qpllfbdiv_top = 66) then
425  return "0101000000" ;
426  elsif (qpllfbdiv_top = 80) then
427  return "0100100000" ;
428  elsif (qpllfbdiv_top = 100) then
429  return "0101110000" ;
430  else
431  return "0000000000" ;
432  end if;
433  end function;
434 
435  impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
436  begin
437  if (qpllfbdiv_top = 16) then
438  return '1';
439  elsif (qpllfbdiv_top = 20) then
440  return '1' ;
441  elsif (qpllfbdiv_top = 32) then
442  return '1' ;
443  elsif (qpllfbdiv_top = 40) then
444  return '1' ;
445  elsif (qpllfbdiv_top = 64) then
446  return '1' ;
447  elsif (qpllfbdiv_top = 66) then
448  return '0' ;
449  elsif (qpllfbdiv_top = 80) then
450  return '1' ;
451  elsif (qpllfbdiv_top = 100) then
452  return '1' ;
453  else
454  return '1' ;
455  end if;
456  end function;
457 
458  constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
459  constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
460 
461 --********************************* Main Body of Code**************************
462 
463 begin
464 
465  tied_to_ground_i <= '0';
466  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
467  tied_to_vcc_i <= '1';
468  gt0_qpllclk_i <= gt0_qplloutclk_i;
469  gt0_qpllrefclk_i <= gt0_qplloutrefclk_i;
470 
471  gt1_qpllclk_i <= gt0_qplloutclk_i;
472  gt1_qpllrefclk_i <= gt0_qplloutrefclk_i;
473 
474 
475 
476  --------------------------- GT Instances -------------------------------
477 
478  --_________________________________________________________________________
479  --_________________________________________________________________________
480  --GT0 (X0Y12)
481 
482  gt0_SFP2_v2_7_i : SFP2_v2_7_GT
483  generic map
484  (
485  -- Simulation attributes
486  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
487  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
488  PMA_RSV_IN => PMA_RSV_IN,
489  PCS_RSVD_ATTR_IN => X"000000000000"
490  )
491  port map
492  (
493  ---------------------------- Channel - DRP Ports --------------------------
494  DRPADDR_IN => GT0_DRPADDR_IN,
495  DRPCLK_IN => GT0_DRPCLK_IN,
496  DRPDI_IN => GT0_DRPDI_IN ,
497  DRPDO_OUT => GT0_DRPDO_OUT,
498  DRPEN_IN => GT0_DRPEN_IN ,
499  DRPRDY_OUT => GT0_DRPRDY_OUT,
500  DRPWE_IN => GT0_DRPWE_IN ,
501  ------------------------------- Clocking Ports -----------------------------
502  QPLLCLK_IN => gt0_qpllclk_i,
503  QPLLREFCLK_IN => gt0_qpllrefclk_i,
504  ------------------------------- Loopback Ports -----------------------------
505  LOOPBACK_IN => GT0_LOOPBACK_IN,
506  ------------------------------ Power-Down Ports ----------------------------
507  RXPD_IN => GT0_RXPD_IN ,
508  TXPD_IN => GT0_TXPD_IN ,
509  --------------------- RX Initialization and Reset Ports --------------------
510  RXUSERRDY_IN => GT0_RXUSERRDY_IN,
511  -------------------------- RX Margin Analysis Ports ------------------------
512  EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
513  ------------------------- Receive Ports - CDR Ports ------------------------
514  RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
515  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
516  RXUSRCLK_IN => GT0_RXUSRCLK_IN,
517  RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
518  ------------------ Receive Ports - FPGA RX interface Ports -----------------
519  RXDATA_OUT => GT0_RXDATA_OUT,
520  ------------------- Receive Ports - Pattern Checker Ports ------------------
521  RXPRBSERR_OUT => GT0_RXPRBSERR_OUT,
522  RXPRBSSEL_IN => GT0_RXPRBSSEL_IN,
523  ------------------- Receive Ports - Pattern Checker ports ------------------
524  RXPRBSCNTRESET_IN => GT0_RXPRBSCNTRESET_IN,
525  --------------------------- Receive Ports - RX AFE -------------------------
526  GTXRXP_IN => GT0_GTXRXP_IN,
527  ------------------------ Receive Ports - RX AFE Ports ----------------------
528  GTXRXN_IN => GT0_GTXRXN_IN,
529  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
530  RXBUFRESET_IN => GT0_RXBUFRESET_IN,
531  RXBUFSTATUS_OUT => GT0_RXBUFSTATUS_OUT,
532  --------------------- Receive Ports - RX Equalizer Ports -------------------
533  RXDFEAGCHOLD_IN => GT0_RXDFEAGCHOLD_IN,
534  RXDFELFHOLD_IN => GT0_RXDFELFHOLD_IN,
535  --------------- Receive Ports - RX Fabric Output Control Ports -------------
536  RXOUTCLK_OUT => GT0_RXOUTCLK_OUT,
537  ---------------------- Receive Ports - RX Gearbox Ports --------------------
538  RXDATAVALID_OUT => GT0_RXDATAVALID_OUT,
539  RXHEADER_OUT => GT0_RXHEADER_OUT,
540  RXHEADERVALID_OUT => GT0_RXHEADERVALID_OUT,
541  --------------------- Receive Ports - RX Gearbox Ports --------------------
542  RXGEARBOXSLIP_IN => GT0_RXGEARBOXSLIP_IN,
543  ------------- Receive Ports - RX Initialization and Reset Ports ------------
544  GTRXRESET_IN => GT0_GTRXRESET_IN,
545  RXPCSRESET_IN => GT0_RXPCSRESET_IN,
546  RXPMARESET_IN => GT0_RXPMARESET_IN,
547  ------------------ Receive Ports - RX Margin Analysis ports ----------------
548  RXLPMEN_IN => GT0_RXLPMEN_IN,
549  -------------- Receive Ports -RX Initialization and Reset Ports ------------
550  RXRESETDONE_OUT => GT0_RXRESETDONE_OUT,
551  --------------------- TX Initialization and Reset Ports --------------------
552  GTTXRESET_IN => GT0_GTTXRESET_IN,
553  TXUSERRDY_IN => GT0_TXUSERRDY_IN,
554  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
555  TXUSRCLK_IN => GT0_TXUSRCLK_IN,
556  TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
557  --------------- Transmit Ports - TX Configurable Driver Ports --------------
558  TXDIFFCTRL_IN => GT0_TXDIFFCTRL_IN,
559  TXINHIBIT_IN => GT0_TXINHIBIT_IN,
560  TXMAINCURSOR_IN => GT0_TXMAINCURSOR_IN,
561  ------------------ Transmit Ports - TX Data Path interface -----------------
562  TXDATA_IN => GT0_TXDATA_IN,
563  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
564  GTXTXN_OUT => GT0_GTXTXN_OUT,
565  GTXTXP_OUT => GT0_GTXTXP_OUT,
566  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
567  TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
568  TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT,
569  TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT,
570  --------------------- Transmit Ports - TX Gearbox Ports --------------------
571  TXHEADER_IN => GT0_TXHEADER_IN,
572  TXSEQUENCE_IN => GT0_TXSEQUENCE_IN,
573  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
574  TXPCSRESET_IN => GT0_TXPCSRESET_IN,
575  TXRESETDONE_OUT => GT0_TXRESETDONE_OUT,
576  ------------------ Transmit Ports - pattern Generator Ports ----------------
577  TXPRBSSEL_IN => GT0_TXPRBSSEL_IN
578 
579  );
580 
581  --_________________________________________________________________________
582  --_________________________________________________________________________
583  --GT1 (X0Y14)
584 
585  gt1_SFP2_v2_7_i : SFP2_v2_7_GT
586  generic map
587  (
588  -- Simulation attributes
589  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
590  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
591  PMA_RSV_IN => PMA_RSV_IN,
592  PCS_RSVD_ATTR_IN => X"000000000000"
593  )
594  port map
595  (
596  ---------------------------- Channel - DRP Ports --------------------------
597  DRPADDR_IN => GT1_DRPADDR_IN,
598  DRPCLK_IN => GT1_DRPCLK_IN,
599  DRPDI_IN => GT1_DRPDI_IN ,
600  DRPDO_OUT => GT1_DRPDO_OUT,
601  DRPEN_IN => GT1_DRPEN_IN ,
602  DRPRDY_OUT => GT1_DRPRDY_OUT,
603  DRPWE_IN => GT1_DRPWE_IN ,
604  ------------------------------- Clocking Ports -----------------------------
605  QPLLCLK_IN => gt1_qpllclk_i,
606  QPLLREFCLK_IN => gt1_qpllrefclk_i,
607  ------------------------------- Loopback Ports -----------------------------
608  LOOPBACK_IN => GT1_LOOPBACK_IN,
609  ------------------------------ Power-Down Ports ----------------------------
610  RXPD_IN => GT1_RXPD_IN ,
611  TXPD_IN => GT1_TXPD_IN ,
612  --------------------- RX Initialization and Reset Ports --------------------
613  RXUSERRDY_IN => GT1_RXUSERRDY_IN,
614  -------------------------- RX Margin Analysis Ports ------------------------
615  EYESCANDATAERROR_OUT => GT1_EYESCANDATAERROR_OUT,
616  ------------------------- Receive Ports - CDR Ports ------------------------
617  RXCDRLOCK_OUT => GT1_RXCDRLOCK_OUT,
618  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
619  RXUSRCLK_IN => GT1_RXUSRCLK_IN,
620  RXUSRCLK2_IN => GT1_RXUSRCLK2_IN,
621  ------------------ Receive Ports - FPGA RX interface Ports -----------------
622  RXDATA_OUT => GT1_RXDATA_OUT,
623  ------------------- Receive Ports - Pattern Checker Ports ------------------
624  RXPRBSERR_OUT => GT1_RXPRBSERR_OUT,
625  RXPRBSSEL_IN => GT1_RXPRBSSEL_IN,
626  ------------------- Receive Ports - Pattern Checker ports ------------------
627  RXPRBSCNTRESET_IN => GT1_RXPRBSCNTRESET_IN,
628  --------------------------- Receive Ports - RX AFE -------------------------
629  GTXRXP_IN => GT1_GTXRXP_IN,
630  ------------------------ Receive Ports - RX AFE Ports ----------------------
631  GTXRXN_IN => GT1_GTXRXN_IN,
632  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
633  RXBUFRESET_IN => GT1_RXBUFRESET_IN,
634  RXBUFSTATUS_OUT => GT1_RXBUFSTATUS_OUT,
635  --------------------- Receive Ports - RX Equalizer Ports -------------------
636  RXDFEAGCHOLD_IN => GT1_RXDFEAGCHOLD_IN,
637  RXDFELFHOLD_IN => GT1_RXDFELFHOLD_IN,
638  --------------- Receive Ports - RX Fabric Output Control Ports -------------
639  RXOUTCLK_OUT => GT1_RXOUTCLK_OUT,
640  ---------------------- Receive Ports - RX Gearbox Ports --------------------
641  RXDATAVALID_OUT => GT1_RXDATAVALID_OUT,
642  RXHEADER_OUT => GT1_RXHEADER_OUT,
643  RXHEADERVALID_OUT => GT1_RXHEADERVALID_OUT,
644  --------------------- Receive Ports - RX Gearbox Ports --------------------
645  RXGEARBOXSLIP_IN => GT1_RXGEARBOXSLIP_IN,
646  ------------- Receive Ports - RX Initialization and Reset Ports ------------
647  GTRXRESET_IN => GT1_GTRXRESET_IN,
648  RXPCSRESET_IN => GT1_RXPCSRESET_IN,
649  RXPMARESET_IN => GT1_RXPMARESET_IN,
650  ------------------ Receive Ports - RX Margin Analysis ports ----------------
651  RXLPMEN_IN => GT1_RXLPMEN_IN,
652  -------------- Receive Ports -RX Initialization and Reset Ports ------------
653  RXRESETDONE_OUT => GT1_RXRESETDONE_OUT,
654  --------------------- TX Initialization and Reset Ports --------------------
655  GTTXRESET_IN => GT1_GTTXRESET_IN,
656  TXUSERRDY_IN => GT1_TXUSERRDY_IN,
657  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
658  TXUSRCLK_IN => GT1_TXUSRCLK_IN,
659  TXUSRCLK2_IN => GT1_TXUSRCLK2_IN,
660  --------------- Transmit Ports - TX Configurable Driver Ports --------------
661  TXDIFFCTRL_IN => GT1_TXDIFFCTRL_IN,
662  TXINHIBIT_IN => GT1_TXINHIBIT_IN,
663  TXMAINCURSOR_IN => GT1_TXMAINCURSOR_IN,
664  ------------------ Transmit Ports - TX Data Path interface -----------------
665  TXDATA_IN => GT1_TXDATA_IN,
666  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
667  GTXTXN_OUT => GT1_GTXTXN_OUT,
668  GTXTXP_OUT => GT1_GTXTXP_OUT,
669  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
670  TXOUTCLK_OUT => GT1_TXOUTCLK_OUT,
671  TXOUTCLKFABRIC_OUT => GT1_TXOUTCLKFABRIC_OUT,
672  TXOUTCLKPCS_OUT => GT1_TXOUTCLKPCS_OUT,
673  --------------------- Transmit Ports - TX Gearbox Ports --------------------
674  TXHEADER_IN => GT1_TXHEADER_IN,
675  TXSEQUENCE_IN => GT1_TXSEQUENCE_IN,
676  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
677  TXPCSRESET_IN => GT1_TXPCSRESET_IN,
678  TXRESETDONE_OUT => GT1_TXRESETDONE_OUT,
679  ------------------ Transmit Ports - pattern Generator Ports ----------------
680  TXPRBSSEL_IN => GT1_TXPRBSSEL_IN
681 
682  );
683 
684  --_________________________________________________________________________
685  --_________________________________________________________________________
686  --_________________________GTXE2_COMMON____________________________________
687 
688  gtxe2_common_0_i : GTXE2_COMMON
689  generic map
690  (
691  -- Simulation attributes
692  SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
693  SIM_QPLLREFCLK_SEL => ("001"),
694  SIM_VERSION => "4.0",
695 
696 
697  ------------------COMMON BLOCK Attributes---------------
698  BIAS_CFG => (x"0000040000001000"),
699  COMMON_CFG => (x"00000000"),
700  QPLL_CFG => (x"0680181"),
701  QPLL_CLKOUT_CFG => ("0000"),
702  QPLL_COARSE_FREQ_OVRD => ("010000"),
703  QPLL_COARSE_FREQ_OVRD_EN => ('0'),
704  QPLL_CP => ("0000011111"),
705  QPLL_CP_MONITOR_EN => ('0'),
706  QPLL_DMONITOR_SEL => ('0'),
707  QPLL_FBDIV => (QPLL_FBDIV_IN),
708  QPLL_FBDIV_MONITOR_EN => ('0'),
709  QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
710  QPLL_INIT_CFG => (x"000006"),
711  QPLL_LOCK_CFG => (x"21E8"),
712  QPLL_LPF => ("1111"),
713  QPLL_REFCLK_DIV => (1)
714 
715 
716  )
717  port map
718  (
719  ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
720  DRPADDR => tied_to_ground_vec_i(7 downto 0),
721  DRPCLK => tied_to_ground_i,
722  DRPDI => tied_to_ground_vec_i(15 downto 0),
723  DRPDO => open,
724  DRPEN => tied_to_ground_i,
725  DRPRDY => open,
726  DRPWE => tied_to_ground_i,
727  ---------------------- Common Block - Ref Clock Ports ---------------------
728  GTGREFCLK => tied_to_ground_i,
729  GTNORTHREFCLK0 => tied_to_ground_i,
730  GTNORTHREFCLK1 => tied_to_ground_i,
731  GTREFCLK0 => GT0_GTREFCLK0_COMMON_IN,
732  GTREFCLK1 => tied_to_ground_i,
733  GTSOUTHREFCLK0 => tied_to_ground_i,
734  GTSOUTHREFCLK1 => tied_to_ground_i,
735  ------------------------- Common Block - QPLL Ports -----------------------
736  QPLLDMONITOR => open,
737  ----------------------- Common Block - Clocking Ports ----------------------
738  QPLLOUTCLK => gt0_qplloutclk_i,
739  QPLLOUTREFCLK => gt0_qplloutrefclk_i,
740  REFCLKOUTMONITOR => open,
741  ------------------------- Common Block - QPLL Ports ------------------------
742  QPLLFBCLKLOST => open,
743  QPLLLOCK => GT0_QPLLLOCK_OUT,
744  QPLLLOCKDETCLK => GT0_QPLLLOCKDETCLK_IN,
745  QPLLLOCKEN => tied_to_vcc_i,
746  QPLLOUTRESET => tied_to_ground_i,
747  QPLLPD => tied_to_ground_i,
748  QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_OUT,
749  QPLLREFCLKSEL => "001",
750  QPLLRESET => GT0_QPLLRESET_IN,
751  QPLLRSVD1 => "0000000000000000",
752  QPLLRSVD2 => "11111",
753  --------------------------------- QPLL Ports -------------------------------
754  BGBYPASSB => tied_to_vcc_i,
755  BGMONITORENB => tied_to_vcc_i,
756  BGPDB => tied_to_vcc_i,
757  BGRCALOVRD => "00000",
758  PMARSVD => "00000000",
759  RCALENB => tied_to_vcc_i
760 
761  );
762 
763 
764 
765 end RTL;
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