AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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XGMII_serdes_wapper.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 14:05:44 12/07/2015
6 -- Design Name:
7 -- Module Name: XGMII_serdes_wapper - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use work.amc13_pack.all;
23 
24 -- Uncomment the following library declaration if using
25 -- arithmetic functions with Signed or Unsigned values
26 --use IEEE.NUMERIC_STD.ALL;
27 
28 -- Uncomment the following library declaration if instantiating
29 -- any Xilinx primitives in this code.
30 library UNISIM;
31 use UNISIM.VComponents.all;
32 
33 entity XGMII_serdes_wapper is
34  Port (
35  DRPclk : in STD_LOGIC;
36  reset : in STD_LOGIC;
37  gtx_reset : in STD_LOGIC;
38 -- SFP ports
39  SFP0_RXN : in STD_LOGIC;
40  SFP0_RXP : in STD_LOGIC;
41  SFP1_RXN : in STD_LOGIC;
42  SFP1_RXP : in STD_LOGIC;
43  SFP0_TXN : out STD_LOGIC;
44  SFP0_TXP : out STD_LOGIC;
45  SFP1_TXN : out STD_LOGIC;
46  SFP1_TXP : out STD_LOGIC;
47  SFP_REFCLK_P : in STD_LOGIC;
48  SFP_REFCLK_N : in STD_LOGIC;
49  clk156 : out STD_LOGIC;
50  PCS_lock : out STD_LOGIC_VECTOR(1 downto 0);
51  gtx_rxresetdone : out STD_LOGIC_VECTOR(1 downto 0);
52  xgmii_txd : in array2x64;
53  xgmii_txc : in array2x8;
54  xgmii_rxd : out array2x64;
55  xgmii_rxc : out array2x8);
56 end XGMII_serdes_wapper;
57 
58 architecture Behavioral of XGMII_serdes_wapper is
59 COMPONENT XGbEPCS32
60  PORT(
61  reset : IN std_logic;
62  clk2x : IN std_logic;
63  clk : IN std_logic;
64  TXUSRCLK : IN std_logic;
65  TX_high : IN std_logic;
66  RXUSRCLK : IN std_logic;
67  RXRESETDONE : IN std_logic;
68  inh_TX : IN std_logic;
69  RESET_TXSync : IN std_logic;
70  GTX_TXD : OUT std_logic_vector(31 downto 0);
71  GTX_TXHEADER : OUT std_logic_vector(1 downto 0);
72  GTX_TX_PAUSE : IN std_logic;
73  GTX_RXD : IN std_logic_vector(31 downto 0);
74  GTX_RXDVLD : IN std_logic;
75  GTX_RXHEADER : IN std_logic_vector(1 downto 0);
76  GTX_RXHEADERVLD : IN std_logic;
77  GTX_RXGOOD : OUT std_logic;
78  GTX_RXGEARBOXSLIP_OUT : OUT std_logic;
79  EmacPhyTxC : IN std_logic_vector(3 downto 0);
80  EmacPhyTxD : IN std_logic_vector(31 downto 0);
81  PhyEmacRxC : OUT std_logic_vector(3 downto 0);
82  PhyEmacRxD : OUT std_logic_vector(31 downto 0)
83  );
84 END COMPONENT;
85 component SFP2_v2_7_init
86 generic
87 (
88  -- Simulation attributes
89  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to 1 to speed up sim reset
90  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
91  STABLE_CLOCK_PERIOD : integer := 20; --Period of the stable clock driving this state-machine, unit is [ns]
92  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
93 
94 );
95 port
96 (
97  SYSCLK_IN : in std_logic;
98  SOFT_RESET_IN : in std_logic;
99  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
100  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
101  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
102  GT0_DATA_VALID_IN : in std_logic;
103  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
104  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
105  GT1_DATA_VALID_IN : in std_logic;
106 
107  --_________________________________________________________________________
108  --GT0 (X1Y12)
109  --____________________________CHANNEL PORTS________________________________
110  ---------------------------- Channel - DRP Ports --------------------------
111  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
112  GT0_DRPCLK_IN : in std_logic;
113  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
114  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
115  GT0_DRPEN_IN : in std_logic;
116  GT0_DRPRDY_OUT : out std_logic;
117  GT0_DRPWE_IN : in std_logic;
118  ------------------------------- Loopback Ports -----------------------------
119  GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
120  ------------------------------ Power-Down Ports ----------------------------
121  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
122  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
123  --------------------- RX Initialization and Reset Ports --------------------
124  GT0_RXUSERRDY_IN : in std_logic;
125  -------------------------- RX Margin Analysis Ports ------------------------
126  GT0_EYESCANDATAERROR_OUT : out std_logic;
127  ------------------------- Receive Ports - CDR Ports ------------------------
128  GT0_RXCDRLOCK_OUT : out std_logic;
129  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
130  GT0_RXUSRCLK_IN : in std_logic;
131  GT0_RXUSRCLK2_IN : in std_logic;
132  ------------------ Receive Ports - FPGA RX interface Ports -----------------
133  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
134  ------------------- Receive Ports - Pattern Checker Ports ------------------
135  GT0_RXPRBSERR_OUT : out std_logic;
136  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
137  ------------------- Receive Ports - Pattern Checker ports ------------------
138  GT0_RXPRBSCNTRESET_IN : in std_logic;
139  --------------------------- Receive Ports - RX AFE -------------------------
140  GT0_GTXRXP_IN : in std_logic;
141  ------------------------ Receive Ports - RX AFE Ports ----------------------
142  GT0_GTXRXN_IN : in std_logic;
143  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
144  GT0_RXBUFRESET_IN : in std_logic;
145  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
146  --------------- Receive Ports - RX Fabric Output Control Ports -------------
147  GT0_RXOUTCLK_OUT : out std_logic;
148  ---------------------- Receive Ports - RX Gearbox Ports --------------------
149  GT0_RXDATAVALID_OUT : out std_logic;
150  GT0_RXHEADER_OUT : out std_logic_vector(1 downto 0);
151  GT0_RXHEADERVALID_OUT : out std_logic;
152  --------------------- Receive Ports - RX Gearbox Ports --------------------
153  GT0_RXGEARBOXSLIP_IN : in std_logic;
154  ------------- Receive Ports - RX Initialization and Reset Ports ------------
155  GT0_GTRXRESET_IN : in std_logic;
156  GT0_RXPMARESET_IN : in std_logic;
157  ------------------ Receive Ports - RX Margin Analysis ports ----------------
158  GT0_RXLPMEN_IN : in std_logic;
159  -------------- Receive Ports -RX Initialization and Reset Ports ------------
160  GT0_RXRESETDONE_OUT : out std_logic;
161  --------------------- TX Initialization and Reset Ports --------------------
162  GT0_GTTXRESET_IN : in std_logic;
163  GT0_TXUSERRDY_IN : in std_logic;
164  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
165  GT0_TXUSRCLK_IN : in std_logic;
166  GT0_TXUSRCLK2_IN : in std_logic;
167  --------------- Transmit Ports - TX Configurable Driver Ports --------------
168  GT0_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
169  GT0_TXINHIBIT_IN : in std_logic;
170  GT0_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
171  ------------------ Transmit Ports - TX Data Path interface -----------------
172  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
173  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
174  GT0_GTXTXN_OUT : out std_logic;
175  GT0_GTXTXP_OUT : out std_logic;
176  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
177  GT0_TXOUTCLK_OUT : out std_logic;
178  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
179  GT0_TXOUTCLKPCS_OUT : out std_logic;
180  --------------------- Transmit Ports - TX Gearbox Ports --------------------
181  GT0_TXHEADER_IN : in std_logic_vector(1 downto 0);
182  GT0_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
183  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
184  GT0_TXRESETDONE_OUT : out std_logic;
185  ------------------ Transmit Ports - pattern Generator Ports ----------------
186  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
187 
188  --_________________________________________________________________________
189  --GT1 (X1Y14)
190  --____________________________CHANNEL PORTS________________________________
191  ---------------------------- Channel - DRP Ports --------------------------
192  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
193  GT1_DRPCLK_IN : in std_logic;
194  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
195  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
196  GT1_DRPEN_IN : in std_logic;
197  GT1_DRPRDY_OUT : out std_logic;
198  GT1_DRPWE_IN : in std_logic;
199  ------------------------------- Loopback Ports -----------------------------
200  GT1_LOOPBACK_IN : in std_logic_vector(2 downto 0);
201  ------------------------------ Power-Down Ports ----------------------------
202  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
203  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
204  --------------------- RX Initialization and Reset Ports --------------------
205  GT1_RXUSERRDY_IN : in std_logic;
206  -------------------------- RX Margin Analysis Ports ------------------------
207  GT1_EYESCANDATAERROR_OUT : out std_logic;
208  ------------------------- Receive Ports - CDR Ports ------------------------
209  GT1_RXCDRLOCK_OUT : out std_logic;
210  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
211  GT1_RXUSRCLK_IN : in std_logic;
212  GT1_RXUSRCLK2_IN : in std_logic;
213  ------------------ Receive Ports - FPGA RX interface Ports -----------------
214  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
215  ------------------- Receive Ports - Pattern Checker Ports ------------------
216  GT1_RXPRBSERR_OUT : out std_logic;
217  GT1_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
218  ------------------- Receive Ports - Pattern Checker ports ------------------
219  GT1_RXPRBSCNTRESET_IN : in std_logic;
220  --------------------------- Receive Ports - RX AFE -------------------------
221  GT1_GTXRXP_IN : in std_logic;
222  ------------------------ Receive Ports - RX AFE Ports ----------------------
223  GT1_GTXRXN_IN : in std_logic;
224  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
225  GT1_RXBUFRESET_IN : in std_logic;
226  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
227  --------------- Receive Ports - RX Fabric Output Control Ports -------------
228  GT1_RXOUTCLK_OUT : out std_logic;
229  ---------------------- Receive Ports - RX Gearbox Ports --------------------
230  GT1_RXDATAVALID_OUT : out std_logic;
231  GT1_RXHEADER_OUT : out std_logic_vector(1 downto 0);
232  GT1_RXHEADERVALID_OUT : out std_logic;
233  --------------------- Receive Ports - RX Gearbox Ports --------------------
234  GT1_RXGEARBOXSLIP_IN : in std_logic;
235  ------------- Receive Ports - RX Initialization and Reset Ports ------------
236  GT1_GTRXRESET_IN : in std_logic;
237  GT1_RXPMARESET_IN : in std_logic;
238  ------------------ Receive Ports - RX Margin Analysis ports ----------------
239  GT1_RXLPMEN_IN : in std_logic;
240  -------------- Receive Ports -RX Initialization and Reset Ports ------------
241  GT1_RXRESETDONE_OUT : out std_logic;
242  --------------------- TX Initialization and Reset Ports --------------------
243  GT1_GTTXRESET_IN : in std_logic;
244  GT1_TXUSERRDY_IN : in std_logic;
245  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
246  GT1_TXUSRCLK_IN : in std_logic;
247  GT1_TXUSRCLK2_IN : in std_logic;
248  --------------- Transmit Ports - TX Configurable Driver Ports --------------
249  GT1_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
250  GT1_TXINHIBIT_IN : in std_logic;
251  GT1_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
252  ------------------ Transmit Ports - TX Data Path interface -----------------
253  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
254  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
255  GT1_GTXTXN_OUT : out std_logic;
256  GT1_GTXTXP_OUT : out std_logic;
257  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
258  GT1_TXOUTCLK_OUT : out std_logic;
259  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
260  GT1_TXOUTCLKPCS_OUT : out std_logic;
261  --------------------- Transmit Ports - TX Gearbox Ports --------------------
262  GT1_TXHEADER_IN : in std_logic_vector(1 downto 0);
263  GT1_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
264  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
265  GT1_TXRESETDONE_OUT : out std_logic;
266  ------------------ Transmit Ports - pattern Generator Ports ----------------
267  GT1_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
268 
269 
270  --____________________________COMMON PORTS________________________________
271  ---------------------- Common Block - Ref Clock Ports ---------------------
272  GT0_GTREFCLK0_COMMON_IN : in std_logic;
273  ------------------------- Common Block - QPLL Ports ------------------------
274  GT0_QPLLLOCK_OUT : out std_logic;
275  GT0_QPLLLOCKDETCLK_IN : in std_logic;
276  GT0_QPLLRESET_IN : in std_logic
277 
278 
279 );
280 end component;
281 signal TCPresetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
282 signal SFP_REFCLK : std_logic := '0';
283 signal REFCLK2XPLLRST : std_logic := '0';
284 signal refclk2x_in : std_logic := '0';
285 signal ClientClk2x_dcm : std_logic := '0';
286 signal ClientClk2x : std_logic := '0';
287 signal ClientClk_dcm : std_logic := '0';
288 signal ClientClk : std_logic := '0';
289 signal ClientClk_lock : std_logic := '0';
290 signal txusrclk : std_logic := '0';
291 signal TX_high : std_logic := '0';
292 signal qplllock : std_logic := '0';
293 signal qpllreset : std_logic := '0';
294 signal inh_TX : std_logic_vector(1 downto 0) := (others => '0');
295 signal reset_TXSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
296 signal ClientClkToggle : std_logic := '0';
297 signal ClientClkToggle_q : std_logic := '0';
298 signal SFP_TXOUTCLK : std_logic_vector(1 downto 0) := (others => '0');
299 signal SFP_TXSEQUENCE : array2X7 := (others => (others => '0'));
300 signal SFP_rxoutclk : std_logic_vector(1 downto 0) := (others => '0');
301 signal SFP_rxusrclk : std_logic_vector(1 downto 0) := (others => '0');
302 signal SFP_txresetdone : std_logic_vector(1 downto 0) := (others => '0');
303 signal SFP_gttxreset : std_logic_vector(1 downto 0) := (others => '0');
304 signal SFP_txuserrdy : std_logic_vector(1 downto 0) := (others => '0');
305 signal SFP_rxresetdone : std_logic_vector(1 downto 0) := (others => '0');
306 signal SFP_gtrxreset : std_logic_vector(1 downto 0) := (others => '0');
307 signal SFP_rxuserrdy : std_logic_vector(1 downto 0) := (others => '0');
308 signal SFP_drprdy : std_logic_vector(1 downto 0) := (others => '0');
309 signal SFP_drpen : std_logic_vector(1 downto 0) := (others => '0');
310 signal SFP_drpwe : std_logic_vector(1 downto 0) := (others => '0');
311 signal SFP_rxdfeagchold : std_logic_vector(1 downto 0) := (others => '0');
312 signal SFP_adapt_done : std_logic_vector(1 downto 0) := (others => '0');
313 signal SFP_rxmonitor : array2X7 := (others => (others => '0'));
314 signal SFP_drpdo : array2X16 := (others => (others => '0'));
315 signal SFP_rxmonitorsel : array2X2 := (others => (others => '0'));
316 signal SFP_drpaddr : array2X9 := (others => (others => '0'));
317 signal SFP_drpdi : array2X16 := (others => (others => '0'));
318 signal GTX_TX_PAUSE : std_logic := '0';
319 signal SFP_LOOPBACK_IN : array2X3 := (others => (others => '0'));
320 signal SFP_pd : array2X2 := (others => (others => '0'));
321 signal SFP_RX_FSM_RESET_DONE : std_logic_vector(1 downto 0) := (others => '0');
322 signal SFP_TX_FSM_RESET_DONE : std_logic_vector(1 downto 0) := (others => '0');
323 signal SFP_RXDVLD : std_logic_vector(1 downto 0) := (others => '0');
324 signal SFP_RXHEADERVLD : std_logic_vector(1 downto 0) := (others => '0');
325 signal SFP_RXGEARBOXSLIP : std_logic_vector(1 downto 0) := (others => '0');
326 signal SFP_RXPRBSERR_OUT : std_logic_vector(1 downto 0) := (others => '0');
327 signal SFP_RXPRBSSEL_IN : array2X3 := (others => (others => '0'));
328 signal SFP_TXPRBSSEL_IN : array2X3 := (others => (others => '0'));
329 signal SFP_EYESCANDATAERROR_OUT : std_logic_vector(1 downto 0) := (others => '0');
330 signal SFP_RXGOOD : std_logic_vector(1 downto 0) := (others => '0');
331 signal SFP_TXD : array2X32 := (others => (others => '0'));
332 signal SFP_TXD_inv : array2X32 := (others => (others => '0'));
333 signal SFP_TXHEADER : array2X2 := (others => (others => '0'));
334 signal SFP_RXD : array2X32 := (others => (others => '0'));
335 signal SFP_RXD_inv : array2X32 := (others => (others => '0'));
336 signal SFP_RXHEADER : array2X2 := (others => (others => '0'));
337 signal SFP_EmacPhyTxD : array2X32 := (others => (others => '0'));
338 signal SFP_EmacPhyTxC : array2X4 := (others => (others => '0'));
339 signal SFP_EmacPhyRxD : array2X32 := (others => (others => '0'));
340 signal SFP_EmacPhyRxC : array2X4 := (others => (others => '0'));
341 signal SFP_EmacPhyRxD_q : array2X32 := (others => (others => '0'));
342 signal SFP_EmacPhyRxC_q : array2X4 := (others => (others => '0'));
343 signal SFP_PhyEmacRxD : array2X32 := (others => (others => '0'));
344 signal SFP_PhyEmacRxC : array2X4 := (others => (others => '0'));
345 signal EmacPhyTxD : array2X32 := (others => (others => '0'));
346 signal EmacPhyTxC : array2X4 := (others => (others => '0'));
347 signal PhyEmacRxD : array2X32 := (others => (others => '0'));
348 signal PhyEmacRxC : array2X4 := (others => (others => '0'));
349 
350 begin
351 clk156 <= ClientClk;
352 gtx_rxresetdone <= SFP_RXRESETDONE;
353 g_XGbEPCS : for i in 0 to 1 generate
354  i_XGbEPCS: XGbEPCS32 PORT MAP (
355  reset => TCPresetSyncRegs (2),
356  clk2x => ClientClk2X,
357  clk => ClientClk ,
358  TXUSRCLK => txusrclk,
359  TX_high => TX_high,
360  RXUSRCLK => SFP_RXUSRCLK(i),
361  RXRESETDONE => SFP_RXRESETDONE (i),
362  inh_TX => inh_TX(i),
363  RESET_TXSync => reset_TXSyncRegs (2),
364  GTX_RXGEARBOXSLIP_OUT => SFP_RXGEARBOXSLIP (i),
365  GTX_TXD => SFP_TXD(i),
366  GTX_TXHEADER => SFP_TXHEADER (i),
367  GTX_TX_PAUSE => GTX_TX_PAUSE ,
368  GTX_RXD => SFP_RXD(i),
369  GTX_RXDVLD => SFP_RXDVLD(i),
370  GTX_RXHEADER => SFP_RXHEADER (i),
371  GTX_RXHEADERVLD => SFP_RXHEADERVLD (i),
372  GTX_RXGOOD => SFP_RXGOOD(i),
373  EmacPhyTxC => SFP_EmacPhyTxc(i),
374  EmacPhyTxD => SFP_EmacPhyTxd(i),
375  PhyEmacRxC => SFP_PhyEmacRxC(i),
376  PhyEmacRxD => SFP_PhyEmacRxD(i)
377  );
378 end generate;
379 process(ClientClk)
380 begin
381  if(ClientClk'event and ClientClk = '1')then
382  ClientClkToggle <= not ClientClkToggle;
383  for i in 0 to 1 loop
384  xgmii_rxd(i) <= SFP_EmacPhyRxd(i) & SFP_EmacPhyRxd_q(i);
385  xgmii_rxc(i) <= SFP_EmacPhyRxc(i) & SFP_EmacPhyRxc_q(i);
386  end loop;
387  end if;
388 end process;
389 process(ClientClk2X)
390 begin
391  if(ClientClk2X'event and ClientClk2X = '1')then
392  ClientClkToggle_q <= ClientClkToggle;
393  SFP_EmacPhyRxd_q <= SFP_EmacPhyRxd;
394  SFP_EmacPhyRxc_q <= SFP_EmacPhyRxc;
395  TX_high <= ClientClkToggle_q xnor ClientClkToggle;
396  for i in 0 to 1 loop
397  if(TX_high = '0')then
398  SFP_EmacPhyTxd(i) <= xgmii_txd(i)(31 downto 0);
399  SFP_EmacPhyTxc(i) <= xgmii_txc(i)(3 downto 0);
400  else
401  SFP_EmacPhyTxd(i) <= xgmii_txd(i)(63 downto 32);
402  SFP_EmacPhyTxc(i) <= xgmii_txc(i)(7 downto 4);
403  end if;
404  end loop;
405  end if;
406 end process;
407 i_SFP2_init : SFP2_v2_7_init
408  port map
409  (
410  SYSCLK_IN => DRPclk,
411  SOFT_RESET_IN => '0',
412  DONT_RESET_ON_DATA_ERROR_IN => '0',
413  GT0_TX_FSM_RESET_DONE_OUT => SFP_TX_FSM_RESET_DONE (0),
414  GT0_RX_FSM_RESET_DONE_OUT => PCS_lock(0),
415  GT0_DATA_VALID_IN => SFP_RXGOOD(0),
416  GT1_TX_FSM_RESET_DONE_OUT => SFP_TX_FSM_RESET_DONE (1),
417  GT1_RX_FSM_RESET_DONE_OUT => PCS_lock(1),
418  GT1_DATA_VALID_IN => SFP_RXGOOD(1),
419 
420 
421 
422 
423 
424  --_____________________________________________________________________
425  --_____________________________________________________________________
426  --GT0 (X1Y12)
427 
428  ---------------------------- Channel - DRP Ports --------------------------
429  GT0_DRPADDR_IN => SFP_drpaddr(0),
430  GT0_DRPCLK_IN => DRPclk,
431  GT0_DRPDI_IN => SFP_drpdi(0),
432  GT0_DRPDO_OUT => SFP_drpdo(0),
433  GT0_DRPEN_IN => SFP_drpen(0),
434  GT0_DRPRDY_OUT => SFP_drprdy(0),
435  GT0_DRPWE_IN => SFP_drpwe(0),
436  ------------------------------- Loopback Ports -----------------------------
437  GT0_LOOPBACK_IN => SFP_LOOPBACK_IN(0),
438  ------------------------------ Power-Down Ports ----------------------------
439  GT0_RXPD_IN => SFP_pd(0),
440  GT0_TXPD_IN => SFP_pd(0),
441  --------------------- RX Initialization and Reset Ports --------------------
442  GT0_RXUSERRDY_IN => SFP_rxuserrdy(0),
443  -------------------------- RX Margin Analysis Ports ------------------------
444  GT0_EYESCANDATAERROR_OUT => SFP_EYESCANDATAERROR_OUT (0),
445  ------------------------- Receive Ports - CDR Ports ------------------------
446  GT0_RXCDRLOCK_OUT => open,
447  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
448  GT0_RXUSRCLK_IN => SFP_RXUSRCLK(0),
449  GT0_RXUSRCLK2_IN => SFP_RXUSRCLK(0),
450  ------------------ Receive Ports - FPGA RX interface Ports -----------------
451  GT0_RXDATA_OUT => SFP_RXD_inv(0),
452  ------------------- Receive Ports - Pattern Checker Ports ------------------
453  GT0_RXPRBSERR_OUT => SFP_RXPRBSERR_OUT (0),
454  GT0_RXPRBSSEL_IN => SFP_RXPRBSSEL_IN (0),
455  ------------------- Receive Ports - Pattern Checker ports ------------------
456  GT0_RXPRBSCNTRESET_IN => '0',
457  --------------------------- Receive Ports - RX AFE -------------------------
458  GT0_GTXRXP_IN => SFP0_RXP,
459  ------------------------ Receive Ports - RX AFE Ports ----------------------
460  GT0_GTXRXN_IN => SFP0_RXN,
461  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
462  GT0_RXBUFRESET_IN => '0',
463  GT0_RXBUFSTATUS_OUT => open,
464  --------------- Receive Ports - RX Fabric Output Control Ports -------------
465  GT0_RXOUTCLK_OUT => SFP_rxoutclk(0),
466  ---------------------- Receive Ports - RX Gearbox Ports --------------------
467  GT0_RXDATAVALID_OUT => SFP_RXDVLD(0),
468  GT0_RXHEADER_OUT => SFP_RXHEADER(0),
469  GT0_RXHEADERVALID_OUT => SFP_RXHEADERVLD(0),
470  --------------------- Receive Ports - RX Gearbox Ports --------------------
471  GT0_RXGEARBOXSLIP_IN => SFP_RXGEARBOXSLIP (0),
472  ------------- Receive Ports - RX Initialization and Reset Ports ------------
473  GT0_GTRXRESET_IN => SFP_gtrxreset(0),
474  GT0_RXPMARESET_IN => '0',
475  ------------------ Receive Ports - RX Margin Analysis ports ----------------
476  GT0_RXLPMEN_IN => '0',
477  -------------- Receive Ports -RX Initialization and Reset Ports ------------
478  GT0_RXRESETDONE_OUT => SFP_rxresetdone(0),
479  --------------------- TX Initialization and Reset Ports --------------------
480  GT0_GTTXRESET_IN => SFP_gttxreset(0),
481  GT0_TXUSERRDY_IN => SFP_txuserrdy(0),
482  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
483  GT0_TXUSRCLK_IN => txusrclk,
484  GT0_TXUSRCLK2_IN => txusrclk,
485  --------------- Transmit Ports - TX Configurable Driver Ports --------------
486  GT0_TXDIFFCTRL_IN => "1110",
487  GT0_TXINHIBIT_IN => '0',
488  GT0_TXMAINCURSOR_IN => (others => '0'),
489  ------------------ Transmit Ports - TX Data Path interface -----------------
490  GT0_TXDATA_IN => SFP_TXD_inv(0),
491  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
492  GT0_GTXTXN_OUT => SFP0_TXN,
493  GT0_GTXTXP_OUT => SFP0_TXP,
494  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
495  GT0_TXOUTCLK_OUT => SFP_TXOUTCLK(0),
496  GT0_TXOUTCLKFABRIC_OUT => open,
497  GT0_TXOUTCLKPCS_OUT => open,
498  --------------------- Transmit Ports - TX Gearbox Ports --------------------
499  GT0_TXHEADER_IN => SFP_TXHEADER(0),
500  GT0_TXSEQUENCE_IN => SFP_TXSEQUENCE(0),
501  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
502  GT0_TXRESETDONE_OUT => SFP_txresetdone(0),
503  ------------------ Transmit Ports - pattern Generator Ports ----------------
504  GT0_TXPRBSSEL_IN => SFP_TXPRBSSEL_IN (0),
505 
506 
507 
508 
509 
510 
511  --_____________________________________________________________________
512  --_____________________________________________________________________
513  --GT1 (X1Y13)
514 
515  ---------------------------- Channel - DRP Ports --------------------------
516  GT1_DRPADDR_IN => SFP_drpaddr(1),
517  GT1_DRPCLK_IN => DRPclk,
518  GT1_DRPDI_IN => SFP_drpdi(1),
519  GT1_DRPDO_OUT => SFP_drpdo(1),
520  GT1_DRPEN_IN => SFP_drpen(1),
521  GT1_DRPRDY_OUT => SFP_drprdy(1),
522  GT1_DRPWE_IN => SFP_drpwe(1),
523  ------------------------------- Loopback Ports -----------------------------
524  GT1_LOOPBACK_IN => SFP_LOOPBACK_IN(1),
525  ------------------------------ Power-Down Ports ----------------------------
526  GT1_RXPD_IN => SFP_pd(1),
527  GT1_TXPD_IN => SFP_pd(1),
528  --------------------- RX Initialization and Reset Ports --------------------
529  GT1_RXUSERRDY_IN => SFP_rxuserrdy(1),
530  -------------------------- RX Margin Analysis Ports ------------------------
531  GT1_EYESCANDATAERROR_OUT => SFP_EYESCANDATAERROR_OUT (1),
532  ------------------------- Receive Ports - CDR Ports ------------------------
533  GT1_RXCDRLOCK_OUT => open,
534  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
535  GT1_RXUSRCLK_IN => SFP_RXUSRCLK(1),
536  GT1_RXUSRCLK2_IN => SFP_RXUSRCLK(1),
537  ------------------ Receive Ports - FPGA RX interface Ports -----------------
538  GT1_RXDATA_OUT => SFP_RXD_inv(1),
539  ------------------- Receive Ports - Pattern Checker Ports ------------------
540  GT1_RXPRBSERR_OUT => SFP_RXPRBSERR_OUT (1),
541  GT1_RXPRBSSEL_IN => SFP_RXPRBSSEL_IN (1),
542  ------------------- Receive Ports - Pattern Checker ports ------------------
543  GT1_RXPRBSCNTRESET_IN => '0',
544  --------------------------- Receive Ports - RX AFE -------------------------
545  GT1_GTXRXP_IN => SFP1_RXP,
546  ------------------------ Receive Ports - RX AFE Ports ----------------------
547  GT1_GTXRXN_IN => SFP1_RXN,
548  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
549  GT1_RXBUFRESET_IN => '0',
550  GT1_RXBUFSTATUS_OUT => open,
551  --------------- Receive Ports - RX Fabric Output Control Ports -------------
552  GT1_RXOUTCLK_OUT => SFP_rxoutclk(1),
553  ---------------------- Receive Ports - RX Gearbox Ports --------------------
554  GT1_RXDATAVALID_OUT => SFP_RXDVLD(1),
555  GT1_RXHEADER_OUT => SFP_RXHEADER(1),
556  GT1_RXHEADERVALID_OUT => SFP_RXHEADERVLD(1),
557  --------------------- Receive Ports - RX Gearbox Ports --------------------
558  GT1_RXGEARBOXSLIP_IN => SFP_RXGEARBOXSLIP (1),
559  ------------- Receive Ports - RX Initialization and Reset Ports ------------
560  GT1_GTRXRESET_IN => SFP_gtrxreset(1),
561  GT1_RXPMARESET_IN => '0',
562  ------------------ Receive Ports - RX Margin Analysis ports ----------------
563  GT1_RXLPMEN_IN => '0',
564  -------------- Receive Ports -RX Initialization and Reset Ports ------------
565  GT1_RXRESETDONE_OUT => SFP_rxresetdone(1),
566  --------------------- TX Initialization and Reset Ports --------------------
567  GT1_GTTXRESET_IN => SFP_gttxreset(1),
568  GT1_TXUSERRDY_IN => SFP_txuserrdy(1),
569  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
570  GT1_TXUSRCLK_IN => txusrclk,
571  GT1_TXUSRCLK2_IN => txusrclk,
572  --------------- Transmit Ports - TX Configurable Driver Ports --------------
573  GT1_TXDIFFCTRL_IN => "1110",
574  GT1_TXINHIBIT_IN => '0',
575  GT1_TXMAINCURSOR_IN => (others => '0'),
576  ------------------ Transmit Ports - TX Data Path interface -----------------
577  GT1_TXDATA_IN => SFP_TXD_inv(1),
578  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
579  GT1_GTXTXN_OUT => SFP1_TXN,
580  GT1_GTXTXP_OUT => SFP1_TXP,
581  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
582  GT1_TXOUTCLK_OUT => open,
583  GT1_TXOUTCLKFABRIC_OUT => open,
584  GT1_TXOUTCLKPCS_OUT => open,
585  --------------------- Transmit Ports - TX Gearbox Ports --------------------
586  GT1_TXHEADER_IN => SFP_TXHEADER(1),
587  GT1_TXSEQUENCE_IN => SFP_TXSEQUENCE(1),
588  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
589  GT1_TXRESETDONE_OUT => SFP_txresetdone(1),
590  ------------------ Transmit Ports - pattern Generator Ports ----------------
591  GT1_TXPRBSSEL_IN => SFP_TXPRBSSEL_IN (1),
592 
593 
594  --____________________________COMMON PORTS________________________________
595  ---------------------- Common Block - Ref Clock Ports ---------------------
596  GT0_GTREFCLK0_COMMON_IN => SFP_REFCLK,
597  ------------------------- Common Block - QPLL Ports ------------------------
598  GT0_QPLLLOCK_OUT => qplllock,
599  GT0_QPLLLOCKDETCLK_IN => DRPclk,
600  GT0_QPLLRESET_IN => qpllreset
601 
602  );
603 process(SFP_TXD,SFP_RXD,SFP_RXD_inv)
604  begin
605  for j in 0 to 1 loop
606  for i in 0 to 31 loop
607  SFP_TXD_inv(j)(i) <= SFP_TXD(j)(31-i);
608  SFP_RXD(j)(i) <= SFP_RXD_inv(j)(31-i);
609  end loop;
610  end loop;
611 end process;
612 i_REFCLK : IBUFDS_GTE2 port map(O => SFP_REFCLK, ODIV2 => open, CEB => '0', I => SFP_REFCLK_P, IB => SFP_REFCLK_N);
613 i_txusrclk : BUFG port map (I => SFP_TXOUTCLK(0), O => txusrclk);
614 g_SFP_rxusrclk : for i in 0 to 1 generate
615  i_SFP_rxusrclk : BUFG port map (I => SFP_RXOUTCLK(i), O => SFP_rxusrclk(i));
616 end generate;
617 i_REFCLK2X_in: bufg port map(i => SFP_REFCLK, o => REFCLK2X_in);
618 i_ClientClk2X : BUFG port map (I => ClientClk2X_dcm, O => ClientClk2X);
619 i_ClientClk : BUFG port map (I => ClientClk_dcm, O => ClientClk);
620 i_REFCLK2XPLLRST : SRL16 generic map(INIT => x"ffff" )
621  port map (
622  Q => REFCLK2XPLLRST, -- SRL data output
623  A0 => '1', -- Select[0] input
624  A1 => '1', -- Select[1] input
625  A2 => '1', -- Select[2] input
626  A3 => '1', -- Select[3] input
627  CLK => REFCLK2X_in, -- Clock input
628  D => '0' -- SRL data input
629  );
630 i_REFCLK2XPLL : PLLE2_BASE
631  generic map (
632  BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
633  CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
634  CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
635  CLKIN1_PERIOD => 6.4, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
636  -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
637  CLKOUT0_DIVIDE => 4,
638  DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
639  REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
640  STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
641  )
642  port map (
643  -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
644  CLKOUT0 => ClientClk2X_dcm ,
645  -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
646  CLKFBOUT => ClientClk_dcm, -- 1-bit output: Feedback clock
647  -- Status Port: 1-bit (each) output: PLL status ports
648  LOCKED => ClientClk_lock, -- 1-bit output: LOCK
649  -- Clock Input: 1-bit (each) input: Clock input
650  CLKIN1 => REFCLK2X_in, -- 1-bit input: Input clock
651  -- Control Ports: 1-bit (each) input: PLL control ports
652  PWRDWN => '0', -- 1-bit input: Power-down
653  RST => REFCLK2XPLLRST, -- 1-bit input: Reset
654  -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
655  CLKFBIN => ClientClk -- 1-bit input: Feedback clock
656  );
657 
658 
659 end Behavioral;
660 
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