AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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serdes5_wrapper.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 10:12:42 12/19/2013
6 -- Design Name:
7 -- Module Name: serdes5_wrapper - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use work.amc13_pack.all;
23 
24 -- Uncomment the following library declaration if using
25 -- arithmetic functions with Signed or Unsigned values
26 --use IEEE.NUMERIC_STD.ALL;
27 
28 -- Uncomment the following library declaration if instantiating
29 -- any Xilinx primitives in this code.
30 library UNISIM;
31 use UNISIM.VComponents.all;
32 
33 entity serdes5_wrapper is
34  Port ( refclk : in STD_LOGIC;
35  DRPclk : in STD_LOGIC;
36  sfp_pd : in array2x2;
37  txusrclk_out : out STD_LOGIC;
38  qplllock : out STD_LOGIC;
39  gtx_reset : in STD_LOGIC;
40  data_valid : in STD_LOGIC_VECTOR (1 downto 0);
41  sfp_rxp : in STD_LOGIC_VECTOR (1 downto 0);
42  sfp_rxn : in STD_LOGIC_VECTOR (1 downto 0);
43  txfsmresetdone : out STD_LOGIC_VECTOR (1 downto 0);
44  rxfsmresetdone : out STD_LOGIC_VECTOR (1 downto 0);
45  rxcdrlock : out STD_LOGIC_VECTOR (1 downto 0);
46  rxnotintable : out array2x4;
47  rxmcommaalignen : in STD_LOGIC_VECTOR (1 downto 0);
48  rxpcommaalignen : in STD_LOGIC_VECTOR (1 downto 0);
49  rxbyteisaligned : out STD_LOGIC_VECTOR (1 downto 0);
50  rxbyterealign : out STD_LOGIC_VECTOR (1 downto 0);
51  rxcommadet : out STD_LOGIC_VECTOR (1 downto 0);
52  rxchariscomma : out array2x4;
53  rxcharisk : out array2x4;
54  rxresetdone : out STD_LOGIC_VECTOR (1 downto 0);
55  txresetdone : out STD_LOGIC_VECTOR (1 downto 0);
56  txcharisk : in array2x4;
57  txdata : in array2x32;
58  rxdata : out array2x32;
59  sfp_txp : out STD_LOGIC_VECTOR (1 downto 0);
60  sfp_txn : out STD_LOGIC_VECTOR (1 downto 0));
61 end serdes5_wrapper;
62 
63 architecture Behavioral of serdes5_wrapper is
64 --component serdes5GpdProd_HCALprod_init
65 --generic
66 --(
67 -- -- Simulation attributes
68 -- EXAMPLE_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to 1 to speed up sim reset
69 -- EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
70 -- STABLE_CLOCK_PERIOD : integer := 20; --Period of the stable clock driving this state-machine, unit is [ns]
71 -- EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
72 
73 --);
74 --port
75 --(
76 -- SYSCLK_IN : in std_logic;
77 -- SOFT_RESET_IN : in std_logic;
78 -- DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
79 -- GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
80 -- GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
81 -- GT0_DATA_VALID_IN : in std_logic;
82 -- GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
83 -- GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
84 -- GT1_DATA_VALID_IN : in std_logic;
85 
86 -- --_________________________________________________________________________
87 -- --GT0 (X1Y13)
88 -- --____________________________CHANNEL PORTS________________________________
89 -- ---------------------------- Channel - DRP Ports --------------------------
90 -- GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
91 -- GT0_DRPCLK_IN : in std_logic;
92 -- GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
93 -- GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
94 -- GT0_DRPEN_IN : in std_logic;
95 -- GT0_DRPRDY_OUT : out std_logic;
96 -- GT0_DRPWE_IN : in std_logic;
97 -- ------------------------------ Power-Down Ports ----------------------------
98 -- GT0_RXPD_IN : in std_logic_vector(1 downto 0);
99 -- GT0_TXPD_IN : in std_logic_vector(1 downto 0);
100 -- --------------------- RX Initialization and Reset Ports --------------------
101 -- GT0_RXUSERRDY_IN : in std_logic;
102 -- -------------------------- RX Margin Analysis Ports ------------------------
103 -- GT0_EYESCANDATAERROR_OUT : out std_logic;
104 -- ------------------------- Receive Ports - CDR Ports ------------------------
105 -- GT0_RXCDRLOCK_OUT : out std_logic;
106 -- ------------------- Receive Ports - Clock Correction Ports -----------------
107 -- GT0_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
108 -- ------------------ Receive Ports - FPGA RX Interface Ports -----------------
109 -- GT0_RXUSRCLK_IN : in std_logic;
110 -- GT0_RXUSRCLK2_IN : in std_logic;
111 -- ------------------ Receive Ports - FPGA RX interface Ports -----------------
112 -- GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
113 -- ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
114 -- GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
115 -- GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
116 -- --------------------------- Receive Ports - RX AFE -------------------------
117 -- GT0_GTXRXP_IN : in std_logic;
118 -- ------------------------ Receive Ports - RX AFE Ports ----------------------
119 -- GT0_GTXRXN_IN : in std_logic;
120 -- ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
121 -- GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
122 -- -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
123 -- GT0_RXBYTEISALIGNED_OUT : out std_logic;
124 -- GT0_RXBYTEREALIGN_OUT : out std_logic;
125 -- GT0_RXCOMMADET_OUT : out std_logic;
126 -- GT0_RXMCOMMAALIGNEN_IN : in std_logic;
127 -- GT0_RXPCOMMAALIGNEN_IN : in std_logic;
128 -- ------------- Receive Ports - RX Initialization and Reset Ports ------------
129 -- GT0_GTRXRESET_IN : in std_logic;
130 -- GT0_RXPMARESET_IN : in std_logic;
131 -- ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
132 -- GT0_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
133 -- GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
134 -- -------------- Receive Ports -RX Initialization and Reset Ports ------------
135 -- GT0_RXRESETDONE_OUT : out std_logic;
136 -- --------------------- TX Initialization and Reset Ports --------------------
137 -- GT0_GTTXRESET_IN : in std_logic;
138 -- GT0_TXUSERRDY_IN : in std_logic;
139 -- ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
140 -- GT0_TXUSRCLK_IN : in std_logic;
141 -- GT0_TXUSRCLK2_IN : in std_logic;
142 -- ------------------ Transmit Ports - TX Data Path interface -----------------
143 -- GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
144 -- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
145 -- GT0_GTXTXN_OUT : out std_logic;
146 -- GT0_GTXTXP_OUT : out std_logic;
147 -- ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
148 -- GT0_TXOUTCLK_OUT : out std_logic;
149 -- GT0_TXOUTCLKFABRIC_OUT : out std_logic;
150 -- GT0_TXOUTCLKPCS_OUT : out std_logic;
151 -- --------------------- Transmit Ports - TX Gearbox Ports --------------------
152 -- GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
153 -- ------------- Transmit Ports - TX Initialization and Reset Ports -----------
154 -- GT0_TXRESETDONE_OUT : out std_logic;
155 
156 -- --_________________________________________________________________________
157 -- --GT1 (X1Y14)
158 -- --____________________________CHANNEL PORTS________________________________
159 -- ---------------------------- Channel - DRP Ports --------------------------
160 -- GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
161 -- GT1_DRPCLK_IN : in std_logic;
162 -- GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
163 -- GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
164 -- GT1_DRPEN_IN : in std_logic;
165 -- GT1_DRPRDY_OUT : out std_logic;
166 -- GT1_DRPWE_IN : in std_logic;
167 -- ------------------------------ Power-Down Ports ----------------------------
168 -- GT1_RXPD_IN : in std_logic_vector(1 downto 0);
169 -- GT1_TXPD_IN : in std_logic_vector(1 downto 0);
170 -- --------------------- RX Initialization and Reset Ports --------------------
171 -- GT1_RXUSERRDY_IN : in std_logic;
172 -- -------------------------- RX Margin Analysis Ports ------------------------
173 -- GT1_EYESCANDATAERROR_OUT : out std_logic;
174 -- ------------------------- Receive Ports - CDR Ports ------------------------
175 -- GT1_RXCDRLOCK_OUT : out std_logic;
176 -- ------------------- Receive Ports - Clock Correction Ports -----------------
177 -- GT1_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
178 -- ------------------ Receive Ports - FPGA RX Interface Ports -----------------
179 -- GT1_RXUSRCLK_IN : in std_logic;
180 -- GT1_RXUSRCLK2_IN : in std_logic;
181 -- ------------------ Receive Ports - FPGA RX interface Ports -----------------
182 -- GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
183 -- ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
184 -- GT1_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
185 -- GT1_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
186 -- --------------------------- Receive Ports - RX AFE -------------------------
187 -- GT1_GTXRXP_IN : in std_logic;
188 -- ------------------------ Receive Ports - RX AFE Ports ----------------------
189 -- GT1_GTXRXN_IN : in std_logic;
190 -- ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
191 -- GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
192 -- -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
193 -- GT1_RXBYTEISALIGNED_OUT : out std_logic;
194 -- GT1_RXBYTEREALIGN_OUT : out std_logic;
195 -- GT1_RXCOMMADET_OUT : out std_logic;
196 -- GT1_RXMCOMMAALIGNEN_IN : in std_logic;
197 -- GT1_RXPCOMMAALIGNEN_IN : in std_logic;
198 -- ------------- Receive Ports - RX Initialization and Reset Ports ------------
199 -- GT1_GTRXRESET_IN : in std_logic;
200 -- GT1_RXPMARESET_IN : in std_logic;
201 -- ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
202 -- GT1_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
203 -- GT1_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
204 -- -------------- Receive Ports -RX Initialization and Reset Ports ------------
205 -- GT1_RXRESETDONE_OUT : out std_logic;
206 -- --------------------- TX Initialization and Reset Ports --------------------
207 -- GT1_GTTXRESET_IN : in std_logic;
208 -- GT1_TXUSERRDY_IN : in std_logic;
209 -- ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
210 -- GT1_TXUSRCLK_IN : in std_logic;
211 -- GT1_TXUSRCLK2_IN : in std_logic;
212 -- ------------------ Transmit Ports - TX Data Path interface -----------------
213 -- GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
214 -- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
215 -- GT1_GTXTXN_OUT : out std_logic;
216 -- GT1_GTXTXP_OUT : out std_logic;
217 -- ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
218 -- GT1_TXOUTCLK_OUT : out std_logic;
219 -- GT1_TXOUTCLKFABRIC_OUT : out std_logic;
220 -- GT1_TXOUTCLKPCS_OUT : out std_logic;
221 -- --------------------- Transmit Ports - TX Gearbox Ports --------------------
222 -- GT1_TXCHARISK_IN : in std_logic_vector(3 downto 0);
223 -- ------------- Transmit Ports - TX Initialization and Reset Ports -----------
224 -- GT1_TXRESETDONE_OUT : out std_logic;
225 
226 
227 -- --____________________________COMMON PORTS________________________________
228 -- ---------------------- Common Block - Ref Clock Ports ---------------------
229 -- GT0_GTREFCLK0_COMMON_IN : in std_logic;
230 -- ------------------------- Common Block - QPLL Ports ------------------------
231 -- GT0_QPLLLOCK_OUT : out std_logic;
232 -- GT0_QPLLLOCKDETCLK_IN : in std_logic;
233 -- GT0_QPLLRESET_IN : in std_logic
234 
235 
236 --);
237 --end component;
238 signal txusrclk : std_logic := '0';
239 signal gt0_txoutclk : std_logic := '0';
240 --signal : std_logic := '0';
241 --signal : std_logic_vector(2 downto 0) := (others => '0');
242 
243 begin
244  serdes5Gpd_HCALprod_init_i : entity work.serdes5Gpd_HCALprod_init
245  port map
246  (
247  SYSCLK_IN => DRPclk ,
248  SOFT_RESET_IN => '0',
249  DONT_RESET_ON_DATA_ERROR_IN => '0',
250  GT0_TX_FSM_RESET_DONE_OUT => txfsmresetdone(0),
251  GT0_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(0),
252  GT0_DATA_VALID_IN => data_valid(0),
253  GT1_TX_FSM_RESET_DONE_OUT => txfsmresetdone(1),
254  GT1_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(1),
255  GT1_DATA_VALID_IN => data_valid(1),
256 
257  --_____________________________________________________________________
258  --_____________________________________________________________________
259  --GT0 (X1Y12)
260 
261  ---------------------------- Channel - DRP Ports --------------------------
262  GT0_DRPADDR_IN => (others => '0'),
263  GT0_DRPCLK_IN => DRPclk,
264  GT0_DRPDI_IN => (others => '0'),
265  GT0_DRPDO_OUT => open,
266  GT0_DRPEN_IN => '0',
267  GT0_DRPRDY_OUT => open,
268  GT0_DRPWE_IN => '0',
269  ------------------------------ Power-Down Ports ----------------------------
270  GT0_RXPD_IN => sfp_pd (0),
271  GT0_TXPD_IN => sfp_pd (0),
272  --------------------- RX Initialization and Reset Ports --------------------
273  GT0_RXUSERRDY_IN => '0',
274  -------------------------- RX Margin Analysis Ports ------------------------
275  GT0_EYESCANDATAERROR_OUT => open,
276  ------------------------- Receive Ports - CDR Ports ------------------------
277  GT0_RXCDRLOCK_OUT => rxcdrlock(0),
278  ------------------- Receive Ports - Clock Correction Ports -----------------
279  GT0_RXCLKCORCNT_OUT => open,
280  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
281  GT0_RXUSRCLK_IN => txusrclk,
282  GT0_RXUSRCLK2_IN => txusrclk,
283  ------------------ Receive Ports - FPGA RX interface Ports -----------------
284  GT0_RXDATA_OUT => rxdata(0),
285  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
286  GT0_RXDISPERR_OUT => open,
287  GT0_RXNOTINTABLE_OUT => rxnotintable (0),
288  --------------------------- Receive Ports - RX AFE -------------------------
289  GT0_GTXRXP_IN => sfp_rxp (0),
290  ------------------------ Receive Ports - RX AFE Ports ----------------------
291  GT0_GTXRXN_IN => sfp_rxn (0),
292  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
293  GT0_RXBUFSTATUS_OUT => open,
294  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
295  GT0_RXBYTEISALIGNED_OUT => rxbyteisaligned(0),
296  GT0_RXBYTEREALIGN_OUT => rxbyterealign(0),
297  GT0_RXCOMMADET_OUT => rxcommadet(0),
298  GT0_RXMCOMMAALIGNEN_IN => rxmcommaalignen(0),
299  GT0_RXPCOMMAALIGNEN_IN => rxpcommaalignen(0),
300  ------------- Receive Ports - RX Initialization and Reset Ports ------------
301  GT0_GTRXRESET_IN => gtx_reset,
302  GT0_RXPMARESET_IN => '0',
303  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
304  GT0_RXCHARISCOMMA_OUT => rxchariscomma(0),
305  GT0_RXCHARISK_OUT => rxcharisk(0),
306  -------------- Receive Ports -RX Initialization and Reset Ports ------------
307  GT0_RXRESETDONE_OUT => rxresetdone (0),
308  --------------------- TX Initialization and Reset Ports --------------------
309  GT0_GTTXRESET_IN => gtx_reset,
310  GT0_TXUSERRDY_IN => '0',
311  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
312  GT0_TXUSRCLK_IN => txusrclk,
313  GT0_TXUSRCLK2_IN => txusrclk,
314  ------------------ Transmit Ports - TX Data Path interface -----------------
315  GT0_TXDATA_IN => txdata(0),
316  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
317  GT0_GTXTXN_OUT => sfp_txn(0),
318  GT0_GTXTXP_OUT => sfp_txp(0),
319  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
320  GT0_TXOUTCLK_OUT => gt0_txoutclk ,
321  GT0_TXOUTCLKFABRIC_OUT => open,
322  GT0_TXOUTCLKPCS_OUT => open,
323  --------------------- Transmit Ports - TX Gearbox Ports --------------------
324  GT0_TXCHARISK_IN => txcharisk(0),
325  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
326  GT0_TXRESETDONE_OUT => txresetdone (0),
327 
328 
329 
330 
331 
332 
333  --_____________________________________________________________________
334  --_____________________________________________________________________
335  --GT1 (X1Y13)
336 
337  ---------------------------- Channel - DRP Ports --------------------------
338  GT1_DRPADDR_IN => (others => '0'),
339  GT1_DRPCLK_IN => DRPclk,
340  GT1_DRPDI_IN => (others => '0'),
341  GT1_DRPDO_OUT => open,
342  GT1_DRPEN_IN => '0',
343  GT1_DRPRDY_OUT => open,
344  GT1_DRPWE_IN => '0',
345  ------------------------------ Power-Down Ports ----------------------------
346  GT1_RXPD_IN => sfp_pd (1),
347  GT1_TXPD_IN => sfp_pd (1),
348  --------------------- RX Initialization and Reset Ports --------------------
349  GT1_RXUSERRDY_IN => '0',
350  -------------------------- RX Margin Analysis Ports ------------------------
351  GT1_EYESCANDATAERROR_OUT => open,
352  ------------------------- Receive Ports - CDR Ports ------------------------
353  GT1_RXCDRLOCK_OUT => rxcdrlock(1),
354  ------------------- Receive Ports - Clock Correction Ports -----------------
355  GT1_RXCLKCORCNT_OUT => open,
356  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
357  GT1_RXUSRCLK_IN => txusrclk,
358  GT1_RXUSRCLK2_IN => txusrclk,
359  ------------------ Receive Ports - FPGA RX interface Ports -----------------
360  GT1_RXDATA_OUT => rxdata(1),
361  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
362  GT1_RXDISPERR_OUT => open,
363  GT1_RXNOTINTABLE_OUT => rxnotintable (1),
364  --------------------------- Receive Ports - RX AFE -------------------------
365  GT1_GTXRXP_IN => sfp_rxp (1),
366  ------------------------ Receive Ports - RX AFE Ports ----------------------
367  GT1_GTXRXN_IN => sfp_rxn (1),
368  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
369  GT1_RXBUFSTATUS_OUT => open,
370  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
371  GT1_RXBYTEISALIGNED_OUT => rxbyteisaligned(1),
372  GT1_RXBYTEREALIGN_OUT => rxbyterealign(1),
373  GT1_RXCOMMADET_OUT => rxcommadet(1),
374  GT1_RXMCOMMAALIGNEN_IN => rxmcommaalignen(1),
375  GT1_RXPCOMMAALIGNEN_IN => rxpcommaalignen(1),
376  ------------- Receive Ports - RX Initialization and Reset Ports ------------
377  GT1_GTRXRESET_IN => gtx_reset,
378  GT1_RXPMARESET_IN => '0',
379  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
380  GT1_RXCHARISCOMMA_OUT => rxchariscomma(1),
381  GT1_RXCHARISK_OUT => rxcharisk(1),
382  -------------- Receive Ports -RX Initialization and Reset Ports ------------
383  GT1_RXRESETDONE_OUT => rxresetdone (1),
384  --------------------- TX Initialization and Reset Ports --------------------
385  GT1_GTTXRESET_IN => gtx_reset,
386  GT1_TXUSERRDY_IN => '0',
387  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
388  GT1_TXUSRCLK_IN => txusrclk,
389  GT1_TXUSRCLK2_IN => txusrclk,
390  ------------------ Transmit Ports - TX Data Path interface -----------------
391  GT1_TXDATA_IN => txdata(1),
392  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
393  GT1_GTXTXN_OUT => sfp_txn(1),
394  GT1_GTXTXP_OUT => sfp_txp(1),
395  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
396  GT1_TXOUTCLK_OUT => open,
397  GT1_TXOUTCLKFABRIC_OUT => open,
398  GT1_TXOUTCLKPCS_OUT => open,
399  --------------------- Transmit Ports - TX Gearbox Ports --------------------
400  GT1_TXCHARISK_IN => txcharisk(1),
401  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
402  GT1_TXRESETDONE_OUT => txresetdone (1),
403 
404 
405  --____________________________COMMON PORTS________________________________
406  ---------------------- Common Block - Ref Clock Ports ---------------------
407  GT0_GTREFCLK0_COMMON_IN => refclk,
408  ------------------------- Common Block - QPLL Ports ------------------------
409  GT0_QPLLLOCK_OUT => qplllock,
410  GT0_QPLLLOCKDETCLK_IN => DRPclk,
411  GT0_QPLLRESET_IN => '0'
412 
413  );
414 
415 i_txusrclk: bufg port map(i => gt0_txoutclk, o => txusrclk);
416 txusrclk_out <= txusrclk;
417 
418 end Behavioral;
419 
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