AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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AMC_if.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 15:55:15 07/09/2010
6 -- Design Name:
7 -- Module Name: AMC_if - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 ----------------------------------------------------------------------------------
19 library IEEE;
20 use IEEE.STD_LOGIC_1164.ALL;
21 use IEEE.STD_LOGIC_ARITH.ALL;
22 use IEEE.STD_LOGIC_UNSIGNED.ALL;
23 use IEEE.std_logic_misc.all;
24 use work.amc13_pack.all;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 --use IEEE.NUMERIC_STD.ALL;
29 
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 library UNISIM;
33 use UNISIM.VComponents.all;
34 Library UNIMACRO;
35 use UNIMACRO.vcomponents.all;
36 
37 entity AMC_if is
38  Generic (useTCPIP : boolean := true; AMC_useTRIG : boolean := false; simulation : boolean := false);
39  Port ( sysclk : in STD_LOGIC;
40  ipb_clk : in std_logic;
41  clk125 : in std_logic;
42  DRPclk : in std_logic;
43  GTXreset : in STD_LOGIC;
44  reset : in STD_LOGIC;
45  DB_cmd : IN std_logic;
46  ReSync : IN std_logic;
47  resetCntr : in STD_LOGIC;
48  run : in STD_LOGIC;
49  en_inject_err : in STD_LOGIC;
50  AllEventBuilt : out STD_LOGIC;
51  Dis_pd : in STD_LOGIC;
52  enSFP : IN std_logic_vector(3 downto 0);
53  en_localL1A : IN std_logic;
54  test : in STD_LOGIC;
55  NoReSyncFake : in STD_LOGIC;
56  WaitMonBuf : in STD_LOGIC;
57  fake_length : in std_logic_vector(19 downto 0);
58  T1_version : in STD_LOGIC_VECTOR(7 downto 0);
59  Source_ID : in array3x12;
60  AMC_en : in STD_LOGIC_VECTOR(11 downto 0);
61  AMC_Ready : out STD_LOGIC_VECTOR(11 downto 0);
62  BC0_lock : out STD_LOGIC_VECTOR(11 downto 0);
63  TTC_lock : out STD_LOGIC;
64  AMC_REFCLK_P : in STD_LOGIC;
65  AMC_REFCLK_N : in STD_LOGIC;
66  AMC_RXN : in STD_LOGIC_VECTOR(12 downto 1);
67  AMC_RXP : in STD_LOGIC_VECTOR(12 downto 1);
68  AMC_TXN : out STD_LOGIC_VECTOR(12 downto 1);
69  AMC_TXP : out STD_LOGIC_VECTOR(12 downto 1);
70  AMC_status : out STD_LOGIC_VECTOR(31 downto 0);
71  evt_data : out array3X67;-- bit 66 is TCP/mon space, bit 65 is end_of_event and bit 64 is end_of_block
72  evt_data_re : in std_logic_vector(2 downto 0);
73  evt_buf_full : in std_logic_vector(2 downto 0);
74  evt_data_we : out std_logic_vector(2 downto 0);
75  evt_data_rdy : out std_logic_vector(2 downto 0);
76  ddr_pa : in STD_LOGIC_VECTOR(9 downto 0);
77  MonBuf_empty : in STD_LOGIC;
78  mon_evt_wc : out STD_LOGIC_VECTOR (47 downto 0);
79  mon_ctrl : out STD_LOGIC_VECTOR (31 downto 0);
80 -- buffer control
81  mon_buf_avl : in STD_LOGIC; --
82  TCPbuf_avl : in STD_LOGIC; --
83  buf_rqst : out STD_LOGIC_VECTOR (3 downto 0);
84 -- ipbus signals
85  ipb_write : in STD_LOGIC;
86  ipb_strobe : in STD_LOGIC;
87  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
88  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
89  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
90  ipb_ack : out STD_LOGIC;
91 -- TTC & TTS signals
92  TTC_clk : in std_logic;
93  TTC_LOS : in std_logic;
94  BC0 : in std_logic;
95  TTS_disable : in std_logic_vector(11 downto 0);
96  ttc_evcnt_reset : in std_logic;
97  event_number_avl : in std_logic;
98  event_number : in std_logic_vector(59 downto 0);
99  evn_buf_full : out std_logic;
100  ovfl_warning : out std_logic;
101  TrigData : out array12x8;
102  TTS_coded : out std_logic_vector(4 downto 0)
103  );
104 end AMC_if;
105 
106 architecture Behavioral of AMC_if is
107 COMPONENT fake_event
108  PORT(
109  sysclk : IN std_logic;
110  UsrClk : IN std_logic;
111  reset : IN std_logic;
112  fifo_rst : IN std_logic;
113  fifo_en : IN std_logic;
114  sync : IN std_logic;
115  LinkFull : in STD_LOGIC;
116  fake_en : IN std_logic;
117  ovfl_warning : in STD_LOGIC;
118  fake_length : in std_logic_vector(19 downto 0);
119  L1A_DATA : IN std_logic_vector(15 downto 0);
120  L1A_WrEn : IN std_logic;
121  fake_header : OUT std_logic;
122  fake_CRC : OUT std_logic;
123  empty_event_flag : out STD_LOGIC;
124  fake_DATA : OUT std_logic_vector(15 downto 0);
125  fake_WrEn : OUT std_logic
126  );
127 END COMPONENT;
128 COMPONENT AMC_Link
129  generic(N : integer := 14; useTRIG : boolean := false; simulation : boolean := false); -- M controls FIFO size, N controls timeout
130  PORT(
131  sysclk : IN std_logic;
132  reset : IN std_logic;
133  resetCntr : IN std_logic;
134  fifo_rst : in std_logic;
135  fifo_en : in std_logic;
136  test : IN std_logic;
137  NoReSyncFake : IN std_logic;
138  UsrClk : IN std_logic;
139  AMC_ID : IN std_logic_vector(3 downto 0);
140  txfsmresetdone : in std_logic;
141  RxResetDone : in std_logic;
142  qpll_lock : in std_logic;
143  rxcommaalignen : out std_logic;
144  DATA_VALID : out std_logic;
145  RXDATA : in std_logic_vector(15 downto 0);
146  RXCHARISCOMMA : in std_logic_vector(1 downto 0);
147  RXCHARISK : in std_logic_vector(1 downto 0);
148  RXNOTINTABLE : in std_logic_vector(1 downto 0);
149  TXDATA : out std_logic_vector(15 downto 0);
150  TXCHARISK : out std_logic_vector(1 downto 0);
151  AMC_en : IN std_logic;
152  TTS_disable : IN std_logic;
153  AMC_DATA_RdEn : IN std_logic;
154  EventInfoRdDone : IN std_logic;
155  L1A_DATA : IN std_logic_vector(15 downto 0);
156  L1A_WrEn : IN std_logic;
157  fake_header : IN std_logic;
158  fake_CRC : IN std_logic;
159  fake_DATA : IN std_logic_vector(15 downto 0);
160  fake_WrEn : IN std_logic;
161  fake_full : OUT std_logic;
162  Cntr_ADDR : IN std_logic_vector(11 downto 0);
163  TTCclk : IN std_logic;
164  BC0 : IN std_logic;
165  TTC_LOS : IN std_logic;
166  Ready : OUT std_logic;
167  AMCinfo : OUT std_logic_vector(15 downto 0);
168  EventInfo : OUT std_logic_vector(31 downto 0);
169  EventInfo_dav : OUT std_logic;
170  AMC_DATA : OUT std_logic_vector(63 downto 0);
171  bad_AMC : OUT std_logic;
172  AMC_OK : OUT std_logic;
173  Cntr_DATA : OUT std_logic_vector(15 downto 0);
174  debug_out : OUT std_logic_vector(255 downto 0);
175  TTC_status : OUT std_logic_vector(127 downto 0);
176  TrigData : OUT std_logic_vector(7 downto 0);
177  TTS_coded : OUT std_logic_vector(4 downto 0)
178  );
179 END COMPONENT;
180 COMPONENT AMC_wrapper
181  Port ( DRPclk : in STD_LOGIC;
182  SOFT_RESET : in STD_LOGIC;
183  UsrClk : in STD_LOGIC;
184  test : in STD_LOGIC;
185  Dis_pd : in STD_LOGIC;
186  AMC_en : in STD_LOGIC_VECTOR(11 downto 0);
187  RXDATA : out array12X16;
188  RxBufOvf : out STD_LOGIC_VECTOR(11 downto 0);
189  RxBufUdf : out STD_LOGIC_VECTOR(11 downto 0);
190  sampleRatio : in STD_LOGIC;
191  updateRatio : in STD_LOGIC;
192  RxClkRatio : out array12x21;
193  rxprbserr : out STD_LOGIC_VECTOR(11 downto 0);
194  rxprbssel : in array12X3;
195  RXNOTINTABLE : out array12X2;
196  rxcommaalignen : in STD_LOGIC_VECTOR(11 downto 0);
197  rxchariscomma : out array12X2;
198  rxcharisk : out array12X2;
199  rxresetdone : out STD_LOGIC_VECTOR(11 downto 0);
200  txdiffctrl : in array12X4;
201  TXDATA : in array12X16;
202  txoutclk : out STD_LOGIC_VECTOR(11 downto 0);
203  txcharisk : in array12X2;
204  txresetdone : out STD_LOGIC_VECTOR(11 downto 0);
205  txprbssel : in array12X3;
206  qpll_lock : out STD_LOGIC_VECTOR(2 downto 0);
207  txfsmresetdone : out STD_LOGIC_VECTOR(11 downto 0);
208  rxfsmresetdone : out STD_LOGIC_VECTOR(11 downto 0);
209  data_valid : in STD_LOGIC_VECTOR(11 downto 0);
210  AMC_REFCLK : in STD_LOGIC;
211  RXN : in STD_LOGIC_VECTOR(11 downto 0);
212  RXP : in STD_LOGIC_VECTOR(11 downto 0);
213  TXN : out STD_LOGIC_VECTOR(11 downto 0);
214  TXP : out STD_LOGIC_VECTOR(11 downto 0)
215  );
216 END COMPONENT;
217 COMPONENT evt_bldr
218  PORT(
219  clk : IN std_logic;
220  reset : IN std_logic;
221  fifo_rst : IN std_logic;
222  fifo_en : IN std_logic;
223  en_inject_err : IN std_logic;
224  OneSFP : IN std_logic;
225  Source_ID : IN std_logic_vector(7 downto 0);
226  block_wc : in STD_LOGIC_VECTOR (15 downto 0);
227  block_wc_we : in STD_LOGIC;
228  AMC_wc : IN std_logic_vector(17 downto 0);
229  AMC_wc_we : IN std_logic;
230  AMC_wc_end : IN std_logic;
231  AMC_header : IN std_logic_vector(65 downto 0);
232  AMC_header_we : IN std_logic;
233  AMC_DATA : IN array12X64;
234  evt_buf_full : IN std_logic;
235  evt_data_re : IN std_logic;
236  bldr_fifo_full : OUT std_logic;
237  AMC_DATA_re : OUT std_logic_vector(11 downto 0);
238  AMCCRC_bad : OUT std_logic_vector(11 downto 0);
239  evt_data : OUT std_logic_vector(66 downto 0);
240  evt_data_we : OUT std_logic;
241  evt_data_rdy : OUT std_logic;
242  debug : out STD_LOGIC_VECTOR (255 downto 0);
243  EventBuilt : OUT std_logic
244  );
245 END COMPONENT;
246 COMPONENT AMC_cntr
247 PORT(
248  UsrClk : IN std_logic;
249  clk125 : IN std_logic;
250  sysclk : IN std_logic;
251  ipb_clk : IN std_logic;
252  resetCntr : IN std_logic;
253  DB_cmd : IN std_logic;
254  AMC_if_data : IN std_logic_vector(15 downto 0);
255  Cntr_DATA : IN array12x16;
256  Cntr_ADDR : OUT std_logic_vector(11 downto 0);
257  ipb_addr : IN std_logic_vector(15 downto 0);
258  ipb_rdata : OUT std_logic_vector(31 downto 0)
259  );
260 END COMPONENT;
261 COMPONENT cmsCRC64
262  PORT(
263  clk : IN std_logic;
264  reset : IN std_logic;
265  data_in : IN std_logic_vector(63 downto 0);
266  ctrl_in : IN std_logic;
267  we_in : IN std_logic;
268  crc : OUT std_logic_vector(15 downto 0);
269  crc_err : OUT std_logic;
270  data_out : OUT std_logic_vector(63 downto 0);
271  ctrl_out : OUT std_logic;
272  we_out : OUT std_logic
273  );
274 END COMPONENT;
275 COMPONENT FIFO_RESET_7S
276  PORT(
277  reset : IN std_logic;
278  clk : IN std_logic;
279  fifo_rst : OUT std_logic;
280  fifo_en : OUT std_logic
281  );
282 END COMPONENT;
283 COMPONENT RAM32x6Db
284  PORT(
285  wclk : IN std_logic;
286  di : IN std_logic_vector(5 downto 0);
287  we : IN std_logic;
288  wa : IN std_logic_vector(4 downto 0);
289  ra : IN std_logic_vector(4 downto 0);
290  do : OUT std_logic_vector(5 downto 0)
291  );
292 END COMPONENT;
293 type array_x12y256 is array(11 downto 0) of std_logic_vector(255 downto 0);
294 type array_x12y16 is array(11 downto 0) of std_logic_vector(15 downto 0);
295 type array_x12y32 is array(11 downto 0) of std_logic_vector(31 downto 0);
296 type array_x12y8 is array(11 downto 0) of std_logic_vector(7 downto 0);
297 type array_x12y5 is array(11 downto 0) of std_logic_vector(4 downto 0);
298 type array_x12y128 is array(11 downto 0) of std_logic_vector(127 downto 0);
299 constant AMC_ID : array12x4 := (x"0",x"1",x"2",x"3",x"4",x"5",x"6",x"7",x"8",x"9",x"a",x"b");
300 constant AMC_txdiffctrl : array12x4 := (others => x"b");
301 constant uFOV : std_logic_vector(3 downto 0) := x"1";
302 signal kAMC : array2x4 := (others => (others => '0'));
303 signal mAMC : array3x4 := (others => (others => '0'));
304 signal nAMC : array3x4 := (others => (others => '0'));
305 signal EventInfo : array_x12y32 := (others => (others => '0'));
306 signal AMCinfo : array12X16 := (others => (others => '0'));
307 signal AMC_DATA : array12X64 := (others => (others => '0'));
308 signal AMC_DATA1 : array12X64 := (others => (others => '0'));
309 signal AMC_DATA2 : array12X64 := (others => (others => '0'));
310 signal Cntr_DATA : array12x16 := (others => (others => '0'));
311 signal AMCCRC_bad : array3X12 := (others => (others => '0'));
312 signal AMC_TTS : array_x12y8 := (others => (others => '0'));
313 signal AMC_debug : array_x12y256 := (others => (others => '0'));
314 signal TTC_status : array_x12y128 := (others => (others => '0'));
315 signal badEventCRC_cntr : array12X16 := (others => (others => '0'));
316 signal ReSyncFakeEvent_cntr : array12X16 := (others => (others => '0'));
317 signal EventInfo_dav : std_logic_vector(11 downto 0);
318 --signal EventInfo_dav_n : std_logic_vector(11 downto 0);
319 signal EventInfoRdDone : std_logic_vector(12 downto 0) := (others => '0');
320 signal AMC_DATA_RdEn : std_logic_vector(11 downto 0) := (others => '0');
321 signal Cntr_ADDR : std_logic_vector(11 downto 0) := (others => '0');
322 signal AMC_if_ADDR : std_logic_vector(7 downto 0) := (others => '0');
323 signal ipb_strobe_q : std_logic := '0';
324 signal UsrClk : std_logic := '0';
325 signal UsrClk_out : std_logic_vector(11 downto 0) := (others => '0');
326 signal resetCntr_SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
327 signal resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
328 signal CntrRst : std_logic := '0';
329 signal CntrRstCycle : std_logic := '0';
330 signal div : std_logic_vector(11 downto 0) := (others => '0');
331 signal inc_div : std_logic_vector(11 downto 0) := (others => '0');
332 signal evn_out : std_logic_vector(59 downto 0) := (others => '0');
333 signal evn_wa : std_logic_vector(8 downto 0) := (others => '0');
334 signal evn_ra : std_logic_vector(8 downto 0) := (others => '0');
335 signal evt_cnt : array3x8 := (others => (others => '0'));
336 signal evn : std_logic_vector(23 downto 0) := (others => '0');
337 signal CDF_in : std_logic_vector(71 downto 0) := (others => '0');
338 signal CDF_out : std_logic_vector(71 downto 0) := (others => '0');
339 signal CDF_wa : std_logic_vector(8 downto 0) := (others => '0');
340 signal CDF_ra : std_logic_vector(8 downto 0) := (others => '0');
341 signal CDF_cnt : std_logic_vector(7 downto 0) := (others => '0');
342 signal empty_event_flag : std_logic := '0';
343 signal evn_buf_full_i : std_logic_vector(2 downto 0) := (others => '0');
344 signal ovfl_warning_i : std_logic_vector(3 downto 0) := (others => '0');
345 signal ovfl_warning_p : std_logic := '0';
346 signal header : std_logic := '0';
347 signal init_bldr : std_logic := '0';
348 signal CDF_header : std_logic := '0';
349 signal CDF_empty : std_logic := '0';
350 signal BlockHeader : std_logic := '0';
351 signal ec_sel_AMC : std_logic := '0';
352 signal sel_AMC : std_logic_vector(3 downto 0) := (others => '0');
353 signal LastBlock : std_logic := '0';
354 signal FirstBlock : std_logic_vector(2 downto 0) := (others => '0');
355 signal sel_CDF : std_logic := '0';
356 signal evn_empty : std_logic := '0';
357 signal sel_evn : std_logic_vector(1 downto 0) := (others => '0');
358 signal L1A_WrEn : std_logic := '0';
359 signal L1A_DATA : std_logic_vector(15 downto 0) := (others => '0');
360 signal EvtTy : std_logic_vector(3 downto 0) := (others => '0');
361 signal CalTy : std_logic_vector(3 downto 0) := (others => '0');
362 signal EventInfo_avl : std_logic := '0';
363 signal rst_init_bldr : std_logic := '0';
364 signal Builder_busy : std_logic_vector(2 downto 0) := (others => '0');
365 signal ec_CDF_ra : std_logic := '0';
366 signal summary : std_logic_vector(63 downto 0) := (others => '0');
367 signal AMC_TTC_status : std_logic_vector(31 downto 0) := (others => '0');
368 signal fake_en: std_logic := '0';
369 signal fake_DATA : std_logic_vector(15 downto 0) := (others => '0');
370 signal fake_header : std_logic := '0';
371 signal fake_CRC : std_logic := '0';
372 signal fake_WrEn : std_logic := '0';
373 signal fake_word_cnt : std_logic_vector(15 downto 0) := (others => '0');
374 signal fake_evt_cnt : std_logic_vector(15 downto 0) := (others => '0');
375 signal empty_evt_cnt : std_logic_vector(15 downto 0) := (others => '0');
376 signal fake_header_cnt: std_logic_vector(15 downto 0) := (others => '0');
377 signal EventBuilt : std_logic_vector(2 downto 0) := (others => '0');
378 signal badEventCRCToggle : std_logic_vector(11 downto 0) := (others => '0');
379 signal ReSyncFakeEventToggle : std_logic_vector(11 downto 0) := (others => '0');
380 signal EventBuiltToggle : std_logic_vector(2 downto 0) := (others => '0');
381 signal badEventCRCToggleSyncRegs : array12x4 := (others => (others => '0'));
382 signal ReSyncFakeEventToggleSyncRegs : array12x4 := (others => (others => '0'));
383 signal EventBuiltToggleSyncRegs : array3x4 := (others => (others => '0'));
384 signal EventBuiltCnt : array3x16 := (others => (others => '0'));
385 signal next_bldr : std_logic_vector(1 downto 0) := (others => '0');
386 signal AMC_wcp : array12x13 := (others => (others => '0'));
387 signal AMC_wc : std_logic_vector(17 downto 0) := (others => '0');
388 signal AMC_wc_we : std_logic_vector(2 downto 0) := (others => '0');
389 signal en_block_wc : std_logic_vector(2 downto 0) := (others => '0');
390 signal block_wc_we : std_logic_vector(2 downto 0) := (others => '0');
391 signal AMC_wc_mask : std_logic_vector(2 downto 0) := (others => '0');
392 signal AMC_header : array3x66 := (others => (others => '0'));
393 signal AMC_header_we : std_logic_vector(2 downto 0) := (others => '0');
394 signal bldr_fifo_full : std_logic_vector(2 downto 0) := (others => '0');
395 type array3X12 is array(0 to 2) of std_logic_vector(11 downto 0);
396 signal AMC_DATA_re : array3X12 := (others => (others => '0'));
397 signal AMC_hasData : std_logic_vector(11 downto 0) := (others =>'0');
398 signal Mbit_word : std_logic_vector(11 downto 0) := (others =>'0');
399 --signal AMC_hasData_l : std_logic_vector(11 downto 0) := (others =>'0');
400 signal AMC_REFCLK : std_logic := '0';
401 signal AMC_TTS_OR : std_logic_vector(7 downto 0) := (others =>'0');
402 signal AMC_qpll_lock : std_logic_vector(2 downto 0) := (others =>'0');
403 signal AMC_rxprbserr : std_logic_vector(11 downto 0) := (others =>'0');
404 signal AMC_rxcommaalignen : std_logic_vector(11 downto 0) := (others =>'0');
405 signal AMC_rxresetdone : std_logic_vector(11 downto 0) := (others =>'0');
406 signal AMC_txfsmresetdone : std_logic_vector(11 downto 0) := (others =>'0');
407 signal AMC_rxfsmresetdone : std_logic_vector(11 downto 0) := (others =>'0');
408 signal AMC_data_valid : std_logic_vector(11 downto 0) := (others =>'0');
409 signal AMC_RXDATA : array12x16 := (others => (others => '0'));
410 signal AMC_TXDATA : array12x16 := (others => (others => '0'));
411 signal AMC_RXNOTINTABLE : array12x2 := (others => (others => '0'));
412 signal AMC_rxchariscomma : array12x2 := (others => (others => '0'));
413 signal AMC_rxcharisk : array12x2 := (others => (others => '0'));
414 signal AMC_txcharisk : array12x2 := (others => (others => '0'));
415 signal AMC_rxprbssel : array12x3 := (others => (others => '0'));
416 signal AMC_txprbssel : array12x3 := (others => (others => '0'));
417 type array3X4 is array(0 to 2) of std_logic_vector(3 downto 0);
418 --signal AMC_rdata : array12x32 := (others => (others => '0'));
419 signal channel : array3X4 := (others => (others => '0'));
420 -- monitor signals
421 signal mon_wc: array3X16 := (others => (others => '0'));
422 signal mon_evt_wcp : std_logic_vector(47 downto 0) := (others => '0');
423 signal zero_wc : std_logic_vector(2 downto 0) := (others => '0');
424 signal more_wc : std_logic_vector(2 downto 0) := (others => '0');
425 signal mon_en: std_logic := '0';
426 signal scale_cntr : std_logic_vector(15 downto 0) := (others => '0');
427 signal ce_scale : std_logic := '0';
428 signal ld_scale : std_logic := '0';
429 --signal MonBufAbort: std_logic := '0';
430 signal rst_mon_wc: std_logic := '0';
431 signal ce_wc_reg_wa: std_logic := '0';
432 signal wc_reg_wa: std_logic_vector(9 downto 0) := (others => '0');
433 --signal start_wc_reg_wa: std_logic_vector(9 downto 0) := (others => '0');
434 signal down_count : std_logic := '0';
435 signal mon_mask: std_logic_vector(19 downto 0) := (others => '0');
436 signal sample_event: std_logic := '0';
437 signal scale : std_logic_vector(31 downto 0) := (others => '0');
438 signal pending : std_logic := '0';
439 signal AMC_Ready_i : std_logic_vector(11 downto 0);
440 signal AMC_OK : std_logic_vector(11 downto 0);
441 signal block_num : std_logic_vector(11 downto 0) := (others => '0');
442 signal resetFIFO : std_logic := '0';
443 signal fifo_rst : std_logic := '0';
444 signal fifo_en : std_logic := '0';
445 signal resetFIFO_AMC : std_logic := '0';
446 signal fifo_rst_AMC : std_logic := '0';
447 signal fifo_en_AMC : std_logic := '0';
448 signal OneSFP : std_logic := '0';
449 signal TwoSFP : std_logic := '0';
450 signal ThreeSFP : std_logic := '0';
451 signal fake_full : std_logic_vector(11 downto 0) := (others => '0');
452 signal LinkFull : std_logic := '0';
453 signal EventInSlink : array3x4 := (others => (others => '0'));
454 signal TTS_FIFO_do : std_logic_vector(5 downto 0) := (others => '0');
455 signal TTS_FIFO_di : std_logic_vector(5 downto 0) := (others => '0');
456 signal TTS_FIFO_wa : std_logic_vector(4 downto 0) := (others => '0');
457 signal TTS_FIFO_ra : std_logic_vector(4 downto 0) := (others => '0');
458 signal TTS_FIFO_waSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
459 signal TTS_FIFO_waSyncRegs2 : std_logic_vector(2 downto 0) := (others => '0');
460 signal TTS_FIFO_waSyncRegs3 : std_logic_vector(2 downto 0) := (others => '0');
461 signal evt_bldr_debug : STD_LOGIC_VECTOR(255 DOWNTO 0);
462 signal stop_mon : std_logic := '0';
463 signal errors : std_logic_vector(7 downto 0) := (others => '0');
464 signal err_TTS : std_logic_vector(7 downto 0) := (others => '0');
465 signal AMC_wc_sum_we : std_logic := '0';
466 signal rst_AMC_wc_sum : std_logic := '0';
467 signal wr_AMC_wc_sum : std_logic := '0';
468 signal sel_AMC_q : std_logic_vector(3 downto 0) := (others => '0');
469 signal AMC_wc_sum_di : std_logic_vector(5 downto 0) := (others => '0');
470 signal AMC_wc_sum_do : std_logic_vector(5 downto 0) := (others => '0');
471 signal AMC_wc_sum_a : std_logic_vector(4 downto 0) := (others => '0');
472 signal enRstAMC_link : std_logic := '0';
473 signal RstAMC_link : std_logic := '0';
474 signal RstAMC_link_dl : std_logic := '0';
475 signal AllEventBuilt_i : std_logic := '0';
476 signal event_number_avl_q : std_logic_vector(2 downto 0) := (others => '0');
477 signal bcnt : std_logic_vector(11 downto 0) := (others => '0');
478 signal event_cnt : std_logic_vector(23 downto 0) := (others => '0');
479 signal event_status : std_logic_vector(19 downto 0) := (others => '0');
480 signal L1A_buf_we : std_logic := '0';
481 signal L1A_buf_do : std_logic_vector(31 downto 0) := (others => '0');
482 signal L1A_buf_di : std_logic_vector(31 downto 0) := (others => '0');
483 signal L1A_buf_wa : std_logic_vector(8 downto 0) := (others => '0');
484 signal RxBufUdfErr : std_logic_vector(11 downto 0) := (others => '0');
485 signal RxBufOvfErr : std_logic_vector(11 downto 0) := (others => '0');
486 signal RxBufOvf : std_logic_vector(11 downto 0) := (others => '0');
487 signal RxBufUdf : std_logic_vector(11 downto 0) := (others => '0');
488 signal RxClkCntr : std_logic_vector(19 downto 0) := (others => '0');
489 signal RxClkCntr19_q : std_logic := '0';
490 signal updateRatio : std_logic := '0';
491 signal RxClkRatio : array12x21 := (others => (others => '0'));
492 signal AMC_if_RdEn : std_logic := '0';
493 signal AMC_if_data : std_logic_vector(15 downto 0) := (others => '0');
494 signal AMC_cntr_data : std_logic_vector(31 downto 0) := (others => '0');
495 component icon2
496  PORT (
497  CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
498  CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
499 
500 end component;
501 component ila128x4096
502  PORT (
503  CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
504  CLK : IN STD_LOGIC;
505  DATA : IN STD_LOGIC_VECTOR(143 DOWNTO 0);
506  TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
507  TRIG1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
508  TRIG2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
509 
510 end component;
511 signal CONTROL0 : STD_LOGIC_VECTOR(35 DOWNTO 0);
512 signal CONTROL1 : STD_LOGIC_VECTOR(35 DOWNTO 0);
513 signal DATA0 : STD_LOGIC_VECTOR(143 DOWNTO 0);
514 signal TRIG0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
515 signal TRIG1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
516 signal TRIG2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
517 signal DATA1 : STD_LOGIC_VECTOR(143 DOWNTO 0);
518 signal TRIG0b : STD_LOGIC_VECTOR(7 DOWNTO 0);
519 signal TRIG1b : STD_LOGIC_VECTOR(7 DOWNTO 0);
520 signal TRIG2b : STD_LOGIC_VECTOR(7 DOWNTO 0);
521 component chipscope1
522  generic (N : integer := 5);
523  Port ( clk : in STD_LOGIC;
524  Din : in STD_LOGIC_VECTOR (303 downto 0));
525 end component;
526 signal CS : STD_LOGIC_VECTOR(303 DOWNTO 0) := (others => '0');
527 begin
528 --i_chipscope : chipscope1 port map(clk => UsrClk, Din => cs);
529 --cs(61 downto 0) <= AMC_debug(3)(61 downto 0);
530 --cs(289) <= AMC_debug(3)(44);
531 --cs(288) <= AMC_debug(3)(40);
532 --i_chipscope : chipscope1 port map(clk => UsrClk, Din => cs);
533 --cs(288) <= AMC_debug(1)(48);
534 --cs(48 downto 0) <= AMC_debug(1)(48 downto 0);
535 --cs(303 downto 296) <= cs(212) & cs(210 downto 204);
536 --cs(295 downto 288) <= cs(147) & cs(145 downto 139);
537 --cs(295 downto 288) <= AMC_debug(0)(80) & AMC_debug(0)(62 downto 56);
538 --cs(288) <= AMC_debug(4)(82);
539 --cs(287) <= sel_CDF;
540 --cs(264 downto 183) <= AMC_debug(4)(81 downto 0);
541 --cs(182 downto 0) <= evt_bldr_debug(182 downto 0);
542 --i_icon : icon2
543 -- port map (
544 -- CONTROL0 => CONTROL0,
545 -- CONTROL1 => CONTROL1);
546 --i_ila : ila128x4096
547 -- port map (
548 -- CONTROL => CONTROL0,
549 -- CLK => UsrClk,
550 -- DATA => DATA0,
551 -- TRIG0 => TRIG0,
552 -- TRIG1 => x"00",
553 -- TRIG2 => x"00");
554 --DATA0(3 downto 0) <= TTC_status(10)(84 downto 81);
555 --DATA0(16 downto 4) <= TTC_status(10)(18 downto 6);
556 --DATA0(44 downto 17) <= TTC_status(10)(118 downto 91);
557 --DATA0(46 downto 45) <= AMC_rxchariscomma(10);
558 --DATA0(48 downto 47) <= AMC_rxcharisk(10);
559 --DATA0(64 downto 49) <= AMC_RXDATA(10);
560 --DATA0(66 downto 65) <= TTC_status(10)(53 downto 52);
561 --DATA0(70 downto 67) <= TTC_status(9)(84 downto 81);
562 --DATA0(83 downto 71) <= TTC_status(9)(18 downto 6);
563 --DATA0(85 downto 84) <= TTC_status(9)(53 downto 52);
564 --DATA0(87 downto 86) <= AMC_rxchariscomma(9);
565 --DATA0(89 downto 88) <= AMC_rxcharisk(9);
566 --DATA0(105 downto 90) <= AMC_RXDATA(9);
567 --DATA0(109 downto 106) <= TTC_status(1)(84 downto 81);
568 --DATA0(122 downto 110) <= TTC_status(1)(18 downto 6);
569 --DATA0(124 downto 123) <= TTC_status(1)(53 downto 52);
570 --DATA0(125) <= AMC_rxchariscomma(1)(0);
571 --DATA0(127 downto 126) <= AMC_rxcharisk(1);
572 --DATA0(143 downto 128) <= AMC_RXDATA(1);
573 --TRIG0(1 downto 0) <= TTC_status(10)(53 downto 52) ;
574 --TRIG0(3 downto 2) <= TTC_status(9)(53 downto 52) ;
575 --TRIG0(5 downto 4) <= TTC_status(1)(53 downto 52) ;
576 --TRIG0(7 downto 6) <= "00" ;
577 --i_ila_b : ila128x4096
578 -- port map (
579 -- CONTROL => CONTROL1,
580 -- CLK => TTC_clk,
581 -- DATA => DATA1,
582 -- TRIG0 => TRIG1,
583 -- TRIG1 => x"00",
584 -- TRIG2 => x"00");
585 --DATA1(0) <= BC0;
586 --DATA1(9 downto 1) <= TTC_status(10)(35 downto 27);
587 --DATA1(46 downto 10) <= TTC_status(10)(90 downto 54);
588 --DATA1(55 downto 47) <= TTC_status(9)(35 downto 27);
589 --DATA1(92 downto 56) <= TTC_status(9)(90 downto 54);
590 --DATA1(101 downto 93) <= TTC_status(1)(35 downto 27);
591 --DATA1(138 downto 102) <= TTC_status(1)(90 downto 54);
592 --DATA1(142 downto 139) <= bcnt;
593 --TRIG1(0) <= BC0;
594 --TRIG1(2 downto 1) <= TTC_status(10)(31 downto 30);
595 --TRIG1(4 downto 3) <= TTC_status(9)(31 downto 30);
596 --TRIG1(6 downto 5) <= TTC_status(1)(31 downto 30);
597 --TRIG1(7) <= '0';
598 AllEventBuilt <= AllEventBuilt_i;
599 AMC_Ready <= AMC_Ready_i;
600 mon_ctrl <= scale;
601 process(sysclk,reset)
602 begin
603  if(reset = '1')then
604  resetSyncRegs <= (others => '1');
605  RstAMC_link <= '1';
606  elsif(sysclk'event and sysclk = '1')then
607  resetSyncRegs <= resetSyncRegs(1 downto 0) & '0';
608  if(enRstAMC_link = '1' and AllEventBuilt_i = '1')then
609  RstAMC_link <= '1';
610  else
611  RstAMC_link <= resetSyncRegs(1);
612  end if;
613  end if;
614 end process;
615 process(sysclk)
616 begin
617  if(sysclk'event and sysclk = '1')then
618  if(resetSyncRegs(2) = '1')then
619  L1A_buf_wa <= (others => '0');
620  elsif(L1A_buf_we = '1')then
621  L1A_buf_wa <= L1A_buf_wa + 1;
622  end if;
623  if(resetSyncRegs(2) = '1' or ttc_evcnt_reset = '1')then
624  event_cnt <= (others => '0');
625  elsif(event_number_avl = '1')then
626  event_cnt <= event_cnt + 1;
627  end if;
628  event_number_avl_q <= event_number_avl_q(1 downto 0) & event_number_avl;
629  if(resetSyncRegs(2) = '1')then
630  L1A_buf_we <= '0';
631  else
632  L1A_buf_we <= event_number_avl or or_reduce(event_number_avl_q);
633  end if;
634  if(event_number_avl = '1')then
635  L1A_buf_di <= event_number(43 downto 12); -- OcN
636  bcnt <= event_number(11 downto 0); -- OcN
637  event_status <= event_number(59 downto 44) &"00" & event_number(45) & not event_number(45);
638  elsif(event_number_avl_q(0) = '1')then
639  L1A_buf_di <= x"00000" & bcnt; -- bcnt
640  elsif(event_number_avl_q(1) = '1')then
641  L1A_buf_di <= x"00" & event_cnt; -- bcnt
642  else
643  L1A_buf_di <= x"000" & event_status; -- bcnt
644  end if;
645  end if;
646 end process;
647 -- if(en_cal_win = '0')then
648 -- event_number(51 downto 48) <= x"0";
649 -- event_number(44) <= '0';
650 -- else
651 -- event_number(51) <= cal_win and brcst_GapTrig and cal_type(3) and not brcst_GapPed;
652 -- event_number(50) <= cal_win and brcst_GapTrig and cal_type(2) and not brcst_GapPed;
653 -- event_number(49) <= cal_win and brcst_GapTrig and cal_type(1) and not brcst_GapPed;
654 -- event_number(48) <= cal_win and ((brcst_GapTrig and cal_type(0)) or brcst_GapPed);
655 -- event_number(44) <= cal_win and (brcst_GapTrig or brcst_GapPed);
656 -- end if;
657 -- event_number(59 downto 56) <= cal_type;
658 -- event_number(55 downto 52) <= state;
659 -- event_number(47) <= brcst_GapTrig;
660 -- event_number(46) <= brcst_GapPed;
661 -- event_number(45) <= cal_win;
662 -- event_number(43 downto 0) <= oc & bcnt;
663 -- receiving L1 information
664 i_L1A_buf : BRAM_SDP_MACRO
665  generic map (
666  BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
667  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
668  WRITE_WIDTH => 32, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
669  READ_WIDTH => 32) -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
670  port map (
671  DO => L1A_buf_do, -- Output read data port, width defined by READ_WIDTH parameter
672  DI => L1A_buf_di, -- Input write data port, width defined by WRITE_WIDTH parameter
673  RDADDR => ipb_addr(8 downto 0), -- Input read address, width defined by read port depth
674  RDCLK => sysclk, -- 1-bit input read clock
675  RDEN => '1', -- 1-bit input read port enable
676  REGCE => '1', -- 1-bit input read output register enable
677  RST => '0', -- 1-bit input reset
678  WE => x"f", -- Input write enable, width defined by write port depth
679  WRADDR => L1A_buf_wa, -- Input write address, width defined by write port depth
680  WRCLK => sysclk, -- 1-bit input write clock
681  WREN => L1A_buf_we -- 1-bit input write port enable
682  );
683 ovfl_warning <= ovfl_warning_i(3);
684 i_evn : BRAM_SDP_MACRO
685  generic map (
686  BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
687  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
688  WRITE_WIDTH => 60, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
689  READ_WIDTH => 60, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
690  DO_REG => 0, -- Optional output register (0 or 1)
691  SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY",
692  -- "GENERATE_X_ONLY" or "NONE"
693  WRITE_MODE => "WRITE_FIRST", -- Specify "READ_FIRST" for same clock or synchronous clocks
694  -- Specify "WRITE_FIRST for asynchrononous clocks on ports
695  INIT => X"000000000000000000") -- Initial values on output port
696  port map (
697  DO => evn_out, -- Output read data port, width defined by READ_WIDTH parameter
698  DI => event_number, -- Input write data port, width defined by WRITE_WIDTH parameter
699  RDADDR => evn_ra, -- Input read address, width defined by read port depth
700  RDCLK => sysclk, -- 1-bit input read clock
701  RDEN => '1', -- 1-bit input read port enable
702  REGCE => '1', -- 1-bit input read output register enable
703  RST => '0', -- 1-bit input reset
704  WE => x"ff", -- Input write enable, width defined by write port depth
705  WRADDR => evn_wa, -- Input write address, width defined by write port depth
706  WRCLK => sysclk, -- 1-bit input write clock
707  WREN => event_number_avl -- 1-bit input write port enable
708  );
709 process(sysclk)
710 variable enable : std_logic_vector(2 downto 0);
711 begin
712  if(ThreeSFP = '1')then
713  enable := "111";
714  elsif(TwoSFP = '1')then
715  enable := "011";
716  else
717  enable := "001";
718  end if;
719  if(sysclk'event and sysclk = '1')then
720  if(resetSyncRegs(2) = '1')then
721  evn_wa <= (others => '0');
722  elsif(event_number_avl = '1')then
723  evn_wa <= evn_wa + 1;
724  end if;
725  if(resetSyncRegs(2) = '1')then
726  evn_ra <= (others => '0');
727  elsif(sel_evn = "10")then
728  evn_ra <= evn_ra + 1;
729  end if;
730  if(ttc_evcnt_reset = '1' or resetSyncRegs(2) = '1')then
731  evn <= x"000001";
732  elsif(sel_evn = "10")then
733  evn <= evn + 1;
734  end if;
735  for i in 0 to 2 loop
736  if(resetSyncRegs(2) = '1' or enable(i) = '0')then
737  evt_cnt(i) <= (others => '0');
738  elsif(event_number_avl = '1' and EventBuilt(i) = '0')then
739  evt_cnt(i) <= evt_cnt(i) + 1;
740  elsif(event_number_avl = '0' and EventBuilt(i) = '1')then
741  evt_cnt(i) <= evt_cnt(i) - 1;
742  end if;
743  if(and_reduce(evt_cnt(i)(7 downto 5)) = '1')then
744  evn_buf_full_i(i) <= '1';
745  else
746  evn_buf_full_i(i) <= '0';
747  end if;
748  -- when reached 0x60, throttle L1A. Return only after go below 0x40
749  if(or_reduce(evt_cnt(i)(7 downto 6)) = '0')then
750  ovfl_warning_i(i) <= '0';
751  elsif(evt_cnt(i)(5) = '1')then
752  ovfl_warning_i(i) <= '1';
753  end if;
754  end loop;
755  evn_buf_full <= or_reduce(evn_buf_full_i);
756  ovfl_warning_i(3) <= or_reduce(ovfl_warning_i(2 downto 0)) or (or_reduce(TTS_FIFO_do(4 downto 0)) and en_localL1A);
757  end if;
758 end process;
759 -- send L1info to AMC_Link
760 process(sysclk)
761 begin
762  if(sysclk'event and sysclk = '1')then
763  if(resetSyncRegs(2) = '1' or evn_wa = evn_ra)then
764  evn_empty <= '1';
765  else
766  evn_empty <= '0';
767  end if;
768  L1A_WrEn <= not evn_empty;
769  if(resetSyncRegs(2) = '1' or evn_empty = '1')then
770  sel_evn <= "00";
771  else
772  sel_evn(1) <= sel_evn(1) xor sel_evn(0);
773  sel_evn(0) <= not sel_evn(0);
774  end if;
775  case sel_evn is
776  when "00" => L1A_DATA <= evn_out(11 downto 0) & x"0"; -- BX
777  when "01" => L1A_DATA <= evn(15 downto 0);
778  when "10" => L1A_DATA <= x"00" & evn(23 downto 16);
779  when others => L1A_DATA <= evn_out(27 downto 12); -- OrN
780  end case;
781  end if;
782 end process;
783 i_CDF : BRAM_SDP_MACRO
784  generic map (
785  BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
786  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
787  WRITE_WIDTH => 72, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
788  READ_WIDTH => 72, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
789  DO_REG => 0, -- Optional output register (0 or 1)
790  SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY",
791  -- "GENERATE_X_ONLY" or "NONE"
792  WRITE_MODE => "WRITE_FIRST", -- Specify "READ_FIRST" for same clock or synchronous clocks
793  -- Specify "WRITE_FIRST for asynchrononous clocks on ports
794  INIT => X"000000000000000000") -- Initial values on output port
795  port map (
796  DO => CDF_out, -- Output read data port, width defined by READ_WIDTH parameter
797  DI => CDF_in, -- Input write data port, width defined by WRITE_WIDTH parameter
798  RDADDR => CDF_ra, -- Input read address, width defined by read port depth
799  RDCLK => sysclk, -- 1-bit input read clock
800  RDEN => '1', -- 1-bit input read port enable
801  REGCE => '1', -- 1-bit input read output register enable
802  RST => '0', -- 1-bit input reset
803  WE => x"ff", -- Input write enable, width defined by write port depth
804  WRADDR => CDF_wa, -- Input write address, width defined by write port depth
805  WRCLK => sysclk, -- 1-bit input write clock
806  WREN => sel_evn(0) -- 1-bit input write port enable
807  );
808 process(sysclk)
809 begin
810  if(sysclk'event and sysclk = '1')then
811  if(resetSyncRegs(2) = '1')then
812  CDF_wa <= (others => '0');
813  elsif(sel_evn(0) = '1')then
814  CDF_wa <= CDF_wa + 1;
815  end if;
816  if(resetSyncRegs(2) = '1')then
817  CDF_ra <= (others => '0');
818  elsif(ec_CDF_ra = '1')then
819  CDF_ra <= CDF_ra + 1;
820  end if;
821  if(resetSyncRegs(2) = '1')then
822  CDF_cnt <= (others => '0');
823  elsif(sel_evn(0) = '1' and CDF_wa(0) = '1' and (ec_CDF_ra = '0' or CDF_ra(0) = '1'))then
824  CDF_cnt <= CDF_cnt + 1;
825  elsif((sel_evn(0) = '0' or CDF_wa(0) = '0') and ec_CDF_ra = '1' and CDF_ra(0) = '0')then
826  CDF_cnt <= CDF_cnt - 1;
827  end if;
828  if(resetSyncRegs(2) = '1')then
829  CDF_empty <= '1';
830  elsif(or_reduce(CDF_cnt(7 downto 1)) = '0' and (CDF_cnt(0) = '0' or ec_CDF_ra = '1'))then
831  CDF_empty <= '1';
832  elsif(or_reduce(CDF_cnt) = '1')then
833  CDF_empty <= '0';
834  end if;
835  if(sel_evn(1) = '0')then
836 -- CDF_in <= x"005" & EvtTy & evn & evn_out(11 downto 0) & Source_ID(11 downto 0) & x"08"; -- header1
837  CDF_in <= x"005" & EvtTy & evn & evn_out(11 downto 0) & x"00008"; -- header1
838  else
839  CDF_in <= x"00" & uFOV & CalTy & x"00000" & evn_out(43 downto 12) & x"0"; -- header2
840  end if;
841  end if;
842 end process;
843 EvtTy <= "00" & evn_out(45) & not evn_out(45);
844 CalTy <= evn_out(51 downto 48);
845 process(sysclk, ThreeSFP, TwoSFP, sel_AMC)
846 variable bldr_mask_sel : std_logic_vector(4 downto 0);
847 variable bldr_mask : std_logic_vector(2 downto 0);
848 --variable Mbit_word : std_logic_vector(11 downto 0);
849 begin
850  bldr_mask_sel(4) := ThreeSFP;
851  bldr_mask_sel(3) := TwoSFP;
852  bldr_mask_sel(2 downto 0) := sel_AMC(3 downto 1);
853  case bldr_mask_sel is
854  when "10100" | "10101" => bldr_mask := "100";
855  when "10000" | "10001" | "01000" | "01001" | "01010" => bldr_mask := "010";
856  when others => bldr_mask := "001";
857  end case;
858 -- for i in 0 to 11 loop
859 -- Mbit_word(i) := EventInfo(i)(25);
860 -- end loop;
861  if(sysclk'event and sysclk = '1')then
862  if(resetSyncRegs(2) = '1')then
863  CDF_header <= '1';
864  header <= '0';
865  init_bldr <= '0';
866  EventInfo_avl <= '0';
867  ec_sel_AMC <= '0';
868  AMC_wc_we <= "000";
869  AMC_wc_sum_we <= '0';
870  BlockHeader <= '0';
871  ec_CDF_ra <= '0';
872  AMC_header_we <= "000";
873  sel_CDF <= '0';
874  buf_rqst <= x"0";
875  sel_AMC <= x"0";
876  else
877  if((and_reduce(not AMC_hasData or EventInfo_dav) = '1' and or_reduce(AMC_hasData) = '1') or (or_reduce(amc_en) = '0' and CDF_empty = '0'))then
878  EventInfo_avl <= '1';
879  else
880  EventInfo_avl <= '0';
881  end if;
882 -- LastBlock <= not or_reduce(AMC_hasData and Mbit_word);
883  LastBlock <= '1';
884  for i in 0 to 11 loop
885  if(AMC_hasData(i) = '1' and EventInfo(i)(25) = '1')then
886  LastBlock <= '0';
887  end if;
888  end loop;
889  if(EventInfo_avl = '1' and init_bldr = '0' and bldr_fifo_full = "000" and ((mon_en = '0' and TCPbuf_avl = '1') or (mon_en = '1' and mon_buf_avl = '1')))then
890  if(CDF_header = '1')then
891  ec_CDF_ra <= '1';
892  zero_wc <= not ThreeSFP & OneSFP & '0';
893  else
894  BlockHeader <= '1';
895  end if;
896  header <= '1';
897  init_bldr <= '1';
898  buf_rqst <= LastBlock & CDF_header & not mon_en & mon_en;
899  AMC_header(0)(64) <= mon_en and mon_buf_avl;
900  AMC_header(1)(64) <= mon_en and mon_buf_avl;
901  AMC_header(2)(64) <= mon_en and mon_buf_avl;
902  more_wc <= "000";
903  for i in 0 to 11 loop
904  Mbit_word(i) <= AMC_hasData(i) and EventInfo(i)(25);
905  end loop;
906  elsif(rst_init_bldr = '1')then
907  init_bldr <= '0';
908 -- zero_wc <= zero_wc or not more_wc;
909  zero_wc <= not more_wc;
910  if(LastBlock = '1')then
911  ec_CDF_ra <= '1';
912  CDF_header <= '1';
913  end if;
914  else
915  header <= '0';
916  ec_CDF_ra <= '0';
917  buf_rqst <= x"0";
918  if(init_bldr = '1')then
919  CDF_header <= '0';
920  BlockHeader <= CDF_header;
921  end if;
922  if(ec_sel_AMC = '1' and Mbit_word(conv_integer(sel_AMC)) = '1')then
923  more_wc <= more_wc or bldr_mask;
924  end if;
925  end if;
926  sel_CDF <= (CDF_header and init_bldr) or BlockHeader;
927 -- if(BlockHeader = '1')then
928 -- AMC_hasData_l <= AMC_hasData;
929 -- end if;
930  if(BlockHeader = '1')then
931  ec_sel_AMC <= '1';
932  elsif(sel_AMC = x"b")then
933  ec_sel_AMC <= '0';
934  end if;
935  if(AMC_hasData(conv_integer(sel_AMC)) = '1' and ec_sel_AMC = '1')then
936  AMC_wc_we <= bldr_mask;
937  AMC_wc_sum_we <= or_reduce(bldr_mask);
938  else
939  AMC_wc_we <= "000";
940  AMC_wc_sum_we <= '0';
941  end if;
942  for i in 0 to 2 loop
943  if((sel_CDF = '1' and (FirstBlock(i) = '1' or nAMC(i) /= x"0")) or AMC_wc_we(i) = '1')then
944  AMC_header_we(i) <= '1';
945  else
946  AMC_header_we(i) <= '0';
947  end if;
948  end loop;
949  if(ec_sel_AMC = '0' or sel_AMC = x"b")then
950  sel_AMC <= x"0";
951  else
952  sel_AMC <= sel_AMC + 1;
953  end if;
954  end if;
955  for i in 0 to 2 loop
956  case AMC_hasData(i*4+3 downto i*4) is
957  when x"1" | x"2" | x"4" | x"8" => mAMC(i) <= x"1";
958  when x"3" | x"5" | x"6" | x"9" | x"a" | x"c" => mAMC(i) <= x"2";
959  when x"7" | x"b" | x"d" | x"e" => mAMC(i) <= x"3";
960  when x"f" => mAMC(i) <= x"4";
961  when others => mAMC(i) <= x"0";
962  end case;
963  end loop;
964  kAMC(0)(1) <= AMC_hasData(5) and AMC_hasData(4);
965  kAMC(0)(0) <= AMC_hasData(5) xor AMC_hasData(4);
966  kAMC(1)(1) <= AMC_hasData(7) and AMC_hasData(6);
967  kAMC(1)(0) <= AMC_hasData(7) xor AMC_hasData(6);
968  if(ThreeSFP = '1')then
969  nAMC(0) <= mAMC(1);
970  elsif(TwoSFP = '1')then
971  nAMC(0) <= mAMC(2) + kAMC(1);
972  else
973  nAMC(0) <= mAMC(0) + mAMC(1) + mAMC(2);
974  end if;
975  if(ThreeSFP = '1')then
976  nAMC(1) <= mAMC(0);
977  elsif(TwoSFP = '1')then
978  nAMC(1) <= mAMC(0) + kAMC(0);
979  else
980  nAMC(1) <= x"0";
981  end if;
982  if(ThreeSFP = '1')then
983  nAMC(2) <= mAMC(2);
984  else
985  nAMC(2) <= x"0";
986  end if;
987  summary <= '0' & EventInfo(conv_integer(sel_AMC))(26 downto 20) & x"0" & EventInfo(conv_integer(sel_AMC))(19 downto 0) & block_num & (sel_AMC+1) & AMCinfo(conv_integer(sel_AMC));
988  for i in 0 to 2 loop
989  AMC_header(i)(65) <= not BlockHeader and sel_CDF;
990  if(sel_CDF = '0')then
991  AMC_header(i)(55 downto 52) <= summary(55 downto 52);
992  elsif(BlockHeader = '1')then
993  AMC_header(i)(55 downto 52) <= CDF_out(55 downto 52);
994  else
995  AMC_header(i)(55 downto 52) <= nAMC(i);
996  end if;
997  if(sel_CDF = '1')then
998  AMC_header(i)(63 downto 56) <= CDF_out(63 downto 56);
999  AMC_header(i)(51 downto 20) <= CDF_out(51 downto 20);
1000  AMC_header(i)(7 downto 0) <= CDF_out(7 downto 0);
1001  else
1002  AMC_header(i)(63 downto 56) <= summary(63 downto 56);
1003  AMC_header(i)(51 downto 20) <= summary(51 downto 20);
1004  AMC_header(i)(7 downto 0) <= summary(7 downto 0);
1005  end if;
1006  end loop;
1007  if(sel_CDF = '0')then
1008  AMC_header(0)(19 downto 8) <= summary(19 downto 8);
1009  AMC_header(1)(19 downto 8) <= summary(19 downto 8);
1010  AMC_header(2)(19 downto 8) <= summary(19 downto 8);
1011  elsif(BlockHeader = '1')then
1012  if(OneSFP = '1')then
1013  AMC_header(0)(19 downto 8) <= source_ID(0);
1014  else
1015  AMC_header(0)(19 downto 8) <= source_ID(1);
1016  end if;
1017  AMC_header(1)(19 downto 8) <= source_ID(0);
1018  AMC_header(2)(19 downto 8) <= source_ID(2);
1019  else
1020  AMC_header(0)(19 downto 8) <= CDF_out(19 downto 8);
1021  AMC_header(1)(19 downto 8) <= CDF_out(19 downto 8);
1022  AMC_header(2)(19 downto 8) <= CDF_out(19 downto 8);
1023  end if;
1024  if(CDF_header = '1')then
1025  FirstBlock(0) <= '1';
1026  FirstBlock(1) <= not OneSFP;
1027  FirstBlock(2) <= ThreeSFP;
1028  block_num <= (others => '0');
1029  elsif(rst_init_bldr = '1')then
1030  FirstBlock <= "000";
1031  block_num <= block_num + 1;
1032  end if;
1033  if(fifo_en = '0' or (EventInfoRdDone(12) = '1' and LastBlock = '1'))then
1034  AMC_hasData <= AMC_en;
1035 -- elsif(ec_sel_AMC = '1' and EventInfo(conv_integer(sel_AMC))(25) = '0')then -- More bit is '0'
1036 -- AMC_hasData(conv_integer(sel_AMC)) <= '0';
1037  elsif(EventInfoRdDone(12) = '1')then
1038  AMC_hasData <= Mbit_word;
1039  end if;
1040  for i in 0 to 11 loop
1041  if(Mbit_word(i) = '1')then
1042  AMC_wcp(i) <= "1000000000000";
1043  else
1044  AMC_wcp(i) <= EventInfo(i)(12 downto 0);
1045  end if;
1046  end loop;
1047  if(OneSFP = '1')then
1048 -- AMC_wc(17) <= not or_reduce(AMC_hasData and Mbit_word);
1049  AMC_wc(17) <= not or_reduce(Mbit_word);
1050  elsif(TwoSFP = '1')then
1051  if(sel_AMC = x"0")then
1052  AMC_wc(17) <= not or_reduce(Mbit_word(5 downto 0));
1053  elsif(sel_AMC = x"6")then
1054  AMC_wc(17) <= not or_reduce(Mbit_word(11 downto 6));
1055  end if;
1056  else
1057  if(sel_AMC = x"0")then
1058  AMC_wc(17) <= not or_reduce(Mbit_word(3 downto 0));
1059  elsif(sel_AMC = x"4")then
1060  AMC_wc(17) <= not or_reduce(Mbit_word(7 downto 4));
1061  elsif(sel_AMC = x"8")then
1062  AMC_wc(17) <= not or_reduce(Mbit_word(11 downto 8));
1063  end if;
1064  end if;
1065  AMC_wc(16 downto 0) <= sel_AMC & AMC_wcp(conv_integer(sel_AMC));
1066  end if;
1067 end process;
1068 kAMC(1)(3 downto 2) <= "00";
1069 kAMC(0)(3 downto 2) <= "00";
1070 --AMC_header(1)(64 downto 56) <= AMC_header(0)(64 downto 56);
1071 --AMC_header(1)(51 downto 0) <= AMC_header(0)(51 downto 0);
1072 --AMC_header(2)(64 downto 56) <= AMC_header(0)(64 downto 56);
1073 --AMC_header(2)(51 downto 0) <= AMC_header(0)(51 downto 0);
1074 i_evt_bldr0: evt_bldr PORT MAP(
1075  clk => sysclk ,
1076  reset => resetSyncRegs(2),
1077  fifo_rst => fifo_rst,
1078  fifo_en => fifo_en,
1079  en_inject_err => en_inject_err ,
1080  OneSFP => OneSFP,
1081  Source_ID => x"00",
1082  block_wc => mon_wc(0),
1083  block_wc_we => block_wc_we (0),
1084  AMC_wc => AMC_wc,
1085  AMC_wc_we => AMC_wc_we(0),
1086  AMC_wc_end => rst_init_bldr,
1087  bldr_fifo_full => bldr_fifo_full (0),
1088  AMC_header => AMC_header(0),
1089  AMC_header_we => AMC_header_we (0),
1090  AMC_DATA => AMC_DATA,
1091  AMC_DATA_re => AMC_DATA_re (0),
1092  AMCCRC_bad => AMCCRC_bad(0),
1093  evt_data => evt_data(0),
1094  evt_data_we => evt_data_we (0),
1095  evt_buf_full => evt_buf_full (0),
1096  evt_data_re => evt_data_re (0),
1097  evt_data_rdy => evt_data_rdy (0),
1098  debug => evt_bldr_debug,
1099  EventBuilt => EventBuilt(0)
1100  );
1101 i_evt_bldr1: evt_bldr PORT MAP(
1102  clk => sysclk ,
1103  reset => resetSyncRegs(2),
1104  fifo_rst => fifo_rst,
1105  fifo_en => fifo_en,
1106  en_inject_err => en_inject_err ,
1107  OneSFP => OneSFP,
1108  Source_ID => x"00",
1109  block_wc => mon_wc(1),
1110  block_wc_we => block_wc_we (1),
1111  AMC_wc => AMC_wc,
1112  AMC_wc_we => AMC_wc_we(1),
1113  AMC_wc_end => rst_init_bldr,
1114  bldr_fifo_full => bldr_fifo_full (1),
1115  AMC_header => AMC_header(1),
1116  AMC_header_we => AMC_header_we (1),
1117  AMC_DATA => AMC_DATA1,
1118  AMC_DATA_re => AMC_DATA_re (1),
1119  AMCCRC_bad => AMCCRC_bad(1),
1120  evt_data => evt_data(1),
1121  evt_data_we => evt_data_we (1),
1122  evt_buf_full => evt_buf_full (1),
1123  evt_data_re => evt_data_re (1),
1124  evt_data_rdy => evt_data_rdy (1),
1125  debug => open,
1126  EventBuilt => EventBuilt(1)
1127  );
1128 g_AMC_DATA1: for i in 0 to 5 generate
1129  AMC_DATA1(i) <= AMC_DATA(i);
1130  AMC_DATA1(i+6) <= (others => '0');
1131 end generate;
1132 i_evt_bldr2: evt_bldr PORT MAP(
1133  clk => sysclk ,
1134  reset => resetSyncRegs(2),
1135  fifo_rst => fifo_rst,
1136  fifo_en => fifo_en,
1137  en_inject_err => en_inject_err ,
1138  OneSFP => OneSFP,
1139  Source_ID => x"00",
1140  block_wc => mon_wc(2),
1141  block_wc_we => block_wc_we (2),
1142  AMC_wc => AMC_wc,
1143  AMC_wc_we => AMC_wc_we(2),
1144  AMC_wc_end => rst_init_bldr,
1145  bldr_fifo_full => bldr_fifo_full (2),
1146  AMC_header => AMC_header(2),
1147  AMC_header_we => AMC_header_we (2),
1148  AMC_DATA => AMC_DATA2,
1149  AMC_DATA_re => AMC_DATA_re (2),
1150  AMCCRC_bad => AMCCRC_bad(2),
1151  evt_data => evt_data(2),
1152  evt_data_we => evt_data_we (2),
1153  evt_buf_full => evt_buf_full (2),
1154  evt_data_re => evt_data_re (2),
1155  evt_data_rdy => evt_data_rdy (2),
1156  debug => open,
1157  EventBuilt => EventBuilt(2)
1158  );
1159 g_AMC_DATA2: for i in 0 to 3 generate
1160  AMC_DATA2(i) <= AMC_DATA(i+8);
1161  AMC_DATA2(i+4) <= AMC_DATA(i+8);
1162  AMC_DATA2(i+8) <= AMC_DATA(i+8);
1163 end generate;
1164 AMC_DATA_RdEn <= AMC_DATA_re(0) or AMC_DATA_re(1) or AMC_DATA_re(2);
1165 process(sysclk)
1166 begin
1167  if(sysclk'event and sysclk = '1')then
1168  for i in 0 to 11 loop
1169  if(AMCCRC_bad(0)(i) = '1' or AMCCRC_bad(1)(i) = '1' or AMCCRC_bad(2)(i) = '1')then
1170  badEventCRCToggle(i) <= not badEventCRCToggle(i);
1171  end if;
1172  if(EventInfo(i)(31) = '1' and EventInfo(i)(25) = '0' and EventInfoRdDone(i) = '1')then
1173  ReSyncFakeEventToggle(i) <= not ReSyncFakeEventToggle(i);
1174  end if;
1175  end loop;
1176  end if;
1177 end process;
1178 i_FIFO_RESET_AMC: FIFO_RESET_7S PORT MAP(
1179  reset => resetFIFO_AMC,
1180  clk => sysclk ,
1181  fifo_rst => fifo_rst_AMC,
1182  fifo_en => fifo_en_AMC
1183  );
1184 resetFIFO_AMC <= reset or or_reduce(not AMC_txfsmresetdone and AMC_en) or RstAMC_link;
1185 g_AMC_Link : for i in 0 to 11 generate
1186  i_AMC_Link: AMC_Link
1187  generic map(useTRIG => AMC_useTRIG)
1188  PORT MAP(
1189  sysclk => sysclk,
1190  reset => RstAMC_link,
1191  resetCntr => CntrRst,
1192  fifo_rst => fifo_rst_AMC,
1193  fifo_en => fifo_en_AMC,
1194  test => test,
1195  NoReSyncFake => NoReSyncFake ,
1196  UsrClk => UsrClk,
1197  RXNOTINTABLE => AMC_RXNOTINTABLE (i),
1198  rxcommaalignen => AMC_rxcommaalignen (i),
1199  rxchariscomma => AMC_rxchariscomma (i),
1200  rxcharisk => AMC_rxcharisk (i),
1201  rxresetdone => AMC_rxresetdone (i),
1202  qpll_lock => AMC_qpll_lock(i/4),
1203  txfsmresetdone => AMC_txfsmresetdone (i),
1204  data_valid => AMC_data_valid(i),
1205  RXDATA => AMC_RXDATA(i),
1206  txcharisk => AMC_txcharisk(i),
1207  TXDATA => AMC_TXDATA(i),
1208  Ready => AMC_Ready_i(i),
1209  AMC_ID => AMC_ID(i),
1210  AMCinfo => AMCinfo(i),
1211  EventInfo => EventInfo(i),
1212  EventInfo_dav => EventInfo_dav (i),
1213  AMC_DATA_RdEn => AMC_DATA_RdEn (i),
1214  EventInfoRdDone => EventInfoRdDone (i),
1215  AMC_DATA => AMC_DATA(i),
1216  bad_AMC => AMC_status(i),
1217  AMC_OK => AMC_OK(i),
1218  L1A_DATA => L1A_DATA,
1219  L1A_WrEn => L1A_WrEn,
1220  fake_header => fake_header,
1221  fake_CRC => fake_CRC,
1222  fake_DATA => fake_DATA,
1223  fake_WrEn => fake_WrEn,
1224  fake_full => fake_full(i),
1225  Cntr_ADDR => Cntr_ADDR,
1226  Cntr_DATA => Cntr_DATA(i),
1227  debug_out => AMC_debug(i),
1228  TTCclk => TTC_clk,
1229  BC0 => BC0,
1230  TTC_LOS => TTC_LOS,
1231  AMC_en => AMC_en(i),
1232  TTS_disable => TTS_disable (i),
1233  TTC_status => TTC_status(i),
1234  TrigData => TrigData(i),
1235  TTS_coded => AMC_TTS(i)(4 downto 0)
1236  );
1237 end generate;
1238 i_AMC_wrapper: AMC_wrapper PORT MAP(
1239  DRPclk => DRPclk,
1240  SOFT_RESET => GTXreset,
1241  UsrClk => UsrClk,
1242  test => test,
1243  Dis_pd => Dis_pd,
1244  AMC_en => AMC_en,
1245  RXDATA => AMC_RXDATA,
1246  RxBufOvf => RxBufOvf,
1247  RxBufUdf => RxBufUdf,
1248  sampleRatio => RxClkCntr19_q ,
1249  updateRatio => updateRatio ,
1250  RxClkRatio => RxClkRatio,
1251  rxprbserr => AMC_rxprbserr,
1252  rxprbssel => AMC_rxprbssel,
1253  RXNOTINTABLE => AMC_RXNOTINTABLE ,
1254  rxcommaalignen => AMC_rxcommaalignen ,
1255  rxchariscomma => AMC_rxchariscomma ,
1256  rxcharisk => AMC_rxcharisk ,
1257  rxresetdone => AMC_rxresetdone ,
1258  txdiffctrl => AMC_txdiffctrl,
1259  TXDATA => AMC_TXDATA,
1260  txoutclk => UsrClk_out,
1261  txcharisk => AMC_txcharisk,
1262  txresetdone => open,
1263  txprbssel => AMC_txprbssel,
1264  qpll_lock => AMC_qpll_lock,
1265  txfsmresetdone => AMC_txfsmresetdone ,
1266  rxfsmresetdone => AMC_rxfsmresetdone ,
1267  data_valid => AMC_data_valid,
1268  AMC_REFCLK => AMC_REFCLK,
1269  RXN => AMC_RXN ,
1270  RXP => AMC_RXP ,
1271  TXN => AMC_TXN ,
1272  TXP => AMC_TXP
1273  );
1274 process(sysclk)
1275 begin
1276  if(sysclk'event and sysclk = '1')then
1277  ovfl_warning_p <= ovfl_warning_i(3) and not en_localL1A;
1278  if(resetSyncRegs(2) = '1')then
1279  AllEventBuilt_i <= '1';
1280  else
1281  for i in 0 to 2 loop
1282  if(EventBuilt(i) = '1')then
1283  EventBuiltToggle(i) <= not EventBuiltToggle(i);
1284  end if;
1285  end loop;
1286  if(evt_cnt(0) = x"00" and evt_cnt(1) = x"00" and evt_cnt(2) = x"00")then
1287  AllEventBuilt_i <= '1';
1288  else
1289  AllEventBuilt_i <= '0';
1290  end if;
1291  end if;
1292  if(RstAMC_link_dl = '1')then
1293  enRstAMC_link <= '0';
1294  elsif(ReSync = '1')then
1295  enRstAMC_link <= '1';
1296  end if;
1297  end if;
1298 end process;
1299 i_RstAMC_link_dl : SRL16E
1300  port map (
1301  Q => RstAMC_link_dl, -- SRL data output
1302  A0 => '1', -- Select[0] input
1303  A1 => '1', -- Select[1] input
1304  A2 => '1', -- Select[2] input
1305  A3 => '1', -- Select[3] input
1306  CE => '1', -- Clock enable input
1307  CLK => sysclk, -- Clock input
1308  D => RstAMC_link -- SRL data input
1309  );
1310 process(UsrClk)
1311 begin
1312  if(UsrClk'event and UsrClk = '1')then
1313  LinkFull <= or_reduce(fake_full);
1314  end if;
1315 end process;
1316 fake_en <= '0' when test = '0' or AMC_en = x"000" else '1';
1317 i_fake_event: fake_event PORT MAP(
1318  sysclk => sysclk,
1319  UsrClk => UsrClk,
1320  reset => resetSyncRegs(2),
1321  fifo_rst => fifo_rst,
1322  fifo_en => fifo_en,
1323  fake_en => fake_en,
1324  sync => '1',
1325  fake_length => fake_length ,
1326  ovfl_warning => ovfl_warning_p ,
1327  LinkFull => LinkFull,
1328  L1A_DATA => L1A_DATA,
1329  L1A_WrEn => L1A_WrEn,
1330  fake_header => fake_header ,
1331  fake_CRC => fake_CRC,
1332  empty_event_flag => empty_event_flag ,
1333  fake_DATA => fake_DATA,
1334  fake_WrEn => fake_WrEn
1335  );
1336 process(UsrClk,reset)
1337 begin
1338  if(reset = '1')then
1339  for i in 0 to 11 loop
1340  AMC_TTS(i)(7 downto 5) <= "000";
1341  end loop;
1342  elsif(UsrClk'event and UsrClk = '1')then
1343  for i in 0 to 11 loop
1344  if(AMC_TTS(i)(2) = '1' and AMC_Ready_i(i) = '1')then -- Out of Sync
1345  AMC_TTS(i)(5) <= '1';
1346  end if;
1347  if(AMC_TTS(i)(3) = '1' and AMC_Ready_i(i) = '1')then -- error
1348  AMC_TTS(i)(6) <= '1';
1349  end if;
1350  if(AMC_TTS(i)(4) = '1' and AMC_Ready_i(i) = '1')then -- disconnected
1351  AMC_TTS(i)(7) <= '1';
1352  end if;
1353  end loop;
1354  end if;
1355 end process;
1356 process(UsrClk)
1357 begin
1358  if(UsrClk'event and UsrClk = '1')then
1359  AMC_TTS_OR <= AMC_TTS(0) or AMC_TTS(1) or AMC_TTS(2) or AMC_TTS(3) or AMC_TTS(4) or AMC_TTS(5) or
1360  AMC_TTS(6) or AMC_TTS(7) or AMC_TTS(8) or AMC_TTS(9) or AMC_TTS(10) or AMC_TTS(11) or err_TTS;
1361  end if;
1362 end process;
1363 err_TTS <= "000000" & stop_mon & '0';
1364 process(UsrClk,reset)
1365 begin
1366  if(reset = '1')then
1367  TTS_FIFO_wa <= (others => '0');
1368  elsif(UsrClk'event and UsrClk = '1')then
1369  case TTS_FIFO_wa(2 downto 0) is
1370  when "000" => TTS_FIFO_wa(2 downto 0) <= "001";
1371  when "001" => TTS_FIFO_wa(2 downto 0) <= "011";
1372  when "011" => TTS_FIFO_wa(2 downto 0) <= "010";
1373  when "010" => TTS_FIFO_wa(2 downto 0) <= "110";
1374  when "110" => TTS_FIFO_wa(2 downto 0) <= "111";
1375  when "111" => TTS_FIFO_wa(2 downto 0) <= "101";
1376  when "101" => TTS_FIFO_wa(2 downto 0) <= "100";
1377  when others => TTS_FIFO_wa(2 downto 0) <= "000";
1378  end case;
1379  end if;
1380 end process;
1381 i_TTS_FIFO: RAM32x6Db PORT MAP(
1382  wclk => UsrClk ,
1383  di => TTS_FIFO_di ,
1384  we => '1',
1385  wa => TTS_FIFO_wa ,
1386  ra => TTS_FIFO_ra ,
1387  do => TTS_FIFO_do
1388  );
1389 TTS_FIFO_di(4 downto 0) <= AMC_TTS_OR(4 downto 0);
1390 TTS_FIFO_ra <= "00" & TTS_FIFO_waSyncRegs3;
1391 process(sysclk)
1392 begin
1393  if(sysclk'event and sysclk = '1')then
1394  TTS_FIFO_waSyncRegs <= TTS_FIFO_wa(2 downto 0);
1395  TTS_FIFO_waSyncRegs2 <= TTS_FIFO_waSyncRegs;
1396  TTS_FIFO_waSyncRegs3 <= TTS_FIFO_waSyncRegs2;
1397  if(enRstAMC_link = '1')then
1398  TTS_coded <= "00010";
1399  elsif(AMC_en = AMC_Ready_i)then
1400  TTS_coded <= TTS_FIFO_do(4 downto 0);
1401  end if;
1402  end if;
1403 end process;
1404 i_UsrClk_buf: bufg port map(i => UsrClk_out(6), o => UsrClk );
1405 process(UsrClk)
1406 begin
1407  if(UsrClk'event and UsrClk = '1')then
1408  RxClkCntr <= RxClkCntr + 1;
1409  RXClkCntr19_q <= RXClkCntr(19);
1410  if(RXClkCntr19_q = '1' and RXClkCntr(19) = '0')then
1411  if(Cntr_ADDR(11 downto 5) = "1110001")then
1412  updateRatio <= '0';
1413  else
1414  updateRatio <= '1';
1415  end if;
1416  end if;
1417  if(Cntr_ADDR(11 downto 7) = "11000" or Cntr_ADDR(11 downto 6) = "111000")then
1418  AMC_if_RdEn <= '1';
1419  else
1420  AMC_if_RdEn <= '0';
1421  end if;
1422  if(Cntr_ADDR(11 downto 7) = "11000" or Cntr_ADDR(11 downto 6) = "111000")then
1423  AMC_if_ADDR <= Cntr_ADDR(9) & Cntr_ADDR(6 downto 0);
1424  else
1425  AMC_if_ADDR <= (others => '0');
1426  end if;
1427  if(AMC_if_RdEn = '0')then
1428  AMC_if_data <= (others => '0');
1429  elsif(AMC_if_ADDR(7) = '0')then
1430  case AMC_if_ADDR(6 downto 4) is
1431  when "000" =>
1432  case AMC_if_ADDR(3 downto 0) is
1433  when x"0" => AMC_if_data <= EventInfo(0)(15 downto 0);
1434  when x"1" => AMC_if_data <= EventInfo(0)(31 downto 16);
1435  when x"2" => AMC_if_data <= EventInfo(1)(15 downto 0);
1436  when x"3" => AMC_if_data <= EventInfo(1)(31 downto 16);
1437  when x"4" => AMC_if_data <= EventInfo(2)(15 downto 0);
1438  when x"5" => AMC_if_data <= EventInfo(2)(31 downto 16);
1439  when x"6" => AMC_if_data <= EventInfo(3)(15 downto 0);
1440  when x"7" => AMC_if_data <= EventInfo(3)(31 downto 16);
1441  when x"8" => AMC_if_data <= EventInfo(4)(15 downto 0);
1442  when x"9" => AMC_if_data <= EventInfo(4)(31 downto 16);
1443  when x"a" => AMC_if_data <= EventInfo(5)(15 downto 0);
1444  when x"b" => AMC_if_data <= EventInfo(5)(31 downto 16);
1445  when x"c" => AMC_if_data <= EventInfo(6)(15 downto 0);
1446  when x"d" => AMC_if_data <= EventInfo(6)(31 downto 16);
1447  when x"e" => AMC_if_data <= EventInfo(7)(15 downto 0);
1448  when others => AMC_if_data <= EventInfo(7)(31 downto 16);
1449  end case;
1450  when "001" =>
1451  case AMC_if_ADDR(3 downto 0) is
1452  when x"0" => AMC_if_data <= EventInfo(8)(15 downto 0);
1453  when x"1" => AMC_if_data <= EventInfo(8)(31 downto 16);
1454  when x"2" => AMC_if_data <= EventInfo(9)(15 downto 0);
1455  when x"3" => AMC_if_data <= EventInfo(9)(31 downto 16);
1456  when x"4" => AMC_if_data <= EventInfo(10)(15 downto 0);
1457  when x"5" => AMC_if_data <= EventInfo(10)(31 downto 16);
1458  when x"6" => AMC_if_data <= EventInfo(11)(15 downto 0);
1459  when x"7" => AMC_if_data <= EventInfo(11)(31 downto 16);
1460  when x"8" => AMC_if_data <= LinkFull & not AMC_qpll_lock & EventInfo_dav;
1461  when x"9" => AMC_if_data <= x"0" & fake_full;
1462  when x"a" => AMC_if_data <= AMC_TTC_status(15 downto 0);
1463  when x"b" => AMC_if_data <= AMC_TTC_status(31 downto 16);
1464  when x"c" => AMC_if_data <= x"0" & AMC_rxfsmresetdone;
1465  when x"d" => AMC_if_data <= x"0" & AMC_txfsmresetdone;
1466  when x"e" => AMC_if_data <= "0000000" & CDF_empty & CDF_cnt;
1467  when others => AMC_if_data <= errors & x"00";
1468  end case;
1469  when "010" =>
1470  case AMC_if_ADDR(3 downto 0) is
1471  when x"0" => AMC_if_data <= "0000000" & evn_wa;
1472  when x"1" => AMC_if_data <= "0000000" & evn_ra;
1473  when x"2" => AMC_if_data <= evn(15 downto 0);
1474  when x"3" => AMC_if_data <= x"00" & evn(23 downto 16);
1475  when x"4" => AMC_if_data <= "0000000" & CDF_wa;
1476  when x"5" => AMC_if_data <= "0000000" & CDF_ra;
1477  when x"6" => AMC_if_data <= ec_CDF_ra & AMC_wc_we & sel_CDF & AMC_header_we & sel_evn & "00" & sel_AMC;
1478  when x"7" => AMC_if_data <= "000" & evt_buf_full & mon_en & WaitMonBuF & TCPbuf_avl & mon_buf_avl & init_bldr & evn_empty & EventInfo_avl & bldr_fifo_full;
1479  when x"8" => AMC_if_data <= fake_word_cnt;
1480  when x"a" => AMC_if_data <= fake_header_cnt;
1481  when x"c" => AMC_if_data <= fake_evt_cnt;
1482  when x"e" => AMC_if_data <= empty_evt_cnt;
1483  when others => AMC_if_data <= (others => '0');
1484  end case;
1485  when "011" =>
1486  case AMC_if_ADDR(3 downto 0) is
1487  when x"0" => AMC_if_data <= TTC_status(3)(5 downto 2) & TTC_status(2)(5 downto 2) & TTC_status(1)(5 downto 2) & TTC_status(0)(5 downto 2);
1488  when x"1" => AMC_if_data <= TTC_status(7)(5 downto 2) & TTC_status(6)(5 downto 2) & TTC_status(5)(5 downto 2) & TTC_status(4)(5 downto 2);
1489  when x"2" => AMC_if_data <= TTC_status(11)(5 downto 2) & TTC_status(10)(5 downto 2) & TTC_status(9)(5 downto 2) & TTC_status(8)(5 downto 2);
1490  when x"4" => AMC_if_data <= AMC_TTS(1) & AMC_TTS(0);
1491  when x"5" => AMC_if_data <= AMC_TTS(3) & AMC_TTS(2);
1492  when x"6" => AMC_if_data <= AMC_TTS(5) & AMC_TTS(4);
1493  when x"7" => AMC_if_data <= AMC_TTS(7) & AMC_TTS(6);
1494  when x"8" => AMC_if_data <= AMC_TTS(9) & AMC_TTS(8);
1495  when x"9" => AMC_if_data <= AMC_TTS(11) & AMC_TTS(10);
1496  when x"a" => AMC_if_data <= evt_cnt(1) & evt_cnt(0);
1497  when x"b" => AMC_if_data <= "000000" & AllEventBuilt_i & AllEventBuilt_i & evt_cnt(2);
1498  when others => AMC_if_data <= (others => '0');
1499  end case;
1500  when "100" =>
1501  case AMC_if_ADDR(3 downto 0) is
1502  when x"0" => AMC_if_data <= badEventCRC_cntr(0);
1503  when x"2" => AMC_if_data <= badEventCRC_cntr(1);
1504  when x"4" => AMC_if_data <= badEventCRC_cntr(2);
1505  when x"6" => AMC_if_data <= badEventCRC_cntr(3);
1506  when x"8" => AMC_if_data <= badEventCRC_cntr(4);
1507  when x"a" => AMC_if_data <= badEventCRC_cntr(5);
1508  when x"c" => AMC_if_data <= badEventCRC_cntr(6);
1509  when x"e" => AMC_if_data <= badEventCRC_cntr(7);
1510  when others => AMC_if_data <= (others => '0');
1511  end case;
1512  when "101" =>
1513  case AMC_if_ADDR(3 downto 0) is
1514  when x"0" => AMC_if_data <= badEventCRC_cntr(8);
1515  when x"2" => AMC_if_data <= badEventCRC_cntr(9);
1516  when x"4" => AMC_if_data <= badEventCRC_cntr(10);
1517  when x"6" => AMC_if_data <= badEventCRC_cntr(11);
1518  when x"8" => AMC_if_data <= EventBuiltCnt(0);
1519  when x"a" => AMC_if_data <= EventBuiltCnt(1);
1520  when x"c" => AMC_if_data <= EventBuiltCnt(2);
1521  when others => AMC_if_data <= (others => '0');
1522  end case;
1523  when "110" | "111" =>
1524  if(AMC_if_ADDR(0) = '0')then
1525  AMC_if_data <= x"00" & "00" & AMC_wc_sum_do;
1526  else
1527  AMC_if_data <= (others => '0');
1528  end if;
1529  when others => AMC_if_data <= (others => '0');
1530  end case;
1531  else
1532  case AMC_if_ADDR(5 downto 4) is
1533  when "00" =>
1534  case AMC_if_ADDR(3 downto 0) is
1535  when x"0" => AMC_if_data <= ReSyncFakeEvent_cntr(0);
1536  when x"2" => AMC_if_data <= ReSyncFakeEvent_cntr(1);
1537  when x"4" => AMC_if_data <= ReSyncFakeEvent_cntr(2);
1538  when x"6" => AMC_if_data <= ReSyncFakeEvent_cntr(3);
1539  when x"8" => AMC_if_data <= ReSyncFakeEvent_cntr(4);
1540  when x"a" => AMC_if_data <= ReSyncFakeEvent_cntr(5);
1541  when x"c" => AMC_if_data <= ReSyncFakeEvent_cntr(6);
1542  when x"e" => AMC_if_data <= ReSyncFakeEvent_cntr(7);
1543  when others => AMC_if_data <= (others => '0');
1544  end case;
1545  when "01" =>
1546  case AMC_if_ADDR(3 downto 0) is
1547  when x"0" => AMC_if_data <= ReSyncFakeEvent_cntr(8);
1548  when x"2" => AMC_if_data <= ReSyncFakeEvent_cntr(9);
1549  when x"4" => AMC_if_data <= ReSyncFakeEvent_cntr(10);
1550  when x"6" => AMC_if_data <= ReSyncFakeEvent_cntr(11);
1551  when others => AMC_if_data <= (others => '0');
1552  end case;
1553  when "10" =>
1554  case AMC_if_ADDR(3 downto 0) is
1555  when x"0" => AMC_if_data <= RxClkRatio(0)(15 downto 0);
1556  when x"1" => AMC_if_data <= x"00" & "000" & RxClkRatio(0)(20 downto 16);
1557  when x"2" => AMC_if_data <= RxClkRatio(1)(15 downto 0);
1558  when x"3" => AMC_if_data <= x"00" & "000" & RxClkRatio(1)(20 downto 16);
1559  when x"4" => AMC_if_data <= RxClkRatio(2)(15 downto 0);
1560  when x"5" => AMC_if_data <= x"00" & "000" & RxClkRatio(2)(20 downto 16);
1561  when x"6" => AMC_if_data <= RxClkRatio(3)(15 downto 0);
1562  when x"7" => AMC_if_data <= x"00" & "000" & RxClkRatio(3)(20 downto 16);
1563  when x"8" => AMC_if_data <= RxClkRatio(4)(15 downto 0);
1564  when x"9" => AMC_if_data <= x"00" & "000" & RxClkRatio(4)(20 downto 16);
1565  when x"a" => AMC_if_data <= RxClkRatio(5)(15 downto 0);
1566  when x"b" => AMC_if_data <= x"00" & "000" & RxClkRatio(5)(20 downto 16);
1567  when x"c" => AMC_if_data <= RxClkRatio(6)(15 downto 0);
1568  when x"d" => AMC_if_data <= x"00" & "000" & RxClkRatio(6)(20 downto 16);
1569  when x"e" => AMC_if_data <= RxClkRatio(7)(15 downto 0);
1570  when others => AMC_if_data <= x"00" & "000" & RxClkRatio(7)(20 downto 16);
1571  end case;
1572  when others =>
1573  case AMC_if_ADDR(3 downto 0) is
1574  when x"0" => AMC_if_data <= RxClkRatio(8)(15 downto 0);
1575  when x"1" => AMC_if_data <= x"00" & "000" & RxClkRatio(8)(20 downto 16);
1576  when x"2" => AMC_if_data <= RxClkRatio(9)(15 downto 0);
1577  when x"3" => AMC_if_data <= x"00" & "000" & RxClkRatio(9)(20 downto 16);
1578  when x"4" => AMC_if_data <= RxClkRatio(10)(15 downto 0);
1579  when x"5" => AMC_if_data <= x"00" & "000" & RxClkRatio(10)(20 downto 16);
1580  when x"6" => AMC_if_data <= RxClkRatio(11)(15 downto 0);
1581  when x"7" => AMC_if_data <= x"00" & "000" & RxClkRatio(11)(20 downto 16);
1582  when x"8" => AMC_if_data <= x"0" & RxBufUdfErr;
1583  when x"9" => AMC_if_data <= x"0" & RxBufOvfErr;
1584  when others => AMC_if_data <= (others => '0');
1585  end case;
1586  end case;
1587  end if;
1588  end if;
1589 end process;
1590 i_AMC_cntr : AMC_cntr PORT MAP (
1591  UsrClk => UsrClk ,
1592  clk125 => clk125 ,
1593  sysclk => sysclk ,
1594  ipb_clk => ipb_clk ,
1595  resetCntr => resetCntr,
1596  DB_cmd => DB_cmd ,
1597  AMC_if_data => AMC_if_data,
1598  Cntr_DATA => Cntr_DATA,
1599  Cntr_ADDR => Cntr_ADDR,
1600  ipb_addr => ipb_addr(15 downto 0),
1601  ipb_rdata => AMC_cntr_data
1602  );
1603 process(UsrClk,reset)
1604 begin
1605  if(reset = '1')then
1606  RxBufOvfErr <= (others => '0');
1607  RxBufUdfErr <= (others => '0');
1608  elsif(UsrClk'event and UsrClk = '1')then
1609  for i in 0 to 11 loop
1610  RxBufOvfErr(i) <= (RxBufOvfErr(i) or RxBufOvf(i)) and AMC_en(i) and not test;
1611  RxBufUdfErr(i) <= (RxBufUdfErr(i) or RxBufUdf(i)) and AMC_en(i) and not test;
1612  end loop;
1613  end if;
1614 end process;
1615 process(TTC_status, AMC_en)
1616 begin
1617  for i in 0 to 11 loop
1618  AMC_TTC_status(i) <= TTC_status(i)(0) and AMC_en(i);
1619  AMC_TTC_status(i+16) <= TTC_status(i)(1) and AMC_en(i);
1620  end loop;
1621 end process;
1622 TTC_lock <= and_reduce(AMC_TTC_status(27 downto 16) or not AMC_en);
1623 BC0_lock <= AMC_TTC_status(11 downto 0);
1624 AMC_TTC_status(31 downto 28) <= x"0";
1625 AMC_TTC_status(15 downto 12) <= x"0";
1626 process(ipb_clk)
1627 begin
1628  if(ipb_clk'event and ipb_clk = '1')then
1629  if(ipb_strobe = '1' and ipb_write = '1' and ipb_addr(14 downto 0) = MON_ctrl_addr(14 downto 0) and ipb_addr(27) = '0')then
1630  scale <= ipb_wdata;
1631  end if;
1632  ipb_strobe_q <= ipb_strobe;
1633  end if;
1634 end process;
1635 ipb_ack <= '0' when ipb_addr(27) = '1' or ipb_addr(15 downto 11) /= AMC_reg_addr(15 downto 11) or ipb_write = '1' else ipb_strobe;
1636 process(ipb_addr)
1637 begin
1638  if(ipb_addr(15 downto 9) = L1A_buf_addr(15 downto 9))then
1639  ipb_rdata <= L1A_buf_do;
1640  elsif(ipb_addr(14 downto 11) /= AMC_reg_addr(14 downto 11))then
1641  ipb_rdata <= (others => '0');
1642  else
1643  ipb_rdata <= AMC_cntr_data;
1644  end if;
1645 end process;
1646 AMC_status(31 downto 28) <= (others => '0');
1647 AMC_status(27 downto 16) <= AMC_data_valid or not AMC_en;
1648 AMC_status(15 downto 12) <= (others => '0');
1649 inc_div <= x"004" when CntrRstCycle = '1' else x"001";
1650 process(UsrClk)
1651 begin
1652  if(UsrClk'event and UsrClk = '1')then
1653  for i in 0 to 2 loop
1654  EventBuiltToggleSyncRegs(i) <= EventBuiltToggleSyncRegs(i)(2 downto 0) & EventBuiltToggle(i);
1655  end loop;
1656  for i in 0 to 11 loop
1657  badEventCRCToggleSyncRegs(i) <= badEventCRCToggleSyncRegs(i)(2 downto 0) & badEventCRCToggle(i);
1658  ReSyncFakeEventToggleSyncRegs(i) <= ReSyncFakeEventToggleSyncRegs(i)(2 downto 0) & ReSyncFakeEventToggle(i);
1659  end loop;
1660  if(CntrRst = '1')then
1661  badEventCRC_cntr <= (others => (others => '0'));
1662  ReSyncFakeEvent_cntr <= (others => (others => '0'));
1663  EventBuiltCnt <= (others => (others => '0'));
1664  fake_word_cnt <= (others => '0');
1665  fake_evt_cnt <= (others => '0');
1666  empty_evt_cnt <= (others => '0');
1667  fake_header_cnt <= (others => '0');
1668  else
1669  for i in 0 to 11 loop
1670  if(badEventCRCToggleSyncRegs(i)(3) /= badEventCRCToggleSyncRegs(i)(2))then
1671  badEventCRC_cntr(i) <= badEventCRC_cntr(i) + 1;
1672  end if;
1673  if(ReSyncFakeEventToggleSyncRegs(i)(3) /= ReSyncFakeEventToggleSyncRegs(i)(2))then
1674  ReSyncFakeEvent_cntr(i) <= ReSyncFakeEvent_cntr(i) + 1;
1675  end if;
1676  end loop;
1677  for i in 0 to 2 loop
1678  if(EventBuiltToggleSyncRegs(i)(3) /= EventBuiltToggleSyncRegs(i)(2))then
1679  EventBuiltCnt(i) <= EventBuiltCnt(i) + 1;
1680  end if;
1681  end loop;
1682  if(fake_WrEn = '1')then
1683  fake_word_cnt <= fake_word_cnt + 1;
1684  end if;
1685  if(fake_CRC = '1')then
1686  fake_evt_cnt <= fake_evt_cnt + 1;
1687  end if;
1688  if(fake_CRC = '1' and empty_event_flag = '1')then
1689  empty_evt_cnt <= empty_evt_cnt + 1;
1690  end if;
1691  if(fake_WrEn = '1' and fake_header = '1')then
1692  fake_header_cnt <= fake_header_cnt + 1;
1693  end if;
1694  end if;
1695  resetCntr_SyncRegs <= resetCntr_SyncRegs(1 downto 0) & resetCntr;
1696  CntrRst <= (not resetCntr_SyncRegs(2) and resetCntr_SyncRegs(1)) or RstAMC_link;
1697  end if;
1698 end process;
1699 i_AMC_refclk: IBUFDS_GTE2
1700  port map
1701  (
1702  O => AMC_REFCLK,
1703  ODIV2 => open,
1704  CEB => '0',
1705  I => AMC_REFCLK_P, -- Connect to package pin AB6
1706  IB => AMC_REFCLK_N -- Connect to package pin AB5
1707  );
1708 -- monitoring logic
1709 process(sysclk)
1710 begin
1711  if(sysclk'event and sysclk = '1')then
1712  if(resetSyncRegs(2) = '1')then
1713  errors <= (others => '0');
1714  stop_mon <= '0';
1715  else
1716  if(or_reduce(AMCCRC_bad(0)) = '1' or or_reduce(AMCCRC_bad(1)) = '1' or or_reduce(AMCCRC_bad(2)) = '1')then
1717  errors(7) <= '1';
1718  end if;
1719  if(or_reduce(errors and scale(31 downto 24)) = '1' and rst_init_bldr = '1' and LastBlock = '1')then
1720  stop_mon <= '1';
1721  end if;
1722  end if;
1723  case scale(22 downto 19) is
1724  when x"0" => mon_mask <= x"00000";
1725  when x"1" => mon_mask <= x"80000";
1726  when x"2" => mon_mask <= x"c0000";
1727  when x"3" => mon_mask <= x"e0000";
1728  when x"4" => mon_mask <= x"f0000";
1729  when x"5" => mon_mask <= x"f8000";
1730  when x"6" => mon_mask <= x"fc000";
1731  when x"7" => mon_mask <= x"fe000";
1732  when x"8" => mon_mask <= x"ff000";
1733  when x"9" => mon_mask <= x"ff800";
1734  when x"a" => mon_mask <= x"ffc00";
1735  when x"b" => mon_mask <= x"ffe00";
1736  when x"c" => mon_mask <= x"fff00";
1737  when x"d" => mon_mask <= x"fff80";
1738  when x"e" => mon_mask <= x"fffc0";
1739  when others => mon_mask <= x"fffe0";
1740  end case;
1741  if(CDF_Header = '1' and init_bldr = '1')then
1742  if(and_reduce(CDF_out(51 downto 32) or mon_mask) = '1')then
1743  sample_event <= '1';
1744  else
1745  sample_event <= '0';
1746  end if;
1747  end if;
1748  if(useTCPIP = true and enSFP(3) = '0' and enSFP(2 downto 0) /= "000")then
1749  mon_en <= '1';
1750  pending <= '0';
1751  elsif(resetSyncRegs(2) = '1')then
1752 -- After reset, the first event will always be recorded
1753  mon_en <= not scale(23);
1754  pending <= '0';
1755  elsif(rst_init_bldr = '1' and LastBlock = '1')then
1756  if(scale(23) = '1')then
1757  mon_en <= sample_event and (mon_buf_avl or WaitMonBuf) and not stop_mon;
1758  pending <= '0';
1759  else
1760  mon_en <= (mon_buf_avl or WaitMonBuf) and not stop_mon and (and_reduce(scale_cntr) or pending);
1761  pending <= not mon_buf_avl and (and_reduce(scale_cntr) or pending);
1762  end if;
1763  end if;
1764 -- if(resetSyncRegs(2) = '1')then
1765 -- start_wc_reg_wa <= (others => '0');
1766 -- elsif(FirstBlock(0) = '1' and ce_wc_reg_wa = '1')then
1767 -- start_wc_reg_wa <= wc_reg_wa;
1768 -- end if;
1769  if(resetSyncRegs(2) = '1' or rst_mon_wc = '1')then
1770  mon_wc(0) <= (others => '0');
1771  elsif(zero_wc(0) = '0' and (header = '1' or sel_CDF = '1' or (more_wc(0) = '0' and rst_init_bldr = '1')))then
1772  mon_wc(0) <= mon_wc(0) + 1;
1773  elsif(AMC_wc_we(0) = '1')then
1774  mon_wc(0) <= mon_wc(0) + ("000" & AMC_wc(12 downto 0)) + 1;
1775  end if;
1776  if(resetSyncRegs(2) = '1' or rst_mon_wc = '1')then
1777  mon_wc(1) <= (others => '0');
1778  elsif(zero_wc(1) = '0' and (header = '1' or sel_CDF = '1' or (more_wc(1) = '0' and rst_init_bldr = '1')))then
1779  mon_wc(1) <= mon_wc(1) + 1;
1780  elsif(AMC_wc_we(1) = '1')then
1781  mon_wc(1) <= mon_wc(1) + ("000" & AMC_wc(12 downto 0)) + 1;
1782  end if;
1783  if(resetSyncRegs(2) = '1' or rst_mon_wc = '1')then
1784  mon_wc(2) <= (others => '0');
1785  elsif(zero_wc(2) = '0' and (header = '1' or sel_CDF = '1' or (more_wc(2) = '0' and rst_init_bldr = '1')))then
1786  mon_wc(2) <= mon_wc(2) + 1;
1787  elsif(AMC_wc_we(2) = '1')then
1788  mon_wc(2) <= mon_wc(2) + ("000" & AMC_wc(12 downto 0)) + 1;
1789  end if;
1790  if(ce_scale = '1')then
1791  if(ld_scale = '1')then
1792  scale_cntr <= not scale(15 downto 0);
1793  else
1794  scale_cntr <= scale_cntr + 1;
1795  end if;
1796  end if;
1797  if(resetSyncRegs(2) = '1')then
1798  ce_scale <= '0';
1799  ld_scale <= '0';
1800  ce_wc_reg_wa <= '0';
1801 -- MonBufAbort <= '0';
1802  else
1803  ce_scale <= init_bldr and CDF_Header;
1804  ld_scale <= mon_en or pending;
1805  ce_wc_reg_wa <= rst_init_bldr and AMC_header(0)(64);
1806 -- MonBufAbort <= rst_init_bldr and mon_en and not AMC_header(0)(64);
1807  end if;
1808  rst_mon_wc <= rst_init_bldr;
1809  if(resetSyncRegs(2) = '1' or rst_mon_wc = '1')then
1810  en_block_wc <= (others => '0');
1811  else
1812  en_block_wc <= en_block_wc or amc_header_we;
1813  end if;
1814  for i in 0 to 2 loop
1815  block_wc_we(i) <= rst_init_bldr and en_block_wc(i);
1816  end loop;
1817  if(resetSyncRegs(2) = '1')then
1818  EventInfoRdDone <= (others => '0');
1819  elsif(sel_AMC = x"b")then
1820 -- EventInfoRdDone <= '1' & AMC_hasData_l;
1821  EventInfoRdDone <= '1' & AMC_hasData;
1822  else
1823  EventInfoRdDone <= (others => '0');
1824  end if;
1825  rst_init_bldr <= EventInfoRdDone(12);
1826  if(resetSyncRegs(2) = '1')then
1827  wc_reg_wa <= (others => '0');
1828 -- elsif(MonBufAbort = '1')then
1829 -- wc_reg_wa <= start_wc_reg_wa;
1830  elsif(ce_wc_reg_wa = '1')then
1831  wc_reg_wa <= wc_reg_wa + 1;
1832  end if;
1833  end if;
1834 end process;
1835 g_mon_evt_wc: for i in 0 to 2 generate
1836  i_mon_evt_wc : BRAM_SDP_MACRO
1837  generic map (
1838  BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
1839  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1840  WRITE_WIDTH => 16, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1841  READ_WIDTH => 16, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1842  DO_REG => 0, -- Optional output register (0 or 1)
1843  SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY",
1844  -- "GENERATE_X_ONLY" or "NONE"
1845  WRITE_MODE => "WRITE_FIRST", -- Specify "READ_FIRST" for same clock or synchronous clocks
1846  -- Specify "WRITE_FIRST for asynchrononous clocks on ports
1847  INIT => X"000000000000000000") -- Initial values on output port
1848  port map (
1849  DO => mon_evt_wcp(i*16+15 downto i*16), -- Output read data port, width defined by READ_WIDTH parameter
1850  DI => mon_wc(i), -- Input write data port, width defined by WRITE_WIDTH parameter
1851  RDADDR => ddr_pa, -- Input read address, width defined by read port depth
1852  RDCLK => ipb_clk, -- 1-bit input read clock
1853  RDEN => '1', -- 1-bit input read port enable
1854  REGCE => '1', -- 1-bit input read output register enable
1855  RST => MonBuf_empty, -- 1-bit input reset
1856  WE => "11", -- Input write enable, width defined by write port depth
1857  WRADDR => wc_reg_wa, -- Input write address, width defined by write port depth
1858  WRCLK => sysclk, -- 1-bit input write clock
1859  WREN => ce_wc_reg_wa -- 1-bit input write port enable
1860  );
1861 end generate;
1862 mon_evt_wc(15 downto 0) <= mon_evt_wcp(15 downto 0) when OneSFP = '1' else mon_evt_wcp(31 downto 16);
1863 mon_evt_wc(31 downto 16) <= x"0000" when OneSFP = '1' else mon_evt_wcp(15 downto 0);
1864 mon_evt_wc(47 downto 32) <= mon_evt_wcp(47 downto 32);
1865 process(sysclk)
1866 begin
1867  if(sysclk'event and sysclk = '1')then
1868  ThreeSFP <= and_reduce(EnSFP(2 downto 0));
1869  if(EnSFP(2 downto 0) = "011" or EnSFP(2 downto 0) = "101" or EnSFP(2 downto 0) = "110")then
1870  TwoSFP <= '1';
1871  else
1872  TwoSFP <= '0';
1873  end if;
1874  if(EnSFP(2 downto 0) = "001" or EnSFP(2 downto 0) = "010" or EnSFP(2 downto 0) = "100" or EnSFP(2 downto 0) = "000")then
1875  OneSFP <= '1';
1876  else
1877  OneSFP <= '0';
1878  end if;
1879  end if;
1880 end process;
1881 i_FIFO_RESET_7S: FIFO_RESET_7S PORT MAP(
1882  reset => resetFIFO,
1883  clk => sysclk ,
1884  fifo_rst => fifo_rst,
1885  fifo_en => fifo_en
1886  );
1887 resetFIFO <= reset or or_reduce(not AMC_txfsmresetdone and AMC_en);
1888 process(sysclk)
1889 begin
1890  if(sysclk'event and sysclk = '1')then
1891  if(resetSyncRegs(2) = '1')then
1892  rst_AMC_wc_sum <= '1';
1893  wr_AMC_wc_sum <= '0';
1894  else
1895  if(wr_AMC_wc_sum = '1' and ec_sel_AMC = '0')then
1896  rst_AMC_wc_sum <= '0';
1897  end if;
1898  wr_AMC_wc_sum <= ec_sel_AMC;
1899  end if;
1900  sel_AMC_q <= sel_AMC;
1901  end if;
1902 end process;
1903 i_AMC_wc_sum: RAM32x6Db PORT MAP(
1904  wclk => sysclk ,
1905  di => AMC_wc_sum_di,
1906  we => AMC_wc_sum_we,
1907  wa => AMC_wc_sum_a ,
1908  ra => AMC_wc_sum_a ,
1909  do => AMC_wc_sum_do
1910  );
1911 AMC_wc_sum_di <= AMC_wc_sum_do + AMC_wc(5 downto 0) when rst_AMC_wc_sum = '0' else AMC_wc(5 downto 0);
1912 AMC_wc_sum_a(3 downto 0) <= sel_AMC_q when wr_AMC_wc_sum = '1' else AMC_if_ADDR(4 downto 1);
1913 end Behavioral;
1914 
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