AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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AMC_Link.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 15:55:15 07/09/2010
6 -- Design Name:
7 -- Module Name: AMC_Link - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 ----------------------------------------------------------------------------------
19 library IEEE;
20 use IEEE.STD_LOGIC_1164.ALL;
21 use IEEE.STD_LOGIC_ARITH.ALL;
22 use IEEE.STD_LOGIC_UNSIGNED.ALL;
23 use IEEE.std_logic_misc.all;
24 use work.amc13_pack.all;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 --use IEEE.NUMERIC_STD.ALL;
29 
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 library UNISIM;
33 use UNISIM.VComponents.all;
34 Library UNIMACRO;
35 use UNIMACRO.vcomponents.all;
36 
37 entity AMC_Link is
38  generic(N : integer := 14; useTRIG : boolean := false; simulation : boolean := false); -- M controls FIFO size, N controls timeout
39  port(
40  sysclk : in std_logic; -- 200MHz
41  reset : in std_logic;
42  resetCntr : in std_logic;
43  fifo_rst : in std_logic;
44  fifo_en : in std_logic;
45  test : in std_logic;
46  NoReSyncFake : in std_logic;
47  UsrClk : in std_logic;
48  Ready : out std_logic; -- Link to AMC established
49  AMC_ID : in STD_LOGIC_VECTOR(3 downto 0);
50  txfsmresetdone : in std_logic;
51  RxResetDone : in std_logic;
52  qpll_lock : in std_logic;
53  rxcommaalignen : out std_logic;
54  DATA_VALID : out std_logic;
55  RXDATA : in std_logic_vector(15 downto 0);
56  RXCHARISCOMMA : in std_logic_vector(1 downto 0);
57  RXCHARISK : in std_logic_vector(1 downto 0);
58  RXNOTINTABLE : in std_logic_vector(1 downto 0);
59  TXDATA : out std_logic_vector(15 downto 0);
60  TXCHARISK : out std_logic_vector(1 downto 0);
61 -------------
62  AMCinfo : out std_logic_vector(15 downto 0);
63  EventInfo : out std_logic_vector(31 downto 0);
64  EventInfo_dav : out std_logic;
65  AMC_en : in std_logic;
66  AMC_DATA_RdEn : in std_logic; -- enable reading AMC event
67  EventInfoRdDone : in std_logic; -- end of reading AMC event
68  AMC_DATA : out std_logic_vector(63 downto 0);
69  L1A_DATA : in std_logic_vector(15 downto 0);
70  L1A_WrEn : in std_logic;
71  fake_header : in std_logic;
72  fake_CRC : in std_logic;
73  fake_DATA : in std_logic_vector(15 downto 0);
74 -- fake_evn : in std_logic_vector(3 downto 0);
75  fake_WrEn : in std_logic;
76  fake_full : out std_logic;
77 -- fake_accept : in std_logic;
78  bad_AMC : out std_logic;
79  AMC_OK : out std_logic;
80 -- scan counters
81 -- Cntr_RdEn : in std_logic;
82 -- Cntr_RdEnp : in std_logic;
83  Cntr_ADDR : in std_logic_vector(11 downto 0);
84  Cntr_DATA : out std_logic_vector(15 downto 0);
85 -- ipbus read signals
86 -- ipb_addr : in std_logic_vector(15 downto 0);
87 -- ipb_rdata : out std_logic_vector(31 downto 0);
88  debug_out : out std_logic_vector(255 downto 0);
89 -- TTC & TTS signals
90  TTCclk : in std_logic;
91  BC0 : in std_logic; -- AMC13 BC0 delayed by four TTC_clk cycles
92  TTC_LOS : in std_logic;
93  TTS_disable : in std_logic;
94  TTC_status : out std_logic_vector(127 downto 0);
95  TrigData : out std_logic_vector(7 downto 0);
96 -- TTS is in the UsrClk domain
97  TTS_coded : out std_logic_vector(4 downto 0)-- Disconnected, Error, Sync Lost, Busy and Overflow Warning
98  );
99 end AMC_Link;
100 
101 architecture Behavioral of AMC_Link is
102 COMPONENT HammingDecode
103  PORT(
104  clk : IN std_logic;
105  din_valid : IN std_logic;
106  din : IN std_logic_vector(23 downto 0);
107  dout_valid : OUT std_logic;
108  dout : OUT std_logic_vector(17 downto 0);
109  sgl_err : OUT std_logic;
110  dbl_err : OUT std_logic
111  );
112 END COMPONENT;
113 COMPONENT crc16D16
114  PORT(
115  clk : IN std_logic;
116  init_crc : IN std_logic;
117  we_crc : IN std_logic;
118  d : IN std_logic_vector(15 downto 0);
119  crc : OUT std_logic_vector(15 downto 0)
120  );
121 END COMPONENT;
122 COMPONENT EthernetCRCD16B
123  PORT(
124  clk : IN std_logic;
125  init : IN std_logic;
126  save : IN std_logic;
127  restore : IN std_logic;
128  ce : IN std_logic;
129  d : IN std_logic_vector(15 downto 0);
130  crc : OUT std_logic_vector(31 downto 0);
131  bad_crc : OUT std_logic
132  );
133 END COMPONENT;
134 COMPONENT AMC_DATA_FIFO
135  PORT(
136  wclk : IN std_logic;
137  rclk : IN std_logic;
138  reset : IN std_logic;
139  fifo_en : IN std_logic;
140  we : IN std_logic;
141  re : IN std_logic;
142  Di : IN std_logic_vector(63 downto 0);
143  Do : OUT std_logic_vector(63 downto 0);
144  WRERR_OUT : OUT std_logic_vector(7 downto 0);
145  RDERR_OUT : OUT std_logic_vector(7 downto 0);
146  full : OUT std_logic
147  );
148 END COMPONENT;
149 COMPONENT TTC_trigger
150  generic(simulation : boolean := false);
151  PORT(
152  reset : IN std_logic;
153  UsrClk : IN std_logic;
154  TTCclk : IN std_logic;
155  HammingData_in : IN std_logic_vector(17 downto 0);
156  HammingDataValid : IN std_logic;
157  BC0 : IN std_logic;
158  BcntMm : OUT std_logic;
159  TTC_lock : OUT std_logic;
160  BC0_lock : OUT std_logic;
161  TrigData : OUT std_logic_vector(7 downto 0)
162  );
163 END COMPONENT;
164 constant Acknowledge : std_logic_vector(7 downto 0) := x"12";
165 constant data : std_logic_vector(7 downto 0) := x"34";
166 constant InitRqst : std_logic_vector(7 downto 0) := x"56";
167 constant Counter : std_logic_vector(7 downto 0) := x"78";
168 constant K_word : std_logic_vector(15 downto 0) := x"3cbc"; -- sequence K28.5 K28.1
169 constant R_word : std_logic_vector(15 downto 0) := x"dcfb"; -- sequence K27.7 K28.6
170 constant eof_word : std_logic_vector(15 downto 0) := x"5cf7"; -- sequence K23.7 K28.2
171 constant IDLE : std_logic_vector(3 downto 0) := x"0"; -- TxState
172 constant SendK : std_logic_vector(3 downto 0) := x"1"; -- TxState sending comma
173 constant SendType : std_logic_vector(3 downto 0) := x"2"; -- TxState sending event data words
174 constant SendSEQ : std_logic_vector(3 downto 0) := x"3"; -- TxState sending sequence number
175 constant SendWC : std_logic_vector(3 downto 0) := x"4"; -- TxState sending payload word count
176 constant WaitCRC : std_logic_vector(3 downto 0) := x"5"; -- TxState same as IDLE
177 constant SendCRC : std_logic_vector(3 downto 0) := x"6"; -- TxState sending CRC
178 constant SendData : std_logic_vector(3 downto 0) := x"7"; -- TxState sending event data words
179 signal AMCRdy : std_logic := '0';
180 signal AMC_IDp1: std_logic_vector(3 downto 0) := (others => '0');
181 signal AMC_IDp4: std_logic_vector(3 downto 0) := (others => '0');
182 signal TxState: std_logic_vector(3 downto 0) := (others => '0');
183 signal InitLink : std_logic := '0';
184 signal RxResetDoneSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
185 signal RXDATA_q : std_logic_vector(15 downto 0) := (others => '0');
186 signal TXDATA_i : std_logic_vector(15 downto 0) := (others => '0');
187 signal reset_SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
188 signal fake_evn : std_logic_vector(3 downto 0) := (others => '0');
189 signal sgl_err : std_logic := '0';
190 signal dbl_err : std_logic := '0';
191 signal sel_TTC : std_logic := '0';
192 signal is_TTS : std_logic := '0';
193 signal update_TTS : std_logic := '0';
194 signal SendTTS : std_logic := '0';
195 signal TTS_in : std_logic_vector(3 downto 0) := (others => '0');
196 signal TTS_tmp : std_logic_vector(7 downto 0) := (others => '0');
197 signal TTS : std_logic_vector(7 downto 0) := (others => '0');
198 signal TTS_coded_i : std_logic_vector(4 downto 0) := (others => '0');
199 signal TTS_valid : std_logic := '0';
200 signal TTC_lock : std_logic := '0';
201 signal BC0_lock : std_logic := '0';
202 signal BcntMm : std_logic := '0';
203 signal BC0_link : std_logic := '0';
204 signal BC0_matchCntr : std_logic_vector(8 downto 0) := (others => '0');
205 signal TTC_missingCntr : std_logic_vector(3 downto 0) := (others => '0');
206 signal HammingOutValid : std_logic := '0';
207 signal bcnt_link : std_logic_vector(11 downto 0) := (others => '0');
208 signal ec_delta_BC0 : std_logic := '0';
209 signal delta_BC0 : std_logic_vector(3 downto 0) := (others => '0');
210 signal MmCntr : std_logic_vector(3 downto 0) := (others => '0');
211 signal TTC_DataValid : std_logic := '0';
212 signal TTC_Data : std_logic_vector(23 downto 0) := (others => '0');
213 signal TTC_FIFO_we : std_logic := '0';
214 signal HammingOut : std_logic_vector(17 downto 0) := (others => '0');
215 signal TTC_FIFO_Di : std_logic_vector(11 downto 0) := (others => '0');
216 signal TTC_FIFO_Do : std_logic_vector(11 downto 0) := (others => '0');
217 signal TTC_FIFO_Do_dl : std_logic_vector(8 downto 0) := (others => '0');
218 signal TTC_FIFO_DoValid : std_logic := '0';
219 signal TTC_FIFO_wa : std_logic_vector(4 downto 0) := (others => '0');
220 signal TTC_FIFO_wa0_SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
221 signal TTC_FIFO_ra : std_logic_vector(4 downto 0) := (others => '0');
222 signal BC0_offset : std_logic_vector(3 downto 0) := (others => '0');
223 signal check_packet : std_logic := '0';
224 signal ACK : std_logic := '0';
225 signal Abort : std_logic := '0';
226 signal CntrAbort : std_logic := '0';
227 signal bad_K : std_logic := '0';
228 signal SEQ_OK : std_logic := '0';
229 signal CRC_OK : std_logic := '0';
230 signal frame_OK : std_logic := '0';
231 signal ACK_OK : std_logic := '0';
232 signal WC_OKp : std_logic := '0';
233 signal WC_OK : std_logic := '0';
234 signal TypeInit : std_logic := '0';
235 signal TypeACK : std_logic := '0';
236 signal TypeData : std_logic := '0';
237 signal TypeData_q : std_logic := '0';
238 signal TypeCntr : std_logic := '0';
239 signal Receiving : std_logic := '0';
240 signal Receiving_q : std_logic := '0';
241 signal Header2 : std_logic := '0';
242 signal IsACK : std_logic := '0';
243 signal ACKNUM_full : std_logic := '0';
244 signal ACKNUM_empty : std_logic := '0';
245 signal ACKNUM_IN : std_logic_vector(7 downto 0) := (others => '0');
246 signal RxSEQNUM : std_logic_vector(7 downto 0) :=(others => '0');
247 signal SEQNUM : std_logic_vector(7 downto 0) :=(others => '0');
248 signal NextSEQNUM : std_logic_vector(7 downto 0) :=(others => '0');
249 signal ACKNUM : std_logic_vector(7 downto 0) := (others => '0');
250 signal CntrACKNUM : std_logic_vector(7 downto 0) := (others => '0');
251 signal ACKNUM_MUX : std_logic_vector(7 downto 0) := (others => '0');
252 signal ACKNUM_l : std_logic_vector(7 downto 0) := (others => '0');
253 signal ACKNUM_a : std_logic_vector(1 downto 0) := (others => '1');
254 signal RxType : std_logic_vector(15 downto 0) := (others => '0');
255 signal RxWC : std_logic_vector(11 downto 0) := (others => '0');
256 signal LinkVersion : std_logic_vector(7 downto 0) := (others => '0');
257 signal accept : std_logic := '0';
258 signal CntrAccept : std_logic := '0';
259 signal we_ACKNUM : std_logic := '0';
260 signal save_start_addr : std_logic := '0';
261 signal eof : std_logic := '0';
262 signal got_eof : std_logic := '0';
263 signal fake_got_eof : std_logic := '0';
264 signal BOE : std_logic := '0';
265 signal AMCinfo_word : std_logic := '0';
266 signal saved_BOE : std_logic := '0';
267 signal dl_cntr : std_logic_vector(2 downto 0) := (others => '0');
268 signal we_rfifo : std_logic := '0';
269 signal rfifo : std_logic_vector(15 downto 0) := (others => '0');
270 signal rfifo_a : std_logic_vector(1 downto 0) := (others => '1');
271 signal EventBuf_ovf : std_logic := '0';
272 signal EventBuf_full : std_logic := '0';
273 signal ec_EventBuf_ra : std_logic := '0';
274 signal ec_EventBuf_ra_q : std_logic := '0';
275 signal evn_word : std_logic_vector(2 downto 0) := (others => '0');
276 signal get_evn : std_logic := '0';
277 signal evn_OK : std_logic_vector(5 downto 0) := (others => '0');
278 signal evn : std_logic_vector(7 downto 0) := (others => '0');
279 signal LengthMatch : std_logic := '0';
280 signal UnknownLength : std_logic := '0';
281 signal bad_EventLength : std_logic := '0';
282 signal bad_AMCCRC : std_logic := '0';
283 signal InitAMCCRC : std_logic := '0';
284 signal AMCCRC : std_logic_vector(31 downto 0) := (others => '0');
285 signal EventBuf_we : std_logic_vector(0 downto 0) := (others => '0');
286 signal EventBuf_start : std_logic_vector(12 downto 0) := (others => '0');
287 signal EventBuf_wa : std_logic_vector(12 downto 0) := (others => '0');
288 signal EventBuf_ra : std_logic_vector(10 downto 0) := (others => '0');
289 signal EventBuf_wc : std_logic_vector(10 downto 0) := (others => '0');
290 signal EventBuf_space : std_logic_vector(10 downto 0) := (others => '0');
291 signal EventBuf_Di : std_logic_vector(15 downto 0) := (others => '0');
292 signal EventBuf_Do : std_logic_vector(63 downto 0) := (others => '0');
293 signal EventWC : std_logic_vector(19 downto 0) := (others => '0');
294 signal AMCinfoDi : std_logic_vector(15 downto 0) := (others => '0');
295 signal EventInfoDi : std_logic_vector(31 downto 0) := (others => '0');
296 signal EventInfoDo : std_logic_vector(31 downto 0) := (others => '0');
297 signal EventInfo_a : std_logic_vector(3 downto 0) := (others => '1');
298 signal EventInfo_ovfl : std_logic_vector(1 downto 0) := (others => '1');
299 signal EventInfoToggleSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
300 signal EventInfo_full : std_logic := '0';
301 signal EventInfo_dav_i : std_logic := '0';
302 signal we_EventInfo : std_logic := '0';
303 signal end_of_block : std_logic := '0';
304 signal end_of_event : std_logic := '0';
305 signal EventInfoToggle : std_logic := '0';
306 signal EventInfoToggle_q : std_logic := '0';
307 signal re_EventInfo : std_logic := '0';
308 signal EventInfoRdDoneToggle : std_logic := '0';
309 signal EventInfoRdDoneToggleSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
310 signal we_RxCRC : std_logic := '0';
311 signal Init_RxCRC : std_logic := '0';
312 signal RxCRC : std_logic_vector(15 downto 0) := (others => '0');
313 signal L1Ainfo_we : std_logic_vector(0 downto 0) := (others => '0');
314 signal L1Ainfo_wa : std_logic_vector(9 downto 0) := (others => '0');
315 signal L1Ainfo_ra : std_logic_vector(9 downto 0) := (others => '0');
316 signal L1Ainfo_start : std_logic_vector(7 downto 0) := (others => '0');
317 signal L1AinfoDo : std_logic_vector(15 downto 0) := (others => '0');
318 signal L1Ainfo_wa2SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
319 signal L1Ainfo_wap : std_logic_vector(7 downto 0) := (others => '0');
320 signal ec_L1Ainfo_ra : std_logic := '0';
321 signal re_L1AinfoDo : std_logic := '0';
322 signal L1Ainfo_empty : std_logic := '0';
323 signal timer : std_logic_vector(N downto 0) := (others => '0');
324 signal ReSend : std_logic := '0';
325 signal ReSend_l : std_logic := '0';
326 signal ReSendQueIn : std_logic_vector(15 downto 0) := (others => '0');
327 signal ReSendQueOut : std_logic_vector(15 downto 0) := (others => '0');
328 signal we_ReSendQue : std_logic := '0';
329 signal ReSendQue_a : std_logic_vector(1 downto 0) := (others => '1');
330 signal ReSendQue_empty : std_logic := '0';
331 signal ReSendQue_full : std_logic := '0';
332 signal got_comma : std_logic := '0';
333 signal GotCntr : std_logic := '0';
334 signal L1Asent : std_logic := '0';
335 signal TxType : std_logic_vector(7 downto 0) := (others => '0');
336 signal packet_wc : std_logic_vector(1 downto 0) := (others => '0');
337 signal we_TxCRC : std_logic := '0';
338 signal Init_TxCRC : std_logic := '0';
339 signal TxCRC : std_logic_vector(15 downto 0) := (others => '0');
340 signal TxIsK : std_logic := '0';
341 signal Cntr_RdEn : std_logic := '0';
342 signal we_CntrBuf : std_logic := '0';
343 signal CntrBuf_Di : std_logic_vector(15 downto 0) := (others => '0');
344 signal CntrBuf_Do : std_logic_vector(15 downto 0) := (others => '0');
345 signal CntrBuf_wa : std_logic_vector(5 downto 0) := (others => '0');
346 signal CntrBuf_ra : std_logic_vector(5 downto 0) := (others => '0');
347 signal we_CntrBuf2p : std_logic := '0';
348 signal we_CntrBuf2 : std_logic := '0';
349 signal CntrBuf2_Di : std_logic_vector(15 downto 0) := (others => '0');
350 signal CntrBuf2_SPO : std_logic_vector(15 downto 0) := (others => '0');
351 signal CntrBuf2_SPO_q : std_logic_vector(15 downto 0) := (others => '0');
352 signal CntrBuf2_Do : std_logic_vector(15 downto 0) := (others => '0');
353 signal CntrBuf2_wa : std_logic_vector(5 downto 0) := (others => '0');
354 signal resetCntrCycle : std_logic := '0';
355 signal CntrBuf_valid : std_logic := '0';
356 signal cntrs : std_logic_vector(6 downto 0) := (others => '0');
357 signal sglErrCntr : std_logic_vector(6 downto 0) := (others => '0');
358 signal dblErrCntr : std_logic_vector(6 downto 0) := (others => '0');
359 signal BC0mmCntr : std_logic_vector(6 downto 0) := (others => '0');
360 signal BcntMmCntr : std_logic_vector(6 downto 0) := (others => '0');
361 signal ResendCntr : std_logic_vector(6 downto 0) := (others => '0');
362 signal AcceptCntr : std_logic_vector(6 downto 0) := (others => '0');
363 signal CntrAcceptCntr : std_logic_vector(6 downto 0) := (others => '0');
364 signal TotalWordCntr : std_logic_vector(15 downto 0) := (others => '0');
365 signal ACKcntr : std_logic_vector(6 downto 0) := (others => '0');
366 signal AbortCntr : std_logic_vector(6 downto 0) := (others => '0');
367 signal RxEventCntr : std_logic_vector(6 downto 0) := (others => '0');
368 signal RdEventCntr : std_logic_vector(6 downto 0) := (others => '0');
369 signal DataAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
370 signal CntrAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
371 signal BUSYCntr : std_logic_vector(6 downto 0) := (others => '0');
372 signal EvtEVNmmCntr : std_logic_vector(6 downto 0) := (others => '0');
373 signal EvtBCNmmCntr : std_logic_vector(6 downto 0) := (others => '0');
374 signal EvtOCNmmCntr : std_logic_vector(6 downto 0) := (others => '0');
375 signal ACKNUM_fullAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
376 signal EventInfo_fullAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
377 signal EventBuf_fullAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
378 signal SEQAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
379 signal CRCAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
380 signal frameAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
381 signal bad_KAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
382 signal bad_EventLengthCntr : std_logic_vector(6 downto 0) := (others => '0');
383 signal BlockCntr : std_logic_vector(6 downto 0) := (others => '0');
384 signal badCRCCntr : std_logic_vector(6 downto 0) := (others => '0');
385 signal TTSCntr : std_logic_vector(6 downto 0) := (others => '0');
386 signal TTCCntr : std_logic_vector(6 downto 0) := (others => '0');
387 signal TTS_ERRcntr : std_logic_vector(6 downto 0) := (others => '0');
388 signal TTS_DCcntr : std_logic_vector(6 downto 0) := (others => '0');
389 signal TTS_OOScntr : std_logic_vector(6 downto 0) := (others => '0');
390 signal TTS_BSYcntr : std_logic_vector(6 downto 0) := (others => '0');
391 signal TTS_OFWcntr : std_logic_vector(6 downto 0) := (others => '0');
392 signal WordCntr : std_logic_vector(15 downto 0) := (others => '0');
393 signal WordCntr_q : std_logic_vector(15 downto 0) := (others => '0');
394 signal AllZero : std_logic := '0';
395 signal zeroWordCntr : std_logic_vector(15 downto 0) := (others => '0');
396 signal Cntr_ra : std_logic_vector(8 downto 0) := (others => '0');
397 signal TTS_wa : std_logic_vector(1 downto 0) := (others =>'0');
398 signal TTS_wa0_SyncRegs : std_logic_vector(1 downto 0) := (others =>'0');
399 signal TTS_wa1_SyncRegs : std_logic_vector(1 downto 0) := (others =>'0');
400 signal TTS_InvalidCntr : std_logic_vector(15 downto 0) := (others =>'0');
401 signal TTS_UpdateCntr : std_logic_vector(15 downto 0) := (others =>'0');
402 signal RxNotInTableCntr : std_logic_vector(15 downto 0) := (others =>'0');
403 signal EofMissingCntr : std_logic_vector(15 downto 0) := (others =>'0');
404 signal WC11p : std_logic := '0';
405 signal WC11 : std_logic := '0';
406 signal RxNotInTableErr : std_logic := '0';
407 signal fake_CRC_q : std_logic := '0';
408 signal fake_CRC_q2 : std_logic := '0';
409 signal AMCCRC_q : std_logic_vector(15 downto 0) := (others => '0');
410 signal AMC_DATA_full : std_logic := '0';
411 signal AMC_DATA_WrEn : std_logic := '0';
412 signal AMC_DATA_Di : std_logic_vector(63 downto 0) := (others => '0');
413 signal WRERR : std_logic_vector(7 downto 0) := (others => '0');
414 signal RDERR : std_logic_vector(7 downto 0) := (others => '0');
415 signal RDCOUNT : array8x12;
416 signal WRCOUNT : array8x12;
417 signal block32K : std_logic := '0';
418 signal EventWC_carry : std_logic := '0';
419 signal LengthInHeader : std_logic_vector(19 downto 0) := (others => '0');
420 signal LengthInTrailer : std_logic_vector(19 downto 0) := (others => '0');
421 signal Ready_i : std_logic := '0';
422 signal TTS_wait : std_logic_vector(7 downto 0) := (others => '0');
423 signal TTS_DC_cntr : std_logic_vector(6 downto 0) := (others => '0');
424 signal TTS_SL_cntr : std_logic_vector(6 downto 0) := (others => '0');
425 signal TTS_ERR_cntr : std_logic_vector(6 downto 0) := (others => '0');
426 signal critical_TTS : std_logic_vector(1 downto 0) := (others =>'0');
427 signal critical_TTS_cntr : std_logic_vector(1 downto 0) := (others =>'0');
428 signal GotMismatch : std_logic := '0';
429 signal FirstMismatch : std_logic_vector(31 downto 0) := (others => '0');
430 begin
431 --debug_out(255 downto 83) <= (others => '0');
432 --debug_out(82) <= L1ASent;
433 --debug_out(81) <= AMC_DATA_WrEn;
434 --debug_out(80 downto 17) <= AMC_DATA_Di;
435 --debug_out(16) <= EventBuf_we(0);
436 --debug_out(15 downto 0) <= EventBuf_Di;
437 rxcommaalignen <= RxResetDoneSyncRegs(2);
438 TXDATA <= TXDATA_i;
439 EventInfo_dav <= EventInfo_dav_i;
440 AMC_OK <= AMCRdy;
441 Ready <= Ready_i;
442 TTC_status(0) <= BC0_lock when useTRIG else '0';
443 TTC_status(1) <= TTC_lock when useTRIG else '0';
444 --TTC_status(5 downto 2) <= TTC_FIFO_ra(3 downto 0);
445 --TTC_status(14 downto 6) <= TTC_FIFO_Di(8 downto 0);
446 --TTC_status(18 downto 15) <= TTC_FIFO_wa(3 downto 0);
447 --TTC_status(27 downto 19) <= TTC_FIFO_Do(8 downto 0);
448 --TTC_status(45 downto 28) <= HammingOut when HammingOutValid = '1' else (others => '0');
449 --TTC_status(49 downto 46) <= delta_BC0;
450 --TTC_status(53 downto 50) <= MmCntr;
451 --TTC_status(54) <= TTC_DataValid;
452 --TTC_status(78 downto 55) <= TTC_Data;
453 --TTC_status(79) <= TTC_FIFO_we;
454 --TTC_status(80) <= sgl_err;
455 --TTC_status(81) <= dbl_err;
456 --TTC_status(127 downto 82) <= (others => '0');
457 debug_out(0) <= EventInfoDi(21);
458 debug_out(6 downto 1) <= evn_OK;
459 debug_out(14 downto 7) <= evn;
460 debug_out(30 downto 15) <= RXDATA;
461 debug_out(32 downto 31) <= RXCHARISK;
462 debug_out(34 downto 33) <= RXCHARISCOMMA;
463 debug_out(35) <= check_packet;
464 debug_out(36) <= accept;
465 debug_out(37) <= eof;
466 debug_out(38) <= got_eof;
467 debug_out(39) <= get_evn;
468 debug_out(40) <= header2;
469 debug_out(41) <= end_of_event;
470 debug_out(42) <= end_of_block;
471 debug_out(43) <= we_EventInfo;
472 debug_out(44) <= TypeDATA;
473 debug_out(45) <= sel_TTC;
474 debug_out(46) <= Receiving;
475 debug_out(49 downto 47) <= evn_word;
476 debug_out(61 downto 50) <= RxWC;
477 debug_out(255 downto 62) <= (others => '0');
478 TTS_coded <= TTS_coded_i;
479 process(UsrClk)
480 variable c : std_logic_vector(3 downto 0);
481 variable s : std_logic_vector(3 downto 0);
482 begin
483  c(0) := RXDATA(8) xor RXDATA(9) xor RXDATA(11) xor RXDATA(12);
484  c(1) := RXDATA(8) xor RXDATA(10) xor RXDATA(11) xor RXDATA(13);
485  c(2) := RXDATA(9) xor RXDATA(10) xor RXDATA(11) xor RXDATA(14);
486  c(3) := not RXDATA(11) xor RXDATA(12) xor RXDATA(13) xor RXDATA(14) xor RXDATA(15);
487  s(0) := TTS_in(0) xor TTS_in(1) xor TTS_in(3);
488  s(1) := TTS_in(0) xor TTS_in(2) xor TTS_in(3);
489  s(2) := TTS_in(1) xor TTS_in(2) xor TTS_in(3);
490  s(3) := not TTS_in(0) xor TTS_in(1) xor TTS_in(2);
491  if(UsrClk'event and UsrClk = '1')then
492  if(AMC_en = '0' or TTS_disable = '1' or test = '1')then
493  TTS_coded_i <= "00000"; -- default is Ready
494  elsif(Ready_i = '0')then
495  TTS_coded_i <= "00010"; -- default is Busy
496  else
497  case TTS(3 downto 0) is
498  when x"0" | x"f" => TTS_coded_i(4 downto 0) <= "10000"; -- disconnected
499  when x"1" => TTS_coded_i <= "00001"; -- Overflow warning
500  when x"2" => TTS_coded_i <= "00100"; -- Out of Sync
501  when x"4" => TTS_coded_i <= "00010"; -- Busy
502  when x"c" => TTS_coded_i <= "01000"; -- error
503  when x"8" => TTS_coded_i <= "00000"; -- ready
504  when others => null;
505  end case;
506  end if;
507  if(not useTRIG and RXCHARISK = "01" and RXDATA(7 downto 0) = x"5c")then
508  is_TTS <= '1';
509  else
510  is_TTS <= '0';
511  end if;
512  if((c(0) = c(3)) and or_reduce(c(2 downto 0)) = '1')then
513  TTS_valid <= '0';
514  else
515  TTS_valid <= '1';
516  end if;
517  if(c = x"3")then
518  TTS_in(0) <= not RXDATA(8);
519  else
520  TTS_in(0) <= RXDATA(8);
521  end if;
522  if(c = x"5")then
523  TTS_in(1) <= not RXDATA(9);
524  else
525  TTS_in(1) <= RXDATA(9);
526  end if;
527  if(c = x"6")then
528  TTS_in(2) <= not RXDATA(10);
529  else
530  TTS_in(2) <= RXDATA(10);
531  end if;
532  if(c = x"7")then
533  TTS_in(3) <= not RXDATA(11);
534  else
535  TTS_in(3) <= RXDATA(11);
536  end if;
537  if(is_TTS = '1' and TTS_valid = '1')then
538  case TTS_in is
539  when x"0" | x"2" | x"c" | x"f" => critical_TTS(0) <= '1';
540  when others => critical_TTS(0) <= '0';
541  end case;
542  else
543  critical_TTS(0) <= '0';
544  end if;
545  if(InitLink = '1' or Ready_i = '0')then
546  critical_TTS_cntr <= "00";
547  elsif(update_TTS = '1')then
548  if(critical_TTS = "00")then
549  critical_TTS_cntr <= "00";
550  else
551  critical_TTS_cntr <= critical_TTS_cntr + 1;
552  end if;
553  end if;
554  if(HammingOutValid = '1')then
555  case HammingOut(11 downto 8) is
556  when x"0" | x"2" | x"c" | x"f" => critical_TTS(1) <= '1';
557  when others => critical_TTS(1) <= '0';
558  end case;
559  else
560  critical_TTS(1) <= '0';
561  end if;
562  if((is_TTS = '1' and TTS_valid = '1') or HammingOutValid = '1')then
563  update_TTS <= '1';
564  else
565  update_TTS <= '0';
566  end if;
567  if(InitLink = '1' or Ready_i = '0')then
568  TTS <= x"52";
569  elsif(update_TTS = '1' and (critical_TTS = "00" or critical_TTS_cntr = "11"))then
570  TTS <= TTS_tmp;
571  end if;
572  if(is_TTS = '1' and TTS_valid = '1')then
573  TTS_tmp <= s & TTS_in;
574  elsif(HammingOutValid = '1')then
575  TTS_tmp(3 downto 0) <= HammingOut(11 downto 8);
576  end if;
577  end if;
578 end process;
579 process(UsrClk,BC0_lock)
580 begin
581  if(BC0_lock = '0')then
582  BcntMmCntr <= (others => '0');
583  elsif(UsrClk'event and UsrClk = '1')then
584  if(resetCntr = '1')then
585  BcntMmCntr <= (others => '0');
586  elsif(BcntMm = '1')then
587  BcntMmCntr <= BcntMmCntr + 1;
588  end if;
589  end if;
590 end process;
591 AMC_IDp1 <= AMC_ID + 1;
592 AMC_IDp4(3) <= AMC_ID(3) or AMC_ID(2);
593 AMC_IDp4(2) <= not AMC_ID(2);
594 AMC_IDp4(1 downto 0) <= AMC_ID(1 downto 0);
595 process(UsrClk)
596 begin
597  if(UsrClk'event and UsrClk = '1')then
598  if(resetCntr = '1')then
599  BC0mmCntr <= (others => '0');
600  elsif(HammingOutValid = '1' and HammingOut(17) /= HammingOut(16))then
601  BC0mmCntr <= BC0mmCntr + 1;
602  end if;
603  if(AMC_en = '0')then
604  Cntr_RdEn <= '0';
605  elsif(Cntr_ADDR(11 downto 8) = AMC_ID or (Cntr_ADDR(11 downto 10) = "11" and Cntr_ADDR(8 downto 5) = AMC_IDp4))then
606  Cntr_RdEn <= '1';
607  else
608  Cntr_RdEn <= '0';
609  end if;
610  if(Cntr_ADDR(11 downto 8) /= AMC_ID and (Cntr_ADDR(11 downto 10) /= "11" or Cntr_ADDR(8 downto 5) /= AMC_IDp4))then
611  Cntr_ra <= (others => '0');
612  elsif(Cntr_ADDR(11 downto 10) = "11")then
613  Cntr_ra <= '1' & Cntr_ADDR(9) & "11" & Cntr_ADDR(4 downto 0);
614  else
615  Cntr_ra <= '0' & Cntr_ADDR(7 downto 2) & "00";
616  end if;
617  if(Cntr_RdEn = '0')then
618  Cntr_DATA <= (others => '0');
619  elsif(Cntr_ra(8 downto 7) = "00")then
620  if(CntrBuf_valid = '1')then
621  Cntr_DATA <= CntrBuf_Do;
622  else
623  Cntr_DATA <= (others => '0');
624  end if;
625  elsif(Cntr_ra(8 downto 2) = "0100000")then
626  Cntr_DATA <= TotalWordCntr;
627  elsif(Cntr_ra(8 downto 7) = "10")then
628  case Cntr_ra(4 downto 0) is
629  when "00000" => Cntr_DATA <= "000" & EventBuf_wa;
630  when "00001" => Cntr_DATA <= "000" & EventBuf_ra & "00";
631  when "00010" => Cntr_DATA <= "000000" & L1Ainfo_wa;
632  when "00011" => Cntr_DATA <= "000000" & L1Ainfo_ra;
633  when "00100" => Cntr_DATA <= x"00" & L1Ainfo_wap;
634  when "00101" => Cntr_DATA <= ReSendQue_a & rfifo_a & ACKNUM_a & reset_SyncRegs(3) & AMCRdy & txfsmresetdone & RxResetDone & qpll_lock & InitLink & TxState;
635  when "00110" => Cntr_DATA <= EventInfo_a & "00000" & AMCRdy & EventInfo_ovfl & TTC_lock & BC0_lock & EventInfoRdDoneToggle & EventInfoToggle;
636  when "01000" => Cntr_DATA <= EventWC(15 downto 0);
637  when "01001" => Cntr_DATA <= block32K & AMC_DATA_full & "0000000000" & EventWC(19 downto 16);
638  when "01010" => Cntr_DATA <= WordCntr_q;
639  when "01011" => Cntr_DATA <= zeroWordCntr;
640  when "01100" => Cntr_DATA <= "000" & EventBuf_start;
641  when "01101" => Cntr_DATA <= "000" & EventBuf_wc & "00";
642  when "01110" => Cntr_DATA <= x"000" & TTS_tmp(3 downto 0);
643  when "10000" => Cntr_DATA <= x"00" & LinkVersion;
644  when "10001" => Cntr_DATA <= x"00" & CTRversion;
645  when "10010" => Cntr_DATA <= FirstMismatch(15 downto 0);
646  when "10011" => Cntr_DATA <= FirstMismatch(31 downto 16);
647  when "10100" => Cntr_DATA <= x"00" & WRERR;
648  when "10110" => Cntr_DATA <= x"00" & RDERR;
649  when "11000" => Cntr_DATA <= TTS_InvalidCntr;
650  when "11001" => Cntr_DATA <= TTS_UpdateCntr;
651  when "11010" => Cntr_DATA <= RxNotInTableCntr;
652  when "11011" => Cntr_DATA <= EofMissingCntr;
653  when others => Cntr_DATA <= x"0000";
654  end case;
655  else
656  Cntr_DATA <= CntrBuf2_Do;
657  end if;
658  if(resetCntr = '1')then
659  sglErrCntr <= (others => '0');
660  elsif(sgl_err = '1')then
661  sglErrCntr <= sglErrCntr + 1;
662  end if;
663  if(resetCntr = '1')then
664  dblErrCntr <= (others => '0');
665  elsif(dbl_err = '1')then
666  dblErrCntr <= dblErrCntr + 1;
667  end if;
668  if(resetCntr = '1')then
669  ResendCntr <= (others => '0');
670  elsif(Resend = '1')then
671  ResendCntr <= ResendCntr + 1;
672  end if;
673  if(resetCntr = '1')then
674  AcceptCntr <= (others => '0');
675  elsif(accept = '1')then
676  AcceptCntr <= AcceptCntr + 1;
677  end if;
678  if(resetCntr = '1')then
679  CntrAcceptCntr <= (others => '0');
680  elsif(CntrAccept = '1')then
681  CntrAcceptCntr <= CntrAcceptCntr + 1;
682  end if;
683  if(resetCntr = '1')then
684  ACKcntr <= (others => '0');
685  elsif(ACK = '1')then
686  ACKcntr <= ACKcntr + 1;
687  end if;
688  if(resetCntr = '1')then
689  TotalWordcntr <= (others => '0');
690  elsif(accept = '1')then
691  if(EventWC_carry = '1')then
692  TotalWordcntr <= TotalWordcntr + x"0200";
693  else
694  TotalWordcntr <= TotalWordcntr + EventWC(8 downto 0);
695  end if;
696  end if;
697  if(resetCntr = '1')then
698  RxEventCntr <= (others => '0');
699  elsif(end_of_event = '1')then
700  RxEventCntr <= RxEventCntr + 1;
701  end if;
702  if(resetCntr = '1')then
703  RdEventCntr <= (others => '0');
704  elsif(re_EventInfo = '1' and EventInfoDo(25) = '0')then
705  RdEventCntr <= RdEventCntr + 1;
706  end if;
707  TypeData_q <= TypeData;
708  if(resetCntr = '1')then
709  DataAbortCntr <= (others => '0');
710  elsif(Abort = '1')then
711  DataAbortCntr <= DataAbortCntr + 1;
712  end if;
713  if(resetCntr = '1')then
714  CntrAbortCntr <= (others => '0');
715  elsif(CntrAbort = '1')then
716  CntrAbortCntr <= CntrAbortCntr + 1;
717  end if;
718  if(resetCntr = '1')then
719  ACKNUM_fullAbortCntr <= (others => '0');
720  elsif(Abort = '1' and ACKNUM_full = '1')then
721  ACKNUM_fullAbortCntr <= ACKNUM_fullAbortCntr + 1;
722  end if;
723  if(resetCntr = '1')then
724  EventInfo_fullAbortCntr <= (others => '0');
725  elsif(Abort = '1' and EventInfo_full = '1')then
726  EventInfo_fullAbortCntr <= EventInfo_fullAbortCntr + 1;
727  end if;
728  if(resetCntr = '1')then
729  EventBuf_fullAbortCntr <= (others => '0');
730  elsif(Abort = '1' and EventBuf_full = '1')then
731  EventBuf_fullAbortCntr <= EventBuf_fullAbortCntr + 1;
732  end if;
733  if(resetCntr = '1')then
734  SEQAbortCntr <= (others => '0');
735  elsif((Abort = '1' or CntrAbort = '1') and SEQ_OK = '0')then
736  SEQAbortCntr <= SEQAbortCntr + 1;
737  end if;
738  if(resetCntr = '1')then
739  CRCAbortCntr <= (others => '0');
740  elsif((Abort = '1' or CntrAbort = '1') and CRC_OK = '0')then
741  CRCAbortCntr <= CRCAbortCntr + 1;
742  end if;
743  if(resetCntr = '1')then
744  frameAbortCntr <= (others => '0');
745  elsif((Abort = '1' or CntrAbort = '1') and frame_OK = '0')then
746  frameAbortCntr <= frameAbortCntr + 1;
747  end if;
748  if(resetCntr = '1')then
749  bad_KAbortCntr <= (others => '0');
750  elsif((Abort = '1' or CntrAbort = '1') and bad_K = '1')then
751  bad_KAbortCntr <= bad_KAbortCntr + 1;
752  end if;
753  if(resetCntr = '1')then
754  BlockCntr <= (others => '0');
755  elsif(we_EventInfo = '1')then
756  BlockCntr <= BlockCntr + 1;
757  end if;
758  if(resetCntr = '1')then
759  badCRCCntr <= (others => '0');
760  elsif(end_of_event = '1' and bad_AMCCRC = '1' and test = '0' and AMC_en = '1')then
761  badCRCCntr <= badCRCCntr + 1;
762  end if;
763  if(resetCntr = '1')then
764  TTSCntr <= (others => '0');
765  elsif(is_TTS = '1')then
766  TTSCntr <= TTSCntr + 1;
767  end if;
768  if(resetCntr = '1')then
769  TTS_DCcntr <= (others => '0');
770  TTS_ERRcntr <= (others => '0');
771  TTS_OOScntr <= (others => '0');
772  TTS_BSYcntr <= (others => '0');
773  TTS_OFWcntr <= (others => '0');
774  elsif(Ready_i = '1')then
775  if(TTS_coded_i(4) = '1')then
776  TTS_DCcntr <= TTS_DCcntr + 1;
777  end if;
778  if(TTS_coded_i(3) = '1')then
779  TTS_ERRcntr <= TTS_ERRcntr + 1;
780  end if;
781  if(TTS_coded_i(2) = '1')then
782  TTS_OOScntr <= TTS_OOScntr + 1;
783  end if;
784  if(TTS_coded_i(1) = '1')then
785  TTS_BSYcntr <= TTS_BSYcntr + 1;
786  end if;
787  if(TTS_coded_i(0) = '1')then
788  TTS_OFWcntr <= TTS_OFWcntr + 1;
789  end if;
790  end if;
791  if(resetCntr = '1')then
792  TTCCntr <= (others => '0');
793  elsif(TTC_DataValid = '1')then
794  TTCCntr <= TTCCntr + 1;
795  end if;
796  if(resetCntr = '1')then
797  bad_EventLengthCntr <= (others => '0');
798  elsif(end_of_event = '1' and bad_EventLength = '1')then
799  bad_EventLengthCntr <= bad_EventLengthCntr + 1;
800  end if;
801  if(resetCntr = '1' or test = '1' or AMC_en = '0')then
802  EvtEVNmmCntr <= (others => '0');
803  elsif(end_of_event = '1' and RxType(0) = '0')then
804  EvtEVNmmCntr <= EvtEVNmmCntr + 1;
805  end if;
806  if(resetCntr = '1' or test = '1' or AMC_en = '0')then
807  EvtBCNmmCntr <= (others => '0');
808  elsif(end_of_event = '1' and RxType(2) = '0')then
809  EvtBCNmmCntr <= EvtBCNmmCntr + 1;
810  end if;
811  if(resetCntr = '1' or test = '1' or AMC_en = '0')then
812  EvtOCNmmCntr <= (others => '0');
813  elsif(end_of_event = '1' and RxType(1) = '0')then
814  EvtOCNmmCntr <= EvtOCNmmCntr + 1;
815  end if;
816  if(reset = '1' or test = '1' or AMC_en = '0')then
817  FirstMismatch <= (others => '0');
818  GotMismatch <= '0';
819  elsif(end_of_event = '1' and GotMismatch = '0')then
820  FirstMismatch(31 downto 28) <= TTS(3 downto 0);
821  FirstMismatch(27 downto 25) <= RxType(2 downto 0);
822  FirstMismatch(24 downto 0) <= FirstMismatch(24 downto 0) + 1;
823  if(RxType(2 downto 0) /= "000")then
824  GotMismatch <= '1';
825  end if;
826  end if;
827  if(resetCntr = '1' or InitLink = '1')then
828  TTS_InvalidCntr <= (others => '0');
829  elsif(is_TTS = '1' and TTS_valid = '0')then
830  TTS_InvalidCntr <= TTS_InvalidCntr + 1;
831  end if;
832  if(resetCntr = '1' or InitLink = '1')then
833  TTS_UpdateCntr <= (others => '0');
834  elsif(update_TTS = '1')then
835  TTS_UpdateCntr <= TTS_UpdateCntr + 1;
836  end if;
837  if(Receiving = '1' and RxNotInTable /= "00")then
838  RxNotInTableErr <= '1';
839  else
840  RxNotInTableErr <= '0';
841  end if;
842  if(resetCntr = '1' or InitLink = '1')then
843  RxNotInTableCntr <= (others => '0');
844  elsif(RxNotInTableErr = '1')then
845  RxNotInTableCntr <= RxNotInTableCntr + 1;
846  end if;
847  if(resetCntr = '1' or InitLink = '1')then
848  EofMissingCntr <= (others => '0');
849  elsif(check_packet = '1' and eof = '0' and WC11 = '0')then
850  EofMissingCntr <= EofMissingCntr + 1;
851  end if;
852  if(resetCntr = '1' or Ready_i = '0')then
853  TTS_SL_cntr <= (others => '0');
854  elsif(update_TTS = '1' and TTS_tmp(3 downto 0) = x"2")then
855  TTS_SL_cntr <= TTS_SL_cntr + 1;
856  end if;
857  if(resetCntr = '1' or Ready_i = '0')then
858  TTS_DC_cntr <= (others => '0');
859  elsif(update_TTS = '1' and (TTS_tmp(3 downto 0) = x"0" or TTS_tmp(3 downto 0) = x"f"))then
860  TTS_DC_cntr <= TTS_DC_cntr + 1;
861  end if;
862  if(resetCntr = '1' or Ready_i = '0')then
863  TTS_ERR_cntr <= (others => '0');
864  elsif(update_TTS = '1' and TTS_tmp(3 downto 0) = x"c")then
865  TTS_ERR_cntr <= TTS_ERR_cntr + 1;
866  end if;
867  end if;
868 end process;
869 process(UsrClk)
870 begin
871  if(UsrClk'event and UsrClk = '1')then
872  if(not useTRIG or RXCHARISK = "00")then
873  sel_TTC <= '0';
874  elsif(RXCHARISK = "01" and RXDATA(7 downto 0) = x"bc")then
875  sel_TTC <= '1';
876  end if;
877  if(RXCHARISK(1) = '0')then
878  TTC_Data(23 downto 8) <= RXDATA;
879  TTC_Data(7 downto 0) <= TTC_Data(23 downto 16);
880  end if;
881  if(sel_TTC = '1' and RXCHARISK = "00" and AMCRdy = '1')then
882  TTC_DataValid <= '1';
883  else
884  TTC_DataValid <= '0';
885  end if;
886  end if;
887 end process;
888 i_TTC_trigger: TTC_trigger generic map(simulation => simulation) PORT MAP(
889  reset => reset,
890  UsrClk => UsrClk,
891  TTCclk => TTCclk,
892  HammingData_in => HammingOut,
893  HammingDataValid => HammingOutValid,
894  BC0 => BC0,
895  BcntMm => BcntMm,
896  TTC_lock => TTC_lock,
897  BC0_lock => BC0_lock,
898  TrigData => TrigData
899  );
900 i_HammingDecode: HammingDecode PORT MAP(
901  clk => UsrClk ,
902  din_valid => TTC_DataValid,
903  din => TTC_Data ,
904  dout_valid => HammingOutValid ,
905  dout => HammingOut ,
906  sgl_err => sgl_err,
907  dbl_err => dbl_err
908  );
909 process(UsrClk,RxResetDone)
910 begin
911  if(RxResetDone = '0')then
912  RxResetDoneSyncRegs <= (others => '0');
913  AMCRdy <= '0';
914  elsif(UsrClk'event and UsrClk = '1')then
915  RxResetDoneSyncRegs <= RxResetDoneSyncRegs(1 downto 0) & '1';
916  if(txfsmresetdone = '1')then
917  AMCRdy <= '1';
918  end if;
919  end if;
920 end process;
921 process(UsrClk,reset,RxResetDone,txfsmresetdone,qpll_lock)
922 begin
923  if(reset = '1' or RxResetDone = '0' or txfsmresetdone = '0' or qpll_lock = '0')then
924  reset_SyncRegs <= (others => '1');
925  EventInfoToggle <= '0';
926  EventInfoToggle_q <= '0';
927  elsif(UsrClk'event and UsrClk = '1')then
928  reset_SyncRegs <= reset_SyncRegs(2 downto 0) & '0';
929  if((we_EventInfo = '1' and EventInfo_a = x"f") or (re_EventInfo = '1' and (EventInfo_a /= x"0" or we_EventInfo = '1')))then
930  EventInfoToggle <= not EventInfoToggle;
931  end if;
932  EventInfoToggle_q <= EventInfoToggle;
933  end if;
934 end process;
935 process(UsrClk)
936 begin
937  if(UsrClk'event and UsrClk = '1')then
938  if(AMC_en = '0')then
939  EventInfo <= (others => '0');
940  else
941  EventInfo <= EventInfoDo;
942  end if;
943  if(RxResetDoneSyncRegs(2) = '0' or or_reduce(RxNotInTable) = '1' or bad_K = '1')then
944  DATA_VALID <= '0';
945  elsif(RXCHARISK(0) = '1' and RXDATA(7 downto 0) = x"bc")then
946  DATA_VALID <= '1';
947  end if;
948  if(InitLink = '1' or AMC_en = '0')then
949  Ready_i <= '0';
950  elsif((is_TTS = '1' and TTS_valid = '1') or HammingOutValid = '1' or test = '1')then
951  Ready_i <= '1';
952  end if;
953  if(InitLink = '1' or Ready_i = '1' or TTS_wait(7) = '1')then
954  TTS_wait <= x"00";
955  else
956  TTS_wait <= TTS_wait + 1;
957  end if;
958  end if;
959 end process;
960 ReSend <= timer(N);
961 process(UsrClk)
962 begin
963  if(UsrClk'event and UsrClk = '1')then
964  if(timer(N) = '1' or ACK = '1' or (ReSendQue_empty = '1' and (got_comma = '0' or InitLink = '0')))then
965  timer <= (others => '0');
966  else
967  timer <= timer + 1;
968  end if;
969  if(ReSend = '1')then
970  ReSend_l <= '1';
971  elsif(TxState = SendSEQ)then
972  ReSend_l <= '0';
973  end if;
974 -- Comma ends a packet and after that, any D-word marks the beginning of a packet
975  if((RXCHARISCOMMA = "11" and RXDATA /= R_word) or test = '1' or AMCRdy = '0')then
976  Receiving <= '0';
977  elsif(sel_TTC = '0' and RXCHARISK = "00")then
978  Receiving <= '1';
979  end if;
980  if(sel_TTC = '0')then
981  if(RxNotInTable /= "00")then
982  bad_K <= '1';
983  elsif(RXCHARISK = "00")then
984  RXDATA_q <= RXDATA;
985  if(Receiving = '0')then
986  bad_K <= '0';
987  RxSEQNUM <= RXDATA(15 downto 8);
988  if(RXDATA(7 downto 0) = InitRqst and InitLink = '1')then
989  TypeInit <= '1';
990  else
991  TypeInit <= '0';
992  end if;
993  if(RXDATA(7 downto 0) = Acknowledge)then
994  TypeACK <= '1';
995  else
996  TypeACK <= '0';
997  end if;
998  if(RXDATA(7 downto 0) = data)then
999  TypeData <= '1';
1000  else
1001  TypeData <= '0';
1002  end if;
1003  if(RXDATA(7 downto 0) = Counter)then
1004  TypeCntr <= '1';
1005  else
1006  TypeCntr <= '0';
1007  end if;
1008  Header2 <= '1';
1009  else
1010  Header2 <= '0';
1011  evn_word <= evn_word(1 downto 0) & Header2;
1012  if(evn_word(2) = '1' and get_evn = '1' and TypeData = '1')then
1013  evn <= RxData(7 downto 0);
1014  end if;
1015  if(Header2 = '1')then
1016  RxWC <= (others => '0');
1017  RxType <= RXDATA;
1018  else
1019  RxWC <= RxWC + 1;
1020  end if;
1021  if(RxWC(11 downto 2) = RxData(11 downto 2) and RxWC(1 downto 0) = "00")then
1022  WC_OKp <= '1';
1023  else
1024  WC_OKp <= '0';
1025  end if;
1026  WC_OK <= WC_OKp;
1027  WC11p <= RxData(11);
1028  WC11 <= WC11p;
1029  if(evn = RxData(15 downto 8))then
1030  evn_OK(0) <= '1';
1031  else
1032  evn_OK(0) <= '0';
1033  end if;
1034  evn_OK(4 downto 1) <= evn_OK(3 downto 0);
1035  end if;
1036  elsif(RXCHARISK = "10" or (RXCHARISK = "11" and RXDATA /= R_word and RXDATA /= eof_word and RXCHARISCOMMA /= "11") or (RXCHARISK = "01" and RXDATA(7 downto 0) /= x"5c" and RXDATA(7 downto 0) /= x"bc"))then
1037  bad_K <= '1';
1038  end if;
1039  end if;
1040  if((TypeACK = '1' or TypeInit = '1') and RXType(15 downto 8) = ReSendQueOut(15 downto 8) and ReSendQue_empty = '0' and ReSend = '0')then -- incoming acknowledge number is what waited for
1041  ACK_OK <= '1';
1042  else
1043  ACK_OK <= '0';
1044  end if;
1045  if(Receiving = '0')then
1046  ACKNUM_IN <= RxSEQNUM;
1047  end if;
1048  if(RxSEQNUM = NextSEQNUM)then -- incoming sequence number is what waited for
1049  SEQ_OK <= '1';
1050  else
1051  SEQ_OK <= '0';
1052  end if;
1053  if(or_reduce(RxCRC) = '0')then
1054  CRC_OK <= '1';
1055  else
1056  CRC_OK <= '0';
1057  end if;
1058  if(WC_OK = '1' and (((TypeData = '1' or TypeCntr = '1' or TypeACK = '1') and InitLink = '0') or (TypeInit = '1' and InitLink = '1')))then
1059  frame_OK <= '1';
1060  else
1061  frame_OK <= '0';
1062  end if;
1063  if(RXCHARISCOMMA = "11" and RXDATA /= R_word and Receiving = '1')then
1064  check_packet <= '1';
1065  else
1066  check_packet <= '0';
1067  end if;
1068  accept <= check_packet and SEQ_OK and CRC_OK and frame_OK and not EventInfo_full and not EventBuf_ovf and not bad_K and not ACKNUM_full and (eof or WC11) and TypeData;
1069  CntrAccept <= check_packet and SEQ_OK and CRC_OK and frame_OK and not bad_K and TypeCntr;
1070  we_ACKNUM <= check_packet and CRC_OK and frame_OK and not bad_K and not ACKNUM_full and not EventInfo_full and not EventBuf_ovf and (eof or WC11) and TypeData;
1071  ACK <= check_packet and ACK_OK and CRC_OK and frame_OK and not bad_K;
1072 -- Abort <= check_packet and (TypeData or TypeCntr) and not(SEQ_OK and CRC_OK and frame_OK and not bad_K and not((ACKNUM_full or EventInfo_full or EventBuf_ovf) and TypeData));
1073 -- Abort <= check_packet and (TypeData or TypeCntr) and not(SEQ_OK and CRC_OK and frame_OK and not bad_K and
1074 -- not((ACKNUM_full or EventInfo_full or EventBuf_ovf or (not eof and not WC11)) and TypeData));
1075  Abort <= check_packet and TypeData and not(SEQ_OK and CRC_OK and frame_OK and not bad_K and not ACKNUM_full and not EventInfo_full and not EventBuf_ovf and (eof or WC11));
1076  CntrAbort <= check_packet and TypeCntr and not(SEQ_OK and CRC_OK and frame_OK and not bad_K);
1077  if(InitLink = '1')then
1078  get_evn <= '1';
1079  elsif(accept = '1')then
1080  get_evn <= got_eof;
1081  end if;
1082  if(test = '1')then
1083  EventInfoDi(30 downto 27) <= fake_evn;
1084  elsif(accept = '1')then
1085  EventInfoDi(30 downto 27) <= evn(3 downto 0);
1086  end if;
1087  if(TxState = SendCRC and TxType = Counter)then
1088  GotCntr <= '0';
1089  elsif(CntrAccept = '1')then
1090  GotCntr <= '1';
1091  end if;
1092  if(InitLink = '1')then
1093  CntrACKNUM <= x"00";
1094  elsif(CntrAccept = '1')then
1095  CntrACKNUM <= RxSEQNUM;
1096  end if;
1097  if(reset_SyncRegs(3) = '1')then
1098  ACKNUM_a <= (others => '1');
1099  elsif(we_ACKNUM = '1' and (TxState /= SendCRC or SendTTS = '1' or IsACK = '0'))then
1100  ACKNUM_a <= ACKNUM_a + 1;
1101  elsif(we_ACKNUM = '0' and TxState = SendCRC and IsACK = '1' and SendTTS = '0')then
1102  ACKNUM_a <= ACKNUM_a - 1;
1103  end if;
1104  if(ACKNUM_a = "11")then
1105  ACKNUM_empty <= '1';
1106  else
1107  ACKNUM_empty <= '0';
1108  end if;
1109  if(ACKNUM_a = "10")then
1110  ACKNUM_full <= '1';
1111  else
1112  ACKNUM_full <= '0';
1113  end if;
1114  if(InitLink = '1')then
1115  ACKNUM_l <= x"00";
1116  elsif(ACKNUM_a /= "11")then
1117  ACKNUM_l <= ACKNUM;
1118  end if;
1119  if(reset_SyncRegs(3) = '1')then
1120  NextSEQNUM <= x"00";
1121  elsif(accept = '1')then
1122  NextSEQNUM <= NextSEQNUM(6 downto 0) & not(NextSEQNUM(7) xor NextSEQNUM(5) xor NextSEQNUM(4) xor NextSEQNUM(3));
1123  end if;
1124 -- Receiving of eof K-word in a packet marks the end of the event
1125 -- if(Receiving = '0' or InitLink = '1')then
1126  if(check_packet = '1' or InitLink = '1')then
1127  eof <= '0';
1128  elsif(RXCHARISK = "11" and RXDATA = eof_word)then
1129  eof <= '1';
1130  end if;
1131 -- latches eof signal
1132  if(check_packet = '1')then
1133  got_eof <= eof;
1134  end if;
1135 -- if buffer is getting full during packet receiving, buffer overflow error is set
1136  if(Receiving = '0')then
1137  EventBuf_ovf <= '0';
1138  elsif(EventBuf_full = '1')then
1139  EventBuf_ovf <= '1';
1140  end if;
1141  Receiving_q <= Receiving;
1142  if(InitLink = '1')then
1143  EventBuf_wa <= (others => '0');
1144  elsif(abort = '1')then
1145  EventBuf_wa <= EventBuf_start;
1146  elsif(EventBuf_we(0) = '1')then
1147  EventBuf_wa <= EventBuf_wa + 1;
1148  end if;
1149  if(InitLink = '1')then
1150  EventBuf_ra <= (others => '0');
1151  elsif(ec_EventBuf_ra = '1')then
1152  EventBuf_ra <= EventBuf_ra + 1;
1153  end if;
1154 -- packet starting write address is recorded before the first data is written to the buffer
1155  if(InitLink = '1')then
1156  EventBuf_start <= (others => '0');
1157  elsif(save_start_addr = '1')then
1158  EventBuf_start <= EventBuf_wa;
1159  end if;
1160 -- accepted data in EventBuf available for read out
1161  if(InitLink = '1')then
1162  EventBuf_wc <= (others => '0');
1163  elsif(ec_EventBuf_ra = '1')then
1164  EventBuf_wc <= EventBuf_wc - 1;
1165  else
1166  EventBuf_wc <= EventBuf_start(12 downto 2) - EventBuf_ra;
1167  end if;
1168  EventBuf_space <= EventBuf_wa(12 downto 2) - EventBuf_ra;
1169 -- buffer almost full
1170  if(and_reduce(EventBuf_space(10 downto 5)) = '1')then
1171  EventBuf_full <= '1';
1172  else
1173  EventBuf_full <= '0';
1174  end if;
1175  fake_full <= EventBuf_full or EventInfo_full;
1176  end if;
1177 end process;
1178 i_RxCRC: crc16D16 PORT MAP(
1179  clk => UsrClk ,
1180  init_crc => Init_RxCRC,
1181  we_crc => we_RxCRC,
1182  d => RXDATA ,
1183  crc => RxCRC
1184  );
1185 we_RxCRC <= '1' when RXCHARISK = "00" and sel_TTC = '0' else '0';
1186 Init_RxCRC <= '1' when RXCHARISCOMMA = "11" else '0';
1187 i_AMCCRC: EthernetCRCD16B PORT MAP(
1188  clk => UsrClk ,
1189  init => InitAMCCRC ,
1190  save => accept ,
1191  restore => abort,
1192  ce => EventBuf_we (0),
1193  d => EventBuf_Di,
1194  crc => AMCCRC ,
1195  bad_crc => bad_AMCCRC
1196  );
1197 process(UsrClk)
1198 begin
1199  if(UsrClk'event and UsrClk = '1')then
1200  if(InitLink = '1' or end_of_event = '1')then
1201  InitAMCCRC <= '1';
1202  else
1203  InitAMCCRC <= '0';
1204  end if;
1205  end if;
1206 end process;
1207 g_ACKNUM : for i in 0 to 7 generate
1208  i_ACKNUM : SRL16E
1209  port map (
1210  Q => ACKNUM(i), -- SRL data output
1211  A0 => ACKNUM_a(0), -- Select[0] input
1212  A1 => ACKNUM_a(1), -- Select[1] input
1213  A2 => '0', -- Select[2] input
1214  A3 => '0', -- Select[3] input
1215  CE => we_ACKNUM, -- Clock enable input
1216  CLK => UsrClk, -- Clock input
1217  D => ACKNUM_IN(i) -- SRL data input
1218  );
1219 end generate;
1220 -- this fifo is used to hold the last couple of received data words before writing to the data buffer.
1221 -- this is because 1. word count and CRC of the packet should not be written to the buffer and more importantly,
1222 -- if the packet is the last packet of the event, the last data word must be properly marked with the LinkCtrl
1223 -- before being written to the buffer. 3. next packet data may arrive before a decision being made to accept or reject a packet.
1224 g_rfifo: for i in 0 to 15 generate
1225  i_rfifo : SRL16E
1226  port map (
1227  Q => rfifo(i), -- SRL data output
1228  A0 => '1', -- Select[0] input
1229  A1 => '0', -- Select[1] input
1230  A2 => '0', -- Select[2] input
1231  A3 => '0', -- Select[3] input
1232  CE => we_rfifo, -- Clock enable input
1233  CLK => UsrClk, -- Clock input
1234  D => RXDATA_q(i) -- SRL data input
1235  );
1236 end generate;
1237 process(UsrClk)
1238 begin
1239  if(UsrClk'event and UsrClk = '1')then
1240  if(sel_TTC = '0' and RXCHARISK = "00")then
1241  we_rfifo <= '1';
1242  else
1243  we_rfifo <= '0';
1244  end if;
1245  if(InitLink = '1' or check_packet = '1')then
1246  dl_cntr <= "000";
1247  elsif(we_rfifo = '1')then
1248  dl_cntr(2) <= dl_cntr(2) or (dl_cntr(1) and dl_cntr(0));
1249  dl_cntr(1) <= dl_cntr(1) xor dl_cntr(0);
1250  dl_cntr(0) <= not dl_cntr(2) and not dl_cntr(0);
1251  end if;
1252  end if;
1253 end process;
1254 g_EventBuffer : for i in 0 to 3 generate
1255  i_EventBuffer : BRAM_SDP_MACRO
1256  generic map (
1257  BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
1258  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1259  WRITE_WIDTH => 4, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1260  READ_WIDTH => 16, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1261  DO_REG => 1, -- Optional output register (0 or 1)
1262  SIM_COLLISION_CHECK => "NONE") -- Collision check enable "ALL", "WARNING_ONLY",
1263  -- "GENERATE_X_ONLY" or "NONE"
1264  port map (
1265  DO => EventBuf_Do(i*16+15 downto i*16), -- Output read data port, width defined by READ_WIDTH parameter
1266  DI => EventBuf_Di(i*4+3 downto i*4), -- Input write data port, width defined by WRITE_WIDTH parameter
1267  RDADDR => EventBuf_ra, -- Input read address, width defined by read port depth
1268  RDCLK => UsrClk, -- 1-bit input read clock
1269  RDEN => '1', -- 1-bit input read port enable
1270  REGCE => '1', -- 1-bit input read output register enable
1271  RST => '0', -- 1-bit input reset
1272  WE => "1", -- Input write enable, width defined by write port depth
1273  WRADDR => EventBuf_wa, -- Input write address, width defined by write port depth
1274  WRCLK => UsrClk, -- 1-bit input write clock
1275  WREN => EventBuf_we(0) -- 1-bit input write port enable
1276  );
1277 end generate;
1278 g_MC_DATA_Di : for i in 0 to 3 generate
1279  g_AMC_DATA_Dij: for j in 0 to 3 generate
1280  AMC_DATA_Di(i*16+j*4+3 downto i*16+j*4) <= EventBuf_Do(i*4+j*16+3 downto i*4+j*16);
1281  end generate;
1282 end generate;
1283 i_AMC_DATA: AMC_DATA_FIFO PORT MAP(
1284  wclk => UsrClk ,
1285  rclk => sysclk ,
1286  reset => fifo_rst,
1287  fifo_en => fifo_en,
1288  we => AMC_DATA_WrEn,
1289  re => AMC_DATA_RdEn,
1290  Di => AMC_DATA_Di ,
1291  Do => AMC_DATA ,
1292  WRERR_OUT => WRERR,
1293  RDERR_OUT => RDERR,
1294  full => AMC_DATA_full
1295  );
1296 --AMC_DATA_WrEn <= fifo_en and not AMC_DATA_full(0) and AMC_DATA_Di_vld;
1297 process(UsrClk)
1298 begin
1299  if(UsrClk'event and UsrClk = '1')then
1300  if(reset_SyncRegs(3) = '1' or fifo_en = '0' or AMC_DATA_full = '1')then
1301  ec_EventBuf_ra <= '0';
1302  elsif(or_reduce(EventBuf_wc(10 downto 1)) = '0' and (EventBuf_wc(0) = '0' or ec_EventBuf_ra = '1'))then
1303  ec_EventBuf_ra <= '0';
1304  else
1305  ec_EventBuf_ra <= '1';
1306  end if;
1307  ec_EventBuf_ra_q <= fifo_en and ec_EventBuf_ra;
1308  AMC_DATA_WrEn <= fifo_en and ec_EventBuf_ra_q;
1309  end if;
1310 end process;
1311 process(UsrClk)
1312 begin
1313  if(UsrClk'event and UsrClk = '1')then
1314  if(InitLink = '1' or (test = '1' and fake_got_eof = '1') or (test = '0' and ((abort = '1' and saved_BOE = '1') or (accept = '1' and got_eof = '1'))))then
1315  BOE <= '1';
1316  elsif(EventBuf_we(0) = '1' and EventBuf_wa(0) = '1')then
1317  BOE <= '0';
1318  end if;
1319  if(InitLink = '1' or accept = '1')then
1320  saved_BOE <= '0';
1321  elsif(BOE = '1')then
1322  saved_BOE <= '1';
1323  end if;
1324  if(BOE = '1')then
1325  AMCinfo_word <= '1';
1326  elsif(AMCinfo_word = '1' and EventBuf_we(0) = '1' and EventBuf_wa(1 downto 0) = "00")then
1327  AMCinfo_word <= '0';
1328  AMCinfoDi <= EventBuf_Di;
1329  end if;
1330 -- if(InitLink = '1' or end_of_block = '1' or end_of_event = '1')then
1331  if(InitLink = '1' or (accept = '1' and end_of_block = '1') or end_of_event = '1')then
1332  block32K <= '0';
1333  elsif(EventWC_carry = '1' and EventWC(11 downto 9) = "111" and(test = '1' or accept = '1'))then
1334  block32K <= '1';
1335  end if;
1336 -- if(InitLink = '0' and AMC_en = '1' and block32K = '1' and end_of_block = '0' and and_reduce(EventWC(9 downto 1)) = '1' and EventBuf_we(0) = '1')then
1337 -- end_of_block <= '1';
1338 -- else
1339 -- end_of_block <= '0';
1340 -- end if;
1341  if(EventBuf_we(0) = '1')then
1342  if(block32K = '1' and and_reduce(EventWC(9 downto 1)) = '1')then
1343  end_of_block <= '1';
1344  else
1345  end_of_block <= '0';
1346  end if;
1347  end if;
1348  if(InitLink = '0' and ((test = '1' and fake_got_eof = '1') or (test = '0' and accept = '1' and got_eof = '1')))then
1349  end_of_event <= '1';
1350  else
1351  end_of_event <= '0';
1352  end if;
1353 -- we_EventInfo <= not InitLink and not(NoReSyncFake and EventInfoDi(31)) and (end_of_block or end_of_event);
1354  if(InitLink = '1' or (NoReSyncFake = '1' and EventInfoDi(31) = '1') or AMC_en = '0')then
1355  we_EventInfo <= '0';
1356  elsif(accept = '1' and end_of_block = '1')then
1357  we_EventInfo <= '1';
1358  elsif(end_of_event = '1')then
1359  we_EventInfo <= '1';
1360  else
1361  we_EventInfo <= '0';
1362  end if;
1363  if(InitLink = '1' or (test = '0' and abort = '1') or end_of_event = '1')then
1364  EventWC(8 downto 0) <= (others => '0');
1365  elsif(EventBuf_we(0) = '1' and EventBuf_wa(1 downto 0) = "11")then
1366  EventWC(8 downto 0) <= EventWC(8 downto 0) + 1;
1367  end if;
1368  if(InitLink = '1' or (test = '0' and (abort = '1' or accept = '1')) or (test = '1' and EventWC_carry = '1'))then
1369  EventWC_carry <= '0';
1370  elsif(EventBuf_we(0) = '1' and EventBuf_wa(1 downto 0) = "11" and and_reduce(EventWC(8 downto 0)) = '1')then
1371  EventWC_carry <= '1';
1372  end if;
1373  if(EventBuf_we(0) = '1' and EventBuf_wa(1 downto 0) = "00")then
1374  LengthInTrailer(15 downto 0) <= EventBuf_Di;
1375  end if;
1376  if(EventBuf_we(0) = '1' and EventBuf_wa(1 downto 0) = "01")then
1377  LengthInTrailer(19 downto 16) <= EventBuf_Di(3 downto 0);
1378  end if;
1379  if(InitLink = '1' or end_of_event = '1')then
1380  EventWC(19 downto 9) <= (others => '0');
1381  elsif(EventWC_carry = '1' and(test = '1' or accept = '1'))then
1382  EventWC(19 downto 9) <= EventWC(19 downto 9) + 1;
1383  end if;
1384  UnknownLength <= and_reduce(LengthInHeader);
1385  if(LengthInHeader = LengthInTrailer or UnknownLength = '1')then
1386  LengthMatch <= '1';
1387  else
1388  LengthMatch <= '0';
1389  end if;
1390  if(EventWC = LengthInTrailer and LengthMatch = '1')then
1391  bad_EventLength <= '0';
1392  else
1393  bad_EventLength <= '1';
1394  end if;
1395  if(end_of_event = '1')then
1396  EventInfoDi(19 downto 0) <= "0000000" & block32K & EventWC(11 downto 0);
1397  EventInfoDi(25) <= '0';-- M bit
1398  EventInfoDi(26) <= bad_EventLength;-- EventLengthErr
1399  elsif(BOE = '1' and EventBuf_we(0) = '1')then
1400  if(EventBuf_wa(0) = '0')then
1401  EventInfoDi(15 downto 0) <= EventBuf_Di;
1402  LengthInHeader(15 downto 0) <= EventBuf_Di;
1403  else
1404  EventInfoDi(19 downto 16) <= EventBuf_Di(3 downto 0);
1405  LengthInHeader(19 downto 16) <= EventBuf_Di(3 downto 0);
1406  end if;
1407  EventInfoDi(24) <= '0';-- S bit
1408  EventInfoDi(25) <= '1';-- M bit
1409  EventInfoDi(26) <= '0';-- EventLengthErr
1410  elsif(we_EventInfo = '1')then
1411  EventInfoDi(19 downto 0) <= x"01000";
1412  EventInfoDi(24) <= '1';-- S bit
1413  EventInfoDi(25) <= '1';-- M bit
1414  end if;
1415  if(InitLink = '1' or we_EventInfo = '1')then
1416  EventInfoDi(20) <= '0';
1417  elsif(end_of_event = '1')then
1418  EventInfoDi(20) <= (not bad_AMCCRC or test) and AMC_en;
1419  end if;
1420  if(AMC_en = '0')then
1421  bad_AMC <= '0';
1422  LinkVersion <= x"00";
1423  elsif(InitLink = '1')then
1424  if(ACK = '1' and CTRversion = RxType(7 downto 0))then
1425  bad_AMC <= '0';
1426  else
1427  bad_AMC <= '1';
1428  end if;
1429  if(ACK = '1')then
1430  LinkVersion <= RxType(7 downto 0);
1431  end if;
1432  end if;
1433  if(check_packet = '1')then
1434  evn_OK(5) <= evn_OK(4) or not eof;
1435  end if;
1436 -- EventInfoDi(21) <= not(RxType(2) and RxType(1) and RxType(0)) and not test and AMC_en;
1437  EventInfoDi(31) <= RxType(3) and AMC_en and not test; -- got faked data during ReSync
1438  EventInfoDi(21) <= ((RxType(2) and RxType(1) and RxType(0) and evn_OK(5)) or test) and AMC_en;
1439  EventInfoDi(22) <= AMC_en;
1440  EventInfoDi(23) <= AMC_en;
1441  fake_CRC_q <= not InitLink and AMC_en and fake_CRC;
1442  fake_CRC_q2 <= not InitLink and fake_CRC_q;
1443  AMCCRC_q <= AMCCRC(31 downto 16);
1444  if(test = '1')then
1445  if(fake_header = '1')then
1446  EventBuf_Di <= x"0" & AMC_IDp1 & fake_DATA(7 downto 0);
1447  fake_evn <= fake_DATA(3 downto 0);
1448  elsif(fake_CRC_q = '1')then
1449  EventBuf_Di <= AMCCRC(15 downto 0);
1450  elsif(fake_CRC_q2 = '1')then
1451  EventBuf_Di <= AMCCRC_q;
1452  else
1453  EventBuf_Di <= fake_DATA;
1454  end if;
1455  else
1456  EventBuf_Di <= rfifo;
1457  end if;
1458  if(test = '1')then
1459  EventBuf_we(0) <= (fake_WrEn or fake_CRC_q2) and not fake_CRC and AMC_en;
1460  elsif(we_rfifo = '1' and dl_cntr(2) = '1' and TypeData = '1' and abort = '0' and EventBuf_full = '0')then
1461  EventBuf_we(0) <= '1';
1462  else
1463  EventBuf_we(0) <= '0';
1464  end if;
1465  if(test = '1' or (InitLink = '0' and accept = '1'))then
1466  save_start_addr <= '1';
1467  else
1468  save_start_addr <= '0';
1469  end if;
1470  if(InitLink = '1')then
1471  EventInfo_a <= (others => '1');
1472  EventInfo_ovfl <= (others => '0');
1473  elsif(we_EventInfo = '1' and re_EventInfo = '0')then
1474  EventInfo_a <= EventInfo_a + 1;
1475  if(EventInfo_a = x"e")then
1476  EventInfo_ovfl(0) <= '1';
1477  end if;
1478  elsif(we_EventInfo = '0' and re_EventInfo = '1')then
1479  EventInfo_a <= EventInfo_a - 1;
1480  if(EventInfo_a = x"f")then
1481  EventInfo_ovfl(1) <= '1';
1482  end if;
1483  end if;
1484  if(EventInfo_a = x"d" or EventInfo_a = x"e" or (test = '1' and EventInfo_a(3) = '1' and EventInfo_a(2 downto 0) /= "111"))then
1485  EventInfo_full <= '1';
1486  else
1487  EventInfo_full <= '0';
1488  end if;
1489  re_EventInfo <= not InitLink and (EventInfoRdDoneToggleSyncRegs(3) xor EventInfoRdDoneToggleSyncRegs(2));
1490  if(InitLink = '1')then
1491  EventInfoRdDoneToggleSyncRegs <= (others => '0');
1492  else
1493  EventInfoRdDoneToggleSyncRegs <= EventInfoRdDoneToggleSyncRegs(2 downto 0) & EventInfoRdDoneToggle;
1494  end if;
1495  if(resetCntrCycle = '1')then
1496  CntrBuf_Di <= (others => '0');
1497  we_CntrBuf <= '1';
1498  else
1499  CntrBuf_Di <= rfifo;
1500  we_CntrBuf <= we_rfifo and dl_cntr(2) and TypeCntr and not Cntrabort;
1501  end if;
1502  if(Receiving = '0')then
1503  CntrBuf_wa(4 downto 0) <= (others => '0');
1504  elsif(we_CntrBuf = '1')then
1505  CntrBuf_wa(4 downto 0) <= CntrBuf_wa(4 downto 0) + 1;
1506  end if;
1507  if(InitLink = '1')then
1508  CntrBuf_wa(5) <= '0';
1509  elsif(CntrAccept = '1')then
1510  CntrBuf_wa(5) <= not CntrBuf_wa(5);
1511  end if;
1512  if(InitLink = '1' or resetCntr = '1')then
1513  CntrBuf_valid <= '0';
1514  elsif(CntrAccept = '1')then
1515  CntrBuf_valid <= '1';
1516  end if;
1517  end if;
1518 end process;
1519 i_fake_got_eof : SRL16E
1520  port map (
1521  Q => fake_got_eof, -- SRL data output
1522  A0 => '0', -- Select[0] input
1523  A1 => '1', -- Select[1] input
1524  A2 => '0', -- Select[2] input
1525  A3 => '0', -- Select[3] input
1526  CE => '1', -- Clock enable input
1527  CLK => UsrClk, -- Clock input
1528  D => fake_CRC_q -- SRL data input
1529  );
1530 g_AMCinfo : for i in 0 to 15 generate
1531  i_AMCinfo : SRL16E
1532  port map (
1533  Q => AMCinfo(i), -- SRL data output
1534  A0 => EventInfo_a(0), -- Select[0] input
1535  A1 => EventInfo_a(1), -- Select[1] input
1536  A2 => EventInfo_a(2), -- Select[2] input
1537  A3 => EventInfo_a(3), -- Select[3] input
1538  CE => we_EventInfo, -- Clock enable input
1539  CLK => UsrClk, -- Clock input
1540  D => AMCinfoDi(i) -- SRL data input
1541  );
1542 end generate;
1543 g_EventInfo : for i in 0 to 31 generate
1544  i_EventInfo : SRL16E
1545  port map (
1546  Q => EventInfoDo(i), -- SRL data output
1547  A0 => EventInfo_a(0), -- Select[0] input
1548  A1 => EventInfo_a(1), -- Select[1] input
1549  A2 => EventInfo_a(2), -- Select[2] input
1550  A3 => EventInfo_a(3), -- Select[3] input
1551  CE => we_EventInfo, -- Clock enable input
1552  CLK => UsrClk, -- Clock input
1553  D => EventInfoDi(i) -- SRL data input
1554  );
1555 end generate;
1556 g_CntrBuf : for i in 0 to 15 generate
1557  i_CntrBuf : RAM64X1D
1558  port map (
1559  DPO => CntrBuf_Do(i), -- Read-only 1-bit data output
1560  SPO => open, -- R/W 1-bit data output
1561  A0 => CntrBuf_wa(0), -- R/W address[0] input bit
1562  A1 => CntrBuf_wa(1), -- R/W address[1] input bit
1563  A2 => CntrBuf_wa(2), -- R/W address[2] input bit
1564  A3 => CntrBuf_wa(3), -- R/W address[3] input bit
1565  A4 => CntrBuf_wa(4), -- R/W address[4] input bit
1566  A5 => CntrBuf_wa(5), -- R/W address[5] input bit
1567  D => CntrBuf_Di(i), -- Write 1-bit data input
1568  DPRA0 => CntrBuf_ra(0), -- Read-only address[0] input bit
1569  DPRA1 => CntrBuf_ra(1), -- Read-only address[1] input bit
1570  DPRA2 => CntrBuf_ra(2), -- Read-only address[2] input bit
1571  DPRA3 => CntrBuf_ra(3), -- Read-only address[3] input bit
1572  DPRA4 => CntrBuf_ra(4), -- Read-only address[4] input bit
1573  DPRA5 => CntrBuf_ra(5), -- Read-only address[5] input bit
1574  WCLK => UsrClk, -- Write clock input
1575  WE => we_CntrBuf -- Write enable input
1576  );
1577 end generate;
1578 CntrBuf_ra <= not CntrBuf_wa(5) & Cntr_ra(6 downto 2);
1579 g_CntrBuf2 : for i in 0 to 15 generate
1580  i_CntrBuf2 : RAM64X1D
1581  port map (
1582  DPO => CntrBuf2_Do(i), -- Read-only 1-bit data output
1583  SPO => CntrBuf2_SPO(i), -- R/W 1-bit data output
1584  A0 => CntrBuf2_wa(0), -- R/W address[0] input bit
1585  A1 => CntrBuf2_wa(1), -- R/W address[1] input bit
1586  A2 => CntrBuf2_wa(2), -- R/W address[2] input bit
1587  A3 => CntrBuf2_wa(3), -- R/W address[3] input bit
1588  A4 => CntrBuf2_wa(4), -- R/W address[4] input bit
1589  A5 => CntrBuf2_wa(5), -- R/W address[5] input bit
1590  D => CntrBuf2_Di(i), -- Write 1-bit data input
1591  DPRA0 => Cntr_ra(2), -- Read-only address[0] input bit
1592  DPRA1 => Cntr_ra(3), -- Read-only address[1] input bit
1593  DPRA2 => Cntr_ra(4), -- Read-only address[2] input bit
1594  DPRA3 => Cntr_ra(5), -- Read-only address[3] input bit
1595  DPRA4 => Cntr_ra(6), -- Read-only address[4] input bit
1596  DPRA5 => Cntr_ra(8), -- Read-only address[5] input bit
1597  WCLK => UsrClk, -- Write clock input
1598  WE => we_CntrBuf2 -- Write enable input
1599  );
1600 end generate;
1601 process(UsrClk)
1602 begin
1603  if(UsrClk'event and UsrClk = '1')then
1604  if(resetCntr = '1')then
1605  zeroWordCntr <= (others => '0');
1606  elsif(or_reduce(EventBuf_Di) = '0' and EventBuf_wa(1 downto 0) = "11" and AllZero = '1' and EventBuf_we(0) = '1')then
1607  zeroWordCntr <= zeroWordCntr + 1;
1608  end if;
1609  if(resetCntr = '1')then
1610  AllZero <= '1';
1611  elsif(EventBuf_we(0) = '1')then
1612  if(EventBuf_wa(1 downto 0) = "11")then
1613  AllZero <= '1';
1614  elsif(or_reduce(EventBuf_Di) = '1')then
1615  AllZero <= '0';
1616  end if;
1617  end if;
1618  we_CntrBuf2p <= not we_CntrBuf2;
1619  we_CntrBuf2 <= we_CntrBuf2p and not we_CntrBuf2;
1620  if(resetCntr = '1')then
1621  CntrBuf2_wa <= "111000";
1622  elsif(we_CntrBuf2 = '1')then
1623  if(CntrBuf2_wa = "011111")then -- 40 counters time 3 is 120 < 128 and 7 bit counters won't overflow
1624  CntrBuf2_wa <= "111000";
1625  else
1626  CntrBuf2_wa <= CntrBuf2_wa + 1;
1627  end if;
1628  end if;
1629  if(resetCntr = '1')then
1630  resetCntrCycle <= '1';
1631  elsif(we_CntrBuf2 = '1' and CntrBuf2_wa = "011111")then
1632  resetCntrCycle <= '0';
1633  end if;
1634  if(CntrBuf2_wa(5) = '1')then
1635  case CntrBuf2_wa(2 downto 0) is
1636  when "000" => Cntrs <= TTS_OFWcntr;
1637  when "001" => Cntrs <= TTS_BSYcntr;
1638  when "010" => Cntrs <= TTS_OOScntr;
1639  when "011" => Cntrs <= TTS_ERRcntr;
1640  when "100" => Cntrs <= TTS_DCcntr;
1641  when others => Cntrs <= (others=> '0');
1642  end case;
1643  elsif(CntrBuf2_wa(4) = '0')then
1644  case CntrBuf2_wa(3 downto 0) is
1645  when x"1" => Cntrs <= sglErrCntr;
1646  when x"2" => Cntrs <= dblErrCntr;
1647  when x"3" => Cntrs <= BC0mmCntr;
1648  when x"4" => Cntrs <= BcntMmCntr;
1649  when x"5" => Cntrs <= ResendCntr;
1650  when x"6" => Cntrs <= AcceptCntr;
1651  when x"7" => Cntrs <= CntrAcceptCntr;
1652  when x"8" => Cntrs <= ACKcntr;
1653  when x"9" => Cntrs <= RxEventCntr;
1654  when x"a" => Cntrs <= RdEventCntr;
1655  when x"b" => Cntrs <= DataAbortCntr;
1656  when x"c" => Cntrs <= CntrAbortCntr;
1657  when x"d" => Cntrs <= ACKNUM_fullAbortCntr;
1658  when x"e" => Cntrs <= EventBuf_fullAbortCntr;
1659  when others => Cntrs <= EventInfo_fullAbortCntr;
1660  end case;
1661  else
1662  case CntrBuf2_wa(3 downto 0) is
1663  when x"0" => Cntrs <= SEQAbortCntr;
1664  when x"1" => Cntrs <= CRCAbortCntr;
1665  when x"2" => Cntrs <= frameAbortCntr;
1666  when x"3" => Cntrs <= bad_KAbortCntr;
1667  when x"4" => Cntrs <= BUSYCntr;
1668  when x"5" => Cntrs <= EvtEVNmmCntr;
1669  when x"6" => Cntrs <= EvtBCNmmCntr;
1670  when x"7" => Cntrs <= EvtOCNmmCntr;
1671  when x"8" => Cntrs <= bad_EventLengthCntr;
1672  when x"9" => Cntrs <= BlockCntr; -- we_EventInfo count
1673  when x"a" => Cntrs <= TTSCntr; -- IS_TTS count
1674  when x"b" => Cntrs <= TTCCntr; -- TTC_DataValid count
1675  when x"c" => Cntrs <= badCRCCntr; -- bad AMC event CRC count
1676  when x"d" => Cntrs <= TTS_ERR_cntr; -- TTC_DataValid count
1677  when x"e" => Cntrs <= TTS_SL_cntr; -- bad AMC event CRC count
1678  when others => Cntrs <= TTS_DC_cntr;
1679  end case;
1680  end if;
1681  CntrBuf2_SPO_q <= CntrBuf2_SPO;
1682  if(resetCntrCycle = '1')then
1683  CntrBuf2_Di(15 downto 7) <= (others => '0');
1684  elsif(Cntrs < CntrBuf2_SPO_q(6 downto 0))then
1685  CntrBuf2_Di(15 downto 7) <= CntrBuf2_SPO_q(15 downto 7) + 1;
1686  else
1687  CntrBuf2_Di(15 downto 7) <= CntrBuf2_SPO_q(15 downto 7);
1688  end if;
1689  if(resetCntrCycle = '1')then
1690  CntrBuf2_Di(6 downto 0) <= (others => '0');
1691  else
1692  CntrBuf2_Di(6 downto 0) <= Cntrs;
1693  end if;
1694  end if;
1695 end process;
1696 process(sysclk,resetCntr)
1697 begin
1698  if(resetCntr = '1')then
1699  WordCntr <= (others => '0');
1700  WordCntr_q <= (others => '0');
1701  elsif(sysclk'event and sysclk = '1')then
1702  if(AMC_DATA_RdEn = '1')then
1703  WordCntr <= WordCntr + 1;
1704  end if;
1705  if(Cntr_RdEn = '0' or Cntr_ra(8 downto 7) /= "10")then
1706  WordCntr_q <= WordCntr;
1707  end if;
1708  end if;
1709 end process;
1710 process(sysclk,InitLink)
1711 begin
1712  if(InitLink = '1')then
1713  EventInfoRdDoneToggle <= '0';
1714  EventInfo_dav_i <= '0';
1715  EventInfoToggleSyncRegs <= (others => '0');
1716  L1Ainfo_wa <= (others => '0');
1717  elsif(sysclk'event and sysclk = '1')then
1718  if(reset = '1')then
1719  EventInfoRdDoneToggle <= '0';
1720  EventInfo_dav_i <= '0';
1721  EventInfoToggleSyncRegs <= (others => '0');
1722  L1Ainfo_wa <= (others => '0');
1723  else
1724  if(EventInfoRdDone = '1')then
1725  EventInfoRdDoneToggle <= not EventInfoRdDoneToggle;
1726  end if;
1727  if(AMC_en = '0' or EventInfoRdDone = '1')then
1728  EventInfo_dav_i <= '0';
1729  elsif(EventInfoToggleSyncRegs(3) /= EventInfoToggleSyncRegs(2))then
1730  EventInfo_dav_i <= '1';
1731  end if;
1732  EventInfoToggleSyncRegs <= EventInfoToggleSyncRegs(2 downto 0) & EventInfoToggle;
1733  if(L1A_WrEn = '1' and AMC_en = '1')then
1734  L1Ainfo_wa <= L1Ainfo_wa + 1;
1735  end if;
1736  end if;
1737  end if;
1738 end process;
1739 i_L1Ainfo : BRAM_SDP_MACRO
1740  generic map (
1741  BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
1742  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1743  WRITE_WIDTH => 16, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1744  READ_WIDTH => 16, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1745  DO_REG => 1, -- Optional output register (0 or 1)
1746  SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY",
1747  -- "GENERATE_X_ONLY" or "NONE"
1748  WRITE_MODE => "WRITE_FIRST", -- Specify "READ_FIRST" for same clock or synchronous clocks
1749  -- Specify "WRITE_FIRST for asynchrononous clocks on ports
1750  INIT => X"000000000000000000") -- Initial values on output port
1751  port map (
1752  DO => L1AinfoDo, -- Output read data port, width defined by READ_WIDTH parameter
1753  DI => L1A_DATA, -- Input write data port, width defined by WRITE_WIDTH parameter
1754  RDADDR => L1Ainfo_ra, -- Input read address, width defined by read port depth
1755  RDCLK => UsrClk, -- 1-bit input read clock
1756  RDEN => re_L1AinfoDo, -- 1-bit input read port enable
1757  REGCE => re_L1AinfoDo, -- 1-bit input read output register enable
1758  RST => '0', -- 1-bit input reset
1759  WE => "11", -- Input write enable, width defined by write port depth
1760  WRADDR => L1Ainfo_wa, -- Input write address, width defined by write port depth
1761  WRCLK => sysclk, -- 1-bit input write clock
1762  WREN => L1A_WrEn -- 1-bit input write port enable
1763  );
1764 re_L1AinfoDo <= not SendTTS;
1765 g_ReSendQueue : for i in 0 to 15 generate
1766  i_ReSendQueue : SRL16E
1767  port map (
1768  Q => ReSendQueOut(i), -- SRL data output
1769  A0 => ReSendQue_a(0), -- Select[0] input
1770  A1 => ReSendQue_a(1), -- Select[1] input
1771  A2 => '0', -- Select[2] input
1772  A3 => '0', -- Select[3] input
1773  CE => we_ReSendQue, -- Clock enable input
1774  CLK => UsrClk, -- Clock input
1775  D => ReSendQueIn(i) -- SRL data input
1776  );
1777 end generate;
1778 ReSendQueIn <= SEQNUM & L1Ainfo_start;
1779 -- Tx logic
1780 process(UsrClk)
1781 begin
1782  if(UsrClk'event and UsrClk = '1')then
1783  if(InitLink = '1')then
1784  L1Ainfo_ra <= (others => '0');
1785  elsif(ReSend = '1')then
1786  L1Ainfo_ra <= ReSendQueOut(7 downto 0) & "00";
1787  elsif(ec_L1Ainfo_ra = '1' and SendTTS = '0')then
1788  L1Ainfo_ra <= L1Ainfo_ra + 1;
1789  end if;
1790  if(InitLink = '1')then
1791  L1Ainfo_start <= (others => '0');
1792  elsif(ReSend = '1')then
1793  L1Ainfo_start <= ReSendQueOut(7 downto 0);
1794  elsif(we_ReSendQue = '1')then
1795  L1Ainfo_start <= L1Ainfo_ra(9 downto 2);
1796  end if;
1797  if(InitLink = '1')then
1798  L1Ainfo_wa2SyncRegs <= (others => '0');
1799  else
1800  L1Ainfo_wa2SyncRegs <= L1Ainfo_wa2SyncRegs(2 downto 0) & L1Ainfo_wa(2);
1801  end if;
1802  if(InitLink = '1')then
1803  L1Ainfo_wap <= (others => '0');
1804  elsif(L1Ainfo_wa2SyncRegs(3) /= L1Ainfo_wa2SyncRegs(2))then
1805  L1Ainfo_wap <= L1Ainfo_wap + 1;
1806  end if;
1807  if(InitLink = '1' or L1Ainfo_wap = L1Ainfo_ra(9 downto 2))then
1808  L1Ainfo_empty <= '1';
1809  else
1810  L1Ainfo_empty <= '0';
1811  end if;
1812  if(reset_SyncRegs(3) = '1')then
1813  InitLink <= '1';
1814  elsif(ACK = '1' or test = '1')then
1815  InitLink <= '0';
1816  end if;
1817  if(reset_SyncRegs(3) = '1' or ReSend = '1')then
1818  ReSendQue_a <= (others => '1');
1819  elsif(we_ReSendQue = '1' and ACK = '0')then
1820  ReSendQue_a <= ReSendQue_a + 1;
1821  elsif(we_ReSendQue = '0' and ACK = '1' and ReSendQue_a /= "11")then
1822  ReSendQue_a <= ReSendQue_a - 1;
1823  end if;
1824  if(TxState = SendWC and Resend = '0'and SendTTS = '0' and (L1ASent = '1' or InitLink = '1'))then
1825  we_ReSendQue <= '1';
1826  else
1827  we_ReSendQue <= '0';
1828  end if;
1829  if(ReSendQue_a = "10")then
1830  ReSendQue_full <= '1';
1831  else
1832  ReSendQue_full <= '0';
1833  end if;
1834  if(reset_SyncRegs(3) = '1' or ReSend = '1')then
1835  ReSendQue_empty <= '1';
1836  elsif(we_ReSendQue = '1')then
1837  ReSendQue_empty <= '0';
1838  elsif(ACK = '1' and ReSendQue_a = "00")then
1839  ReSendQue_empty <= '1';
1840  end if;
1841  if(InitLink = '1')then
1842  SEQNUM <= x"01";
1843  elsif(ReSend = '1')then
1844  SEQNUM <= ReSendQueOut(15 downto 8);
1845  elsif(we_ReSendQue = '1')then
1846  SEQNUM <= SEQNUM(6 downto 0) & not(SEQNUM(7) xor SEQNUM(5) xor SEQNUM(4) xor SEQNUM(3));
1847  end if;
1848  if(reset_SyncRegs(3) = '1')then
1849  got_comma <= '0';
1850  elsif(RXCHARISCOMMA = "11")then
1851  got_comma <= '1';
1852  end if;
1853  if(AMCRdy = '0' or reset_SyncRegs(3) = '1' or ReSend = '1')then
1854  TxState <= IDLE;
1855  ec_L1Ainfo_ra <= '0';
1856  elsif(SendTTS = '0')then
1857  case TxState is
1858  when IDLE => -- send R_word (idle)
1859  TxState <= SendK;
1860  ec_L1Ainfo_ra <= '0';
1861  when SendK => -- send K_word
1862  if((ReSend_l = '1' and InitLink = '1') or (ReSendQue_full = '0' and L1Ainfo_empty = '0' and InitLink = '0') or ACKNUM_empty = '0' or GotCntr = '1')then
1863  TxState <= SendSEQ;
1864  else
1865  TxState <= IDLE;
1866  end if;
1867  if(InitLink = '1')then
1868  L1ASent <= '0';
1869  IsACK <= '0';
1870  TxType <= InitRqst;
1871  elsif(GotCntr = '1')then
1872  L1ASent <= '0';
1873  IsACK <= '0';
1874  TxType <= Counter;
1875  elsif(ReSendQue_full = '0' and L1Ainfo_empty = '0')then
1876  L1ASent <= '1';
1877  ec_L1Ainfo_ra <= '1';
1878  IsACK <= '0';
1879  TxType <= data;
1880  else
1881  L1ASent <= '0';
1882  IsACK <= '1';
1883  TxType <= Acknowledge;
1884  end if;
1885  when SendSEQ => -- send packet type
1886  TxState <= SendType;
1887  if(IsACK = '0')then
1888  ACKNUM_MUX <= CntrACKNUM;
1889  else
1890  ACKNUM_MUX <= ACKNUM_l;
1891  end if;
1892  when SendType => -- send packet_seq
1893  if(L1Asent = '0')then
1894  TxState <= SendWC;
1895  else
1896  TxState <= SendData;
1897  end if;
1898  when SendWC => -- send packet_wc
1899  TxState <= WaitCRC;
1900  when WaitCRC => -- wait for CRC
1901  TxState <= SendCRC;
1902  when SendData => -- send L1A info
1903  if(packet_wc = "11")then
1904  TxState <= SendWC;
1905  end if;
1906  if(packet_wc = "01")then
1907  ec_L1Ainfo_ra <= '0';
1908  end if;
1909  when others => TxState <= IDLE;
1910  end case;
1911  end if;
1912  if(TxState = SendK)then
1913  packet_wc <= (others => '0');
1914  elsif(TxState = SendData and SendTTS = '0')then
1915  packet_wc(1) <= packet_wc(1) xor packet_wc(0);
1916  packet_wc(0) <= not packet_wc(0);
1917  end if;
1918  if(is_TTS = '1' or TTS_wait(7) = '1' or (InitLink = '1' and ACK = '1'))then
1919  SendTTS <= '1';
1920  else
1921  SendTTS <= '0';
1922  end if;
1923  if(SendTTS = '1')then
1924  TXDATA_i <= TTS & x"5c";
1925  TxIsK <= '1';
1926  TXCHARISK <= "01";
1927  else
1928  case TxState is
1929  when SendK => TXDATA_i <= K_word;
1930  when SendData => TXDATA_i <= L1AinfoDo;
1931  when SendSEQ => TXDATA_i <= SEQNUM & TxType;
1932  when SendType => TXDATA_i <= ACKNUM_MUX & x"0" & AMC_IDp1;
1933  when SendWC => TXDATA_i <= x"000" & '0' & L1Asent & "00";
1934  when SendCRC => TXDATA_i <= TxCRC;
1935  when others => TXDATA_i <= R_word;
1936  end case;
1937  case TxState is
1938  when IDLE | SendK | WaitCRC => TxIsK <= '1';
1939  TXCHARISK <= "11";
1940  when others => TxIsK <= '0';
1941  TXCHARISK <= "00";
1942  end case;
1943  end if;
1944  if(TxState = IDLE or TxState = SendK)then
1945  Init_TxCRC <= '1';
1946  else
1947  Init_TxCRC <= '0';
1948  end if;
1949  end if;
1950 end process;
1951 i_TxCRC: crc16D16 PORT MAP(
1952  clk => UsrClk ,
1953  init_crc => Init_TxCRC,
1954  we_crc => we_TxCRC,
1955  d => TXDATA_i ,
1956  crc => TxCRC
1957  );
1958 we_TxCRC <= not TxIsK;
1959 end Behavioral;
1960 
Generated on Sun Mar 6 2016 12:24:19 for AMC13 by   doxygen 1.8.1