AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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AMC13_T1_g2.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 14:49:29 05/12/2010
6 -- Design Name:
7 -- Module Name: DTC_T2 - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 use work.ipbus.ALL;
26 use work.amc13_pack.all;
27 
28 -- Uncomment the following library declaration if using
29 -- arithmetic functions with Signed or Unsigned values
30 -- use IEEE.NUMERIC_STD.ALL;
31 
32 -- Uncomment the following library declaration if instantiating
33 -- any Xilinx primitives in this code.
34 library UNISIM;
35 use UNISIM.VComponents.all;
36 Library UNIMACRO;
37 use UNIMACRO.vcomponents.all;
38 
39 entity AMC13_T1_g2 is
40  Port (
41  VAUXP : in STD_LOGIC_VECTOR(12 downto 0);
42  VAUXN : in STD_LOGIC_VECTOR(12 downto 0);
43 -- I2C interface
44  CLK_SCL : out STD_LOGIC;
45  CLK_SDA : inout STD_LOGIC;
46  SFP_SCL : out STD_LOGIC_VECTOR(3 downto 0);
47  SFP_SDA : inout STD_LOGIC_VECTOR(3 downto 0);
48 -- SFP slow control
49  SFP_LOS : in STD_LOGIC_VECTOR(2 downto 0);
50  SFP_ABS : in STD_LOGIC_VECTOR(3 downto 0);
51  TxFault : in STD_LOGIC_VECTOR(3 downto 0);
52  TxDisable : out STD_LOGIC_VECTOR(3 downto 0);
53 -- RATE : out STD_LOGIC_VECTOR(3 downto 0);
54 -- CDR signals
55  DIV4 : out STD_LOGIC;
56  DIV_nRST : out STD_LOGIC;
57  CDRclk_p : in STD_LOGIC;
58  CDRclk_n : in STD_LOGIC;
59  CDRdata_p : in STD_LOGIC;
60  CDRdata_n : in STD_LOGIC;
61  TTCdata_p : out STD_LOGIC;
62  TTCdata_n : out STD_LOGIC;
63  TTCclk_p : in STD_LOGIC;
64  TTCclk_n : in STD_LOGIC;
65  TTC_LOS : in STD_LOGIC;
66  TTC_LOL : in STD_LOGIC;
67  TTS_out_p : out STD_LOGIC;
68  TTS_out_n : out STD_LOGIC;
69 -- SPI interface
70  SPI_SCK : in STD_LOGIC;
71  SPI_CS_b : in STD_LOGIC;
72  SPI_MOSI : in STD_LOGIC;
73  SPI_MISO : out STD_LOGIC;
74 -- DDR3 pins
75  sys_clk_p : in STD_LOGIC;
76  sys_clk_n : in STD_LOGIC;
77  ddr3_dq : inout STD_LOGIC_VECTOR(31 downto 0);
78  ddr3_addr : out STD_LOGIC_VECTOR(13 downto 0);
79  ddr3_ba : out STD_LOGIC_VECTOR (2 downto 0);
80  ddr3_dm : out STD_LOGIC_VECTOR (3 downto 0);
81  ddr3_dqs_p : inout STD_LOGIC_VECTOR(3 downto 0);
82  ddr3_dqs_n : inout STD_LOGIC_VECTOR(3 downto 0);
83  ddr3_ras_n : out STD_LOGIC;
84  ddr3_cas_n : out STD_LOGIC;
85  ddr3_we_n : out STD_LOGIC;
86  ddr3_reset_n : out STD_LOGIC;
87  ddr3_cke : out STD_LOGIC_vector(0 to 0);
88  ddr3_odt : out STD_LOGIC_vector(0 to 0);
89  ddr3_ck_p : out STD_LOGIC_vector(0 to 0);
90  ddr3_ck_n : out STD_LOGIC_vector(0 to 0);
91  SFP0_RXN : in STD_LOGIC;
92  SFP0_RXP : in STD_LOGIC;
93  SFP1_RXN : in STD_LOGIC;
94  SFP1_RXP : in STD_LOGIC;
95  SFP2_RXN : in STD_LOGIC;
96  SFP2_RXP : in STD_LOGIC;
97  SFP0_TXN : out STD_LOGIC;
98  SFP0_TXP : out STD_LOGIC;
99  SFP1_TXN : out STD_LOGIC;
100  SFP1_TXP : out STD_LOGIC;
101  SFP2_TXN : out STD_LOGIC;
102  SFP2_TXP : out STD_LOGIC;
103  SFP_REFCLK_N : in STD_LOGIC;
104  SFP_REFCLK_P : in STD_LOGIC;
105  AMC_REFCLK_N : in STD_LOGIC;
106  AMC_REFCLK_P : in STD_LOGIC;
107  AMC_RXN : in STD_LOGIC_VECTOR(12 downto 1);
108  AMC_RXP : in STD_LOGIC_VECTOR(12 downto 1);
109  AMC_TXN : out STD_LOGIC_VECTOR(12 downto 1);
110  AMC_TXP : out STD_LOGIC_VECTOR(12 downto 1);
111 -- signal to/from DTC_T2
112  S6LINK_RXN : in STD_LOGIC;
113  S6LINK_RXP : in STD_LOGIC;
114  S6LINK_TXN : out STD_LOGIC;
115  S6LINK_TXP : out STD_LOGIC;
116  S2V_p : in STD_LOGIC;
117  S2V_n : in STD_LOGIC;
118 -- V2S_p : in STD_LOGIC;
119 -- V2S_n : in STD_LOGIC;
120  GbE_REFCLK_N : in STD_LOGIC;
121  GbE_REFCLK_P : in STD_LOGIC);
122 end AMC13_T1_g2;
123 
124 architecture Behavioral of AMC13_T1_g2 is
125 COMPONENT TTS_if
126  PORT(
127  sysclk : IN std_logic;
128  TTS_clk : IN std_logic;
129  reset : IN std_logic;
130  local_TTC : in STD_LOGIC;
131  TTS : IN std_logic_vector(3 downto 0);
132  TTS_out_p : OUT std_logic;
133  TTS_out_n : OUT std_logic
134  );
135 END COMPONENT;
136 COMPONENT ttc_if
137  PORT(
138  clk : IN std_logic;
139  refclk : IN std_logic;
140  reset : IN std_logic;
141  run : IN std_logic;
142  IsG2 : IN std_logic;
143  sys_lock : IN std_logic;
144  local_TTC : IN std_logic;
145  local_TTCcmd : IN std_logic;
146  single_TTCcmd : in STD_LOGIC;
147  CDRclk_p : IN std_logic;
148  CDRclk_n : IN std_logic;
149  CDRdata_p : IN std_logic;
150  CDRdata_n : IN std_logic;
151  TTC_LOS : IN std_logic;
152  TTC_LOL : IN std_logic;
153  BCN_off : IN std_logic_vector(12 downto 0);
154  OC_off : IN std_logic_vector(3 downto 0);
155  en_cal_win : IN std_logic;
156  cal_win_high : IN std_logic_vector(11 downto 0);
157  cal_win_low : IN std_logic_vector(11 downto 0);
158  en_localL1A : IN std_logic;
159  LocalL1A_cfg : IN std_logic_vector(31 downto 0);
160  localL1A_s : IN std_logic;
161  localL1A_r : IN std_logic;
162  T3_trigger : IN std_logic;
163  EvnRSt_l : IN std_logic;
164  OcnRSt_l : IN std_logic;
165  ovfl_warning : IN std_logic;
166  ipb_clk : IN std_logic;
167  ipb_write : IN std_logic;
168  ipb_strobe : IN std_logic;
169  ipb_addr : IN std_logic_vector(31 downto 0);
170  ipb_wdata : IN std_logic_vector(31 downto 0);
171  en_brcst : IN std_logic;
172  state : IN std_logic_vector(3 downto 0);
173  evn_fifo_full : IN std_logic;
174  BC0 : OUT std_logic;
175  TTC_strobe : OUT std_logic;
176  TTS_clk : OUT std_logic;
177  DIV4 : OUT std_logic;
178  DIV_nRST : OUT std_logic;
179  CDRclk_out : OUT std_logic;
180  TTCdata_p : OUT std_logic;
181  TTCdata_n : OUT std_logic;
182  CalType : OUT std_logic_vector(3 downto 0);
183  TTC_Brcst : OUT std_logic_vector(3 downto 0);
184  localL1A_periodic : OUT std_logic;
185  ipb_rdata : OUT std_logic_vector(31 downto 0);
186  ttc_start : OUT std_logic;
187  ttc_stop : OUT std_logic;
188  ttc_soft_reset : OUT std_logic;
189  ttc_ready : OUT std_logic;
190  ttc_serr : OUT std_logic;
191  ttc_derr : OUT std_logic;
192  ttc_bcnt_err : OUT std_logic;
193  rate_OFW : OUT std_logic;
194  sync_lost : OUT std_logic;
195  inc_oc : OUT std_logic;
196  inc_l1ac : OUT std_logic;
197  inc_bcnterr : OUT std_logic;
198  inc_serr : OUT std_logic;
199  inc_derr : OUT std_logic;
200  ttc_evcnt_reset : OUT std_logic;
201  event_number_avl : OUT std_logic;
202  event_number : OUT std_logic_vector(59 downto 0)
203  );
204 END COMPONENT;
205 COMPONENT AMC_if
206  Generic (useTCPIP : boolean := true; AMC_useTRIG : boolean := false; simulation : boolean := false);
207  PORT(
208  sysclk : IN std_logic;
209  ipb_clk : IN std_logic;
210  clk125 : IN std_logic;
211  DRPclk : IN std_logic;
212  GTXreset : IN std_logic;
213  reset : IN std_logic;
214  resetCntr : IN std_logic;
215  ReSync : IN std_logic;
216  AllEventBuilt : OUT std_logic;
217  run : IN std_logic;
218  Dis_pd : in STD_LOGIC;
219  enSFP : IN std_logic_vector(3 downto 0);
220  en_localL1A : IN std_logic;
221  test : IN std_logic;
222  NoReSyncFake : IN std_logic;
223  WaitMonBuf : IN std_logic;
224  fake_length : IN std_logic_vector(19 downto 0);
225  T1_version : IN std_logic_vector(7 downto 0);
226  Source_ID : IN array3x12;
227  AMC_en : IN std_logic_vector(11 downto 0);
228  TTS_disable : IN std_logic_vector(11 downto 0);
229  AMC_REFCLK_P : IN std_logic;
230  AMC_REFCLK_N : IN std_logic;
231  AMC_RXN : IN std_logic_vector(12 downto 1);
232  AMC_RXP : IN std_logic_vector(12 downto 1);
233  evt_data_re : IN std_logic_vector(2 downto 0);
234  evt_buf_full : IN std_logic_vector(2 downto 0);
235  ddr_pa : IN std_logic_vector(9 downto 0);
236  MonBuf_empty : IN std_logic;
237  mon_buf_avl : IN std_logic;
238  TCPbuf_avl : IN std_logic;
239  ipb_write : IN std_logic;
240  ipb_strobe : IN std_logic;
241  ipb_addr : IN std_logic_vector(31 downto 0);
242  ipb_wdata : IN std_logic_vector(31 downto 0);
243  TTC_clk : IN std_logic;
244  TTC_LOS : IN std_logic;
245  BC0 : IN std_logic;
246  ttc_evcnt_reset : IN std_logic;
247  event_number_avl : IN std_logic;
248  event_number : IN std_logic_vector(59 downto 0);
249  AMC_Ready : OUT std_logic_vector(11 downto 0);
250  TTC_lock: OUT std_logic;
251  BC0_lock : OUT std_logic_vector(11 downto 0);
252  AMC_TXN : OUT std_logic_vector(12 downto 1);
253  AMC_TXP : OUT std_logic_vector(12 downto 1);
254  AMC_status : OUT std_logic_vector(31 downto 0);
255  evt_data : OUT array3x67;
256  evt_data_we : OUT std_logic_vector(2 downto 0);
257  evt_data_rdy : OUT std_logic_vector(2 downto 0);
258  mon_evt_wc : OUT std_logic_vector(47 downto 0);
259  mon_ctrl : OUT std_logic_vector(31 downto 0);
260  buf_rqst : OUT std_logic_vector(3 downto 0);
261  ipb_rdata : OUT std_logic_vector(31 downto 0);
262  ipb_ack : OUT std_logic;
263  evn_buf_full : OUT std_logic;
264  ovfl_warning : OUT std_logic;
265  TrigData : OUT array12x8;
266  TTS_coded : OUT std_logic_vector(4 downto 0)
267  );
268 END COMPONENT;
269 COMPONENT I2C
270  PORT(
271  clk : IN std_logic;
272  ipb_clk : IN std_logic;
273  reset : IN std_logic;
274  addr : IN std_logic_vector(31 downto 0);
275  SFP_ABS : IN std_logic_vector(3 downto 0);
276  SFP_LOS : IN std_logic_vector(2 downto 0);
277  CLK_SDA : INOUT std_logic;
278  SFP_SDA : INOUT std_logic_vector(3 downto 0);
279  rdata : OUT std_logic_vector(31 downto 0);
280  CLK_rdy : OUT std_logic;
281  CLK_SCL : OUT std_logic;
282  SFP_SCL : OUT std_logic_vector(3 downto 0)
283  );
284 END COMPONENT;
285 COMPONENT SPI_if
286  PORT(
287  SCK : IN std_logic;
288  CSn : IN std_logic;
289  MOSI : IN std_logic;
290  SN : IN std_logic_vector(8 downto 0);
291  OT : IN std_logic;
292  IsT1 : IN std_logic;
293  SPI_rdata : IN std_logic_vector(7 downto 0);
294  MISO : OUT std_logic;
295  SPI_we : OUT std_logic;
296  en_RARP : out STD_LOGIC;
297  newIPADDR : OUT std_logic;
298  IPADDR : OUT std_logic_vector(31 downto 0);
299  SPI_wdata : OUT std_logic_vector(7 downto 0);
300  SPI_addr : OUT std_logic_vector(7 downto 0)
301  );
302 END COMPONENT;
303 COMPONENT ddr_if
304  port(
305  clk_ref : in std_logic;
306  mem_clk_p : in std_logic;
307  mem_clk_n : in std_logic;
308  mem_rst : in std_logic;
309  sysclk : in std_logic;
310  TCPclk : in std_logic;
311  reset : in std_logic;
312  resetsys : in std_logic;
313  run : in std_logic;
314  mem_test : in std_logic_VECTOR(1 downto 0);
315  EventData : in array3X67;
316  EventData_we : in std_logic_VECTOR(2 downto 0);
317  wport_rdy : out std_logic_VECTOR(2 downto 0);
318  WrtMonBlkDone : OUT std_logic_VECTOR(2 downto 0);
319  WrtMonEvtDone : OUT std_logic_VECTOR(2 downto 0);
320  KiloByte_toggle : OUT std_logic_VECTOR(2 downto 0);
321  EoB_toggle : OUT std_logic_VECTOR(2 downto 0);
322  EventBufAddr : in array3x14;
323  EventBufAddr_we : in std_logic_VECTOR(2 downto 0);
324  EventFIFOfull : out std_logic_VECTOR(2 downto 0);
325  TCP_din : in std_logic_vector(31 downto 0);
326  TCP_channel : in STD_LOGIC_VECTOR (1 downto 0);
327  TCP_we : in STD_LOGIC;
328  TCP_wcount : out STD_LOGIC_VECTOR (2 downto 0);
329  TCP_dout : out STD_LOGIC_VECTOR(31 downto 0); -- TCP data are written in unit of 32-bit words
330  TCP_dout_type : out STD_LOGIC_VECTOR(2 downto 0); -- TCP data destination
331  TCP_raddr : in std_logic_vector(28 downto 0); -- 28-26 encoded request source 25-0 address in 64 bit word
332  TCP_length : in std_logic_vector(10 downto 0); -- in 64 bit word, actual length - 1
333  TCP_dout_valid : out STD_LOGIC;
334  TCP_rrqst : in STD_LOGIC;
335  TCP_rack : out STD_LOGIC;
336  TCP_lastword : out STD_LOGIC;
337  cs_out : out STD_LOGIC_VECTOR(511 downto 0);
338 -- ipbus signals
339  ipb_clk : in STD_LOGIC;
340  ipb_write : in STD_LOGIC;
341  ipb_strobe : in STD_LOGIC;
342  page_addr : in STD_LOGIC_VECTOR(9 downto 0);
343  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
344  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
345  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
346  ipb_ack : out STD_LOGIC;
347  mem_stat : out STD_LOGIC_VECTOR (63 downto 0);
348  device_temp : in STD_LOGIC_VECTOR(11 downto 0);
349 -- ddr3 memory pins
350  ddr3_dq : inout STD_LOGIC_VECTOR (31 downto 0);
351  ddr3_dm : out STD_LOGIC_VECTOR (3 downto 0);
352  ddr3_addr : out STD_LOGIC_VECTOR (13 downto 0);
353  ddr3_ba : out STD_LOGIC_VECTOR (2 downto 0);
354  ddr3_dqs_p : inout STD_LOGIC_VECTOR (3 downto 0);
355  ddr3_dqs_n : inout STD_LOGIC_VECTOR (3 downto 0);
356  ddr3_ras_n : out STD_LOGIC;
357  ddr3_cas_n : out STD_LOGIC;
358  ddr3_we_n : out STD_LOGIC;
359  ddr3_reset_n : out STD_LOGIC;
360  ddr3_cke : out STD_LOGIC_vector(0 to 0);
361  ddr3_odt : out STD_LOGIC_vector(0 to 0);
362  ddr3_ck_p : out STD_LOGIC_vector(0 to 0);
363  ddr3_ck_n : out STD_LOGIC_vector(0 to 0)
364  );
365 END COMPONENT;
366 COMPONENT ipbus_if
367  generic(RXPOLARITY : std_logic := '0'; TXPOLARITY : std_logic := '0');
368  port(
369  ipb_clk : IN std_logic;
370  UsRclk : IN std_logic;
371  DRPclk : IN std_logic;
372  got_SN : out std_logic;
373  reset : IN std_logic;
374  GTX_RESET : IN std_logic;
375  GbE_REFCLK : in std_logic;
376  S6LINK_RXN : in std_logic;
377  S6LINK_RXP : in std_logic;
378  S6LINK_TXN : out std_logic;
379  S6LINK_TXP : out std_logic;
380  wr_amc_en : in std_logic;
381  amc_en : in STD_LOGIC_VECTOR(11 downto 0);
382  en_RARP : in std_logic;
383  IPADDR : in STD_LOGIC_VECTOR(31 downto 0);
384  MACADDR : in STD_LOGIC_VECTOR(47 downto 0);
385  ipb_out : out ipb_wbus;
386  ipb_in : in ipb_rbus;
387  SN : out STD_LOGIC_VECTOR(8 downto 0);
388  debug_in : IN std_logic_vector(31 downto 0);
389  debug_out : OUT std_logic_vector(127 downto 0)
390  );
391 end COMPONENT;
392 COMPONENT sysmon_if
393  PORT(
394  DRPclk : IN std_logic;
395  DB_cmd : IN std_logic;
396  SN : IN std_logic_vector(8 downto 0);
397  VAUXN_IN : IN std_logic_vector(12 downto 0);
398  VAUXP_IN : IN std_logic_vector(12 downto 0);
399  addr : IN std_logic_vector(15 downto 0);
400  data : OUT std_logic_vector(31 downto 0);
401  device_temp : OUT std_logic_vector(11 downto 0);
402  ALM : OUT std_logic_vector(7 downto 0);
403  OT : OUT std_logic
404  );
405 END COMPONENT;
406 COMPONENT TCPIP_if
407  generic (simulation : boolean := false; en_KEEPALIVE : std_logic := '0');
408  Port ( sysclk : in STD_LOGIC;
409  DRPclk : in STD_LOGIC;
410  reset : in STD_LOGIC;
411  TCPreset : in STD_LOGIC;
412  rstCntr : in STD_LOGIC;
413  test : in STD_LOGIC;
414  Dis_pd : in STD_LOGIC;
415  enSFP : IN std_logic_vector(3 downto 0);
416  SFP_down : OUT std_logic_vector(2 downto 0);
417  inc_ddr_pa : in STD_LOGIC;
418 -- event data in
419  evt_data_rdy : in std_logic_vector(2 downto 0);
420  EventData_in : in array3X67;
421  EventData_we : in std_logic_VECTOR(2 downto 0);
422  EventData_re : out std_logic_VECTOR(2 downto 0); --
423  evt_buf_full : out std_logic_vector(2 downto 0);
424  buf_rqst : in std_logic_vector(3 downto 0);
425  WaitMonBuf : IN std_logic;
426  MonBufOverWrite : in STD_LOGIC;
427  TCPBuf_avl : out STD_LOGIC;
428  MonBuf_avl : out STD_LOGIC;
429  MonBuf_empty : out STD_LOGIC;
430  MonBufOvfl : out STD_LOGIC;
431  mon_evt_cnt : out std_logic_vector(31 downto 0);
432  WrtMonBlkDone : in STD_LOGIC_VECTOR(2 downto 0);
433  WrtMonEvtDone : in STD_LOGIC_VECTOR(2 downto 0);
434  KiloByte_toggle : in STD_LOGIC_VECTOR(2 downto 0);
435  EoB_toggle : in STD_LOGIC_VECTOR(2 downto 0);
436 -- ddr wportA status
437  wport_rdy : in std_logic_vector(2 downto 0);
438  wport_FIFO_full : in std_logic_vector(2 downto 0);
439 -- signal to ddr_if, AMC_if to start moving data
440  EventBufAddr_we : out std_logic_VECTOR(2 downto 0);
441  EventBufAddr : out array3X14;
442 -- ddr wportB signals in sysclk domain
443  TCPclk : out STD_LOGIC;
444  TCP_dout : out std_logic_vector(31 downto 0); -- TCP data are written in unit of 32-bit words
445  TCP_channel : out std_logic_vector(1 downto 0); -- Each entry has four 32bit words, each address saves two entries. Addresses are kept in ddr_wportB
446  TCP_we : out STD_LOGIC;
447  TCP_wcount : in STD_LOGIC_VECTOR (2 downto 0);
448 -- ddr rport signals
449  TCP_raddr : out STD_LOGIC_VECTOR(28 downto 0); -- 28-26 encoded request source 25-0 address in 64 bit word
450  TCP_length : out STD_LOGIC_VECTOR(10 downto 0); -- in 64 bit word, actual length - 1
451  TCP_rrqst : out STD_LOGIC;
452  TCP_rack : in STD_LOGIC;
453  TCP_din : in STD_LOGIC_VECTOR(31 downto 0); -- TCP data are written in unit of 32-bit words
454  TCP_din_type : in STD_LOGIC_VECTOR(2 downto 0); -- TCP data destination
455  TCP_din_valid : in STD_LOGIC;
456  TCP_lastword : in STD_LOGIC;
457 -- SFP ports
458  SFP0_RXN : in STD_LOGIC;
459  SFP0_RXP : in STD_LOGIC;
460  SFP1_RXN : in STD_LOGIC;
461  SFP1_RXP : in STD_LOGIC;
462  SFP2_RXN : in STD_LOGIC;
463  SFP2_RXP : in STD_LOGIC;
464  SFP0_TXN : out STD_LOGIC;
465  SFP0_TXP : out STD_LOGIC;
466  SFP1_TXN : out STD_LOGIC;
467  SFP1_TXP : out STD_LOGIC;
468  SFP2_TXN : out STD_LOGIC;
469  SFP2_TXP : out STD_LOGIC;
470  SFP_REFCLK_N : in STD_LOGIC;
471  SFP_REFCLK_P : in STD_LOGIC;
472  cs_out : out STD_LOGIC_VECTOR(511 downto 0);
473 -- ipbus signals
474  ipb_clk : in STD_LOGIC;
475  ipb_write : in STD_LOGIC;
476  ipb_strobe : in STD_LOGIC;
477  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
478  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
479  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0)
480  );
481 END COMPONENT;
482 COMPONENT TTC_cntr
483  PORT(
484  sysclk : IN std_logic;
485  clk125 : IN std_logic;
486  ipb_clk : IN std_logic;
487  reset : IN std_logic;
488  rst_cntr : IN std_logic;
489  DB_cmd : IN std_logic;
490  inc_serr : IN std_logic;
491  inc_derr : IN std_logic;
492  inc_bcnterr : IN std_logic;
493  inc_l1ac : IN std_logic;
494  run : IN std_logic;
495  state : IN std_logic_vector(3 downto 0);
496  ttc_resync : IN std_logic;
497  ipb_addr : IN std_logic_vector(15 downto 0);
498  ipb_rdata : OUT std_logic_vector(31 downto 0)
499  );
500 END COMPONENT;
501 constant ipbus_ver_addr : std_logic_vector(15 downto 0) := x"0000";
502 constant ipbus_sfp_addr: std_logic_vector(15 downto 0) := x"0002";
503 constant CDRclk_pol : std_logic := '0';
504 constant CDRdata_pol : std_logic := '1';
505 constant TTCclk_pol : std_logic := '1';
506 constant TTCdata_pol : std_logic := '1';
507 constant Coarse_Delay: std_logic_vector(3 downto 0) := x"0";
508 signal rst_ipbus : std_logic := '0';
509 signal LDC_UsrClk : std_logic := '0';
510 signal wr_AMC_en : std_logic := '0';
511 signal fake_length : std_logic_vector(19 downto 0) := x"00400";
512 signal AMC_en : std_logic_vector(11 downto 0) := (others =>'0');
513 signal TTS_disable : std_logic_vector(11 downto 0) := (others =>'0');
514 signal AMC_Ready : std_logic_vector(11 downto 0) := (others =>'0');
515 signal BC0_lock : std_logic_vector(11 downto 0) := (others =>'0');
516 signal AMC_status : std_logic_vector(31 downto 0) := (others =>'0');
517 signal AMC_DATA : std_logic_vector(31 downto 0) := (others =>'0');
518 signal AMC_ack : std_logic := '0';
519 signal L1Aovfl_warning : std_logic := '0';
520 signal TTS_coded : std_logic_vector(4 downto 0) := (others =>'0');
521 --signal AMC_trig : std_logic := '0';
522 signal pattern : std_logic_vector(3 downto 0) := (others =>'0');
523 signal SPI_SCK_buf : std_logic := '0';
524 signal CLK_rdy : std_logic := '0';
525 signal I2C_data : std_logic_vector(31 downto 0) := (others =>'0');
526 signal TTCclk_in : std_logic := '0';
527 signal TTC_Clk : std_logic := '0';
528 signal TTC_strobe : std_logic := '0';
529 signal BcntErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
530 signal SinErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
531 signal DbErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
532 signal L1_reg : std_logic_vector(15 downto 0) := (others =>'0');
533 signal Bcnt_reg : std_logic_vector(11 downto 0) := (others =>'0');
534 signal OC_reg : std_logic_vector(31 downto 0) := (others =>'0');
535 signal V2S : std_logic := '0';
536 signal S2V : std_logic := '0';
537 signal S2V_cntr : std_logic_vector(5 downto 0) := (others => '0');
538 signal S2V_sr : std_logic_vector(3 downto 0) := (others => '0');
539 signal ddr_rdata : std_logic_vector(7 downto 0) := (others =>'0');
540 signal ipb_clk_dcm : std_logic := '0';
541 signal ipb_clk : std_logic := '0';
542 signal clk125_dcm : std_logic := '0';
543 signal clk125 : std_logic := '0';
544 signal DRPclk_dcm : std_logic := '0';
545 signal DRPclk : std_logic := '0';
546 signal sysclk_dcm : std_logic := '0';
547 signal sysclk : std_logic := '0';
548 signal TCPclk : std_logic := '0';
549 signal clkfb : std_logic := '0';
550 signal refclk_dcm : std_logic := '0';
551 signal refclk : std_logic := '0';
552 signal mem_clk_dcm : std_logic := '0';
553 signal mem_clk : std_logic := '0';
554 signal sysclk_inp : std_logic := '0';
555 signal sysclk_in : std_logic := '0';
556 --signal clk125 : std_logic := '0';
557 signal sys_lock : std_logic := '0';
558 signal sys_lock_n : std_logic := '0';
559 signal ldc_reset : std_logic := '0';
560 signal ldc_GTXreset : std_logic := '0';
561 signal lsc_reset : std_logic := '0';
562 signal TCPIP_GTXreset : std_logic := '0';
563 signal amc_reset : std_logic := '0';
564 signal amc_GTXreset : std_logic := '0';
565 signal conf7_q : std_logic := '0';
566 signal conf7_fall : std_logic := '0';
567 signal run : std_logic := '0';
568 signal LSC_LinkDown : std_logic := '0';
569 signal mem_rst : std_logic := '0';
570 signal mem_test : std_logic_vector(1 downto 0) := (others =>'0');
571 signal mem_stat : std_logic_vector(63 downto 0) := (others =>'0');
572 signal mem_ack : std_logic := '0';
573 signal mem_data : std_logic_vector(31 downto 0) := (others =>'0');
574 signal EventData : array3X67 := (others => (others => '0'));
575 signal wport_rdy : std_logic_vector(2 downto 0) := (others =>'0');
576 signal EventBufAddr : array3x14 := (others => (others => '0'));
577 signal EventBufAddr_we : std_logic_vector(2 downto 0) := (others =>'0');
578 signal evt_buf_full : std_logic_vector(2 downto 0) := (others =>'0');
579 signal wport_FIFO_full : std_logic_vector(2 downto 0) := (others =>'0');
580 signal TCP_din : std_logic_vector(31 downto 0) := (others =>'0');
581 signal TCP_channel : std_logic_vector(1 downto 0) := (others =>'0');
582 signal TCP_we : std_logic := '0';
583 signal TCP_wcount : std_logic_vector(2 downto 0) := (others =>'0');
584 signal TCP_dout : std_logic_vector(31 downto 0) := (others =>'0');
585 signal TCP_dout_type : std_logic_vector(2 downto 0) := (others =>'0');
586 signal TCP_raddr : std_logic_vector(28 downto 0) := (others =>'0');
587 signal TCP_length : std_logic_vector(10 downto 0) := (others =>'0');
588 signal TCP_dout_valid : std_logic := '0';
589 signal TCP_rrqst : std_logic := '0';
590 signal TCP_rack : std_logic := '0';
591 signal TCP_lastword : std_logic := '0';
592 signal MonBufOvfl : std_logic := '0';
593 signal MonBuf_empty : std_logic := '0';
594 signal mon_evt_wc : std_logic_vector(47 downto 0) := (others =>'0');
595 signal mon_evt_cnt : std_logic_vector(31 downto 0) := (others =>'0');
596 signal mon_ctrl : std_logic_vector(31 downto 0) := (others =>'0');
597 signal TCPbuf_avl : std_logic := '0';
598 signal mon_buf_avl : std_logic := '0';
599 signal EventBufAddrAvl : std_logic := '0';
600 signal EventBufAddrRe : std_logic := '0';
601 signal mon_wp : std_logic_vector(31 downto 0) := (others =>'0');
602 signal EventBuf_rqst : std_logic_vector(3 downto 0) := (others =>'0');
603 signal rst_cntr : std_logic := '0';
604 signal rst_ddr_pa : std_logic := '0';
605 signal inc_ddr_pa : std_logic := '0';
606 signal Source_ID : array3x12 := (others => (others => '0'));
607 signal ddr_pa : std_logic_vector(9 downto 0) := (others =>'0');
608 signal CDRclk : std_logic := '0';
609 signal TTS_clk : std_logic := '0';
610 signal BC0 : std_logic := '0';
611 --signal BC0_dlp : std_logic := '0';
612 --signal BC0_dlp2 : std_logic := '0';
613 --signal BC0_dl : std_logic := '0';
614 signal T3_trigger : std_logic := '0';
615 --signal BC0_delay : std_logic_vector(4 downto 0) := "11000";
616 --signal bcnt : std_logic_vector(3 downto 0) := x"0";
617 signal LocalL1A_cfg : std_logic_vector(31 downto 0) := (others =>'0');
618 signal BCN_off : std_logic_vector(12 downto 0) := (others =>'0');
619 signal OC_off : std_logic_vector(3 downto 0) := (others =>'0');
620 signal en_cal_win : std_logic := '0';
621 signal CalibCtrl : std_logic_vector(31 downto 0) := x"0d800d80";
622 signal cal_win_high : std_logic_vector(11 downto 0) := (others =>'0');
623 signal cal_win_low : std_logic_vector(11 downto 0) := (others =>'0');
624 signal CalType : std_logic_vector(3 downto 0) := (others =>'0');
625 signal TTC_Brcst : std_logic_vector(3 downto 0) := (others =>'0');
626 signal local_TTCcmd : std_logic := '0';
627 signal en_brcst : std_logic := '0';
628 signal ttc_start : std_logic := '0';
629 signal ttc_stop : std_logic := '0';
630 signal ttc_soft_reset : std_logic := '0';
631 signal ttc_soft_resetp : std_logic := '0';
632 signal ttc_ready : std_logic := '0';
633 signal ttc_serr : std_logic := '0';
634 signal ttc_derr : std_logic := '0';
635 signal ttc_bcnt_err : std_logic := '0';
636 signal ttc_evcnt_reset : std_logic := '0';
637 signal inc_rate_ofw : std_logic := '0';
638 signal rate_ofw : std_logic := '0';
639 signal rate_ofwp : std_logic := '0';
640 signal rate_ofw_q : std_logic := '0';
641 signal sync_lost : std_logic := '0';
642 signal oc_cntr : std_logic_vector(3 downto 0) := (others =>'0');
643 signal ttc_resync : std_logic := '0';
644 signal AllEventBuilt : std_logic := '0';
645 signal dcc_quiet : std_logic := '0';
646 signal inc_oc : std_logic := '0';
647 signal inc_L1ac : std_logic := '0';
648 signal inc_bcnterr : std_logic := '0';
649 signal inc_serr : std_logic := '0';
650 signal inc_derr : std_logic := '0';
651 signal evn_fifo_full : std_logic := '0';
652 signal event_number_avl : std_logic := '0';
653 signal state : std_logic_vector(3 downto 0) := (others =>'0');
654 signal TTS_wait : std_logic_vector(20 downto 0) := (others =>'0');
655 signal event_number : std_logic_vector(59 downto 0) := (others =>'0');
656 --signal TTC_serr_cntr : std_logic_vector(7 downto 0) := (others =>'0');
657 --signal TTC_derr_cntr : std_logic_vector(7 downto 0) := (others =>'0');
658 --signal TTC_BcntErr_cntr : std_logic_vector(7 downto 0) := (others =>'0');
659 --signal L1A_cntr : std_logic_vector(7 downto 0) := (others =>'0');
660 --signal run_cntr : std_logic_vector(7 downto 0) := (others =>'0');
661 --signal ready_cntr : std_logic_vector(7 downto 0) := (others =>'0');
662 --signal busy_cntr : std_logic_vector(7 downto 0) := (others =>'0');
663 --signal sync_cntr : std_logic_vector(7 downto 0) := (others =>'0');
664 --signal ovfl_cntr : std_logic_vector(7 downto 0) := (others =>'0');
665 signal ReSync_cntr : std_logic_vector(15 downto 0) := (others =>'0');
666 --signal counter_we : std_logic_vector(3 downto 0) := (others => '0');
667 --signal counter_wa : std_logic_vector(9 downto 0) := (others => '0');
668 --signal counter_ra_l : std_logic_vector(9 downto 0) := (others => '0');
669 --signal counter_ra_h : std_logic_vector(9 downto 0) := (others => '0');
670 --signal CounterDi : std_logic_vector(47 downto 0) := (others => '0');
671 --signal CounterDoA : std_logic_vector(47 downto 0) := (others => '0');
672 --signal CounterDoB : std_logic_vector(63 downto 0) := (others => '0');
673 --signal div : std_logic_vector(7 downto 0) := (others =>'0');
674 --signal CntrRst : std_logic := '0';
675 --signal CntrRstCycle : std_logic := '0';
676 --signal CounterDoB_h : std_logic := '0';
677 signal TTC_cntr_data : std_logic_vector(31 downto 0) := (others => '0');
678 signal got_SN : std_logic := '0';
679 signal ipb_strobe_q : std_logic := '0';
680 signal SFP_clk : std_logic := '0';
681 signal AMC_clk : std_logic := '0';
682 signal AMC_clk_in : std_logic := '0';
683 signal SV_Cntr : std_logic_vector(7 downto 0) := (others => '0');
684 signal sysclk_div : std_logic_vector(7 downto 0) := (others => '0');
685 signal SFP_UsrClk : std_logic := '0';
686 signal SFP_TxOutClk : std_logic := '0';
687 signal I2C_debug_out : std_logic_vector(15 downto 0) := (others =>'0');
688 signal SFPOSC_rdy : std_logic := '0';
689 signal reset : std_logic := '0';
690 signal cmd0_dl : std_logic_vector(1 downto 0) := (others =>'0');
691 signal DAQ_reset : std_logic := '0';
692 signal AMCOSC_rdy : std_logic := '0';
693 signal TTC_debug : std_logic_vector(63 downto 0) := (others =>'0');
694 signal TxDisable_i : std_logic_vector(3 downto 0) := (others => '0');
695 signal DAQfifo_re : std_logic := '0';
696 signal DAQfifoAlmostEmpty : std_logic := '0';
697 signal DAQfifoEmpty : std_logic := '0';
698 signal DAQfifo_do : std_logic_vector(63 downto 0) := (others =>'0');
699 signal DAQ_debug_in : std_logic_vector(63 downto 0) := (others =>'0');
700 signal LDC_debug_out : std_logic_vector(63 downto 0) := (others =>'0');
701 signal LSC_debug_out : std_logic_vector(63 downto 0) := (others =>'0');
702 signal ddr_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
703 signal ddr_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
704 signal GbE_REFCLK : std_logic := '0';
705 signal S6Link_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
706 signal S6Link_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
707 signal GbE_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
708 signal GbE_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
709 signal AMC_debug_in : std_logic_vector(255 downto 0) := (others =>'0');
710 signal AMC_debug_out : std_logic_vector(255 downto 0) := (others =>'0');
711 signal SFP0_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
712 signal SFP0_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
713 signal SFP1_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
714 signal SFP1_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
715 signal ipb_master_out : ipb_wbus;
716 signal ipb_master_in : ipb_rbus;
717 signal SN : std_logic_vector(8 downto 0) := (others =>'0');
718 signal MACADDR : std_logic_vector(47 downto 0) := (others =>'0');
719 signal ipaddr : std_logic_vector(31 downto 0) := (others =>'0');
720 signal en_RARP : std_logic := '0';
721 signal status : std_logic_vector(31 downto 0) := (others =>'0');
722 signal cmd : std_logic_vector(31 downto 0) := (others =>'0');
723 signal conf : std_logic_vector(15 downto 0) := (others =>'0');
724 signal OT : std_logic := '0';
725 signal inc_HTRCRC_err : std_logic := '0';
726 signal ttc_data : std_logic_vector(31 downto 0) := (others => '0');
727 signal sysmon_data : std_logic_vector(31 downto 0) := (others => '0');
728 signal device_temp : std_logic_vector(11 downto 0) := (others =>'0');
729 signal ALM : std_logic_vector(7 downto 0) := (others =>'0');
730 signal evt_data_rdy : std_logic_vector(2 downto 0) := (others => '0');
731 signal evt_data_re : std_logic_vector(2 downto 0) := (others => '0');
732 signal evt_data_we : std_logic_vector(2 downto 0) := (others => '0');
733 signal SFP_data : std_logic_vector(31 downto 0) := (others =>'0');
734 signal SFP_ack : std_logic := '0';
735 signal S2V_SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
736 signal resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
737 signal sysclk_div7SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
738 signal resetCntr_SyncRegs : std_logic_vector(2 downto 0) := (others =>'0');
739 signal newIPADDR : std_logic := '0';
740 signal newIPADDRSyncRegs : std_logic_vector(2 downto 0) := (others =>'0');
741 signal DNA_out : std_logic := '0';
742 signal shift_DNA : std_logic := '0';
743 signal load_DNA : std_logic_vector(1 downto 0) := (others =>'0');
744 signal DNA_cntr : std_logic_vector(5 downto 0) := (others =>'0');
745 signal DNA : std_logic_vector(56 downto 0) := (others =>'0');
746 signal Dis_pd : std_logic := '0';
747 signal WaitMonBuf : std_logic := '0';
748 signal enSFP : std_logic_vector(3 downto 0) := (others =>'0');
749 signal SFP_down : std_logic_vector(2 downto 0) := (others =>'0');
750 signal WrtMonBlkDone : std_logic_vector(2 downto 0) := (others =>'0');
751 signal WrtMonEvtDone : std_logic_vector(2 downto 0) := (others =>'0');
752 signal KiloByte_toggle : std_logic_vector(2 downto 0) := (others =>'0');
753 signal EoB_toggle : std_logic_vector(2 downto 0) := (others =>'0');
754 signal TCP_cs_out : std_logic_vector(511 downto 0) := (others =>'0');
755 signal ddr_cs_out : std_logic_vector(511 downto 0) := (others =>'0');
756 component icon2
757  PORT (
758  CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
759  CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
760 
761 end component;
762 component ila16x32k
763  PORT (
764  CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
765  CLK : IN STD_LOGIC;
766  DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
767  TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
768 
769 end component;
770 signal CONTROL0 : std_logic_vector(35 downto 0) := (others => '0');
771 signal CONTROL1 : std_logic_vector(35 downto 0) := (others => '0');
772 signal TRIG0 : std_logic_vector(7 downto 0) := (others => '0');
773 signal TRIG1 : std_logic_vector(7 downto 0) := (others => '0');
774 signal DATA0 : std_logic_vector(15 downto 0) := (others => '0');
775 signal DATA1 : std_logic_vector(15 downto 0) := (others => '0');
776 component chipscope1
777  generic (N : integer := 2);
778  Port ( clk : in STD_LOGIC;
779  Din : in STD_LOGIC_VECTOR (303 downto 0));
780 end component;
781 signal CS : STD_LOGIC_VECTOR(303 DOWNTO 0) := (others => '0');
782 COMPONENT chipscope1b
783  generic (USER2 : boolean := false);
784  PORT(
785  clk : IN std_logic;
786  Din : IN std_logic_vector(303 downto 0)
787  );
788 END COMPONENT;
789 begin
790 --i_chipscope1: chipscope1b PORT MAP(
791 -- clk => TCPclk,
792 -- Din => cs
793 -- );
794 --cs(288) <= TCP_cs_out(122);
795 --cs(287 downto 122) <= ddr_cs_out(165 downto 0);
796 --cs(121 downto 0) <= TCP_cs_out(121 downto 0);
797 --i_chipscope : chipscope1 port map(clk => sysclk, Din => cs);
798 --cs(298 downto 296) <= EventBufAddr_we;
799 --cs(293 downto 291) <= evt_data_re;
800 --cs(290 downto 288) <= evt_data_we;
801 --cs(251) <= evt_data_re(2);
802 --cs(250) <= evt_data_re(1);
803 --cs(249) <= EventBufAddr_we(2);
804 --cs(248 downto 235) <= EventBufAddr(2);
805 --cs(234) <= EventBufAddr_we(1);
806 --cs(233 downto 220) <= EventBufAddr(1);
807 --cs(219) <= evt_data_we(2);
808 --cs(218 downto 152) <= EventData(2);
809 --cs(151) <= evt_data_we(1);
810 --cs(150 downto 84) <= EventData(1);
811 --cs(83) <= evt_data_re(0);
812 --cs(82) <= EventBufAddr_we(0);
813 --cs(81 downto 68) <= EventBufAddr(0);
814 --cs(67) <= evt_data_we(0);
815 --cs(66 downto 0) <= EventData(0);
816 --i_icon : icon2
817 -- port map (
818 -- CONTROL0 => CONTROL0,
819 -- CONTROL1 => CONTROL1);
820 --i_ila : ila16x32k
821 -- port map (
822 -- CONTROL => CONTROL0,
823 -- CLK => sysclk,
824 -- DATA => DATA0,
825 -- TRIG0 => TRIG0);
826 --DATA0(14) <= evt_buf_full(0);
827 --DATA0(13) <= evt_data_re(0);
828 --DATA0(12) <= evt_data_rdy(0);
829 --DATA0(11 downto 10) <= EventBufAddr(0)(5 downto 4);
830 --DATA0(9 downto 8) <= EventData(0)(65 downto 64);
831 --DATA0(7) <= wport_rdy(0);
832 --DATA0(6) <= wport_FIFO_full(0);
833 --DATA0(5) <= evt_data_we(0);
834 --DATA0(4) <= EventBufAddr_we(0);
835 --DATA0(3 downto 0) <= mem_stat(3 downto 0);
836 --TRIG0(7 downto 4) <= (others => '0');
837 --TRIG0(3) <= wport_rdy(0);
838 --TRIG0(2) <= EventBufAddr_we(0);
839 --TRIG0(1) <= evt_data_re(0);
840 --TRIG0(0) <= evt_data_rdy(0);
841 --
842 --i_il2 : ila16x32k
843 -- port map (
844 -- CONTROL => CONTROL1,
845 -- CLK => mem_stat(19),
846 -- DATA => DATA1,
847 -- TRIG0 => TRIG1);
848 --DATA1(14 downto 0) <= mem_stat(18 downto 4);
849 --TRIG1(7 downto 2) <= (others => '0');
850 --TRIG1(1 downto 0) <= mem_stat(18 downto 17);
851 i_TTS_if: TTS_if PORT MAP(
852  sysclk => sysclk,
853  TTS_clk => TTS_clk,
854  reset => sys_lock_n,
855  local_TTC => conf(8),
856  TTS => state,
857  TTS_out_p => TTS_out_p,
858  TTS_out_n => TTS_out_n
859  );
860 --process(TTC_Clk)
861 --begin
862 -- if(TTC_Clk'event and TTC_Clk = '1')then
863 -- BC0_dl <= BC0_dlp2;
864 -- if(BC0_dlp2 = '1')then
865 -- bcnt <= x"0";
866 -- else
867 -- bcnt <= bcnt + 1;
868 -- end if;
869 -- end if;
870 --end process;
871 TxDisable <= TxDisable_i;
872 i_I2C: I2C PORT MAP(
873  clk => DRPclk ,
874  ipb_clk => clk125,
875  reset => sys_lock_n,
876  addr => ipb_master_out.ipb_addr,
877  rdata => I2C_data,
878  CLK_rdy => CLK_rdy,
879  CLK_SCL => CLK_SCL ,
880  CLK_SDA => CLK_SDA,
881  SFP_ABS => SFP_ABS,
882  SFP_LOS => SFP_LOS,
883  SFP_SCL => SFP_SCL,
884  SFP_SDA => SFP_SDA
885  );
886 i_SPI_SCK_buf: bufh port map(i => SPI_SCK, o => SPI_SCK_buf);
887 i_SPI_if: SPI_if PORT MAP(
888  SCK => SPI_SCK ,
889  CSn => SPI_CS_b ,
890  MOSI => SPI_MOSI ,
891  MISO => SPI_MISO ,
892  SN => SN,
893  OT => ALM(0),
894  IsT1 => '1',
895  SPI_we => open,
896  en_RARP => en_RARP,
897  newIPADDR => newIPADDR,
898  IPADDR => IPADDR,
899  SPI_rdata => (others => '0'),
900  SPI_wdata => open,
901  SPI_addr => open
902  );
903 i_ttc_if: ttc_if PORT MAP(
904  clk => sysclk ,
905  refclk => sysclk,
906  reset => reset,
907  run => run,
908  IsG2 => '1',
909  TTC_strobe => TTC_strobe,
910  sys_lock => sys_lock,
911  local_TTC => conf(8),
912  local_TTCcmd => local_TTCcmd ,
913  single_TTCcmd => cmd(8),
914  TTS_clk => TTS_clk,
915  BC0 => BC0,
916  DIV4 => DIV4,
917  DIV_nRST => DIV_nRST,
918  CDRclk_p => CDRclk_p,
919  CDRclk_n => CDRclk_n,
920  CDRclk_out => CDRclk,
921  CDRdata_p => CDRdata_p,
922  CDRdata_n => CDRdata_n,
923  TTCdata_p => TTCdata_p,
924  TTCdata_n => TTCdata_n,
925  TTC_LOS => TTC_LOS,
926  TTC_LOL => TTC_LOL,
927  BCN_off => BCN_off,
928  OC_off => OC_off,
929  en_cal_win => en_cal_win,
930  cal_win_high => cal_win_high ,
931  cal_win_low => cal_win_low ,
932  CalType => CalType,
933  TTC_Brcst => TTC_Brcst,
934  ovfl_warning => L1Aovfl_warning ,
935  ipb_clk => ipb_clk,
936  ipb_write => ipb_master_out.ipb_write ,
937  ipb_strobe => ipb_master_out.ipb_strobe ,
938  ipb_addr => ipb_master_out.ipb_addr ,
939  ipb_wdata => ipb_master_out.ipb_wdata ,
940  ipb_rdata => ttc_data,
941  en_localL1A => conf(2),
942  LocalL1A_cfg => LocalL1A_cfg ,
943  localL1A_s => cmd(26),
944  localL1A_r => cmd(10),
945  T3_trigger => T3_trigger,
946  localL1A_periodic => status(10),
947  EvnRSt_l => cmd(11),
948  OcnRSt_l => cmd(12),
949  en_brcst => en_brcst,
950  ttc_start => ttc_start,
951  ttc_stop => ttc_stop,
952  ttc_soft_reset => ttc_soft_reset ,
953  ttc_ready => ttc_ready,
954  ttc_serr => ttc_serr,
955  ttc_derr => ttc_derr,
956  ttc_bcnt_err => ttc_bcnt_err ,
957  rate_OFW => rate_OFW,
958  sync_lost => sync_lost,
959  inc_oc => inc_oc,
960  inc_l1ac => inc_l1ac,
961  inc_bcnterr => inc_bcnterr ,
962  inc_serr => inc_serr,
963  inc_derr => inc_derr,
964  state => state,
965  evn_fifo_full => evn_fifo_full ,
966  ttc_evcnt_reset => ttc_evcnt_reset ,
967  event_number_avl => event_number_avl ,
968  event_number => event_number
969  );
970 local_TTCcmd <= conf(5) or conf(8);
971 CalibCtrl(31) <= en_cal_win;
972 CalibCtrl(30 downto 28) <= "000";
973 CalibCtrl(27 downto 16) <= cal_win_high;
974 CalibCtrl(15 downto 12) <= CalType;
975 CalibCtrl(11 downto 0) <= cal_win_low;
976 cal_win_high(11 downto 6) <= "110110";
977 cal_win_low(11 downto 6) <= "110110";
978 i_S2V: IBUFDS generic map(DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25") port map(i => S2V_p, ib => S2V_n, o => S2V);
979 --i_V2S: OBUFDS generic map(IOSTANDARD => "LVDS_25") port map (O => V2S_p, OB => V2S_n, I => sysclk_div(7));
980 --process(sysclk)
981 --begin
982 -- if(sysclk'event and sysclk = '1')then
983 ---- SPI_we_SyncRegs <= SPI_we_SyncRegs(1 downto 0) & SPI_we;
984 ---- SPI_wr(0) <= SPI_we_SyncRegs(2) and not SPI_we_SyncRegs(1);
985 -- sysclk_div <= sysclk_div + 1;
986 -- sysclk_div7SyncRegs <= sysclk_div7SyncRegs(2 downto 0) & S2V;
987 -- if(resetSyncRegs(2) = '1')then
988 -- SV_Cntr <= (others => '0');
989 -- elsif(and_reduce(sysclk_div(6 downto 0)) = '1')then
990 -- SV_Cntr <= SV_Cntr + 1;
991 -- elsif(sysclk_div7SyncRegs(3) /= sysclk_div7SyncRegs(2))then
992 -- SV_Cntr <= SV_Cntr - 1;
993 -- end if;
994 -- end if;
995 --end process;
996 process(CDRclk)
997 begin
998  if(CDRclk'event and CDRclk = '1')then
999  if(conf(15) = '0')then
1000  T3_trigger <= '0';
1001  else
1002  T3_trigger <= S2V;
1003  end if;
1004  end if;
1005 end process;
1006 i_GbE_REFCLK: IBUFDS_GTE2
1007  port map
1008  (
1009  O => GbE_REFCLK,
1010  ODIV2 => open,
1011  CEB => '0',
1012  I => GbE_REFCLK_P, -- Connect to package pin AB6
1013  IB => GbE_REFCLK_N -- Connect to package pin AB5
1014  );
1015 i_TTCclk_in : IBUFGDS generic map (DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25")
1016  port map (
1017  O => TTCclk_in, -- Clock buffer output
1018  I => TTCclk_p, -- Diff_p clock buffer input
1019  IB => TTCclk_n -- Diff_n clock buffer input
1020  );
1021 i_TTC_CLK_buf: bufg port map(i => TTCclk_in, o => TTC_Clk);
1022 i_sysclk_in_buf: bufh port map(i => GbE_REFCLK, o => sysclk_in);
1023 i_PLL_sysclk : PLLE2_BASE
1024  generic map (
1025  BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
1026  CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
1027  CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
1028  CLKIN1_PERIOD => 8.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
1029  -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
1030  CLKOUT0_DIVIDE => 5,
1031  CLKOUT1_DIVIDE => 32,
1032  CLKOUT2_DIVIDE => 20,
1033  DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
1034  REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
1035  STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
1036  )
1037  port map (
1038  -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
1039  CLKOUT0 => sysclk_dcm,
1040  CLKOUT1 => ipb_clk_dcm ,
1041  CLKOUT2 => DRPclk_dcm,
1042  -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
1043  CLKFBOUT => clk125_dcm, -- 1-bit output: Feedback clock
1044  -- Status Port: 1-bit (each) output: PLL status ports
1045  LOCKED => sys_lock, -- 1-bit output: LOCK
1046  -- Clock Input: 1-bit (each) input: Clock input
1047  CLKIN1 => sysclk_in, -- 1-bit input: Input clock
1048  -- Control Ports: 1-bit (each) input: PLL control ports
1049  PWRDWN => '0', -- 1-bit input: Power-down
1050  RST => '0', -- 1-bit input: Reset
1051  -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
1052  CLKFBIN => clk125 -- 1-bit input: Feedback clock
1053  );
1054 i_clk125_buf: bufg port map(i => clk125_dcm, o => clk125 );
1055 i_ipb_clk_buf: bufg port map(i => ipb_clk_dcm, o => ipb_clk);
1056 i_DRPclk_buf: bufg port map(i => DRPclk_dcm, o => DRPclk );
1057 i_sysclk_buf: bufg port map(i => sysclk_dcm, o => sysclk );
1058 --i_refclk_buf: bufg port map(i => refclk_dcm, o => refclk);
1059 reset <= not sys_lock or cmd(0);
1060 --sysclk <= refclk;
1061 process(sysclk,reset)
1062 begin
1063  if(reset = '1')then
1064  resetSyncRegs <= (others => '1');
1065  elsif(sysclk'event and sysclk = '1')then
1066  resetSyncRegs <= resetSyncRegs(1 downto 0) & '0';
1067  end if;
1068 end process;
1069 i_ddr_if: ddr_if PORT MAP(
1070  mem_clk_p => sys_clk_p,
1071  mem_clk_n => sys_clk_n,
1072  mem_rst => mem_rst,
1073  clk_ref => sysclk,
1074  sysclk => sysclk,
1075  TCPclk => TCPclk,
1076  reset => reset,
1077  resetsys => resetSyncRegs(2),
1078  run => run,
1079  mem_test => mem_test,
1080  EventData => EventData,
1081  EventData_we => evt_data_we,
1082  wport_rdy => wport_rdy,
1083  WrtMonBlkDone => WrtMonBlkDone ,
1084  WrtMonEvtDone => WrtMonEvtDone ,
1085  KiloByte_toggle => KiloByte_toggle ,
1086  EoB_toggle => EoB_toggle,
1087  EventBufAddr => EventBufAddr ,
1088  EventBufAddr_we => EventBufAddr_we ,
1089  EventFIFOfull => wport_FIFO_full ,
1090  TCP_din => TCP_din,
1091  TCP_channel => TCP_channel ,
1092  TCP_we => TCP_we,
1093  TCP_wcount => TCP_wcount,
1094  TCP_dout => TCP_dout,
1095  TCP_dout_type => TCP_dout_type ,
1096  TCP_raddr => TCP_raddr,
1097  TCP_length => TCP_length,
1098  TCP_dout_valid => TCP_dout_valid ,
1099  TCP_rrqst => TCP_rrqst,
1100  TCP_rack => TCP_rack,
1101  TCP_lastword => TCP_lastword ,
1102  page_addr => ddr_pa,
1103  cs_out => ddr_cs_out,
1104  ipb_clk => ipb_clk,
1105  ipb_write => ipb_master_out.ipb_write ,
1106  ipb_strobe => ipb_master_out.ipb_strobe ,
1107  ipb_addr => ipb_master_out.ipb_addr ,
1108  ipb_wdata => ipb_master_out.ipb_wdata ,
1109  ipb_rdata => mem_data,
1110  ipb_ack => mem_ack,
1111  mem_stat => mem_stat,
1112  device_temp => device_temp ,
1113  ddr3_dq => ddr3_dq,
1114  ddr3_dm => ddr3_dm,
1115  ddr3_addr => ddr3_addr,
1116  ddr3_ba => ddr3_ba,
1117  ddr3_dqs_p => ddr3_dqs_p,
1118  ddr3_dqs_n => ddr3_dqs_n,
1119  ddr3_ras_n => ddr3_ras_n,
1120  ddr3_cas_n => ddr3_cas_n,
1121  ddr3_we_n => ddr3_we_n,
1122  ddr3_reset_n => ddr3_reset_n ,
1123  ddr3_cke => ddr3_cke,
1124  ddr3_odt => ddr3_odt,
1125  ddr3_ck_p => ddr3_ck_p,
1126  ddr3_ck_n => ddr3_ck_n
1127  );
1128 --mem_rst <= not sys_lock or not CLK_rdy or cmd(5) or cmd(0);
1129 mem_rst <= not sys_lock or not CLK_rdy or cmd(5);
1130 MACADDR <= x"080030f30" & '0' & not SN(8) & '0' & not SN(7 downto 6) & '1' & SN(5 downto 0);
1131 i_ipbus_if: ipbus_if PORT MAP(
1132  ipb_clk => ipb_clk,
1133  UsRclk => clk125,
1134  DRPclk => DRPclk,
1135  reset => rst_ipbus,
1136  GTX_RESET => sys_lock_n,
1137  MACADDR => MACADDR, -- new mac range 08-00-30-F3-00-00 to 08-00-30-F3-00-7F
1138  en_RARP => en_RARP,
1139  IPADDR => IPADDR,
1140  GbE_REFCLK => GbE_REFCLK,
1141  S6LINK_RXN => S6LINK_RXN,
1142  S6LINK_RXP => S6LINK_RXP,
1143  S6LINK_TXN => S6LINK_TXN,
1144  S6LINK_TXP => S6LINK_TXP,
1145  wr_AMC_en => wr_AMC_en,
1146  amc_en => AMC_en,
1147  ipb_out => ipb_master_out,
1148  ipb_in => ipb_master_in,
1149  got_SN => got_SN,
1150  SN => SN,
1151  debug_in => (others => '0'),
1152  debug_out => open
1153  );
1154 --LSC_LinkDown <= '1' when conf(1) = '0' or or_reduce(EnSFP(2 downto 0) and SFP_down) = '1' else '0';
1155 --status(0) <= LSC_LinkDown;
1156 status(0) <= or_reduce(SFP_down);
1157 status(1) <= MonBufOvfl;
1158 status(2) <= mon_evt_cnt(10);
1159 status(3) <= MonBuf_empty;
1160 --status(4) <= mem_stat(0); -- monitor input FIFO overflow
1161 status(5) <= not ttc_ready;
1162 status(6) <= ttc_bcnt_err;
1163 status(7) <= ttc_serr;
1164 status(8) <= ttc_derr;
1165 status(9) <= sync_lost;
1166 status(13) <= L1Aovfl_warning;
1167 status(15) <= mem_stat(63);
1168 status(23) <= '0';
1169 run <= conf(0);
1170 EnSFP(3) <= not conf(1);
1171 mem_test <= conf(6) & conf(4);
1172 --en_brcst <= conf(5);
1173 en_brcst <= '0';
1174 i_cmd0_dl0 : SRL16E
1175  port map (
1176  Q => cmd0_dl(0), -- SRL data output
1177  A0 => '1', -- Select[0] input
1178  A1 => '1', -- Select[1] input
1179  A2 => '1', -- Select[2] input
1180  A3 => '0', -- Select[3] input
1181  CE => '1', -- Clock enable input
1182  CLK => ipb_clk, -- Clock input
1183  D => cmd(0) -- SRL data input
1184  );
1185 i_cmd0_dl1 : SRL16E
1186  port map (
1187  Q => cmd0_dl(1), -- SRL data output
1188  A0 => '1', -- Select[0] input
1189  A1 => '1', -- Select[1] input
1190  A2 => '1', -- Select[2] input
1191  A3 => '0', -- Select[3] input
1192  CE => '1', -- Clock enable input
1193  CLK => ipb_clk, -- Clock input
1194  D => cmd0_dl(0) -- SRL data input
1195  );
1196 process(ipb_clk)
1197 begin
1198  if(ipb_clk'event and ipb_clk = '1')then
1199  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = CSR_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1200  cmd <= ipb_master_out.ipb_wdata;
1201  else
1202  cmd <= (others => '0');
1203 -- cmd(31 downto 1) <= (others => '0');
1204 -- if(reset_dl = '1')then
1205 -- cmd(0) <= '0';
1206 -- end if;
1207  end if;
1208  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = CFG_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1209  conf <= ipb_master_out.ipb_wdata(15 downto 0);
1210  end if;
1211  conf7_q <= conf(7);
1212  conf7_fall <= conf7_q and not conf(7);
1213  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = HTR_EN_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1214  Dis_pd <= ipb_master_out.ipb_wdata(15);
1215  EnSFP(2 downto 0) <= ipb_master_out.ipb_wdata(14 downto 12);
1216  AMC_en <= ipb_master_out.ipb_wdata(11 downto 0);
1217  wr_AMC_en <= '1';
1218  else
1219  wr_AMC_en <= '0';
1220  end if;
1221  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"001a" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1222  TTS_disable <= ipb_master_out.ipb_wdata(11 downto 0);
1223  end if;
1224  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = TTC_cal_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1225  en_cal_win <= ipb_master_out.ipb_wdata(31);
1226  cal_win_high(5 downto 0) <= ipb_master_out.ipb_wdata(21 downto 16);
1227  cal_win_low(5 downto 0) <= ipb_master_out.ipb_wdata(5 downto 0);
1228  end if;
1229 -- if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = BC0_delay_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1230 -- BC0_delay <= ipb_master_out.ipb_wdata(4 downto 0);
1231 -- end if;
1232  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1233  Source_ID(0) <= ipb_master_out.ipb_wdata(11 downto 0);
1234  end if;
1235  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id1_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1236  Source_ID(1) <= ipb_master_out.ipb_wdata(11 downto 0);
1237  end if;
1238  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id2_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1239  Source_ID(2) <= ipb_master_out.ipb_wdata(11 downto 0);
1240  end if;
1241  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"001c" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1242  LocalL1A_cfg <= ipb_master_out.ipb_wdata;
1243  end if;
1244  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SFP_CSR_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1245  TxDisable_i <= ipb_master_out.ipb_wdata(15 downto 12);
1246  end if;
1247  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = TTC_bcnt_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1248  OC_OFF <= ipb_master_out.ipb_wdata(19 downto 16);
1249  BCN_OFF <= ipb_master_out.ipb_wdata(12 downto 0);
1250  end if;
1251  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = fake_length_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1252  fake_length <= ipb_master_out.ipb_wdata(19 downto 0);
1253  end if;
1254  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"0019" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1255  pattern <= ipb_master_out.ipb_wdata(11 downto 8);
1256  end if;
1257  if(reset = '1' or (ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = MON_ctrl_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1'))then
1258  ddr_pa <= (others => '0');
1259  elsif(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = PAGE_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1260  if(run = '1')then
1261  if(MonBuf_empty = '0')then
1262  ddr_pa <= ddr_pa + 1;
1263  end if;
1264  else
1265  ddr_pa <= ipb_master_out.ipb_wdata(9 downto 0);
1266  end if;
1267  end if;
1268  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = PAGE_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1' and run = '1' and MonBuf_empty = '0')then
1269  inc_ddr_pa <= '1';
1270  else
1271  inc_ddr_pa <= '0';
1272  end if;
1273 -- ipb_strobe_q <= ipb_master_out.ipb_strobe;
1274 -- if(ipb_master_out.ipb_addr(27) = '1' or or_reduce(ipb_master_out.ipb_addr(15 downto 11)) = '1')then
1275 -- ipb_master_in.ipb_ack <= mem_ack or AMC_ack;
1276 -- elsif(or_reduce(ipb_master_out.ipb_addr(8 downto 6)) = '1')then
1277 -- ipb_master_in.ipb_ack <= ipb_strobe_q;
1278 -- else
1279 -- ipb_master_in.ipb_ack <= ipb_master_out.ipb_strobe;
1280 -- end if;
1281  end if;
1282 end process;
1283 ipb_master_in.ipb_ack <= ipb_master_out.ipb_strobe when ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(17) = '0' else mem_ack;
1284 process(ipb_master_out.ipb_addr)
1285 begin
1286  if(ipb_master_out.ipb_addr(27) = '1' or ipb_master_out.ipb_addr(17) = '1')then
1287  ipb_master_in.ipb_rdata <= mem_data;
1288 -- elsif(ipb_master_out.ipb_addr(20 downto 18) /= "000")then
1289 -- if(ipb_master_out.ipb_addr(0) = '0')then
1290 -- ipb_master_in.ipb_rdata <= mem_stat(31 downto 0);
1291 -- else
1292 -- ipb_master_in.ipb_rdata <= mem_stat(63 downto 32);
1293 -- end if;
1294  elsif(ipb_master_out.ipb_addr(15 downto 5) = CSR_addr(15 downto 5))then
1295  case ipb_master_out.ipb_addr(4 downto 0) is
1296  when "00000" => ipb_master_in.ipb_rdata <= not SN(7 downto 0) & not SN(8) & status(22 downto 0);
1297  when "00001" => ipb_master_in.ipb_rdata <= K7version & conf;
1298  when "00010" => ipb_master_in.ipb_rdata <= mon_ctrl;
1299  when "00011" => ipb_master_in.ipb_rdata <= '0' & SFP_down & AMC_Ready & Dis_pd & EnSFP(2 downto 0) & AMC_en;
1300  when "00100" => ipb_master_in.ipb_rdata <= x"0000" & TxDisable_i & TxFault & (TTC_LOL or TTC_LOL) & SFP_LOS & SFP_ABS;
1301  when "00101" => ipb_master_in.ipb_rdata <= AMC_status;
1302 -- when "00110" => ipb_master_in.ipb_rdata <= x"0" & BC0_lock & x"00" & "000" & BC0_delay;
1303  when "00111" => ipb_master_in.ipb_rdata <= x"00000" & Source_ID(0);
1304  when "01000" => ipb_master_in.ipb_rdata <= x"000" & OC_OFF & "000" & BCN_OFF;
1305  when "01001" => ipb_master_in.ipb_rdata <= CalibCtrl;
1306  when "01010" => ipb_master_in.ipb_rdata <= mem_stat(31 downto 0);
1307  when "01011" => ipb_master_in.ipb_rdata <= mem_stat(63 downto 32);
1308  when "01100" => ipb_master_in.ipb_rdata <= x"00000" & "00" & ddr_pa;
1309  when "01101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(15 downto 0) & '0';
1310  when "01110" => ipb_master_in.ipb_rdata <= mon_evt_cnt;
1311  when "01111" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(31 downto 16) & '0';
1312  when "10000" => ipb_master_in.ipb_rdata <= x"000" & "00" & mon_buf_avl & TCPbuf_avl & '0' & wport_FIFO_full & '0' & wport_rdy & x"0" & '0' & evt_data_rdy;
1313  when "10001" => ipb_master_in.ipb_rdata <= x"00000" & Source_ID(1);
1314  when "10010" => ipb_master_in.ipb_rdata <= x"00000" & Source_ID(2);
1315  when "11000" => ipb_master_in.ipb_rdata <= x"000" & fake_length;
1316  when "11001" => ipb_master_in.ipb_rdata <= x"00" & "000" & TTS_coded & state & pattern & x"00";
1317  when "11010" => ipb_master_in.ipb_rdata <= ReSync_cntr & x"0" & TTS_disable;
1318  when "11100" => ipb_master_in.ipb_rdata <= LocalL1A_cfg;
1319  when "11101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(47 downto 32) & '0';
1320  when "11110" => ipb_master_in.ipb_rdata <= DNA(31 downto 0);
1321  when "11111" => ipb_master_in.ipb_rdata <= "0000000" & DNA(56 downto 32);
1322  when others => ipb_master_in.ipb_rdata <= (others => '0');
1323  end case;
1324  else
1325 -- ipb_master_in.ipb_rdata <= AMC_data or CounterDoB(63 downto 32) or CounterDoB(31 downto 0) or I2C_data or sysmon_data or SFP_data or ttc_data;
1326  ipb_master_in.ipb_rdata <= AMC_data or TTC_cntr_data or I2C_data or sysmon_data or SFP_data or ttc_data;
1327  end if;
1328 end process;
1329 rst_cntr <= cmd(1) or cmd(0);
1330 --process(sysClk, rst_cntr,reset)
1331 --begin
1332 -- if(reset = '1' or rst_cntr = '1')then
1333 -- TTC_serr_cntr <= (others =>'0');
1334 -- TTC_derr_cntr <= (others =>'0');
1335 -- TTC_BcntErr_cntr <= (others =>'0');
1336 -- L1A_cntr <= (others =>'0');
1337 -- run_cntr <= (others =>'0');
1338 -- ready_cntr <= (others =>'0');
1339 -- busy_cntr <= (others =>'0');
1340 -- sync_cntr <= (others =>'0');
1341 -- ovfl_cntr <= (others =>'0');
1342 -- ReSync_cntr <= (others =>'0');
1343 -- elsif(sysClk'event and sysClk = '1')then
1344 -- if(inc_serr = '1')then
1345 -- TTC_serr_cntr <= TTC_serr_cntr + 1;
1346 -- end if;
1347 -- if(inc_derr = '1')then
1348 -- TTC_derr_cntr <= TTC_derr_cntr + 1;
1349 -- end if;
1350 -- if(inc_bcnterr = '1')then
1351 -- TTC_BcntErr_cntr <= TTC_BcntErr_cntr + 1;
1352 -- end if;
1353 -- if(inc_l1ac = '1')then
1354 -- L1A_cntr <= L1A_cntr + 1;
1355 -- end if;
1356 -- if(run = '1')then
1357 -- run_cntr <= run_cntr + 1;
1358 -- if(state(3 downto 2) = "10")then
1359 -- ready_cntr <= ready_cntr + 1;
1360 -- end if;
1361 -- if(state(3 downto 2) = "01")then
1362 -- busy_cntr <= busy_cntr + 1;
1363 -- end if;
1364 -- if(state(3) = '0' and state(1) = '1')then
1365 -- sync_cntr <= sync_cntr + 1;
1366 -- end if;
1367 -- if(state(3) = '0' and state(0) = '1')then
1368 -- ovfl_cntr <= ovfl_cntr + 1;
1369 -- end if;
1370 -- end if;
1371 -- if(ttc_resync = '1')then
1372 -- ReSync_cntr <= ReSync_cntr + 1;
1373 -- end if;
1374 -- end if;
1375 --end process;
1376 ttc_resync <= ttc_soft_reset;
1377 process(sysClk,reset)
1378 begin
1379  if(reset = '1')then
1380  TTS_wait <= (others => '0');
1381  elsif(sysClk'event and sysClk = '1')then
1382  if(ttc_resync = '1')then
1383  TTS_wait <= (others => '0');
1384  elsif(TTS_wait(20) = '0' and sync_lost = '0' and AllEventBuilt = '1')then
1385  TTS_wait <= TTS_wait + 1;
1386  end if;
1387  end if;
1388 end process;
1389 process(sysClk,reset)
1390 begin
1391  if(reset = '1')then
1392  state <= "0100";
1393  elsif(sysClk'event and sysClk = '1')then
1394  if(run = '0' and conf(12) = '1')then
1395  state <= pattern;
1396  elsif(run = '0')then
1397  state <= "0100"; -- changed upon request starting version 0x3023
1398  elsif(ttc_resync = '1')then
1399  state <= "0100";
1400  else
1401  case state is
1402  when "1000" => -- Ready
1403  if(TTS_coded(4) = '1')then
1404  state <= "1111";
1405  elsif(TTS_coded(3) = '1')then
1406  state <= "1100";
1407  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1408  state <= "0010";
1409  elsif(L1Aovfl_warning = '1' or evn_fifo_full = '1' or rate_OFWp = '1' or TTS_coded(1) = '1' or TTS_coded(0) = '1')then
1410  state <= "0001";
1411  end if;
1412  when "0001" => -- OFW
1413  if(TTS_coded(4) = '1')then
1414  state <= "1111";
1415  elsif(TTS_coded(3) = '1')then
1416  state <= "1100";
1417  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1418  state <= "0010";
1419  elsif(evn_fifo_full = '1' or rate_OFWp = '1' or TTS_coded(1) = '1')then
1420  state <= "0100";
1421  elsif(L1Aovfl_warning = '0' and rate_OFWp = '0' and TTS_coded(0) = '0')then
1422  state <= "1000";
1423  end if;
1424  when "0100" => -- Busy
1425  if(TTS_wait(20) = '0')then
1426  elsif(TTS_coded(4) = '1')then
1427  state <= "1111";
1428  elsif(TTS_coded(3) = '1')then
1429  state <= "1100";
1430  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1431  state <= "0010";
1432  elsif(evn_fifo_full = '0' and rate_OFWp = '0' and TTS_coded(1) = '0')then
1433  state <= "0001";
1434  end if;
1435  when others => null; -- x"0" or x"f" disconnected, x"2" OOS, x"c" error
1436  end case;
1437  end if;
1438  end if;
1439 end process;
1440 ipb_master_in.ipb_err <= '0';
1441 --i_BC0_dl2 : SRLC32E
1442 -- port map (
1443 -- Q => BC0_dlp2, -- SRL data output
1444 -- Q31 => open, -- SRL cascade output pin
1445 -- A => "01111", -- 5-bit shift depth select input
1446 -- CE => '1', -- Clock enable input
1447 -- CLK => TTC_clk, -- Clock input
1448 -- D => BC0_dlp -- SRL data input
1449 -- );
1450 --i_BC0_dl : SRLC32E
1451 -- port map (
1452 -- Q => BC0_dlp, -- SRL data output
1453 -- Q31 => open, -- SRL cascade output pin
1454 -- A => BC0_delay, -- 5-bit shift depth select input
1455 -- CE => '1', -- Clock enable input
1456 -- CLK => TTC_clk, -- Clock input
1457 -- D => BC0 -- SRL data input
1458 -- );
1459 WaitMonBuf <= '1' when conf(14) = '1' and (conf(1) = '0' or enSFP(2 downto 0) = "000") else '0';
1460 i_AMC_if: AMC_if PORT MAP(
1461  sysclk => sysclk,
1462  ipb_clk => ipb_clk,
1463  clk125 => clk125 ,
1464  DRPclk => DRPclk,
1465  reset => AMC_reset,
1466  GTXreset => amc_GTXreset,
1467  resetCntr => rst_cntr,
1468  ReSync => ttc_resync,
1469  AllEventBuilt => AllEventBuilt ,
1470  run => run,
1471  Dis_pd => Dis_pd,
1472  enSFP => enSFP,
1473  test => conf(7),
1474  NoReSyncFake => conf(11),
1475  WaitMonBuf => WaitMonBuf,
1476  fake_length => fake_length ,
1477  en_localL1A => conf(2),
1478  T1_version => K7version(7 downto 0),
1479  Source_ID => Source_ID,
1480  AMC_en => AMC_en,
1481  TTS_disable => TTS_disable ,
1482  AMC_Ready => AMC_Ready,
1483  BC0_lock => open,
1484  TTC_lock => open,
1485  AMC_REFCLK_P => AMC_REFCLK_P ,
1486  AMC_REFCLK_N => AMC_REFCLK_N ,
1487  AMC_RXN => AMC_RXN,
1488  AMC_RXP => AMC_RXP,
1489  AMC_TXN => AMC_TXN,
1490  AMC_TXP => AMC_TXP,
1491  AMC_status => AMC_status,
1492  evt_data => EventData,
1493  evt_data_we => evt_data_we ,
1494  evt_buf_full => evt_buf_full ,
1495  evt_data_re => evt_data_re ,
1496  evt_data_rdy => evt_data_rdy ,
1497  ddr_pa => ddr_pa ,
1498  MonBuf_empty => MonBuf_empty ,
1499  mon_evt_wc => mon_evt_wc,
1500  mon_ctrl => mon_ctrl,
1501  mon_buf_avl => mon_buf_avl ,
1502  TCPbuf_avl => TCPbuf_avl,
1503  buf_rqst => EventBuf_rqst,
1504  ipb_write => ipb_master_out.ipb_write ,
1505  ipb_strobe => ipb_master_out.ipb_strobe ,
1506  ipb_addr => ipb_master_out.ipb_addr ,
1507  ipb_wdata => ipb_master_out.ipb_wdata ,
1508  ipb_rdata => AMC_data,
1509  ipb_ack => AMC_ack,
1510  TTC_clk => TTC_clk,
1511  TTC_LOS => TTC_LOS,
1512  BC0 => '0',
1513  ttc_evcnt_reset => ttc_evcnt_reset ,
1514  event_number_avl => event_number_avl ,
1515  event_number => event_number ,
1516  evn_buf_full => evn_fifo_full,
1517  ovfl_warning => L1Aovfl_warning ,
1518  TrigData => open,
1519  TTS_coded => TTS_coded
1520  );
1521 amc_GTXreset <= wr_AMC_en or conf7_fall or not sys_lock;
1522 AMC_reset <= not sys_lock or cmd(0) or cmd0_dl(1);
1523 sys_lock_n <= not sys_lock;
1524 i_TCPIP_if: TCPIP_if PORT MAP(
1525  sysclk => sysclk,
1526  DRPclk => DRPclk,
1527  reset => AMC_reset,
1528  TCPreset => TCPIP_GTXreset,
1529  rstCntr => rst_cntr,
1530  test => conf(9),
1531  Dis_pd => Dis_pd,
1532  enSFP => enSFP,
1533  SFP_down => SFP_down,
1534  inc_ddr_pa => inc_ddr_pa,
1535  evt_data_rdy => evt_data_rdy ,
1536  EventData_in => EventData,
1537  EventData_we => evt_data_we,
1538  EventData_re => evt_data_re,
1539  evt_buf_full => evt_buf_full ,
1540  buf_rqst => EventBuf_rqst,
1541  TCPBuf_avl => TCPbuf_avl,
1542  MonBuf_avl => mon_buf_avl,
1543  WaitMonBuf => WaitMonBuf,
1544  MonBufOverWrite => conf(13),
1545  MonBuf_empty => MonBuf_empty ,
1546  MonBufOvfl => MonBufOvfl,
1547  mon_evt_cnt => mon_evt_cnt ,
1548  WrtMonBlkDone => WrtMonBlkDone ,
1549  WrtMonEvtDone => WrtMonEvtDone ,
1550  KiloByte_toggle => KiloByte_toggle ,
1551  EoB_toggle => EoB_toggle,
1552  wport_rdy => wport_rdy,
1553  wport_FIFO_full => wport_FIFO_full ,
1554  EventBufAddr_we => EventBufAddr_we ,
1555  EventBufAddr => EventBufAddr ,
1556  TCPclk => TCPclk,
1557  TCP_dout => TCP_din,
1558  TCP_channel => TCP_channel ,
1559  TCP_we => TCP_we,
1560  TCP_wcount => TCP_wcount,
1561  TCP_raddr => TCP_raddr,
1562  TCP_length => TCP_length,
1563  TCP_rrqst => TCP_rrqst,
1564  TCP_rack => TCP_rack,
1565  TCP_din => TCP_dout,
1566  TCP_din_type => TCP_dout_type,
1567  TCP_din_valid => TCP_dout_valid,
1568  TCP_lastword => TCP_lastword ,
1569  SFP0_RXN => SFP0_RXN,
1570  SFP0_RXP => SFP0_RXP,
1571  SFP1_RXN => SFP1_RXN,
1572  SFP1_RXP => SFP1_RXP,
1573  SFP2_RXN => SFP2_RXN,
1574  SFP2_RXP => SFP2_RXP,
1575  SFP0_TXN => SFP0_TXN,
1576  SFP0_TXP => SFP0_TXP,
1577  SFP1_TXN => SFP1_TXN,
1578  SFP1_TXP => SFP1_TXP,
1579  SFP2_TXN => SFP2_TXN,
1580  SFP2_TXP => SFP2_TXP,
1581  SFP_REFCLK_N => SFP_REFCLK_N ,
1582  SFP_REFCLK_P => SFP_REFCLK_P ,
1583  cs_out => TCP_cs_out,
1584  ipb_clk => ipb_clk,
1585  ipb_write => ipb_master_out.ipb_write ,
1586  ipb_strobe => ipb_master_out.ipb_strobe ,
1587  ipb_addr => ipb_master_out.ipb_addr ,
1588  ipb_wdata => ipb_master_out.ipb_wdata ,
1589  ipb_rdata => SFP_data
1590  );
1591 TCPIP_GTXreset <= wr_AMC_en or not sys_lock or cmd(4) or cmd0_dl(0);
1592 i_sysmon_if: sysmon_if PORT MAP(
1593  DRPclk => DRPclk,
1594  DB_cmd => cmd(9),
1595  SN => SN,
1596  VAUXN_IN => VAUXN,
1597  VAUXP_IN => VAUXP,
1598  addr => ipb_master_out.ipb_addr(15 downto 0),
1599  data => sysmon_data ,
1600  device_temp => device_temp ,
1601  ALM => ALM,
1602  OT => OT
1603  );
1604 --i_counter_L : BRAM_TDP_MACRO
1605 -- generic map (
1606 -- BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
1607 -- DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1608 -- DOA_REG => 0, -- Optional port A output register (0 or 1)
1609 -- DOB_REG => 0, -- Optional port B output register (0 or 1)
1610 -- INIT_A => X"000000000", -- Initial values on A output port
1611 -- INIT_B => X"000000000", -- Initial values on B output port
1612 -- INIT_FILE => "NONE",
1613 -- READ_WIDTH_A => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1614 -- READ_WIDTH_B => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1615 -- SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY",
1616 -- -- "GENERATE_X_ONLY" or "NONE"
1617 -- SRVAL_A => X"000000000", -- Set/Reset value for A port output
1618 -- SRVAL_B => X"000000000", -- Set/Reset value for B port output
1619 -- WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
1620 -- WRITE_MODE_B => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
1621 -- WRITE_WIDTH_A => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1622 -- WRITE_WIDTH_B => 32) -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1623 -- port map (
1624 -- DOA => CounterDoA(31 downto 0), -- Output port-A data, width defined by READ_WIDTH_A parameter
1625 -- DOB => CounterDoB(31 downto 0), -- Output port-B data, width defined by READ_WIDTH_B parameter
1626 -- ADDRA => counter_wa, -- Input port-A address, width defined by Port A depth
1627 -- ADDRB => counter_ra_l, -- Input port-B address, width defined by Port B depth
1628 -- CLKA => sysclk, -- 1-bit input port-A clock
1629 -- CLKB => clk125, -- 1-bit input port-B clock
1630 -- DIA => CounterDi(31 downto 0), -- Input port-A data, width defined by WRITE_WIDTH_A parameter
1631 -- DIB => (others => '0'), -- Input port-B data, width defined by WRITE_WIDTH_B parameter
1632 -- ENA => '1', -- 1-bit input port-A enable
1633 -- ENB => '1', -- 1-bit input port-B enable
1634 -- REGCEA => '1', -- 1-bit input port-A output register enable
1635 -- REGCEB => '1', -- 1-bit input port-B output register enable
1636 -- RSTA => '0', -- 1-bit input port-A reset
1637 -- RSTB => '0', -- 1-bit input port-B reset
1638 -- WEA => counter_we, -- Input port-A write enable, width defined by Port A depth
1639 -- WEB => x"0" -- Input port-B write enable, width defined by Port B depth
1640 -- );
1641 --i_counter_H : BRAM_TDP_MACRO
1642 -- generic map (
1643 -- BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
1644 -- DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1645 -- DOA_REG => 0, -- Optional port A output register (0 or 1)
1646 -- DOB_REG => 0, -- Optional port B output register (0 or 1)
1647 -- INIT_A => X"000000000", -- Initial values on A output port
1648 -- INIT_B => X"000000000", -- Initial values on B output port
1649 -- INIT_FILE => "NONE",
1650 -- READ_WIDTH_A => 16, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1651 -- READ_WIDTH_B => 16, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1652 -- SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY",
1653 -- -- "GENERATE_X_ONLY" or "NONE"
1654 -- SRVAL_A => X"000000000", -- Set/Reset value for A port output
1655 -- SRVAL_B => X"000000000", -- Set/Reset value for B port output
1656 -- WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
1657 -- WRITE_MODE_B => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
1658 -- WRITE_WIDTH_A => 16, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1659 -- WRITE_WIDTH_B => 16) -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1660 -- port map (
1661 -- DOA => CounterDoA(47 downto 32), -- Output port-A data, width defined by READ_WIDTH_A parameter
1662 -- DOB => CounterDoB(47 downto 32), -- Output port-B data, width defined by READ_WIDTH_B parameter
1663 -- ADDRA => counter_wa, -- Input port-A address, width defined by Port A depth
1664 -- ADDRB => counter_ra_h, -- Input port-B address, width defined by Port B depth
1665 -- CLKA => sysclk, -- 1-bit input port-A clock
1666 -- CLKB => clk125, -- 1-bit input port-B clock
1667 -- DIA => CounterDi(47 downto 32), -- Input port-A data, width defined by WRITE_WIDTH_A parameter
1668 -- DIB => (others => '0'), -- Input port-B data, width defined by WRITE_WIDTH_B parameter
1669 -- ENA => '1', -- 1-bit input port-A enable
1670 -- ENB => '1', -- 1-bit input port-B enable
1671 -- REGCEA => '1', -- 1-bit input port-A output register enable
1672 -- REGCEB => '1', -- 1-bit input port-B output register enable
1673 -- RSTA => '0', -- 1-bit input port-A reset
1674 -- RSTB => '0', -- 1-bit input port-B reset
1675 -- WEA => counter_we(1 downto 0), -- Input port-A write enable, width defined by Port A depth
1676 -- WEB => "00" -- Input port-B write enable, width defined by Port B depth
1677 -- );
1678 --counter_we <= x"f" when div(1 downto 0) = "11" else x"0";
1679 process(ipb_clk)
1680 begin
1681  if(ipb_clk'event and ipb_clk = '1')then
1682  newIPADDRSyncRegs <= newIPADDRSyncRegs(1 downto 0) & newIPADDR;
1683  rst_ipbus <= not newIPADDRSyncRegs(2) and newIPADDR;
1684  end if;
1685 end process;
1686 --CounterDi(47 downto 8) <= (others => '0') when CntrRstCycle = '1' else
1687 --CounterDoA(47 downto 8) + 1 when CounterDi(7 downto 0) < CounterDoA(7 downto 0) else CounterDoA(47 downto 8);
1688 --counter_wa <= "00000" & div(6 downto 2);
1689 --counter_ra_l(4 downto 0) <= ipb_master_out.ipb_addr(5 downto 1);
1690 --counter_ra_h(4 downto 0) <= ipb_master_out.ipb_addr(5 downto 1);
1691 --counter_ra_l(5) <= ipb_master_out.ipb_addr(0);
1692 --counter_ra_h(5) <= not ipb_master_out.ipb_addr(0);
1693 --counter_ra_l(9 downto 6) <= x"0" when ipb_master_out.ipb_addr(15 downto 6) = misc_cntr_addr(15 downto 6) else x"1";
1694 --counter_ra_h(9 downto 6) <= x"0" when ipb_master_out.ipb_addr(15 downto 6) = misc_cntr_addr(15 downto 6) else x"1";
1695 --process(sysClk)
1696 --begin
1697 -- if(sysclk'event and sysclk = '1')then
1698 -- if(CntrRst = '1')then
1699 -- div <= (others => '0');
1700 -- else
1701 -- div <= div + 1;
1702 -- end if;
1703 -- resetCntr_SyncRegs <= resetCntr_SyncRegs(1 downto 0) & rst_cntr;
1704 -- CntrRst <= not resetCntr_SyncRegs(2) and resetCntr_SyncRegs(1);
1705 -- if(CntrRst = '1')then
1706 -- CntrRstCycle <= '1';
1707 -- elsif(and_reduce(div) = '1')then
1708 -- CntrRstCycle <= '0';
1709 -- end if;
1710 -- if(CntrRstCycle = '1')then
1711 -- CounterDi(7 downto 0) <= (others => '0');
1712 -- else
1713 -- case div(6 downto 2) is
1714 -- when "00000" => CounterDi(7 downto 0) <= TTC_serr_cntr;
1715 -- when "00001" => CounterDi(7 downto 0) <= TTC_derr_cntr;
1716 -- when "00010" => CounterDi(7 downto 0) <= TTC_BcntErr_cntr;
1717 -- when "00011" => CounterDi(7 downto 0) <= L1A_cntr;
1718 -- when "00100" => CounterDi(7 downto 0) <= run_cntr;
1719 -- when "00101" => CounterDi(7 downto 0) <= ready_cntr;
1720 -- when "00110" => CounterDi(7 downto 0) <= busy_cntr;
1721 -- when "00111" => CounterDi(7 downto 0) <= sync_cntr;
1722 -- when "01000" => CounterDi(7 downto 0) <= ovfl_cntr;
1723 -- when others => CounterDi(7 downto 0) <= (others => '0');
1724 -- end case;
1725 -- end if;
1726 -- end if;
1727 --end process;
1728 i_TTC_cntr: TTC_cntr PORT MAP(
1729  sysclk => sysclk,
1730  clk125 => clk125,
1731  ipb_clk => ipb_clk,
1732  reset => reset,
1733  rst_cntr => rst_cntr,
1734  DB_cmd => cmd(9),
1735  inc_serr => inc_serr,
1736  inc_derr => inc_derr,
1737  inc_bcnterr => inc_bcnterr ,
1738  inc_l1ac => inc_l1ac,
1739  run => run,
1740  state => state,
1741  ttc_resync => ttc_resync,
1742  ipb_addr => ipb_master_out.ipb_addr (15 downto 0),
1743  ipb_rdata => TTC_cntr_data
1744  );
1745 i_DNA_PORT : DNA_PORT
1746  generic map (
1747  SIM_DNA_VALUE => X"00123456789abcd" -- Specifies a sample 57-bit DNA value for simulation
1748  )
1749  port map (
1750  DOUT => DNA_out, -- 1-bit output: DNA output data.
1751  CLK => ipb_clk, -- 1-bit input: Clock input.
1752  DIN => '0', -- 1-bit input: User data input pin.
1753  READ => load_DNA(1), -- 1-bit input: Active high load DNA, active low read input.
1754  SHIFT => shift_DNA -- 1-bit input: Active high shift enable input.
1755  );
1756 process(ipb_clk,sys_lock)
1757 begin
1758  if(sys_lock = '0')then
1759  load_DNA <= "11";
1760  elsif(ipb_clk'event and ipb_clk = '1')then
1761  load_DNA <= load_DNA(0) & '0';
1762  if(shift_DNA = '1')then
1763  DNA <= DNA(55 downto 0) & DNA_OUT;
1764  end if;
1765  end if;
1766 end process;
1767 process(ipb_clk,sys_lock)
1768 begin
1769  if(sys_lock = '0')then
1770  shift_DNA <= '0';
1771  DNA_cntr <= "111001";
1772  elsif(ipb_clk'event and ipb_clk = '0')then
1773  if(or_reduce(DNA_cntr(5 downto 1)) = '0')then
1774  shift_DNA <= '0';
1775  else
1776  shift_DNA <= not load_DNA(1);
1777  end if;
1778  if(shift_DNA = '1')then
1779  DNA_cntr <= DNA_cntr - 1;
1780  end if;
1781  end if;
1782 end process;
1783 end Behavioral;
1784 
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