AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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AMC13_T1_CMS.vhd
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1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 14:49:29 05/12/2010
6 -- Design Name:
7 -- Module Name: DTC_T2 - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
21 ----------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
24 use IEEE.STD_LOGIC_ARITH.ALL;
25 use IEEE.STD_LOGIC_UNSIGNED.ALL;
26 use IEEE.std_logic_misc.all;
27 use work.ipbus.ALL;
28 use work.amc13_pack.all;
29 
30 -- Uncomment the following library declaration if using
31 -- arithmetic functions with Signed or Unsigned values
32 -- use IEEE.NUMERIC_STD.ALL;
33 
34 -- Uncomment the following library declaration if instantiating
35 -- any Xilinx primitives in this code.
36 library UNISIM;
37 use UNISIM.VComponents.all;
38 Library UNIMACRO;
39 use UNIMACRO.vcomponents.all;
40 
42 entity AMC13_T1_CMS is
43  Port (
44  VAUXP : in STD_LOGIC_VECTOR(12 downto 0);
45  VAUXN : in STD_LOGIC_VECTOR(12 downto 0);
46 -- I2C interface
47  CLK_SCL : out STD_LOGIC;
48  CLK_SDA : inout STD_LOGIC;
49  SFP_SCL : out STD_LOGIC_VECTOR(3 downto 0);
50  SFP_SDA : inout STD_LOGIC_VECTOR(3 downto 0);
51 -- SFP slow control
52  SFP_LOS : in STD_LOGIC_VECTOR(2 downto 0);
53  SFP_ABS : in STD_LOGIC_VECTOR(3 downto 0);
54  TxFault : in STD_LOGIC_VECTOR(3 downto 0);
55  TxDisable : out STD_LOGIC_VECTOR(3 downto 0);
56 -- RATE : out STD_LOGIC_VECTOR(3 downto 0);
57 -- CDR signals
58  DIV4 : out STD_LOGIC;
59  DIV_nRST : out STD_LOGIC;
60  CDRclk_p : in STD_LOGIC;
61  CDRclk_n : in STD_LOGIC;
62  CDRdata_p : in STD_LOGIC;
63  CDRdata_n : in STD_LOGIC;
64  TTCdata_p : out STD_LOGIC;
65  TTCdata_n : out STD_LOGIC;
66  TTCclk_p : in STD_LOGIC;
67  TTCclk_n : in STD_LOGIC;
68  TTC_LOS : in STD_LOGIC;
69  TTC_LOL : in STD_LOGIC;
70  TTS_out_p : out STD_LOGIC;
71  TTS_out_n : out STD_LOGIC;
72 -- SPI interface
73  SPI_SCK : in STD_LOGIC;
74  SPI_CS_b : in STD_LOGIC;
75  SPI_MOSI : in STD_LOGIC;
76  SPI_MISO : out STD_LOGIC;
77 -- DDR3 pins
78  sys_clk_p : in STD_LOGIC;
79  sys_clk_n : in STD_LOGIC;
80  ddr3_dq : inout STD_LOGIC_VECTOR(31 downto 0);
81  ddr3_addr : out STD_LOGIC_VECTOR(13 downto 0);
82  ddr3_ba : out STD_LOGIC_VECTOR (2 downto 0);
83  ddr3_dm : out STD_LOGIC_VECTOR (3 downto 0);
84  ddr3_dqs_p : inout STD_LOGIC_VECTOR(3 downto 0);
85  ddr3_dqs_n : inout STD_LOGIC_VECTOR(3 downto 0);
86  ddr3_ras_n : out STD_LOGIC;
87  ddr3_cas_n : out STD_LOGIC;
88  ddr3_we_n : out STD_LOGIC;
89  ddr3_reset_n : out STD_LOGIC;
90  ddr3_cke : out STD_LOGIC_vector(0 to 0);
91  ddr3_odt : out STD_LOGIC_vector(0 to 0);
92  ddr3_ck_p : out STD_LOGIC_vector(0 to 0);
93  ddr3_ck_n : out STD_LOGIC_vector(0 to 0);
94  SFP0_RXN : in STD_LOGIC;
95  SFP0_RXP : in STD_LOGIC;
96  SFP1_RXN : in STD_LOGIC;
97  SFP1_RXP : in STD_LOGIC;
98  SFP2_RXN : in STD_LOGIC;
99  SFP2_RXP : in STD_LOGIC;
100  SFP0_TXN : out STD_LOGIC;
101  SFP0_TXP : out STD_LOGIC;
102  SFP1_TXN : out STD_LOGIC;
103  SFP1_TXP : out STD_LOGIC;
104  SFP2_TXN : out STD_LOGIC;
105  SFP2_TXP : out STD_LOGIC;
106  SFP_REFCLK_N : in STD_LOGIC;
107  SFP_REFCLK_P : in STD_LOGIC;
108  AMC_REFCLK_N : in STD_LOGIC;
109  AMC_REFCLK_P : in STD_LOGIC;
110  AMC_RXN : in STD_LOGIC_VECTOR(12 downto 1);
111  AMC_RXP : in STD_LOGIC_VECTOR(12 downto 1);
112  AMC_TXN : out STD_LOGIC_VECTOR(12 downto 1);
113  AMC_TXP : out STD_LOGIC_VECTOR(12 downto 1);
114 -- signal to/from DTC_T2
115  S6LINK_RXN : in STD_LOGIC;
116  S6LINK_RXP : in STD_LOGIC;
117  S6LINK_TXN : out STD_LOGIC;
118  S6LINK_TXP : out STD_LOGIC;
119  S2V_p : in STD_LOGIC;
120  S2V_n : in STD_LOGIC;
121 -- V2S_p : out STD_LOGIC;
122 -- V2S_n : out STD_LOGIC;
123  GbE_REFCLK_N : in STD_LOGIC;
124  GbE_REFCLK_P : in STD_LOGIC);
125 end AMC13_T1_CMS;
126 
127 architecture Behavioral of AMC13_T1_CMS is
128 COMPONENT TTS_if
129  PORT(
130  sysclk : IN std_logic;
131  TTS_clk : IN std_logic;
132  reset : IN std_logic;
133  local_TTC : in STD_LOGIC;
134  TTS : IN std_logic_vector(3 downto 0);
135  TTS_out_p : OUT std_logic;
136  TTS_out_n : OUT std_logic
137  );
138 END COMPONENT;
139 COMPONENT ttc_if
140  PORT(
141  clk : IN std_logic;
142  refclk : IN std_logic;
143  reset : IN std_logic;
144  run : IN std_logic;
145  IsG2 : IN std_logic;
146  DB_cmd_in : IN std_logic;
147  DB_cmd_Out : OUT std_logic;
148  sys_lock : IN std_logic;
149  local_TTC : IN std_logic;
150  local_TTCcmd : IN std_logic;
151  single_TTCcmd : in STD_LOGIC;
152  CDRclk_p : IN std_logic;
153  CDRclk_n : IN std_logic;
154  CDRdata_p : IN std_logic;
155  CDRdata_n : IN std_logic;
156  TTC_LOS : IN std_logic;
157  TTC_LOL : IN std_logic;
158  BCN_off : IN std_logic_vector(12 downto 0);
159  OC_off : IN std_logic_vector(3 downto 0);
160  en_cal_win : IN std_logic;
161  cal_win_high : IN std_logic_vector(11 downto 0);
162  cal_win_low : IN std_logic_vector(11 downto 0);
163  en_localL1A : IN std_logic;
164  LocalL1A_cfg : IN std_logic_vector(31 downto 0);
165  localL1A_s : IN std_logic;
166  localL1A_r : IN std_logic;
167  T3_trigger : in std_logic;
168  EvnRSt_l : in std_logic;
169  OcnRSt_l : in std_logic;
170  ovfl_warning : IN std_logic;
171  ipb_clk : IN std_logic;
172  ipb_write : in STD_LOGIC;
173  ipb_strobe : in STD_LOGIC;
174  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
175  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
176  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
177  en_brcst : IN std_logic;
178  state : IN std_logic_vector(3 downto 0);
179  evn_fifo_full : IN std_logic;
180  BC0 : OUT std_logic;
181  TTC_strobe : OUT std_logic;
182  TTS_clk : OUT std_logic;
183  DIV4 : OUT std_logic;
184  DIV_nRST : OUT std_logic;
185  CDRclk_out : OUT std_logic;
186  TTCdata_p : OUT std_logic;
187  TTCdata_n : OUT std_logic;
188  CalType : OUT std_logic_vector(3 downto 0);
189  TTC_Brcst : OUT std_logic_vector(3 downto 0);
190  localL1A_periodic : OUT std_logic;
191  ttc_start : OUT std_logic;
192  ttc_stop : OUT std_logic;
193  ttc_soft_reset : OUT std_logic;
194  ttc_ready : OUT std_logic;
195  ttc_serr : OUT std_logic;
196  ttc_derr : OUT std_logic;
197  ttc_bcnt_err : OUT std_logic;
198  rate_OFW : OUT std_logic;
199  sync_lost : OUT std_logic;
200  inc_oc : OUT std_logic;
201  inc_l1ac : OUT std_logic;
202  inc_bcnterr : OUT std_logic;
203  inc_serr : OUT std_logic;
204  inc_derr : OUT std_logic;
205  ttc_evcnt_reset : OUT std_logic;
206  event_number_avl : OUT std_logic;
207  event_number : OUT std_logic_vector(59 downto 0)
208  );
209 END COMPONENT;
210 COMPONENT AMC_if
211  Generic (useTCPIP : boolean := false; AMC_useTRIG : boolean := false; simulation : boolean := false);
212  PORT(
213  sysclk : IN std_logic;
214  ipb_clk : IN std_logic;
215  clk125 : IN std_logic;
216  DRPclk : IN std_logic;
217  GTXreset : IN std_logic;
218  reset : IN std_logic;
219  DB_cmd : IN std_logic;
220  ReSync : IN std_logic;
221  resetCntr : IN std_logic;
222  AllEventBuilt : OUT std_logic;
223  run : IN std_logic;
224  en_inject_err : in STD_LOGIC;
225  Dis_pd : in STD_LOGIC;
226  enSFP : IN std_logic_vector(3 downto 0);
227  en_localL1A : IN std_logic;
228  test : IN std_logic;
229  NoReSyncFake : IN std_logic;
230  WaitMonBuf : IN std_logic;
231  fake_length : IN std_logic_vector(19 downto 0);
232  T1_version : IN std_logic_vector(7 downto 0);
233  Source_ID : IN array3x12;
234  AMC_en : IN std_logic_vector(11 downto 0);
235  TTS_disable : IN std_logic_vector(11 downto 0);
236  AMC_REFCLK_P : IN std_logic;
237  AMC_REFCLK_N : IN std_logic;
238  AMC_RXN : IN std_logic_vector(12 downto 1);
239  AMC_RXP : IN std_logic_vector(12 downto 1);
240  evt_data_re : IN std_logic_vector(2 downto 0);
241  evt_buf_full : IN std_logic_vector(2 downto 0);
242  ddr_pa : IN std_logic_vector(9 downto 0);
243  MonBuf_empty : IN std_logic;
244  mon_buf_avl : IN std_logic;
245  TCPbuf_avl : IN std_logic;
246  ipb_write : IN std_logic;
247  ipb_strobe : IN std_logic;
248  ipb_addr : IN std_logic_vector(31 downto 0);
249  ipb_wdata : IN std_logic_vector(31 downto 0);
250  TTC_clk : IN std_logic;
251  TTC_LOS : IN std_logic;
252  BC0 : IN std_logic;
253  ttc_evcnt_reset : IN std_logic;
254  event_number_avl : IN std_logic;
255  event_number : IN std_logic_vector(59 downto 0);
256  AMC_Ready : OUT std_logic_vector(11 downto 0);
257  BC0_lock : OUT std_logic_vector(11 downto 0);
258  TTC_lock : OUT std_logic;
259  AMC_TXN : OUT std_logic_vector(12 downto 1);
260  AMC_TXP : OUT std_logic_vector(12 downto 1);
261  AMC_status : OUT std_logic_vector(31 downto 0);
262  evt_data : OUT array3x67;
263  evt_data_we : OUT std_logic_vector(2 downto 0);
264  evt_data_rdy : OUT std_logic_vector(2 downto 0);
265  mon_evt_wc : OUT std_logic_vector(47 downto 0);
266  mon_ctrl : OUT std_logic_vector(31 downto 0);
267  buf_rqst : OUT std_logic_vector(3 downto 0);
268  ipb_rdata : OUT std_logic_vector(31 downto 0);
269  ipb_ack : OUT std_logic;
270  evn_buf_full : OUT std_logic;
271  ovfl_warning : OUT std_logic;
272  TrigData : OUT array12x8;
273  TTS_coded : OUT std_logic_vector(4 downto 0)
274  );
275 END COMPONENT;
276 COMPONENT I2C
277  PORT(
278  clk : IN std_logic;
279  ipb_clk : IN std_logic;
280  reset : IN std_logic;
281  addr : IN std_logic_vector(31 downto 0);
282  SFP_ABS : IN std_logic_vector(3 downto 0);
283  SFP_LOS : IN std_logic_vector(2 downto 0);
284  CLK_SDA : INOUT std_logic;
285  SFP_SDA : INOUT std_logic_vector(3 downto 0);
286  rdata : OUT std_logic_vector(31 downto 0);
287  CLK_rdy : OUT std_logic;
288  CLK_SCL : OUT std_logic;
289  SFP_SCL : OUT std_logic_vector(3 downto 0)
290  );
291 END COMPONENT;
292 COMPONENT SPI_if
293  PORT(
294  SCK : IN std_logic;
295  CSn : IN std_logic;
296  MOSI : IN std_logic;
297  SN : IN std_logic_vector(8 downto 0);
298  OT : IN std_logic;
299  IsT1 : IN std_logic;
300  SPI_rdata : IN std_logic_vector(7 downto 0);
301  MISO : OUT std_logic;
302  SPI_we : OUT std_logic;
303  en_RARP : out STD_LOGIC;
304  newIPADDR : OUT std_logic;
305  IPADDR : OUT std_logic_vector(31 downto 0);
306  SPI_wdata : OUT std_logic_vector(7 downto 0);
307  SPI_addr : OUT std_logic_vector(7 downto 0)
308  );
309 END COMPONENT;
310 COMPONENT ddr_if
311  port(
312  clk_ref : in std_logic;
313  mem_clk_p : in std_logic;
314  mem_clk_n : in std_logic;
315  mem_rst : in std_logic;
316  sysclk : in std_logic;
317  TCPclk : in std_logic;
318  reset : in std_logic;
319  resetsys : in std_logic;
320  run : in std_logic;
321  mem_test : in std_logic_VECTOR(1 downto 0);
322  EventData : in array3X67;
323  EventData_we : in std_logic_VECTOR(2 downto 0);
324  wport_rdy : out std_logic_VECTOR(2 downto 0);
325  WrtMonBlkDone : OUT std_logic_VECTOR(2 downto 0);
326  WrtMonEvtDone : OUT std_logic_VECTOR(2 downto 0);
327  KiloByte_toggle : OUT std_logic_VECTOR(2 downto 0);
328  EoB_toggle : OUT std_logic_VECTOR(2 downto 0);
329  EventBufAddr : in array3x14;
330  EventBufAddr_we : in std_logic_VECTOR(2 downto 0);
331  EventFIFOfull : out std_logic_VECTOR(2 downto 0);
332  TCP_din : in std_logic_vector(31 downto 0);
333  TCP_channel : in STD_LOGIC_VECTOR (1 downto 0);
334  TCP_we : in STD_LOGIC;
335  TCP_wcount : out STD_LOGIC_VECTOR (2 downto 0);
336  TCP_dout : out STD_LOGIC_VECTOR(31 downto 0); -- TCP data are written in unit of 32-bit words
337  TCP_raddr : in std_logic_vector(28 downto 0); -- 28-26 encoded request source 25-0 address in 64 bit word
338  TCP_length : in std_logic_vector(10 downto 0); -- in 64 bit word, actual length - 1
339  TCP_dout_valid : out STD_LOGIC;
340  TCP_rrqst : in STD_LOGIC;
341  TCP_rack : out STD_LOGIC;
342  TCP_lastword : out STD_LOGIC;
343 -- ipbus signals
344  ipb_clk : in STD_LOGIC;
345  ipb_write : in STD_LOGIC;
346  ipb_strobe : in STD_LOGIC;
347  page_addr : in STD_LOGIC_VECTOR(9 downto 0);
348  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
349  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
350  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
351  ipb_ack : out STD_LOGIC;
352  mem_stat : out STD_LOGIC_VECTOR (63 downto 0);
353  device_temp : in STD_LOGIC_VECTOR(11 downto 0);
354 -- ddr3 memory pins
355  ddr3_dq : inout STD_LOGIC_VECTOR (31 downto 0);
356  ddr3_dm : out STD_LOGIC_VECTOR (3 downto 0);
357  ddr3_addr : out STD_LOGIC_VECTOR (13 downto 0);
358  ddr3_ba : out STD_LOGIC_VECTOR (2 downto 0);
359  ddr3_dqs_p : inout STD_LOGIC_VECTOR (3 downto 0);
360  ddr3_dqs_n : inout STD_LOGIC_VECTOR (3 downto 0);
361  ddr3_ras_n : out STD_LOGIC;
362  ddr3_cas_n : out STD_LOGIC;
363  ddr3_we_n : out STD_LOGIC;
364  ddr3_reset_n : out STD_LOGIC;
365  ddr3_cke : out STD_LOGIC_vector(0 to 0);
366  ddr3_odt : out STD_LOGIC_vector(0 to 0);
367  ddr3_ck_p : out STD_LOGIC_vector(0 to 0);
368  ddr3_ck_n : out STD_LOGIC_vector(0 to 0)
369  );
370 END COMPONENT;
371 COMPONENT ipbus_if
372  generic(RXPOLARITY : std_logic := '0'; TXPOLARITY : std_logic := '0');
373  port(
374  ipb_clk : IN std_logic;
375  UsRclk : IN std_logic;
376  DRPclk : IN std_logic;
377  got_SN : out std_logic;
378  reset : IN std_logic;
379  GTX_RESET : IN std_logic;
380  GbE_REFCLK : in std_logic;
381  S6LINK_RXN : in std_logic;
382  S6LINK_RXP : in std_logic;
383  S6LINK_TXN : out std_logic;
384  S6LINK_TXP : out std_logic;
385  wr_amc_en : in std_logic;
386  amc_en : in STD_LOGIC_VECTOR(11 downto 0);
387  en_RARP : in std_logic;
388  IPADDR : in STD_LOGIC_VECTOR(31 downto 0);
389  MACADDR : in STD_LOGIC_VECTOR(47 downto 0);
390  ipb_out : out ipb_wbus;
391  ipb_in : in ipb_rbus;
392  SN : out STD_LOGIC_VECTOR(8 downto 0);
393  debug_in : IN std_logic_vector(31 downto 0);
394  debug_out : OUT std_logic_vector(127 downto 0)
395  );
396 end COMPONENT;
397 COMPONENT sysmon_if
398  PORT(
399  DRPclk : IN std_logic;
400  DB_cmd : IN std_logic;
401  SN : IN std_logic_vector(8 downto 0);
402  VAUXN_IN : IN std_logic_vector(12 downto 0);
403  VAUXP_IN : IN std_logic_vector(12 downto 0);
404  addr : IN std_logic_vector(15 downto 0);
405  data : OUT std_logic_vector(31 downto 0);
406  device_temp : OUT std_logic_vector(11 downto 0);
407  ALM : OUT std_logic_vector(7 downto 0);
408  OT : OUT std_logic
409  );
410 END COMPONENT;
411 COMPONENT DAQLSCXG_3x_if
412  PORT(
413  sysclk : IN std_logic;
414  clk125 : IN std_logic;
415  DRPclk : IN std_logic;
416  reset : IN std_logic;
417  daq_reset : IN std_logic;
418  gtx_reset : IN std_logic;
419  rstCntr : IN std_logic;
420  Dis_pd : in STD_LOGIC;
421  test : IN std_logic;
422  DB_cmd : IN std_logic;
423  enSFP : IN std_logic_vector(3 downto 0);
424  SFP_ABS : IN std_logic_vector(2 downto 0);
425  LSC_ID : IN std_logic_vector(15 downto 0);
426  inc_ddr_pa : IN std_logic;
427  evt_data_rdy : IN std_logic_vector(2 downto 0);
428  EventData_in : IN array3x67;
429  EventData_we : IN std_logic_vector(2 downto 0);
430  buf_rqst : IN std_logic_vector(3 downto 0);
431  WaitMonBuf : IN std_logic;
432  WrtMonBlkDone : IN std_logic_vector(2 downto 0);
433  WrtMonEvtDone : IN std_logic_vector(2 downto 0);
434  wport_rdy : IN std_logic_vector(2 downto 0);
435  wport_FIFO_full : IN std_logic_vector(2 downto 0);
436  SFP0_RXN : IN std_logic;
437  SFP0_RXP : IN std_logic;
438  SFP1_RXN : IN std_logic;
439  SFP1_RXP : IN std_logic;
440  SFP2_RXN : IN std_logic;
441  SFP2_RXP : IN std_logic;
442  SFP_REFCLK_P : in std_logic;
443  SFP_REFCLK_N : in std_logic;
444  ipb_clk : IN std_logic;
445  ipb_write : IN std_logic;
446  ipb_strobe : IN std_logic;
447  ipb_addr : IN std_logic_vector(31 downto 0);
448  ipb_wdata : IN std_logic_vector(31 downto 0);
449  SFP_down : OUT std_logic_vector(2 downto 0);
450  EventData_re : OUT std_logic_vector(2 downto 0);
451  evt_buf_full : OUT std_logic_vector(2 downto 0);
452  MonBufOverWrite : IN std_logic;
453  MonBuf_avl : OUT std_logic;
454  MonBuf_empty : OUT std_logic;
455  MonBufOvfl : OUT std_logic;
456  mon_evt_cnt : OUT std_logic_vector(31 downto 0);
457  EventBufAddr_we : OUT std_logic_vector(2 downto 0);
458  EventBufAddr : OUT array3x14;
459  SFP0_TXN : OUT std_logic;
460  SFP0_TXP : OUT std_logic;
461  SFP1_TXN : OUT std_logic;
462  SFP1_TXP : OUT std_logic;
463  SFP2_TXN : OUT std_logic;
464  SFP2_TXP : OUT std_logic;
465  ipb_rdata : OUT std_logic_vector(31 downto 0);
466  ipb_ack : OUT std_logic
467  );
468 END COMPONENT;
469 COMPONENT TTC_cntr
470  PORT(
471  sysclk : IN std_logic;
472  clk125 : IN std_logic;
473  ipb_clk : IN std_logic;
474  reset : IN std_logic;
475  rst_cntr : IN std_logic;
476  DB_cmd : IN std_logic;
477  inc_serr : IN std_logic;
478  inc_derr : IN std_logic;
479  inc_bcnterr : IN std_logic;
480  inc_l1ac : IN std_logic;
481  run : IN std_logic;
482  state : IN std_logic_vector(3 downto 0);
483  ttc_resync : IN std_logic;
484  ipb_addr : IN std_logic_vector(15 downto 0);
485  ipb_rdata : OUT std_logic_vector(31 downto 0)
486  );
487 END COMPONENT;
488 constant ipbus_ver_addr : std_logic_vector(15 downto 0) := x"0000";
489 constant ipbus_sfp_addr: std_logic_vector(15 downto 0) := x"0002";
490 constant CDRclk_pol : std_logic := '0';
491 constant CDRdata_pol : std_logic := '1';
492 constant TTCclk_pol : std_logic := '1';
493 constant TTCdata_pol : std_logic := '1';
494 constant Coarse_Delay: std_logic_vector(3 downto 0) := x"0";
495 signal rst_ipbus : std_logic := '0';
496 signal LDC_UsrClk : std_logic := '0';
497 signal wr_AMC_en : std_logic := '0';
498 signal wr_EnSFP : std_logic := '0';
499 signal fake_length : std_logic_vector(19 downto 0) := x"00400";
500 signal AMC_en : std_logic_vector(11 downto 0) := (others =>'0');
501 signal TTS_disable : std_logic_vector(11 downto 0) := (others =>'0');
502 signal AMC_Ready : std_logic_vector(11 downto 0) := (others =>'0');
503 signal AMC_status : std_logic_vector(31 downto 0) := (others =>'0');
504 signal AMC_DATA : std_logic_vector(31 downto 0) := (others =>'0');
505 signal AMC_ack : std_logic := '0';
506 signal L1Aovfl_warning : std_logic := '0';
507 --signal TRIGDATA : std_logic_vector(7 downto 0) := (others =>'0');
508 signal TTS_coded : std_logic_vector(4 downto 0) := (others =>'0');
509 --signal AMC_trig : std_logic := '0';
510 signal pattern : std_logic_vector(3 downto 0) := (others =>'0');
511 --signal Trig_mask : std_logic_vector(7 downto 0) := (others =>'0');
512 signal SPI_SCK_buf : std_logic := '0';
513 signal CLK_rdy : std_logic := '0';
514 signal I2C_data : std_logic_vector(31 downto 0) := (others =>'0');
515 signal TTCclk_in : std_logic := '0';
516 signal TTC_Clk : std_logic := '0';
517 signal TTC_strobe : std_logic := '0';
518 signal BcntErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
519 signal SinErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
520 signal DbErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
521 signal L1_reg : std_logic_vector(15 downto 0) := (others =>'0');
522 signal Bcnt_reg : std_logic_vector(11 downto 0) := (others =>'0');
523 signal OC_reg : std_logic_vector(31 downto 0) := (others =>'0');
524 signal V2S : std_logic := '0';
525 signal S2V : std_logic := '0';
526 signal S2V_cntr : std_logic_vector(5 downto 0) := (others => '0');
527 signal S2V_sr : std_logic_vector(3 downto 0) := (others => '0');
528 signal ddr_rdata : std_logic_vector(7 downto 0) := (others =>'0');
529 signal ipb_clk_dcm : std_logic := '0';
530 signal ipb_clk : std_logic := '0';
531 signal clk125_dcm : std_logic := '0';
532 signal clk125 : std_logic := '0';
533 signal DRPclk_dcm : std_logic := '0';
534 signal DRPclk : std_logic := '0';
535 signal sysclk_dcm : std_logic := '0';
536 signal sysclk : std_logic := '0';
537 signal clkfb : std_logic := '0';
538 signal refclk_dcm : std_logic := '0';
539 signal refclk : std_logic := '0';
540 signal mem_clk_dcm : std_logic := '0';
541 signal mem_clk : std_logic := '0';
542 signal sysclk_inp : std_logic := '0';
543 signal sysclk_in : std_logic := '0';
544 --signal clk125 : std_logic := '0';
545 signal sys_lock : std_logic := '0';
546 signal sys_lock_n : std_logic := '0';
547 signal ldc_reset : std_logic := '0';
548 signal ldc_GTXreset : std_logic := '0';
549 signal lsc_start : std_logic := '0';
550 signal lsc_reset : std_logic := '0';
551 signal lsc_GTXreset : std_logic := '0';
552 signal amc_reset : std_logic := '0';
553 signal amc_GTXreset : std_logic := '0';
554 signal DB_cmd : std_logic := '0';
555 signal conf7_q : std_logic := '0';
556 signal conf7_fall : std_logic := '0';
557 signal run : std_logic := '0';
558 signal LSC_LinkDown : std_logic := '0';
559 signal mem_rst : std_logic := '0';
560 signal mem_test : std_logic_vector(1 downto 0) := (others =>'0');
561 signal mem_stat : std_logic_vector(63 downto 0) := (others =>'0');
562 signal mem_ack : std_logic := '0';
563 signal mem_data : std_logic_vector(31 downto 0) := (others =>'0');
564 signal ttc_data : std_logic_vector(31 downto 0) := (others =>'0');
565 signal EventData : array3X67 := (others => (others => '0'));
566 signal wport_rdy : std_logic_vector(2 downto 0) := (others =>'0');
567 signal EventBufAddr : array3x14 := (others => (others => '0'));
568 signal EventBufAddr_we : std_logic_vector(2 downto 0) := (others =>'0');
569 signal evt_buf_full : std_logic_vector(2 downto 0) := (others =>'0');
570 signal wport_FIFO_full : std_logic_vector(2 downto 0) := (others =>'0');
571 --signal TCP_din : std_logic_vector(31 downto 0) := (others =>'0');
572 --signal TCP_channel : std_logic_vector(1 downto 0) := (others =>'0');
573 --signal TCP_wrqst : std_logic := '0';
574 --signal TCP_re : std_logic := '0';
575 --signal TCP_dout : std_logic_vector(31 downto 0) := (others =>'0');
576 --signal TCP_raddr : std_logic_vector(23 downto 0) := (others =>'0');
577 --signal TCP_length : std_logic_vector(11 downto 0) := (others =>'0');
578 --signal TCP_dout_valid : std_logic := '0';
579 --signal TCP_rrqst : std_logic := '0';
580 --signal TCP_rack : std_logic := '0';
581 --signal TCP_lastword : std_logic := '0';
582 signal MonBufOvfl : std_logic := '0';
583 signal MonBuf_empty : std_logic := '0';
584 --signal inc_mon_cntr : std_logic := '0';
585 signal mon_evt_wc : std_logic_vector(47 downto 0) := (others =>'0');
586 signal mon_evt_cnt : std_logic_vector(31 downto 0) := (others =>'0');
587 signal mon_ctrl : std_logic_vector(31 downto 0) := (others =>'0');
588 --signal TCPbuf_avl : std_logic := '0';
589 signal mon_buf_avl : std_logic := '0';
590 signal EventBufAddrAvl : std_logic := '0';
591 signal EventBufAddrRe : std_logic := '0';
592 signal mon_wp : std_logic_vector(31 downto 0) := (others =>'0');
593 --signal TCP_releaseAck : std_logic_vector(2 downto 0) := (others =>'0');
594 --signal TCP_releaseRqst : std_logic_vector(2 downto 0) := (others =>'0');
595 --signal TCP_releaseAddr : array3X13 := (others => (others => '0'));
596 signal EventBuf_rqst : std_logic_vector(3 downto 0) := (others =>'0');
597 signal rst_cntr : std_logic := '0';
598 signal rst_ddr_pa : std_logic := '0';
599 signal inc_ddr_pa : std_logic := '0';
600 signal Source_ID : array3x12 := (others => (others => '0'));
601 signal ddr_pa : std_logic_vector(9 downto 0) := (others =>'0');
602 signal CDRclk : std_logic := '0';
603 signal TTS_clk : std_logic := '0';
604 signal BC0 : std_logic := '0';
605 signal T3_trigger : std_logic := '0';
606 signal BC0_delay : std_logic_vector(4 downto 0) := "11000";
607 signal bcnt : std_logic_vector(3 downto 0) := x"0";
608 signal LocalL1A_cfg : std_logic_vector(31 downto 0) := (others =>'0');
609 signal BCN_off : std_logic_vector(12 downto 0) := (others =>'0');
610 signal OC_off : std_logic_vector(3 downto 0) := (others =>'0');
611 signal en_cal_win : std_logic := '0';
612 signal CalibCtrl : std_logic_vector(31 downto 0) := x"0d800d80";
613 signal cal_win_high : std_logic_vector(11 downto 0) := (others =>'0');
614 signal cal_win_low : std_logic_vector(11 downto 0) := (others =>'0');
615 signal CalType : std_logic_vector(3 downto 0) := (others =>'0');
616 signal TTC_Brcst : std_logic_vector(3 downto 0) := (others =>'0');
617 signal local_TTCcmd : std_logic := '0';
618 signal en_brcst : std_logic := '0';
619 signal ttc_start : std_logic := '0';
620 signal ttc_stop : std_logic := '0';
621 signal ttc_soft_reset : std_logic := '0';
622 signal ttc_soft_resetp : std_logic := '0';
623 signal ttc_ready : std_logic := '0';
624 signal ttc_serr : std_logic := '0';
625 signal ttc_derr : std_logic := '0';
626 signal ttc_bcnt_err : std_logic := '0';
627 signal ttc_evcnt_reset : std_logic := '0';
628 signal inc_rate_ofw : std_logic := '0';
629 signal rate_ofw : std_logic := '0';
630 signal rate_ofwp : std_logic := '0';
631 signal rate_ofw_q : std_logic := '0';
632 signal sync_lost : std_logic := '0';
633 signal oc_cntr : std_logic_vector(3 downto 0) := (others =>'0');
634 signal ttc_resync : std_logic := '0';
635 signal AllEventBuilt : std_logic := '0';
636 signal resync_done : std_logic := '0';
637 signal dcc_quiet : std_logic := '0';
638 signal inc_oc : std_logic := '0';
639 signal inc_L1ac : std_logic := '0';
640 signal inc_bcnterr : std_logic := '0';
641 signal inc_serr : std_logic := '0';
642 signal inc_derr : std_logic := '0';
643 signal evn_fifo_full : std_logic := '0';
644 signal event_number_avl : std_logic := '0';
645 signal state : std_logic_vector(3 downto 0) := (others =>'0');
646 signal TTS_wait : std_logic_vector(20 downto 0) := (others =>'0');
647 signal event_number : std_logic_vector(59 downto 0) := (others =>'0');
648 signal status_l : std_logic_vector(22 downto 0) := (others =>'0');
649 signal SFP_down_l : std_logic_vector(2 downto 0) := (others =>'0');
650 signal SFP_status_l : std_logic_vector(11 downto 0) := (others =>'0');
651 signal AMC_status_l : std_logic_vector(31 downto 0) := (others =>'0');
652 signal TTC_cntr_data : std_logic_vector(31 downto 0) := (others => '0');
653 signal got_SN : std_logic := '0';
654 signal ipb_strobe_q : std_logic := '0';
655 signal SFP_clk : std_logic := '0';
656 signal AMC_clk : std_logic := '0';
657 signal AMC_clk_in : std_logic := '0';
658 signal SV_Cntr : std_logic_vector(7 downto 0) := (others => '0');
659 signal sysclk_div : std_logic_vector(7 downto 0) := (others => '0');
660 signal SFP_UsrClk : std_logic := '0';
661 signal SFP_TxOutClk : std_logic := '0';
662 signal I2C_debug_out : std_logic_vector(15 downto 0) := (others =>'0');
663 signal SFPOSC_rdy : std_logic := '0';
664 signal reset : std_logic := '0';
665 signal DAQ_reset : std_logic := '0';
666 signal AMCOSC_rdy : std_logic := '0';
667 --signal cs_clk_in : std_logic := '0';
668 --signal cs_clk : std_logic := '0';
669 signal TTC_debug : std_logic_vector(63 downto 0) := (others =>'0');
670 signal TxDisable_i : std_logic_vector(3 downto 0) := (others => '0');
671 signal DAQfifo_re : std_logic := '0';
672 signal DAQfifoAlmostEmpty : std_logic := '0';
673 signal DAQfifoEmpty : std_logic := '0';
674 signal DAQfifo_do : std_logic_vector(63 downto 0) := (others =>'0');
675 signal DAQ_debug_in : std_logic_vector(63 downto 0) := (others =>'0');
676 signal LDC_debug_out : std_logic_vector(63 downto 0) := (others =>'0');
677 signal LSC_debug_out : std_logic_vector(63 downto 0) := (others =>'0');
678 signal ddr_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
679 signal ddr_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
680 signal GbE_REFCLK : std_logic := '0';
681 signal S6Link_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
682 signal S6Link_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
683 signal GbE_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
684 signal GbE_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
685 signal AMC_debug_in : std_logic_vector(255 downto 0) := (others =>'0');
686 signal AMC_debug_out : std_logic_vector(255 downto 0) := (others =>'0');
687 signal SFP0_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
688 signal SFP0_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
689 signal SFP1_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
690 signal SFP1_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
691 signal ipb_master_out : ipb_wbus;
692 signal ipb_master_in : ipb_rbus;
693 signal SN : std_logic_vector(8 downto 0) := (others =>'0');
694 signal MACADDR : std_logic_vector(47 downto 0) := (others =>'0');
695 signal ipaddr : std_logic_vector(31 downto 0) := (others =>'0');
696 signal en_RARP : std_logic := '0';
697 --signal SPI_IP : std_logic_vector(31 downto 0) := (others =>'0');
698 signal status : std_logic_vector(31 downto 0) := (others =>'0');
699 signal cmd : std_logic_vector(31 downto 0) := (others =>'0');
700 signal cmd0_dl : std_logic_vector(1 downto 0) := (others =>'0');
701 signal cmd2_dl : std_logic_vector(1 downto 0) := (others =>'0');
702 signal conf : std_logic_vector(15 downto 0) := (others =>'0');
703 signal LSC_ID : std_logic_vector(15 downto 0) := x"1234";
704 signal OT : std_logic := '0';
705 signal inc_HTRCRC_err : std_logic := '0';
706 signal sysmon_data : std_logic_vector(31 downto 0) := (others => '0');
707 signal device_temp : std_logic_vector(11 downto 0) := (others =>'0');
708 signal ALM : std_logic_vector(7 downto 0) := (others =>'0');
709 signal evt_data_rdy : std_logic_vector(2 downto 0) := (others => '0');
710 signal evt_data_re : std_logic_vector(2 downto 0) := (others => '0');
711 signal evt_data_we : std_logic_vector(2 downto 0) := (others => '0');
712 --signal event_size : array3x13;
713 signal SFP_data : std_logic_vector(31 downto 0) := (others =>'0');
714 signal SFP_ack : std_logic := '0';
715 --signal TCP_data : std_logic_vector(31 downto 0) := (others =>'0');
716 --signal TCP_ack : std_logic := '0';
717 signal S2V_SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
718 signal resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
719 signal sysclk_div7SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
720 signal resetCntr_SyncRegs : std_logic_vector(2 downto 0) := (others =>'0');
721 signal newIPADDR : std_logic := '0';
722 signal newIPADDRSyncRegs : std_logic_vector(2 downto 0) := (others =>'0');
723 signal DNA_out : std_logic := '0';
724 signal load_DNA : std_logic := '0';
725 signal shift_DNA : std_logic_vector(2 downto 0) := (others =>'0');
726 signal DNA_cntr : std_logic_vector(5 downto 0) := (others =>'0');
727 signal DNA : std_logic_vector(56 downto 0) := (others =>'0');
728 signal Dis_pd : std_logic := '0';
729 signal enSFP : std_logic_vector(3 downto 0) := (others =>'0');
730 signal SFP_down : std_logic_vector(2 downto 0) := (others =>'0');
731 --signal evt_buf_space : std_logic_vector(2 downto 0) := (others =>'0');
732 signal WrtMonBlkDone : std_logic_vector(2 downto 0) := (others =>'0');
733 signal WrtMonEvtDone : std_logic_vector(2 downto 0) := (others =>'0');
734 component icon2
735  PORT (
736  CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
737  CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
738 
739 end component;
740 component ila16x32k
741  PORT (
742  CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
743  CLK : IN STD_LOGIC;
744  DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
745  TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
746 
747 end component;
748 signal CONTROL0 : std_logic_vector(35 downto 0) := (others => '0');
749 signal CONTROL1 : std_logic_vector(35 downto 0) := (others => '0');
750 signal TRIG0 : std_logic_vector(7 downto 0) := (others => '0');
751 signal TRIG1 : std_logic_vector(7 downto 0) := (others => '0');
752 signal DATA0 : std_logic_vector(15 downto 0) := (others => '0');
753 signal DATA1 : std_logic_vector(15 downto 0) := (others => '0');
754 begin
755 --i_icon : icon2
756 -- port map (
757 -- CONTROL0 => CONTROL0,
758 -- CONTROL1 => CONTROL1);
759 --i_ila : ila16x32k
760 -- port map (
761 -- CONTROL => CONTROL0,
762 -- CLK => sysclk,
763 -- DATA => DATA0,
764 -- TRIG0 => TRIG0);
765 --DATA0(14) <= evt_buf_full(0);
766 --DATA0(13) <= evt_data_re(0);
767 --DATA0(12) <= evt_data_rdy(0);
768 --DATA0(11 downto 10) <= EventBufAddr(0)(5 downto 4);
769 --DATA0(9 downto 8) <= EventData(0)(65 downto 64);
770 --DATA0(7) <= wport_rdy(0);
771 --DATA0(6) <= wport_FIFO_full(0);
772 --DATA0(5) <= evt_data_we(0);
773 --DATA0(4) <= EventBufAddr_we(0);
774 --DATA0(3 downto 0) <= mem_stat(3 downto 0);
775 --TRIG0(7 downto 4) <= (others => '0');
776 --TRIG0(3) <= wport_rdy(0);
777 --TRIG0(2) <= EventBufAddr_we(0);
778 --TRIG0(1) <= evt_data_re(0);
779 --TRIG0(0) <= evt_data_rdy(0);
780 --
781 --i_il2 : ila16x32k
782 -- port map (
783 -- CONTROL => CONTROL1,
784 -- CLK => mem_stat(19),
785 -- DATA => DATA1,
786 -- TRIG0 => TRIG1);
787 --DATA1(14 downto 0) <= mem_stat(18 downto 4);
788 --TRIG1(7 downto 2) <= (others => '0');
789 --TRIG1(1 downto 0) <= mem_stat(18 downto 17);
790 i_TTS_if: TTS_if PORT MAP(
791  sysclk => sysclk,
792  TTS_clk => TTS_clk,
793  reset => sys_lock_n,
794  local_TTC => conf(8),
795  TTS => state,
796  TTS_out_p => TTS_out_p,
797  TTS_out_n => TTS_out_n
798  );
799 TxDisable <= TxDisable_i;
800 i_I2C: I2C PORT MAP(
801  clk => DRPclk ,
802  ipb_clk => clk125,
803  reset => sys_lock_n,
804  addr => ipb_master_out.ipb_addr,
805  rdata => I2C_data,
806  CLK_rdy => CLK_rdy,
807  CLK_SCL => CLK_SCL,
808  CLK_SDA => CLK_SDA,
809  SFP_ABS => SFP_ABS,
810  SFP_LOS => SFP_LOS,
811  SFP_SCL => SFP_SCL,
812  SFP_SDA => SFP_SDA
813  );
814 i_SPI_SCK_buf: bufh port map(i => SPI_SCK, o => SPI_SCK_buf);
815 i_SPI_if: SPI_if PORT MAP(
816  SCK => SPI_SCK ,
817  CSn => SPI_CS_b ,
818  MOSI => SPI_MOSI ,
819  MISO => SPI_MISO ,
820  SN => SN,
821  OT => ALM(0),
822  IsT1 => '1',
823  SPI_we => open,
824  en_RARP => en_RARP,
825  newIPADDR => newIPADDR,
826  IPADDR => IPADDR,
827  SPI_rdata => (others => '0'),
828  SPI_wdata => open,
829  SPI_addr => open
830  );
831 i_ttc_if: ttc_if PORT MAP(
832  clk => sysclk ,
833  refclk => sysclk,
834  reset => reset,
835  run => run,
836  DB_cmd_in => cmd(9),
837  DB_cmd_out => DB_cmd,
838  IsG2 => '0',
839  TTC_strobe => TTC_strobe,
840  sys_lock => sys_lock,
841  local_TTC => conf(8),
842  local_TTCcmd => local_TTCcmd ,
843  single_TTCcmd => cmd(8),
844  TTS_clk => TTS_clk,
845  BC0 => BC0,
846  DIV4 => DIV4,
847  DIV_nRST => DIV_nRST,
848  CDRclk_p => CDRclk_p,
849  CDRclk_n => CDRclk_n,
850  CDRclk_out => CDRclk,
851  CDRdata_p => CDRdata_p,
852  CDRdata_n => CDRdata_n,
853  TTCdata_p => TTCdata_p,
854  TTCdata_n => TTCdata_n,
855  TTC_LOS => TTC_LOS,
856  TTC_LOL => TTC_LOL,
857  BCN_off => BCN_off,
858  OC_off => OC_off,
859  en_cal_win => en_cal_win,
860  cal_win_high => cal_win_high ,
861  cal_win_low => cal_win_low ,
862  CalType => CalType,
863  TTC_Brcst => TTC_Brcst,
864  ovfl_warning => L1Aovfl_warning ,
865  ipb_clk => ipb_clk,
866  ipb_write => ipb_master_out.ipb_write ,
867  ipb_strobe => ipb_master_out.ipb_strobe ,
868  ipb_addr => ipb_master_out.ipb_addr ,
869  ipb_wdata => ipb_master_out.ipb_wdata ,
870  ipb_rdata => ttc_data,
871  en_localL1A => conf(2),
872  LocalL1A_cfg => LocalL1A_cfg ,
873  localL1A_s => cmd(26),
874  localL1A_r => cmd(10),
875  localL1A_periodic => status(10),
876  EvnRSt_l => cmd(11),
877  OcnRSt_l => cmd(12),
878  T3_trigger => T3_trigger,
879  en_brcst => en_brcst,
880  ttc_start => ttc_start,
881  ttc_stop => ttc_stop,
882  ttc_soft_reset => ttc_soft_reset ,
883  ttc_ready => ttc_ready,
884  ttc_serr => ttc_serr,
885  ttc_derr => ttc_derr,
886  ttc_bcnt_err => ttc_bcnt_err ,
887  rate_OFW => rate_OFW,
888  sync_lost => sync_lost,
889  inc_oc => inc_oc,
890  inc_l1ac => inc_l1ac,
891  inc_bcnterr => inc_bcnterr ,
892  inc_serr => inc_serr,
893  inc_derr => inc_derr,
894  state => state,
895  evn_fifo_full => evn_fifo_full ,
896  ttc_evcnt_reset => ttc_evcnt_reset ,
897  event_number_avl => event_number_avl ,
898  event_number => event_number
899  );
900 local_TTCcmd <= conf(5) or conf(8);
901 CalibCtrl(31) <= en_cal_win;
902 CalibCtrl(30 downto 28) <= "000";
903 CalibCtrl(27 downto 16) <= cal_win_high;
904 CalibCtrl(15 downto 12) <= CalType;
905 CalibCtrl(11 downto 0) <= cal_win_low;
906 cal_win_high(11 downto 6) <= "110110";
907 cal_win_low(11 downto 6) <= "110110";
908 i_S2V: IBUFDS generic map(DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25") port map(i => S2V_p, ib => S2V_n, o => S2V);
909 process(CDRclk)
910 begin
911  if(CDRclk'event and CDRclk = '1')then
912  if(conf(15) = '0')then
913  T3_trigger <= '0';
914  else
915  T3_trigger <= S2V;
916  end if;
917  end if;
918 end process;
919 i_GbE_REFCLK: IBUFDS_GTE2
920  port map
921  (
922  O => GbE_REFCLK,
923  ODIV2 => open,
924  CEB => '0',
925  I => GbE_REFCLK_P, -- Connect to package pin AB6
926  IB => GbE_REFCLK_N -- Connect to package pin AB5
927  );
928 i_TTCclk_in : IBUFGDS generic map (DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25")
929  port map (
930  O => TTCclk_in, -- Clock buffer output
931  I => TTCclk_p, -- Diff_p clock buffer input
932  IB => TTCclk_n -- Diff_n clock buffer input
933  );
934 i_TTC_CLK_buf: bufg port map(i => TTCclk_in, o => TTC_Clk);
935 i_sysclk_in_buf: bufh port map(i => GbE_REFCLK, o => sysclk_in);
936 i_PLL_sysclk : PLLE2_BASE
937  generic map (
938  BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
939  CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
940  CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
941  CLKIN1_PERIOD => 8.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
942  -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
943  CLKOUT0_DIVIDE => 5,
944  CLKOUT1_DIVIDE => 32,
945  CLKOUT2_DIVIDE => 20,
946  DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
947  REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
948  STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
949  )
950  port map (
951  -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
952  CLKOUT0 => sysclk_dcm,
953  CLKOUT1 => ipb_clk_dcm ,
954  CLKOUT2 => DRPclk_dcm,
955  -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
956  CLKFBOUT => clk125_dcm, -- 1-bit output: Feedback clock
957  -- Status Port: 1-bit (each) output: PLL status ports
958  LOCKED => sys_lock, -- 1-bit output: LOCK
959  -- Clock Input: 1-bit (each) input: Clock input
960  CLKIN1 => sysclk_in, -- 1-bit input: Input clock
961  -- Control Ports: 1-bit (each) input: PLL control ports
962  PWRDWN => '0', -- 1-bit input: Power-down
963  RST => '0', -- 1-bit input: Reset
964  -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
965  CLKFBIN => clk125 -- 1-bit input: Feedback clock
966  );
967 i_clk125_buf: bufg port map(i => clk125_dcm, o => clk125 );
968 i_ipb_clk_buf: bufg port map(i => ipb_clk_dcm, o => ipb_clk);
969 i_DRPclk_buf: bufg port map(i => DRPclk_dcm, o => DRPclk );
970 i_sysclk_buf: bufg port map(i => sysclk_dcm, o => sysclk );
971 --i_refclk_buf: bufg port map(i => refclk_dcm, o => refclk);
972 reset <= not sys_lock or cmd(0);
973 --sysclk <= refclk;
974 process(sysclk,reset)
975 begin
976  if(reset = '1')then
977  resetSyncRegs <= (others => '1');
978  elsif(sysclk'event and sysclk = '1')then
979  resetSyncRegs <= resetSyncRegs(1 downto 0) & '0';
980  end if;
981 end process;
982 i_ddr_if: ddr_if PORT MAP(
983  mem_clk_p => sys_clk_p,
984  mem_clk_n => sys_clk_n,
985  mem_rst => mem_rst,
986  clk_ref => sysclk,
987  sysclk => sysclk,
988  TCPclk => sysclk ,
989  reset => reset,
990  resetsys => resetSyncRegs(2),
991  run => run,
992  mem_test => mem_test,
993  EventData => EventData,
994  EventData_we => evt_data_we,
995  wport_rdy => wport_rdy,
996  WrtMonBlkDone => WrtMonBlkDone ,
997  WrtMonEvtDone => WrtMonEvtDone ,
998  KiloByte_toggle => open,
999  EoB_toggle => open,
1000  EventBufAddr => EventBufAddr ,
1001  EventBufAddr_we => EventBufAddr_we ,
1002  EventFIFOfull => wport_FIFO_full ,
1003  TCP_din => (others => '0'),
1004  TCP_channel => (others => '0'),
1005  TCP_we => '0',
1006  TCP_wcount => open,
1007  TCP_dout => open,
1008  TCP_raddr => (others => '0'),
1009  TCP_length => (others => '0'),
1010  TCP_dout_valid => open,
1011  TCP_rrqst => '0',
1012  TCP_rack => open,
1013  TCP_lastword => open,
1014  page_addr => ddr_pa,
1015  ipb_clk => ipb_clk,
1016  ipb_write => ipb_master_out.ipb_write ,
1017  ipb_strobe => ipb_master_out.ipb_strobe ,
1018  ipb_addr => ipb_master_out.ipb_addr ,
1019  ipb_wdata => ipb_master_out.ipb_wdata ,
1020  ipb_rdata => mem_data,
1021  ipb_ack => mem_ack,
1022  mem_stat => mem_stat,
1023  device_temp => device_temp ,
1024  ddr3_dq => ddr3_dq,
1025  ddr3_dm => ddr3_dm,
1026  ddr3_addr => ddr3_addr,
1027  ddr3_ba => ddr3_ba,
1028  ddr3_dqs_p => ddr3_dqs_p,
1029  ddr3_dqs_n => ddr3_dqs_n,
1030  ddr3_ras_n => ddr3_ras_n,
1031  ddr3_cas_n => ddr3_cas_n,
1032  ddr3_we_n => ddr3_we_n,
1033  ddr3_reset_n => ddr3_reset_n ,
1034  ddr3_cke => ddr3_cke,
1035  ddr3_odt => ddr3_odt,
1036  ddr3_ck_p => ddr3_ck_p,
1037  ddr3_ck_n => ddr3_ck_n
1038  );
1039 --mem_rst <= not sys_lock or not CLK_rdy or cmd(5) or cmd(0);
1040 mem_rst <= not sys_lock or not CLK_rdy or cmd(5);
1041 MACADDR <= x"080030f30" & '0' & not SN(8) & '0' & not SN(7 downto 6) & '1' & SN(5 downto 0);
1042 i_ipbus_if: ipbus_if PORT MAP(
1043  ipb_clk => ipb_clk,
1044  UsRclk => clk125,
1045  DRPclk => DRPclk,
1046  reset => rst_ipbus,
1047  GTX_RESET => sys_lock_n,
1048  MACADDR => MACADDR, -- new mac range 08-00-30-F3-00-00 to 08-00-30-F3-00-7F
1049  en_RARP => en_RARP,
1050  IPADDR => IPADDR,
1051  GbE_REFCLK => GbE_REFCLK,
1052  S6LINK_RXN => S6LINK_RXN,
1053  S6LINK_RXP => S6LINK_RXP,
1054  S6LINK_TXN => S6LINK_TXN,
1055  S6LINK_TXP => S6LINK_TXP,
1056  wr_AMC_en => wr_AMC_en,
1057  amc_en => AMC_en,
1058  ipb_out => ipb_master_out,
1059  ipb_in => ipb_master_in,
1060  got_SN => got_SN,
1061  SN => SN,
1062  debug_in => (others => '0'),
1063  debug_out => open
1064  );
1065 status(0) <= or_reduce(SFP_down);
1066 status(1) <= MonBufOvfl;
1067 status(2) <= mon_evt_cnt(10);
1068 status(3) <= MonBuf_empty;
1069 status(4) <= mem_stat(0); -- monitor input FIFO overflow
1070 status(5) <= not ttc_ready;
1071 status(6) <= ttc_bcnt_err;
1072 status(7) <= ttc_serr;
1073 status(8) <= ttc_derr;
1074 status(9) <= sync_lost;
1075 status(13) <= L1Aovfl_warning;
1076 status(15) <= mem_stat(63);
1077 status(23) <= '0';
1078 run <= conf(0);
1079 EnSFP(3) <= not conf(1);
1080 mem_test <= conf(6) & conf(4);
1081 --en_brcst <= conf(5);
1082 en_brcst <= '0';
1083 i_cmd0_dl0 : SRL16E
1084  port map (
1085  Q => cmd0_dl(0), -- SRL data output
1086  A0 => '1', -- Select[0] input
1087  A1 => '1', -- Select[1] input
1088  A2 => '1', -- Select[2] input
1089  A3 => '0', -- Select[3] input
1090  CE => '1', -- Clock enable input
1091  CLK => ipb_clk, -- Clock input
1092  D => cmd(0) -- SRL data input
1093  );
1094 i_cmd0_dl1 : SRL16E
1095  port map (
1096  Q => cmd0_dl(1), -- SRL data output
1097  A0 => '1', -- Select[0] input
1098  A1 => '1', -- Select[1] input
1099  A2 => '1', -- Select[2] input
1100  A3 => '0', -- Select[3] input
1101  CE => '1', -- Clock enable input
1102  CLK => ipb_clk, -- Clock input
1103  D => cmd0_dl(0) -- SRL data input
1104  );
1105 i_cmd2_dl0 : SRL16E
1106  port map (
1107  Q => cmd2_dl(0), -- SRL data output
1108  A0 => '1', -- Select[0] input
1109  A1 => '1', -- Select[1] input
1110  A2 => '1', -- Select[2] input
1111  A3 => '0', -- Select[3] input
1112  CE => '1', -- Clock enable input
1113  CLK => ipb_clk, -- Clock input
1114  D => cmd(2) -- SRL data input
1115  );
1116 i_cmd2_dl1 : SRL16E
1117  port map (
1118  Q => cmd2_dl(1), -- SRL data output
1119  A0 => '1', -- Select[0] input
1120  A1 => '1', -- Select[1] input
1121  A2 => '1', -- Select[2] input
1122  A3 => '0', -- Select[3] input
1123  CE => '1', -- Clock enable input
1124  CLK => ipb_clk, -- Clock input
1125  D => cmd2_dl(0) -- SRL data input
1126  );
1127 process(ipb_clk)
1128 begin
1129  if(ipb_clk'event and ipb_clk = '1')then
1130  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = CSR_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1131  cmd <= ipb_master_out.ipb_wdata;
1132  else
1133  cmd <= (others => '0');
1134  end if;
1135  conf7_q <= conf(7);
1136  conf7_fall <= conf7_q and not conf(7);
1137  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = CFG_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1138  conf <= ipb_master_out.ipb_wdata(15 downto 0);
1139  end if;
1140  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = HTR_EN_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1141  Dis_pd <= ipb_master_out.ipb_wdata(15);
1142  EnSFP(2 downto 0) <= ipb_master_out.ipb_wdata(14 downto 12);
1143  AMC_en <= ipb_master_out.ipb_wdata(11 downto 0);
1144  if(AMC_en = ipb_master_out.ipb_wdata(11 downto 0))then
1145  wr_AMC_en <= '0';
1146  else
1147  wr_AMC_en <= '1';
1148  end if;
1149  if(EnSFP(2 downto 0) = ipb_master_out.ipb_wdata(14 downto 12))then
1150  wr_EnSFP <= '0';
1151  else
1152  wr_EnSFP <= '1';
1153  end if;
1154  else
1155  wr_AMC_en <= '0';
1156  wr_EnSFP <= '0';
1157  end if;
1158  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"001a" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1159  TTS_disable <= ipb_master_out.ipb_wdata(11 downto 0);
1160  end if;
1161  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = TTC_cal_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1162  en_cal_win <= ipb_master_out.ipb_wdata(31);
1163  cal_win_high(5 downto 0) <= ipb_master_out.ipb_wdata(21 downto 16);
1164  cal_win_low(5 downto 0) <= ipb_master_out.ipb_wdata(5 downto 0);
1165  end if;
1166  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1167  Source_ID(0)(11 downto 0) <= ipb_master_out.ipb_wdata(11 downto 0);
1168  end if;
1169  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id1_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1170  Source_ID(1)(11 downto 0) <= ipb_master_out.ipb_wdata(11 downto 0);
1171  end if;
1172  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id2_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1173  Source_ID(2)(11 downto 0) <= ipb_master_out.ipb_wdata(11 downto 0);
1174  end if;
1175  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"001c" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1176  LocalL1A_cfg <= ipb_master_out.ipb_wdata;
1177  end if;
1178  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SFP_CSR_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1179  LSC_ID(15 downto 2) <= ipb_master_out.ipb_wdata(31 downto 18);
1180  TxDisable_i <= ipb_master_out.ipb_wdata(15 downto 12);
1181  end if;
1182  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = TTC_bcnt_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1183  OC_OFF <= ipb_master_out.ipb_wdata(19 downto 16);
1184  BCN_OFF <= ipb_master_out.ipb_wdata(12 downto 0);
1185  end if;
1186  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = fake_length_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1187  fake_length <= ipb_master_out.ipb_wdata(19 downto 0);
1188  end if;
1189  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"0019" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1190  pattern <= ipb_master_out.ipb_wdata(11 downto 8);
1191  end if;
1192  if(reset = '1' or (ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = MON_ctrl_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1'))then
1193  ddr_pa <= (others => '0');
1194  elsif(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = PAGE_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1195  if(run = '1')then
1196  if(MonBuf_empty = '0')then
1197  ddr_pa <= ddr_pa + 1;
1198  end if;
1199  else
1200  ddr_pa <= ipb_master_out.ipb_wdata(9 downto 0);
1201  end if;
1202  end if;
1203  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = PAGE_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1' and run = '1' and MonBuf_empty = '0')then
1204  inc_ddr_pa <= '1';
1205  else
1206  inc_ddr_pa <= '0';
1207  end if;
1208  if(DB_cmd = '1')then
1209  status_l <= status(22 downto 0);
1210  SFP_down_l <= SFP_down;
1211  SFP_status_l <= TxFault & (TTC_LOL or TTC_LOL) & SFP_LOS & SFP_ABS;
1212  AMC_status_l <= AMC_status;
1213  end if;
1214  end if;
1215 end process;
1216 ipb_master_in.ipb_ack <= ipb_master_out.ipb_strobe when ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(17) = '0' else mem_ack;
1217 process(ipb_master_out.ipb_addr)
1218 begin
1219  if(ipb_master_out.ipb_addr(27) = '1' or ipb_master_out.ipb_addr(17) = '1')then
1220  ipb_master_in.ipb_rdata <= mem_data;
1221  elsif(ipb_master_out.ipb_addr(14 downto 5) = CSR_addr(14 downto 5))then
1222  if(ipb_master_out.ipb_addr(15) = '0')then
1223  case ipb_master_out.ipb_addr(4 downto 0) is
1224  when "00000" => ipb_master_in.ipb_rdata <= not SN(7 downto 0) & not SN(8) & status(22 downto 0);
1225  when "00001" => ipb_master_in.ipb_rdata <= K7version & conf;
1226  when "00010" => ipb_master_in.ipb_rdata <= mon_ctrl;
1227  when "00011" => ipb_master_in.ipb_rdata <= '0' & SFP_down & AMC_Ready & Dis_pd & EnSFP(2 downto 0) & AMC_en;
1228  when "00100" => ipb_master_in.ipb_rdata <= LSC_ID & TxDisable_i & TxFault & (TTC_LOL or TTC_LOL) & SFP_LOS & SFP_ABS;
1229  when "00101" => ipb_master_in.ipb_rdata <= AMC_status;
1230  when "00111" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(0);
1231  when "01000" => ipb_master_in.ipb_rdata <= x"000" & OC_OFF & "000" & BCN_OFF;
1232  when "01001" => ipb_master_in.ipb_rdata <= CalibCtrl;
1233  when "01010" => ipb_master_in.ipb_rdata <= mem_stat(31 downto 0);
1234  when "01011" => ipb_master_in.ipb_rdata <= mem_stat(63 downto 32);
1235  when "01100" => ipb_master_in.ipb_rdata <= x"00000" & "00" & ddr_pa;
1236  when "01101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(15 downto 0) & '0';
1237  when "01110" => ipb_master_in.ipb_rdata <= mon_evt_cnt;
1238  when "01111" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(31 downto 16) & '0';
1239  when "10000" => ipb_master_in.ipb_rdata <= x"000" & "00" & mon_buf_avl & '1' & '0' & wport_FIFO_full & '0' & wport_rdy & x"0" & '0' & evt_data_rdy;
1240  when "10001" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(1);
1241  when "10010" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(2);
1242  when "11000" => ipb_master_in.ipb_rdata <= x"000" & fake_length;
1243  when "11001" => ipb_master_in.ipb_rdata <= x"00" & "000" & TTS_coded & state & pattern & x"00";
1244  when "11010" => ipb_master_in.ipb_rdata <= x"00000" & TTS_disable;
1245  when "11100" => ipb_master_in.ipb_rdata <= LocalL1A_cfg;
1246  when "11101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(47 downto 32) & '0';
1247  when "11110" => ipb_master_in.ipb_rdata <= DNA(31 downto 0);
1248  when "11111" => ipb_master_in.ipb_rdata <= "0000000" & DNA(56 downto 32);
1249  when others => ipb_master_in.ipb_rdata <= (others => '0');
1250  end case;
1251  else
1252  case ipb_master_out.ipb_addr(4 downto 0) is
1253  when "00000" => ipb_master_in.ipb_rdata <= not SN(7 downto 0) & not SN(8) & status_l;
1254  when "00001" => ipb_master_in.ipb_rdata <= K7version & conf;
1255  when "00010" => ipb_master_in.ipb_rdata <= mon_ctrl;
1256  when "00011" => ipb_master_in.ipb_rdata <= '0' & SFP_down_l & AMC_Ready & Dis_pd & EnSFP(2 downto 0) & AMC_en;
1257  when "00100" => ipb_master_in.ipb_rdata <= LSC_ID & TxDisable_i & SFP_status_l;
1258  when "00101" => ipb_master_in.ipb_rdata <= AMC_status_l;
1259  when "00111" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(0);
1260  when "01000" => ipb_master_in.ipb_rdata <= x"000" & OC_OFF & "000" & BCN_OFF;
1261  when "01001" => ipb_master_in.ipb_rdata <= CalibCtrl;
1262  when "01010" => ipb_master_in.ipb_rdata <= mem_stat(31 downto 0);
1263  when "01011" => ipb_master_in.ipb_rdata <= mem_stat(63 downto 32);
1264  when "01100" => ipb_master_in.ipb_rdata <= x"00000" & "00" & ddr_pa;
1265  when "01101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(15 downto 0) & '0';
1266  when "01110" => ipb_master_in.ipb_rdata <= mon_evt_cnt;
1267  when "01111" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(31 downto 16) & '0';
1268  when "10000" => ipb_master_in.ipb_rdata <= x"000" & "00" & mon_buf_avl & '1' & '0' & wport_FIFO_full & '0' & wport_rdy & x"0" & '0' & evt_data_rdy;
1269  when "10001" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(1);
1270  when "10010" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(2);
1271  when "11000" => ipb_master_in.ipb_rdata <= x"000" & fake_length;
1272  when "11001" => ipb_master_in.ipb_rdata <= x"00" & "000" & TTS_coded & state & pattern & x"00";
1273  when "11010" => ipb_master_in.ipb_rdata <= x"00000" & TTS_disable;
1274  when "11100" => ipb_master_in.ipb_rdata <= LocalL1A_cfg;
1275  when "11101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(47 downto 32) & '0';
1276  when "11110" => ipb_master_in.ipb_rdata <= DNA(31 downto 0);
1277  when "11111" => ipb_master_in.ipb_rdata <= "0000000" & DNA(56 downto 32);
1278  when others => ipb_master_in.ipb_rdata <= (others => '0');
1279  end case;
1280  end if;
1281  else
1282  ipb_master_in.ipb_rdata <= AMC_data or TTC_cntr_data or I2C_data or sysmon_data or SFP_data or ttc_data;
1283  end if;
1284 end process;
1285 rst_cntr <= cmd(1) or cmd(0);
1286 ttc_resync <= ttc_soft_reset;
1287 process(sysClk,reset)
1288 begin
1289  if(reset = '1')then
1290  TTS_wait <= (others => '0');
1291  elsif(sysClk'event and sysClk = '1')then
1292  if(ttc_resync = '1')then
1293  TTS_wait <= (others => '0');
1294  elsif(TTS_wait(20) = '0' and sync_lost = '0' and AllEventBuilt = '1')then
1295  TTS_wait <= TTS_wait + 1;
1296  end if;
1297  end if;
1298 end process;
1299 process(sysClk,reset)
1300 begin
1301  if(reset = '1')then
1302  state <= "0100";
1303  elsif(sysClk'event and sysClk = '1')then
1304  if(run = '0' and conf(12) = '1')then
1305  state <= pattern;
1306  elsif(run = '0')then
1307  state <= "0100"; -- changed upon request starting version 0x3023
1308  elsif(ttc_resync = '1')then
1309  state <= "0100";
1310  else
1311  case state is
1312  when "1000" => -- Ready
1313  if(TTS_coded(4) = '1')then
1314  state <= "1111";
1315  elsif(TTS_coded(3) = '1')then
1316  state <= "1100";
1317  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1318  state <= "0010";
1319  elsif(L1Aovfl_warning = '1' or evn_fifo_full = '1' or rate_OFWp = '1' or TTS_coded(1) = '1' or TTS_coded(0) = '1')then
1320  state <= "0001";
1321  end if;
1322  when "0001" => -- OFW
1323  if(TTS_coded(4) = '1')then
1324  state <= "1111";
1325  elsif(TTS_coded(3) = '1')then
1326  state <= "1100";
1327  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1328  state <= "0010";
1329  elsif(evn_fifo_full = '1' or rate_OFWp = '1' or TTS_coded(1) = '1')then
1330  state <= "0100";
1331  elsif(L1Aovfl_warning = '0' and rate_OFWp = '0' and TTS_coded(0) = '0')then
1332  state <= "1000";
1333  end if;
1334  when "0100" => -- Busy
1335  if(TTS_wait(20) = '0')then
1336  elsif(TTS_coded(4) = '1')then
1337  state <= "1111";
1338  elsif(TTS_coded(3) = '1')then
1339  state <= "1100";
1340  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1341  state <= "0010";
1342  elsif(evn_fifo_full = '0' and rate_OFWp = '0' and TTS_coded(1) = '0')then
1343  state <= "0001";
1344  end if;
1345  when others => null; -- x"0" or x"f" disconnected, x"2" OOS, x"c" error
1346  end case;
1347  end if;
1348  end if;
1349 end process;
1350 ipb_master_in.ipb_err <= '0';
1351 i_AMC_if: AMC_if PORT MAP(
1352  sysclk => sysclk,
1353  ipb_clk => ipb_clk,
1354  clk125 => clk125,
1355  DRPclk => DRPclk,
1356  reset => AMC_reset,
1357  DB_cmd => DB_cmd,
1358  ReSync => ttc_resync,
1359  GTXreset => amc_GTXreset,
1360  resetCntr => rst_cntr,
1361  AllEventBuilt => AllEventBuilt ,
1362  run => run,
1363  en_inject_err => conf(10),
1364  Dis_pd => Dis_pd,
1365  enSFP => enSFP,
1366  test => conf(7),
1367  NoReSyncFake => conf(11),
1368  WaitMonBuf => conf(14),
1369  fake_length => fake_length ,
1370  en_localL1A => conf(2),
1371  T1_version => K7version(7 downto 0),
1372  Source_ID => Source_ID,
1373  AMC_en => AMC_en,
1374  TTS_disable => TTS_disable ,
1375  AMC_Ready => AMC_Ready,
1376  BC0_lock => open,
1377  TTC_lock => open,
1378  AMC_REFCLK_P => AMC_REFCLK_P ,
1379  AMC_REFCLK_N => AMC_REFCLK_N ,
1380  AMC_RXN => AMC_RXN,
1381  AMC_RXP => AMC_RXP,
1382  AMC_TXN => AMC_TXN,
1383  AMC_TXP => AMC_TXP,
1384  AMC_status => AMC_status,
1385  evt_data => EventData,
1386  evt_data_we => evt_data_we ,
1387  evt_buf_full => evt_buf_full ,
1388  evt_data_re => evt_data_re ,
1389  evt_data_rdy => evt_data_rdy ,
1390  ddr_pa => ddr_pa,
1391  MonBuf_empty => MonBuf_empty ,
1392  mon_evt_wc => mon_evt_wc,
1393  mon_ctrl => mon_ctrl,
1394  mon_buf_avl => mon_buf_avl ,
1395  TCPbuf_avl => '1',
1396  buf_rqst => EventBuf_rqst,
1397  ipb_write => ipb_master_out.ipb_write ,
1398  ipb_strobe => ipb_master_out.ipb_strobe ,
1399  ipb_addr => ipb_master_out.ipb_addr ,
1400  ipb_wdata => ipb_master_out.ipb_wdata ,
1401  ipb_rdata => AMC_data,
1402  ipb_ack => AMC_ack,
1403  TTC_clk => TTC_clk,
1404  TTC_LOS => TTC_LOS,
1405  BC0 => '0',
1406  ttc_evcnt_reset => ttc_evcnt_reset ,
1407  event_number_avl => event_number_avl ,
1408  event_number => event_number ,
1409  evn_buf_full => evn_fifo_full,
1410  ovfl_warning => L1Aovfl_warning ,
1411  TrigData => open,
1412  TTS_coded => TTS_coded
1413  );
1414 AMC_reset <= not sys_lock or cmd(0) or cmd0_dl(1);
1415 amc_GTXreset <= wr_AMC_en or conf7_fall or not sys_lock;
1416 sys_lock_n <= not sys_lock;
1417 i_DAQLSC_if: DAQLSCXG_3x_if PORT MAP(
1418  sysclk => sysclk,
1419  clk125 => clk125,
1420  DRPclk => DRPclk,
1421  reset => AMC_reset,
1422  daq_reset => lsc_reset,
1423  gtx_reset => lsc_GTXreset,
1424  rstCntr => rst_cntr,
1425  test => '0',
1426  DB_cmd => DB_cmd,
1427  Dis_pd => Dis_pd,
1428  enSFP => enSFP,
1429  SFP_ABS => SFP_ABS(2 downto 0),
1430  LSC_ID => LSC_ID,
1431  SFP_down => SFP_down,
1432  inc_ddr_pa => inc_ddr_pa,
1433  evt_data_rdy => evt_data_rdy ,
1434  EventData_in => EventData,
1435  EventData_we => evt_data_we,
1436  EventData_re => evt_data_re,
1437  evt_buf_full => evt_buf_full ,
1438  buf_rqst => EventBuf_rqst,
1439  WaitMonBuf => conf(14),
1440  MonBufOverWrite => conf(13),
1441  MonBuf_avl => mon_buf_avl,
1442  MonBuf_empty => MonBuf_empty ,
1443  MonBufOvfl => MonBufOvfl,
1444  mon_evt_cnt => mon_evt_cnt ,
1445  WrtMonBlkDone => WrtMonBlkDone ,
1446  WrtMonEvtDone => WrtMonEvtDone ,
1447  wport_rdy => wport_rdy,
1448  wport_FIFO_full => wport_FIFO_full ,
1449  EventBufAddr_we => EventBufAddr_we ,
1450  EventBufAddr => EventBufAddr ,
1451  SFP0_RXN => SFP0_RXN,
1452  SFP0_RXP => SFP0_RXP,
1453  SFP1_RXN => SFP1_RXN,
1454  SFP1_RXP => SFP1_RXP,
1455  SFP2_RXN => SFP2_RXN,
1456  SFP2_RXP => SFP2_RXP,
1457  SFP0_TXN => SFP0_TXN,
1458  SFP0_TXP => SFP0_TXP,
1459  SFP1_TXN => SFP1_TXN,
1460  SFP1_TXP => SFP1_TXP,
1461  SFP2_TXN => SFP2_TXN,
1462  SFP2_TXP => SFP2_TXP,
1463  SFP_REFCLK_P => GbE_REFCLK,
1464  SFP_REFCLK_N => '0',
1465  ipb_clk => ipb_clk,
1466  ipb_write => ipb_master_out.ipb_write ,
1467  ipb_strobe => ipb_master_out.ipb_strobe ,
1468  ipb_addr => ipb_master_out.ipb_addr ,
1469  ipb_wdata => ipb_master_out.ipb_wdata ,
1470  ipb_rdata => SFP_data,
1471  ipb_ack => SFP_ack
1472  );
1473 --lsc_reset <= not sys_lock or cmd(2) or cmd2_dl(1);
1474 --lsc_GTXreset <= wr_enSFP or not sys_lock or cmd2_dl(0);
1475 lsc_reset <= lsc_start or cmd(2) or cmd2_dl(1);
1476 lsc_GTXreset <= lsc_start or cmd2_dl(0);
1477 process(DRPclk, sys_lock)
1478 begin
1479  if(sys_lock = '0')then
1480  lsc_start <= '1';
1481  elsif(DRPclk'event and DRPclk = '1')then
1482  if(CLK_rdy = '1')then
1483  lsc_start <= '0';
1484  end if;
1485  end if;
1486 end process;
1487 i_sysmon_if: sysmon_if PORT MAP(
1488  DRPclk => ipb_clk,
1489  DB_cmd => DB_cmd,
1490  SN => SN,
1491  VAUXN_IN => VAUXN,
1492  VAUXP_IN => VAUXP,
1493  addr => ipb_master_out.ipb_addr(15 downto 0),
1494  data => sysmon_data ,
1495  device_temp => device_temp ,
1496  ALM => ALM,
1497  OT => OT
1498  );
1499 process(ipb_clk)
1500 begin
1501  if(ipb_clk'event and ipb_clk = '1')then
1502  newIPADDRSyncRegs <= newIPADDRSyncRegs(1 downto 0) & newIPADDR;
1503  rst_ipbus <= not newIPADDRSyncRegs(2) and newIPADDR;
1504  end if;
1505 end process;
1506 i_TTC_cntr: TTC_cntr PORT MAP(
1507  sysclk => sysclk,
1508  clk125 => clk125,
1509  ipb_clk => ipb_clk,
1510  reset => reset,
1511  rst_cntr => rst_cntr,
1512  DB_cmd => DB_cmd,
1513  inc_serr => inc_serr,
1514  inc_derr => inc_derr,
1515  inc_bcnterr => inc_bcnterr ,
1516  inc_l1ac => inc_l1ac,
1517  run => run,
1518  state => state,
1519  ttc_resync => ttc_resync,
1520  ipb_addr => ipb_master_out.ipb_addr (15 downto 0),
1521  ipb_rdata => TTC_cntr_data
1522  );
1523 i_DNA_PORT : DNA_PORT
1524  generic map (
1525  SIM_DNA_VALUE => X"00123456789abcd" -- Specifies a sample 57-bit DNA value for simulation
1526  )
1527  port map (
1528  DOUT => DNA_out, -- 1-bit output: DNA output data.
1529  CLK => ipb_clk, -- 1-bit input: Clock input.
1530  DIN => '0', -- 1-bit input: User data input pin.
1531  READ => load_DNA, -- 1-bit input: Active high load DNA, active low read input.
1532  SHIFT => shift_DNA(1) -- 1-bit input: Active high shift enable input.
1533  );
1534 process(ipb_clk)
1535 begin
1536  if(ipb_clk'event and ipb_clk = '1')then
1537  load_DNA <= not sys_lock;
1538  if(sys_lock = '0')then
1539  shift_DNA(0) <= '0';
1540  elsif(load_DNA = '1')then
1541  shift_DNA(0) <= '1';
1542  elsif(shift_DNA(2) = '1' and or_reduce(DNA_cntr(5 downto 1)) = '0')then
1543  shift_DNA(0) <= '0';
1544  end if;
1545  shift_DNA(2) <= shift_DNA(0);
1546  if(shift_DNA(2) = '1')then
1547  DNA_cntr <= DNA_cntr - 1;
1548  elsif(shift_DNA(0) = '1')then
1549  DNA_cntr <= "110111";
1550  end if;
1551  if(shift_DNA(2) = '1')then
1552  DNA <= DNA(55 downto 0) & DNA_OUT;
1553  end if;
1554  end if;
1555 end process;
1556 process(ipb_clk)
1557 begin
1558  if(ipb_clk'event and ipb_clk = '0')then
1559  shift_DNA(1) <= shift_DNA(0);
1560  end if;
1561 end process;
1562 end Behavioral;
1563 
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