AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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AMC13_T1_CMS10G.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 14:49:29 05/12/2010
6 -- Design Name:
7 -- Module Name: DTC_T2 - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 use work.ipbus.ALL;
26 use work.amc13_pack.all;
27 
28 -- Uncomment the following library declaration if using
29 -- arithmetic functions with Signed or Unsigned values
30 -- use IEEE.NUMERIC_STD.ALL;
31 
32 -- Uncomment the following library declaration if instantiating
33 -- any Xilinx primitives in this code.
34 library UNISIM;
35 use UNISIM.VComponents.all;
36 Library UNIMACRO;
37 use UNIMACRO.vcomponents.all;
38 
39 entity AMC13_T1 is
40  Port (
41  VAUXP : in STD_LOGIC_VECTOR(12 downto 0);
42  VAUXN : in STD_LOGIC_VECTOR(12 downto 0);
43 -- I2C interface
44  CLK_SCL : out STD_LOGIC;
45  CLK_SDA : inout STD_LOGIC;
46  SFP_SCL : out STD_LOGIC_VECTOR(3 downto 0);
47  SFP_SDA : inout STD_LOGIC_VECTOR(3 downto 0);
48 -- SFP slow control
49  SFP_LOS : in STD_LOGIC_VECTOR(2 downto 0);
50  SFP_ABS : in STD_LOGIC_VECTOR(3 downto 0);
51  TxFault : in STD_LOGIC_VECTOR(3 downto 0);
52  TxDisable : out STD_LOGIC_VECTOR(3 downto 0);
53 -- RATE : out STD_LOGIC_VECTOR(3 downto 0);
54 -- CDR signals
55  DIV4 : out STD_LOGIC;
56  DIV_nRST : out STD_LOGIC;
57  CDRclk_p : in STD_LOGIC;
58  CDRclk_n : in STD_LOGIC;
59  CDRdata_p : in STD_LOGIC;
60  CDRdata_n : in STD_LOGIC;
61  TTCdata_p : out STD_LOGIC;
62  TTCdata_n : out STD_LOGIC;
63  TTCclk_p : in STD_LOGIC;
64  TTCclk_n : in STD_LOGIC;
65  TTC_LOS : in STD_LOGIC;
66  TTC_LOL : in STD_LOGIC;
67  TTS_out_p : out STD_LOGIC;
68  TTS_out_n : out STD_LOGIC;
69 -- SPI interface
70  SPI_SCK : in STD_LOGIC;
71  SPI_CS_b : in STD_LOGIC;
72  SPI_MOSI : in STD_LOGIC;
73  SPI_MISO : out STD_LOGIC;
74 -- DDR3 pins
75  sys_clk_p : in STD_LOGIC;
76  sys_clk_n : in STD_LOGIC;
77  ddr3_dq : inout STD_LOGIC_VECTOR(31 downto 0);
78  ddr3_addr : out STD_LOGIC_VECTOR(13 downto 0);
79  ddr3_ba : out STD_LOGIC_VECTOR (2 downto 0);
80  ddr3_dm : out STD_LOGIC_VECTOR (3 downto 0);
81  ddr3_dqs_p : inout STD_LOGIC_VECTOR(3 downto 0);
82  ddr3_dqs_n : inout STD_LOGIC_VECTOR(3 downto 0);
83  ddr3_ras_n : out STD_LOGIC;
84  ddr3_cas_n : out STD_LOGIC;
85  ddr3_we_n : out STD_LOGIC;
86  ddr3_reset_n : out STD_LOGIC;
87  ddr3_cke : out STD_LOGIC_vector(0 to 0);
88  ddr3_odt : out STD_LOGIC_vector(0 to 0);
89  ddr3_ck_p : out STD_LOGIC_vector(0 to 0);
90  ddr3_ck_n : out STD_LOGIC_vector(0 to 0);
91  SFP0_RXN : in STD_LOGIC;
92  SFP0_RXP : in STD_LOGIC;
93  SFP1_RXN : in STD_LOGIC;
94  SFP1_RXP : in STD_LOGIC;
95  SFP2_RXN : in STD_LOGIC;
96  SFP2_RXP : in STD_LOGIC;
97  SFP0_TXN : out STD_LOGIC;
98  SFP0_TXP : out STD_LOGIC;
99  SFP1_TXN : out STD_LOGIC;
100  SFP1_TXP : out STD_LOGIC;
101  SFP2_TXN : out STD_LOGIC;
102  SFP2_TXP : out STD_LOGIC;
103  SFP_REFCLK_N : in STD_LOGIC;
104  SFP_REFCLK_P : in STD_LOGIC;
105  AMC_REFCLK_N : in STD_LOGIC;
106  AMC_REFCLK_P : in STD_LOGIC;
107  AMC_RXN : in STD_LOGIC_VECTOR(12 downto 1);
108  AMC_RXP : in STD_LOGIC_VECTOR(12 downto 1);
109  AMC_TXN : out STD_LOGIC_VECTOR(12 downto 1);
110  AMC_TXP : out STD_LOGIC_VECTOR(12 downto 1);
111 -- signal to/from DTC_T2
112  S6LINK_RXN : in STD_LOGIC;
113  S6LINK_RXP : in STD_LOGIC;
114  S6LINK_TXN : out STD_LOGIC;
115  S6LINK_TXP : out STD_LOGIC;
116  S2V_p : in STD_LOGIC;
117  S2V_n : in STD_LOGIC;
118 -- V2S_p : out STD_LOGIC;
119 -- V2S_n : out STD_LOGIC;
120  GbE_REFCLK_N : in STD_LOGIC;
121  GbE_REFCLK_P : in STD_LOGIC);
122 end AMC13_T1;
123 
124 architecture Behavioral of AMC13_T1 is
125 COMPONENT TTS_if
126  PORT(
127  sysclk : IN std_logic;
128  TTS_clk : IN std_logic;
129  reset : IN std_logic;
130  local_TTC : in STD_LOGIC;
131  TTS : IN std_logic_vector(3 downto 0);
132  TTS_out_p : OUT std_logic;
133  TTS_out_n : OUT std_logic
134  );
135 END COMPONENT;
136 COMPONENT ttc_if
137  PORT(
138  clk : IN std_logic;
139  refclk : IN std_logic;
140  reset : IN std_logic;
141  run : IN std_logic;
142  IsG2 : IN std_logic;
143  sys_lock : IN std_logic;
144  local_TTC : IN std_logic;
145  local_TTCcmd : IN std_logic;
146  single_TTCcmd : in STD_LOGIC;
147  CDRclk_p : IN std_logic;
148  CDRclk_n : IN std_logic;
149  CDRdata_p : IN std_logic;
150  CDRdata_n : IN std_logic;
151  TTC_LOS : IN std_logic;
152  TTC_LOL : IN std_logic;
153  BCN_off : IN std_logic_vector(12 downto 0);
154  OC_off : IN std_logic_vector(3 downto 0);
155  en_cal_win : IN std_logic;
156  cal_win_high : IN std_logic_vector(11 downto 0);
157  cal_win_low : IN std_logic_vector(11 downto 0);
158  en_localL1A : IN std_logic;
159  LocalL1A_cfg : IN std_logic_vector(31 downto 0);
160  localL1A_s : IN std_logic;
161  localL1A_r : IN std_logic;
162  T3_trigger : in std_logic;
163  EvnRSt_l : in std_logic;
164  OcnRSt_l : in std_logic;
165  ovfl_warning : IN std_logic;
166  ipb_clk : IN std_logic;
167  ipb_write : in STD_LOGIC;
168  ipb_strobe : in STD_LOGIC;
169  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
170  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
171  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
172  en_brcst : IN std_logic;
173  state : IN std_logic_vector(3 downto 0);
174  evn_fifo_full : IN std_logic;
175  BC0 : OUT std_logic;
176  TTC_strobe : OUT std_logic;
177  TTS_clk : OUT std_logic;
178  DIV4 : OUT std_logic;
179  DIV_nRST : OUT std_logic;
180  CDRclk_out : OUT std_logic;
181  TTCdata_p : OUT std_logic;
182  TTCdata_n : OUT std_logic;
183  CalType : OUT std_logic_vector(3 downto 0);
184  TTC_Brcst : OUT std_logic_vector(3 downto 0);
185  localL1A_periodic : OUT std_logic;
186  ttc_start : OUT std_logic;
187  ttc_stop : OUT std_logic;
188  ttc_soft_reset : OUT std_logic;
189  ttc_ready : OUT std_logic;
190  ttc_serr : OUT std_logic;
191  ttc_derr : OUT std_logic;
192  ttc_bcnt_err : OUT std_logic;
193  rate_OFW : OUT std_logic;
194  sync_lost : OUT std_logic;
195  inc_oc : OUT std_logic;
196  inc_l1ac : OUT std_logic;
197  inc_bcnterr : OUT std_logic;
198  inc_serr : OUT std_logic;
199  inc_derr : OUT std_logic;
200  ttc_evcnt_reset : OUT std_logic;
201  event_number_avl : OUT std_logic;
202  event_number : OUT std_logic_vector(59 downto 0)
203  );
204 END COMPONENT;
205 COMPONENT AMC_if
206  Generic (useTCPIP : boolean := false; AMC_useTRIG : boolean := false; simulation : boolean := false);
207  PORT(
208  sysclk : IN std_logic;
209  ipb_clk : IN std_logic;
210  clk125 : IN std_logic;
211  DRPclk : IN std_logic;
212  GTXreset : IN std_logic;
213  reset : IN std_logic;
214  resetCntr : IN std_logic;
215  ReSync : IN std_logic;
216  AllEventBuilt : OUT std_logic;
217  run : IN std_logic;
218  Dis_pd : in STD_LOGIC;
219  enSFP : IN std_logic_vector(3 downto 0);
220  en_localL1A : IN std_logic;
221  test : IN std_logic;
222  NoReSyncFake : IN std_logic;
223  WaitMonBuf : IN std_logic;
224  fake_length : IN std_logic_vector(19 downto 0);
225  T1_version : IN std_logic_vector(7 downto 0);
226  Source_ID : IN array3x12;
227  AMC_en : IN std_logic_vector(11 downto 0);
228  TTS_disable : IN std_logic_vector(11 downto 0);
229  AMC_REFCLK_P : IN std_logic;
230  AMC_REFCLK_N : IN std_logic;
231  AMC_RXN : IN std_logic_vector(12 downto 1);
232  AMC_RXP : IN std_logic_vector(12 downto 1);
233  evt_data_re : IN std_logic_vector(2 downto 0);
234  evt_buf_full : IN std_logic_vector(2 downto 0);
235  ddr_pa : IN std_logic_vector(9 downto 0);
236  MonBuf_empty : IN std_logic;
237  mon_buf_avl : IN std_logic;
238  TCPbuf_avl : IN std_logic;
239  ipb_write : IN std_logic;
240  ipb_strobe : IN std_logic;
241  ipb_addr : IN std_logic_vector(31 downto 0);
242  ipb_wdata : IN std_logic_vector(31 downto 0);
243  TTC_clk : IN std_logic;
244  TTC_LOS : IN std_logic;
245  BC0 : IN std_logic;
246  ttc_evcnt_reset : IN std_logic;
247  event_number_avl : IN std_logic;
248  event_number : IN std_logic_vector(59 downto 0);
249  AMC_Ready : OUT std_logic_vector(11 downto 0);
250  BC0_lock : OUT std_logic_vector(11 downto 0);
251  TTC_lock : OUT std_logic;
252  AMC_TXN : OUT std_logic_vector(12 downto 1);
253  AMC_TXP : OUT std_logic_vector(12 downto 1);
254  AMC_status : OUT std_logic_vector(31 downto 0);
255  evt_data : OUT array3x67;
256  evt_data_we : OUT std_logic_vector(2 downto 0);
257  evt_data_rdy : OUT std_logic_vector(2 downto 0);
258  mon_evt_wc : OUT std_logic_vector(47 downto 0);
259  mon_ctrl : OUT std_logic_vector(31 downto 0);
260  buf_rqst : OUT std_logic_vector(3 downto 0);
261  ipb_rdata : OUT std_logic_vector(31 downto 0);
262  ipb_ack : OUT std_logic;
263  evn_buf_full : OUT std_logic;
264  ovfl_warning : OUT std_logic;
265  TrigData : OUT array12x8;
266  TTS_coded : OUT std_logic_vector(4 downto 0)
267  );
268 END COMPONENT;
269 COMPONENT I2C
270  PORT(
271  clk : IN std_logic;
272  ipb_clk : IN std_logic;
273  reset : IN std_logic;
274  addr : IN std_logic_vector(31 downto 0);
275  SFP_ABS : IN std_logic_vector(3 downto 0);
276  SFP_LOS : IN std_logic_vector(2 downto 0);
277  CLK_SDA : INOUT std_logic;
278  SFP_SDA : INOUT std_logic_vector(3 downto 0);
279  rdata : OUT std_logic_vector(31 downto 0);
280  CLK_rdy : OUT std_logic;
281  CLK_SCL : OUT std_logic;
282  SFP_SCL : OUT std_logic_vector(3 downto 0)
283  );
284 END COMPONENT;
285 COMPONENT SPI_if
286  PORT(
287  SCK : IN std_logic;
288  CSn : IN std_logic;
289  MOSI : IN std_logic;
290  SN : IN std_logic_vector(8 downto 0);
291  OT : IN std_logic;
292  IsT1 : IN std_logic;
293  SPI_rdata : IN std_logic_vector(7 downto 0);
294  MISO : OUT std_logic;
295  SPI_we : OUT std_logic;
296  en_RARP : out STD_LOGIC;
297  newIPADDR : OUT std_logic;
298  IPADDR : OUT std_logic_vector(31 downto 0);
299  SPI_wdata : OUT std_logic_vector(7 downto 0);
300  SPI_addr : OUT std_logic_vector(7 downto 0)
301  );
302 END COMPONENT;
303 COMPONENT ddr_if
304  port(
305  clk_ref : in std_logic;
306  mem_clk_p : in std_logic;
307  mem_clk_n : in std_logic;
308  mem_rst : in std_logic;
309  sysclk : in std_logic;
310  TCPclk : in std_logic;
311  reset : in std_logic;
312  resetsys : in std_logic;
313  run : in std_logic;
314  mem_test : in std_logic_VECTOR(1 downto 0);
315  EventData : in array3X67;
316  EventData_we : in std_logic_VECTOR(2 downto 0);
317  wport_rdy : out std_logic_VECTOR(2 downto 0);
318  WrtMonBlkDone : OUT std_logic_VECTOR(2 downto 0);
319  WrtMonEvtDone : OUT std_logic_VECTOR(2 downto 0);
320  KiloByte_toggle : OUT std_logic_VECTOR(2 downto 0);
321  EoB_toggle : OUT std_logic_VECTOR(2 downto 0);
322  EventBufAddr : in array3x14;
323  EventBufAddr_we : in std_logic_VECTOR(2 downto 0);
324  EventFIFOfull : out std_logic_VECTOR(2 downto 0);
325  TCP_din : in std_logic_vector(31 downto 0);
326  TCP_channel : in STD_LOGIC_VECTOR (1 downto 0);
327  TCP_we : in STD_LOGIC;
328  TCP_wcount : out STD_LOGIC_VECTOR (2 downto 0);
329  TCP_dout : out STD_LOGIC_VECTOR(31 downto 0); -- TCP data are written in unit of 32-bit words
330  TCP_raddr : in std_logic_vector(28 downto 0); -- 28-26 encoded request source 25-0 address in 64 bit word
331  TCP_length : in std_logic_vector(10 downto 0); -- in 64 bit word, actual length - 1
332  TCP_dout_valid : out STD_LOGIC;
333  TCP_rrqst : in STD_LOGIC;
334  TCP_rack : out STD_LOGIC;
335  TCP_lastword : out STD_LOGIC;
336 -- ipbus signals
337  ipb_clk : in STD_LOGIC;
338  ipb_write : in STD_LOGIC;
339  ipb_strobe : in STD_LOGIC;
340  page_addr : in STD_LOGIC_VECTOR(9 downto 0);
341  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
342  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
343  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
344  ipb_ack : out STD_LOGIC;
345  mem_stat : out STD_LOGIC_VECTOR (63 downto 0);
346  device_temp : in STD_LOGIC_VECTOR(11 downto 0);
347 -- ddr3 memory pins
348  ddr3_dq : inout STD_LOGIC_VECTOR (31 downto 0);
349  ddr3_dm : out STD_LOGIC_VECTOR (3 downto 0);
350  ddr3_addr : out STD_LOGIC_VECTOR (13 downto 0);
351  ddr3_ba : out STD_LOGIC_VECTOR (2 downto 0);
352  ddr3_dqs_p : inout STD_LOGIC_VECTOR (3 downto 0);
353  ddr3_dqs_n : inout STD_LOGIC_VECTOR (3 downto 0);
354  ddr3_ras_n : out STD_LOGIC;
355  ddr3_cas_n : out STD_LOGIC;
356  ddr3_we_n : out STD_LOGIC;
357  ddr3_reset_n : out STD_LOGIC;
358  ddr3_cke : out STD_LOGIC_vector(0 to 0);
359  ddr3_odt : out STD_LOGIC_vector(0 to 0);
360  ddr3_ck_p : out STD_LOGIC_vector(0 to 0);
361  ddr3_ck_n : out STD_LOGIC_vector(0 to 0)
362  );
363 END COMPONENT;
364 COMPONENT ipbus_if
365  generic(RXPOLARITY : std_logic := '0'; TXPOLARITY : std_logic := '0');
366  port(
367  ipb_clk : IN std_logic;
368  UsRclk : IN std_logic;
369  DRPclk : IN std_logic;
370  got_SN : out std_logic;
371  reset : IN std_logic;
372  GTX_RESET : IN std_logic;
373  GbE_REFCLK : in std_logic;
374  S6LINK_RXN : in std_logic;
375  S6LINK_RXP : in std_logic;
376  S6LINK_TXN : out std_logic;
377  S6LINK_TXP : out std_logic;
378  wr_amc_en : in std_logic;
379  amc_en : in STD_LOGIC_VECTOR(11 downto 0);
380  en_RARP : in std_logic;
381  IPADDR : in STD_LOGIC_VECTOR(31 downto 0);
382  MACADDR : in STD_LOGIC_VECTOR(47 downto 0);
383  ipb_out : out ipb_wbus;
384  ipb_in : in ipb_rbus;
385  SN : out STD_LOGIC_VECTOR(8 downto 0);
386  debug_in : IN std_logic_vector(31 downto 0);
387  debug_out : OUT std_logic_vector(127 downto 0)
388  );
389 end COMPONENT;
390 COMPONENT sysmon_if
391  PORT(
392  DRPclk : IN std_logic;
393  SN : IN std_logic_vector(8 downto 0);
394  VAUXN_IN : IN std_logic_vector(12 downto 0);
395  VAUXP_IN : IN std_logic_vector(12 downto 0);
396  addr : IN std_logic_vector(15 downto 0);
397  data : OUT std_logic_vector(31 downto 0);
398  device_temp : OUT std_logic_vector(11 downto 0);
399  ALM : OUT std_logic_vector(7 downto 0);
400  OT : OUT std_logic
401  );
402 END COMPONENT;
403 COMPONENT DAQLSCXG_if
404  PORT(
405  sysclk : IN std_logic;
406  clk125 : IN std_logic;
407  DRPclk : IN std_logic;
408  reset : IN std_logic;
409  daq_reset : IN std_logic;
410  gtx_reset : IN std_logic;
411  rstCntr : IN std_logic;
412  Dis_pd : in STD_LOGIC;
413  test : IN std_logic;
414  enSFP : IN std_logic_vector(3 downto 0);
415  SFP_ABS : IN std_logic_vector(2 downto 0);
416  LSC_ID : IN std_logic_vector(15 downto 0);
417  inc_ddr_pa : IN std_logic;
418  evt_data_rdy : IN std_logic_vector(2 downto 0);
419  EventData_in : IN array3x67;
420  EventData_we : IN std_logic_vector(2 downto 0);
421  buf_rqst : IN std_logic_vector(3 downto 0);
422  WaitMonBuf : IN std_logic;
423  WrtMonBlkDone : IN std_logic_vector(2 downto 0);
424  WrtMonEvtDone : IN std_logic_vector(2 downto 0);
425  wport_rdy : IN std_logic_vector(2 downto 0);
426  wport_FIFO_full : IN std_logic_vector(2 downto 0);
427  SFP0_RXN : IN std_logic;
428  SFP0_RXP : IN std_logic;
429  SFP1_RXN : IN std_logic;
430  SFP1_RXP : IN std_logic;
431  SFP2_RXN : IN std_logic;
432  SFP2_RXP : IN std_logic;
433  SFP_REFCLK_P : IN std_logic;
434  SFP_REFCLK_N : IN std_logic;
435  ipb_clk : IN std_logic;
436  ipb_write : IN std_logic;
437  ipb_strobe : IN std_logic;
438  ipb_addr : IN std_logic_vector(31 downto 0);
439  ipb_wdata : IN std_logic_vector(31 downto 0);
440  SFP_down : OUT std_logic_vector(2 downto 0);
441  EventData_re : OUT std_logic_vector(2 downto 0);
442  evt_buf_full : OUT std_logic_vector(2 downto 0);
443  MonBufOverWrite : IN std_logic;
444  MonBuf_avl : OUT std_logic;
445  MonBuf_empty : OUT std_logic;
446  MonBufOvfl : OUT std_logic;
447  mon_evt_cnt : OUT std_logic_vector(31 downto 0);
448  EventBufAddr_we : OUT std_logic_vector(2 downto 0);
449  EventBufAddr : OUT array3x14;
450  SFP0_TXN : OUT std_logic;
451  SFP0_TXP : OUT std_logic;
452  SFP1_TXN : OUT std_logic;
453  SFP1_TXP : OUT std_logic;
454  SFP2_TXN : OUT std_logic;
455  SFP2_TXP : OUT std_logic;
456  ipb_rdata : OUT std_logic_vector(31 downto 0);
457  ipb_ack : OUT std_logic
458  );
459 END COMPONENT;
460 constant ipbus_ver_addr : std_logic_vector(15 downto 0) := x"0000";
461 constant ipbus_sfp_addr: std_logic_vector(15 downto 0) := x"0002";
462 constant CDRclk_pol : std_logic := '0';
463 constant CDRdata_pol : std_logic := '1';
464 constant TTCclk_pol : std_logic := '1';
465 constant TTCdata_pol : std_logic := '1';
466 constant Coarse_Delay: std_logic_vector(3 downto 0) := x"0";
467 signal rst_ipbus : std_logic := '0';
468 signal LDC_UsrClk : std_logic := '0';
469 signal wr_AMC_en : std_logic := '0';
470 signal wr_EnSFP : std_logic := '0';
471 signal fake_length : std_logic_vector(19 downto 0) := x"00400";
472 signal AMC_en : std_logic_vector(11 downto 0) := (others =>'0');
473 signal TTS_disable : std_logic_vector(11 downto 0) := (others =>'0');
474 signal AMC_Ready : std_logic_vector(11 downto 0) := (others =>'0');
475 signal AMC_status : std_logic_vector(31 downto 0) := (others =>'0');
476 signal AMC_DATA : std_logic_vector(31 downto 0) := (others =>'0');
477 signal AMC_ack : std_logic := '0';
478 signal L1Aovfl_warning : std_logic := '0';
479 --signal TRIGDATA : std_logic_vector(7 downto 0) := (others =>'0');
480 signal TTS_coded : std_logic_vector(4 downto 0) := (others =>'0');
481 --signal AMC_trig : std_logic := '0';
482 signal pattern : std_logic_vector(3 downto 0) := (others =>'0');
483 --signal Trig_mask : std_logic_vector(7 downto 0) := (others =>'0');
484 signal SPI_SCK_buf : std_logic := '0';
485 signal CLK_rdy : std_logic := '0';
486 signal I2C_data : std_logic_vector(31 downto 0) := (others =>'0');
487 signal TTCclk_in : std_logic := '0';
488 signal TTC_Clk : std_logic := '0';
489 signal TTC_strobe : std_logic := '0';
490 signal BcntErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
491 signal SinErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
492 signal DbErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
493 signal L1_reg : std_logic_vector(15 downto 0) := (others =>'0');
494 signal Bcnt_reg : std_logic_vector(11 downto 0) := (others =>'0');
495 signal OC_reg : std_logic_vector(31 downto 0) := (others =>'0');
496 signal V2S : std_logic := '0';
497 signal S2V : std_logic := '0';
498 signal S2V_cntr : std_logic_vector(5 downto 0) := (others => '0');
499 signal S2V_sr : std_logic_vector(3 downto 0) := (others => '0');
500 signal ddr_rdata : std_logic_vector(7 downto 0) := (others =>'0');
501 signal ipb_clk_dcm : std_logic := '0';
502 signal ipb_clk : std_logic := '0';
503 signal clk125_dcm : std_logic := '0';
504 signal clk125 : std_logic := '0';
505 signal DRPclk_dcm : std_logic := '0';
506 signal DRPclk : std_logic := '0';
507 signal sysclk_dcm : std_logic := '0';
508 signal sysclk : std_logic := '0';
509 signal clkfb : std_logic := '0';
510 signal refclk_dcm : std_logic := '0';
511 signal refclk : std_logic := '0';
512 signal mem_clk_dcm : std_logic := '0';
513 signal mem_clk : std_logic := '0';
514 signal sysclk_inp : std_logic := '0';
515 signal sysclk_in : std_logic := '0';
516 --signal clk125 : std_logic := '0';
517 signal sys_lock : std_logic := '0';
518 signal sys_lock_n : std_logic := '0';
519 signal ldc_reset : std_logic := '0';
520 signal ldc_GTXreset : std_logic := '0';
521 signal lsc_start : std_logic := '0';
522 signal lsc_reset : std_logic := '0';
523 signal lsc_GTXreset : std_logic := '0';
524 signal amc_reset : std_logic := '0';
525 signal amc_GTXreset : std_logic := '0';
526 signal conf7_q : std_logic := '0';
527 signal conf7_fall : std_logic := '0';
528 signal run : std_logic := '0';
529 signal LSC_LinkDown : std_logic := '0';
530 signal mem_rst : std_logic := '0';
531 signal mem_test : std_logic_vector(1 downto 0) := (others =>'0');
532 signal mem_stat : std_logic_vector(63 downto 0) := (others =>'0');
533 signal mem_ack : std_logic := '0';
534 signal mem_data : std_logic_vector(31 downto 0) := (others =>'0');
535 signal ttc_data : std_logic_vector(31 downto 0) := (others =>'0');
536 signal EventData : array3X67 := (others => (others => '0'));
537 signal wport_rdy : std_logic_vector(2 downto 0) := (others =>'0');
538 signal EventBufAddr : array3x14 := (others => (others => '0'));
539 signal EventBufAddr_we : std_logic_vector(2 downto 0) := (others =>'0');
540 signal evt_buf_full : std_logic_vector(2 downto 0) := (others =>'0');
541 signal wport_FIFO_full : std_logic_vector(2 downto 0) := (others =>'0');
542 --signal TCP_din : std_logic_vector(31 downto 0) := (others =>'0');
543 --signal TCP_channel : std_logic_vector(1 downto 0) := (others =>'0');
544 --signal TCP_wrqst : std_logic := '0';
545 --signal TCP_re : std_logic := '0';
546 --signal TCP_dout : std_logic_vector(31 downto 0) := (others =>'0');
547 --signal TCP_raddr : std_logic_vector(23 downto 0) := (others =>'0');
548 --signal TCP_length : std_logic_vector(11 downto 0) := (others =>'0');
549 --signal TCP_dout_valid : std_logic := '0';
550 --signal TCP_rrqst : std_logic := '0';
551 --signal TCP_rack : std_logic := '0';
552 --signal TCP_lastword : std_logic := '0';
553 signal MonBufOvfl : std_logic := '0';
554 signal MonBuf_empty : std_logic := '0';
555 --signal inc_mon_cntr : std_logic := '0';
556 signal mon_evt_wc : std_logic_vector(47 downto 0) := (others =>'0');
557 signal mon_evt_cnt : std_logic_vector(31 downto 0) := (others =>'0');
558 signal mon_ctrl : std_logic_vector(31 downto 0) := (others =>'0');
559 --signal TCPbuf_avl : std_logic := '0';
560 signal mon_buf_avl : std_logic := '0';
561 signal EventBufAddrAvl : std_logic := '0';
562 signal EventBufAddrRe : std_logic := '0';
563 signal mon_wp : std_logic_vector(31 downto 0) := (others =>'0');
564 --signal TCP_releaseAck : std_logic_vector(2 downto 0) := (others =>'0');
565 --signal TCP_releaseRqst : std_logic_vector(2 downto 0) := (others =>'0');
566 --signal TCP_releaseAddr : array3X13 := (others => (others => '0'));
567 signal EventBuf_rqst : std_logic_vector(3 downto 0) := (others =>'0');
568 signal rst_cntr : std_logic := '0';
569 signal rst_ddr_pa : std_logic := '0';
570 signal inc_ddr_pa : std_logic := '0';
571 signal Source_ID : array3x12 := (others => (others => '0'));
572 signal ddr_pa : std_logic_vector(9 downto 0) := (others =>'0');
573 signal CDRclk : std_logic := '0';
574 signal TTS_clk : std_logic := '0';
575 signal BC0 : std_logic := '0';
576 signal T3_trigger : std_logic := '0';
577 signal BC0_delay : std_logic_vector(4 downto 0) := "11000";
578 signal bcnt : std_logic_vector(3 downto 0) := x"0";
579 signal LocalL1A_cfg : std_logic_vector(31 downto 0) := (others =>'0');
580 signal BCN_off : std_logic_vector(12 downto 0) := (others =>'0');
581 signal OC_off : std_logic_vector(3 downto 0) := (others =>'0');
582 signal en_cal_win : std_logic := '0';
583 signal CalibCtrl : std_logic_vector(31 downto 0) := x"0d800d80";
584 signal cal_win_high : std_logic_vector(11 downto 0) := (others =>'0');
585 signal cal_win_low : std_logic_vector(11 downto 0) := (others =>'0');
586 signal CalType : std_logic_vector(3 downto 0) := (others =>'0');
587 signal TTC_Brcst : std_logic_vector(3 downto 0) := (others =>'0');
588 signal local_TTCcmd : std_logic := '0';
589 signal en_brcst : std_logic := '0';
590 signal ttc_start : std_logic := '0';
591 signal ttc_stop : std_logic := '0';
592 signal ttc_soft_reset : std_logic := '0';
593 signal ttc_soft_resetp : std_logic := '0';
594 signal ttc_ready : std_logic := '0';
595 signal ttc_serr : std_logic := '0';
596 signal ttc_derr : std_logic := '0';
597 signal ttc_bcnt_err : std_logic := '0';
598 signal ttc_evcnt_reset : std_logic := '0';
599 signal inc_rate_ofw : std_logic := '0';
600 signal rate_ofw : std_logic := '0';
601 signal rate_ofwp : std_logic := '0';
602 signal rate_ofw_q : std_logic := '0';
603 signal sync_lost : std_logic := '0';
604 signal oc_cntr : std_logic_vector(3 downto 0) := (others =>'0');
605 signal ttc_resync : std_logic := '0';
606 signal AllEventBuilt : std_logic := '0';
607 signal resync_done : std_logic := '0';
608 signal dcc_quiet : std_logic := '0';
609 signal inc_oc : std_logic := '0';
610 signal inc_L1ac : std_logic := '0';
611 signal inc_bcnterr : std_logic := '0';
612 signal inc_serr : std_logic := '0';
613 signal inc_derr : std_logic := '0';
614 signal evn_fifo_full : std_logic := '0';
615 signal event_number_avl : std_logic := '0';
616 signal state : std_logic_vector(3 downto 0) := (others =>'0');
617 signal TTS_wait : std_logic_vector(20 downto 0) := (others =>'0');
618 signal event_number : std_logic_vector(59 downto 0) := (others =>'0');
619 signal TTC_serr_cntr : std_logic_vector(7 downto 0) := (others =>'0');
620 signal TTC_derr_cntr : std_logic_vector(7 downto 0) := (others =>'0');
621 signal TTC_BcntErr_cntr : std_logic_vector(7 downto 0) := (others =>'0');
622 signal L1A_cntr : std_logic_vector(7 downto 0) := (others =>'0');
623 signal L1A_OFW_cntr : std_logic_vector(7 downto 0) := (others =>'0');
624 signal L1A_BUSY_cntr : std_logic_vector(7 downto 0) := (others =>'0');
625 signal L1A_LOS_cntr : std_logic_vector(7 downto 0) := (others =>'0');
626 signal run_cntr : std_logic_vector(7 downto 0) := (others =>'0');
627 signal ready_cntr : std_logic_vector(7 downto 0) := (others =>'0');
628 signal busy_cntr : std_logic_vector(7 downto 0) := (others =>'0');
629 signal sync_cntr : std_logic_vector(7 downto 0) := (others =>'0');
630 signal ovfl_cntr : std_logic_vector(7 downto 0) := (others =>'0');
631 signal ReSync_cntr : std_logic_vector(15 downto 0) := (others =>'0');
632 signal counter_we : std_logic_vector(3 downto 0) := (others => '0');
633 signal counter_wa : std_logic_vector(9 downto 0) := (others => '0');
634 signal counter_ra_l : std_logic_vector(9 downto 0) := (others => '0');
635 signal counter_ra_h : std_logic_vector(9 downto 0) := (others => '0');
636 signal CounterDi : std_logic_vector(47 downto 0) := (others => '0');
637 signal CounterDoA : std_logic_vector(47 downto 0) := (others => '0');
638 signal CounterDoB : std_logic_vector(63 downto 0) := (others => '0');
639 signal div : std_logic_vector(7 downto 0) := (others =>'0');
640 signal CntrRst : std_logic := '0';
641 signal CntrRstCycle : std_logic := '0';
642 signal CounterDoB_h : std_logic := '0';
643 signal got_SN : std_logic := '0';
644 signal ipb_strobe_q : std_logic := '0';
645 signal SFP_clk : std_logic := '0';
646 signal AMC_clk : std_logic := '0';
647 signal AMC_clk_in : std_logic := '0';
648 signal SV_Cntr : std_logic_vector(7 downto 0) := (others => '0');
649 signal sysclk_div : std_logic_vector(7 downto 0) := (others => '0');
650 signal SFP_UsrClk : std_logic := '0';
651 signal SFP_TxOutClk : std_logic := '0';
652 signal I2C_debug_out : std_logic_vector(15 downto 0) := (others =>'0');
653 signal SFPOSC_rdy : std_logic := '0';
654 signal reset : std_logic := '0';
655 signal DAQ_reset : std_logic := '0';
656 signal AMCOSC_rdy : std_logic := '0';
657 --signal cs_clk_in : std_logic := '0';
658 --signal cs_clk : std_logic := '0';
659 signal TTC_debug : std_logic_vector(63 downto 0) := (others =>'0');
660 signal TxDisable_i : std_logic_vector(3 downto 0) := (others => '0');
661 signal DAQfifo_re : std_logic := '0';
662 signal DAQfifoAlmostEmpty : std_logic := '0';
663 signal DAQfifoEmpty : std_logic := '0';
664 signal DAQfifo_do : std_logic_vector(63 downto 0) := (others =>'0');
665 signal DAQ_debug_in : std_logic_vector(63 downto 0) := (others =>'0');
666 signal LDC_debug_out : std_logic_vector(63 downto 0) := (others =>'0');
667 signal LSC_debug_out : std_logic_vector(63 downto 0) := (others =>'0');
668 signal ddr_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
669 signal ddr_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
670 signal GbE_REFCLK : std_logic := '0';
671 signal S6Link_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
672 signal S6Link_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
673 signal GbE_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
674 signal GbE_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
675 signal AMC_debug_in : std_logic_vector(255 downto 0) := (others =>'0');
676 signal AMC_debug_out : std_logic_vector(255 downto 0) := (others =>'0');
677 signal SFP0_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
678 signal SFP0_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
679 signal SFP1_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
680 signal SFP1_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
681 signal ipb_master_out : ipb_wbus;
682 signal ipb_master_in : ipb_rbus;
683 signal SN : std_logic_vector(8 downto 0) := (others =>'0');
684 signal MACADDR : std_logic_vector(47 downto 0) := (others =>'0');
685 signal ipaddr : std_logic_vector(31 downto 0) := (others =>'0');
686 signal en_RARP : std_logic := '0';
687 --signal SPI_IP : std_logic_vector(31 downto 0) := (others =>'0');
688 signal status : std_logic_vector(31 downto 0) := (others =>'0');
689 signal cmd : std_logic_vector(31 downto 0) := (others =>'0');
690 signal cmd0_dl : std_logic_vector(1 downto 0) := (others =>'0');
691 signal cmd2_dl : std_logic_vector(1 downto 0) := (others =>'0');
692 signal conf : std_logic_vector(15 downto 0) := (others =>'0');
693 signal LSC_ID : std_logic_vector(15 downto 0) := x"1234";
694 signal OT : std_logic := '0';
695 signal inc_HTRCRC_err : std_logic := '0';
696 signal sysmon_data : std_logic_vector(31 downto 0) := (others => '0');
697 signal device_temp : std_logic_vector(11 downto 0) := (others =>'0');
698 signal ALM : std_logic_vector(7 downto 0) := (others =>'0');
699 signal evt_data_rdy : std_logic_vector(2 downto 0) := (others => '0');
700 signal evt_data_re : std_logic_vector(2 downto 0) := (others => '0');
701 signal evt_data_we : std_logic_vector(2 downto 0) := (others => '0');
702 --signal event_size : array3x13;
703 signal SFP_data : std_logic_vector(31 downto 0) := (others =>'0');
704 signal SFP_ack : std_logic := '0';
705 --signal TCP_data : std_logic_vector(31 downto 0) := (others =>'0');
706 --signal TCP_ack : std_logic := '0';
707 signal S2V_SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
708 signal resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
709 signal sysclk_div7SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
710 signal resetCntr_SyncRegs : std_logic_vector(2 downto 0) := (others =>'0');
711 signal newIPADDR : std_logic := '0';
712 signal newIPADDRSyncRegs : std_logic_vector(2 downto 0) := (others =>'0');
713 signal DNA_out : std_logic := '0';
714 signal load_DNA : std_logic := '0';
715 signal shift_DNA : std_logic_vector(2 downto 0) := (others =>'0');
716 signal DNA_cntr : std_logic_vector(5 downto 0) := (others =>'0');
717 signal DNA : std_logic_vector(56 downto 0) := (others =>'0');
718 signal Dis_pd : std_logic := '0';
719 signal enSFP : std_logic_vector(3 downto 0) := (others =>'0');
720 signal SFP_down : std_logic_vector(2 downto 0) := (others =>'0');
721 --signal evt_buf_space : std_logic_vector(2 downto 0) := (others =>'0');
722 signal WrtMonBlkDone : std_logic_vector(2 downto 0) := (others =>'0');
723 signal WrtMonEvtDone : std_logic_vector(2 downto 0) := (others =>'0');
724 component icon2
725  PORT (
726  CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
727  CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
728 
729 end component;
730 component ila16x32k
731  PORT (
732  CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
733  CLK : IN STD_LOGIC;
734  DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
735  TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
736 
737 end component;
738 signal CONTROL0 : std_logic_vector(35 downto 0) := (others => '0');
739 signal CONTROL1 : std_logic_vector(35 downto 0) := (others => '0');
740 signal TRIG0 : std_logic_vector(7 downto 0) := (others => '0');
741 signal TRIG1 : std_logic_vector(7 downto 0) := (others => '0');
742 signal DATA0 : std_logic_vector(15 downto 0) := (others => '0');
743 signal DATA1 : std_logic_vector(15 downto 0) := (others => '0');
744 begin
745 --i_icon : icon2
746 -- port map (
747 -- CONTROL0 => CONTROL0,
748 -- CONTROL1 => CONTROL1);
749 --i_ila : ila16x32k
750 -- port map (
751 -- CONTROL => CONTROL0,
752 -- CLK => sysclk,
753 -- DATA => DATA0,
754 -- TRIG0 => TRIG0);
755 --DATA0(14) <= evt_buf_full(0);
756 --DATA0(13) <= evt_data_re(0);
757 --DATA0(12) <= evt_data_rdy(0);
758 --DATA0(11 downto 10) <= EventBufAddr(0)(5 downto 4);
759 --DATA0(9 downto 8) <= EventData(0)(65 downto 64);
760 --DATA0(7) <= wport_rdy(0);
761 --DATA0(6) <= wport_FIFO_full(0);
762 --DATA0(5) <= evt_data_we(0);
763 --DATA0(4) <= EventBufAddr_we(0);
764 --DATA0(3 downto 0) <= mem_stat(3 downto 0);
765 --TRIG0(7 downto 4) <= (others => '0');
766 --TRIG0(3) <= wport_rdy(0);
767 --TRIG0(2) <= EventBufAddr_we(0);
768 --TRIG0(1) <= evt_data_re(0);
769 --TRIG0(0) <= evt_data_rdy(0);
770 --
771 --i_il2 : ila16x32k
772 -- port map (
773 -- CONTROL => CONTROL1,
774 -- CLK => mem_stat(19),
775 -- DATA => DATA1,
776 -- TRIG0 => TRIG1);
777 --DATA1(14 downto 0) <= mem_stat(18 downto 4);
778 --TRIG1(7 downto 2) <= (others => '0');
779 --TRIG1(1 downto 0) <= mem_stat(18 downto 17);
780 i_TTS_if: TTS_if PORT MAP(
781  sysclk => sysclk,
782  TTS_clk => TTS_clk,
783  reset => sys_lock_n,
784  local_TTC => conf(8),
785  TTS => state,
786  TTS_out_p => TTS_out_p,
787  TTS_out_n => TTS_out_n
788  );
789 TxDisable <= TxDisable_i;
790 i_I2C: I2C PORT MAP(
791  clk => DRPclk ,
792  ipb_clk => clk125,
793  reset => sys_lock_n,
794  addr => ipb_master_out.ipb_addr,
795  rdata => I2C_data,
796  CLK_rdy => CLK_rdy,
797  CLK_SCL => CLK_SCL,
798  CLK_SDA => CLK_SDA,
799  SFP_ABS => SFP_ABS,
800  SFP_LOS => SFP_LOS,
801  SFP_SCL => SFP_SCL,
802  SFP_SDA => SFP_SDA
803  );
804 i_SPI_SCK_buf: bufh port map(i => SPI_SCK, o => SPI_SCK_buf);
805 i_SPI_if: SPI_if PORT MAP(
806  SCK => SPI_SCK ,
807  CSn => SPI_CS_b ,
808  MOSI => SPI_MOSI ,
809  MISO => SPI_MISO ,
810  SN => SN,
811  OT => ALM(0),
812  IsT1 => '1',
813  SPI_we => open,
814  en_RARP => en_RARP,
815  newIPADDR => newIPADDR,
816  IPADDR => IPADDR,
817  SPI_rdata => (others => '0'),
818  SPI_wdata => open,
819  SPI_addr => open
820  );
821 i_ttc_if: ttc_if PORT MAP(
822  clk => sysclk ,
823  refclk => sysclk,
824  reset => reset,
825  run => run,
826  IsG2 => '0',
827  TTC_strobe => TTC_strobe,
828  sys_lock => sys_lock,
829  local_TTC => conf(8),
830  local_TTCcmd => local_TTCcmd ,
831  single_TTCcmd => cmd(8),
832  TTS_clk => TTS_clk,
833  BC0 => BC0,
834  DIV4 => DIV4,
835  DIV_nRST => DIV_nRST,
836  CDRclk_p => CDRclk_p,
837  CDRclk_n => CDRclk_n,
838  CDRclk_out => CDRclk,
839  CDRdata_p => CDRdata_p,
840  CDRdata_n => CDRdata_n,
841  TTCdata_p => TTCdata_p,
842  TTCdata_n => TTCdata_n,
843  TTC_LOS => TTC_LOS,
844  TTC_LOL => TTC_LOL,
845  BCN_off => BCN_off,
846  OC_off => OC_off,
847  en_cal_win => en_cal_win,
848  cal_win_high => cal_win_high ,
849  cal_win_low => cal_win_low ,
850  CalType => CalType,
851  TTC_Brcst => TTC_Brcst,
852  ovfl_warning => L1Aovfl_warning ,
853  ipb_clk => ipb_clk,
854  ipb_write => ipb_master_out.ipb_write ,
855  ipb_strobe => ipb_master_out.ipb_strobe ,
856  ipb_addr => ipb_master_out.ipb_addr ,
857  ipb_wdata => ipb_master_out.ipb_wdata ,
858  ipb_rdata => ttc_data,
859  en_localL1A => conf(2),
860  LocalL1A_cfg => LocalL1A_cfg ,
861  localL1A_s => cmd(26),
862  localL1A_r => cmd(10),
863  localL1A_periodic => status(10),
864  EvnRSt_l => cmd(11),
865  OcnRSt_l => cmd(12),
866  T3_trigger => T3_trigger,
867  en_brcst => en_brcst,
868  ttc_start => ttc_start,
869  ttc_stop => ttc_stop,
870  ttc_soft_reset => ttc_soft_reset ,
871  ttc_ready => ttc_ready,
872  ttc_serr => ttc_serr,
873  ttc_derr => ttc_derr,
874  ttc_bcnt_err => ttc_bcnt_err ,
875  rate_OFW => rate_OFW,
876  sync_lost => sync_lost,
877  inc_oc => inc_oc,
878  inc_l1ac => inc_l1ac,
879  inc_bcnterr => inc_bcnterr ,
880  inc_serr => inc_serr,
881  inc_derr => inc_derr,
882  state => state,
883  evn_fifo_full => evn_fifo_full ,
884  ttc_evcnt_reset => ttc_evcnt_reset ,
885  event_number_avl => event_number_avl ,
886  event_number => event_number
887  );
888 local_TTCcmd <= conf(5) or conf(8);
889 CalibCtrl(31) <= en_cal_win;
890 CalibCtrl(30 downto 28) <= "000";
891 CalibCtrl(27 downto 16) <= cal_win_high;
892 CalibCtrl(15 downto 12) <= CalType;
893 CalibCtrl(11 downto 0) <= cal_win_low;
894 cal_win_high(11 downto 6) <= "110110";
895 cal_win_low(11 downto 6) <= "110110";
896 i_S2V: IBUFDS generic map(DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25") port map(i => S2V_p, ib => S2V_n, o => S2V);
897 process(CDRclk)
898 begin
899  if(CDRclk'event and CDRclk = '1')then
900  if(conf(15) = '0')then
901  T3_trigger <= '0';
902  else
903  T3_trigger <= S2V;
904  end if;
905  end if;
906 end process;
907 i_GbE_REFCLK: IBUFDS_GTE2
908  port map
909  (
910  O => GbE_REFCLK,
911  ODIV2 => open,
912  CEB => '0',
913  I => GbE_REFCLK_P, -- Connect to package pin AB6
914  IB => GbE_REFCLK_N -- Connect to package pin AB5
915  );
916 i_TTCclk_in : IBUFGDS generic map (DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25")
917  port map (
918  O => TTCclk_in, -- Clock buffer output
919  I => TTCclk_p, -- Diff_p clock buffer input
920  IB => TTCclk_n -- Diff_n clock buffer input
921  );
922 i_TTC_CLK_buf: bufg port map(i => TTCclk_in, o => TTC_Clk);
923 i_sysclk_in_buf: bufh port map(i => GbE_REFCLK, o => sysclk_in);
924 i_PLL_sysclk : PLLE2_BASE
925  generic map (
926  BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
927  CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
928  CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
929  CLKIN1_PERIOD => 8.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
930  -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
931  CLKOUT0_DIVIDE => 5,
932  CLKOUT1_DIVIDE => 32,
933  CLKOUT2_DIVIDE => 20,
934  DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
935  REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
936  STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
937  )
938  port map (
939  -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
940  CLKOUT0 => sysclk_dcm,
941  CLKOUT1 => ipb_clk_dcm ,
942  CLKOUT2 => DRPclk_dcm,
943  -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
944  CLKFBOUT => clk125_dcm, -- 1-bit output: Feedback clock
945  -- Status Port: 1-bit (each) output: PLL status ports
946  LOCKED => sys_lock, -- 1-bit output: LOCK
947  -- Clock Input: 1-bit (each) input: Clock input
948  CLKIN1 => sysclk_in, -- 1-bit input: Input clock
949  -- Control Ports: 1-bit (each) input: PLL control ports
950  PWRDWN => '0', -- 1-bit input: Power-down
951  RST => '0', -- 1-bit input: Reset
952  -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
953  CLKFBIN => clk125 -- 1-bit input: Feedback clock
954  );
955 i_clk125_buf: bufg port map(i => clk125_dcm, o => clk125 );
956 i_ipb_clk_buf: bufg port map(i => ipb_clk_dcm, o => ipb_clk);
957 i_DRPclk_buf: bufg port map(i => DRPclk_dcm, o => DRPclk );
958 i_sysclk_buf: bufg port map(i => sysclk_dcm, o => sysclk );
959 --i_refclk_buf: bufg port map(i => refclk_dcm, o => refclk);
960 reset <= not sys_lock or cmd(0);
961 --sysclk <= refclk;
962 process(sysclk,reset)
963 begin
964  if(reset = '1')then
965  resetSyncRegs <= (others => '1');
966  elsif(sysclk'event and sysclk = '1')then
967  resetSyncRegs <= resetSyncRegs(1 downto 0) & '0';
968  end if;
969 end process;
970 i_ddr_if: ddr_if PORT MAP(
971  mem_clk_p => sys_clk_p,
972  mem_clk_n => sys_clk_n,
973  mem_rst => mem_rst,
974  clk_ref => sysclk,
975  sysclk => sysclk,
976  TCPclk => sysclk,
977  reset => reset,
978  resetsys => resetSyncRegs(2),
979  run => run,
980  mem_test => mem_test,
981  EventData => EventData,
982  EventData_we => evt_data_we,
983  wport_rdy => wport_rdy,
984  WrtMonBlkDone => WrtMonBlkDone ,
985  WrtMonEvtDone => WrtMonEvtDone ,
986  KiloByte_toggle => open,
987  EoB_toggle => open,
988  EventBufAddr => EventBufAddr ,
989  EventBufAddr_we => EventBufAddr_we ,
990  EventFIFOfull => wport_FIFO_full ,
991  TCP_din => (others => '0'),
992  TCP_channel => (others => '0'),
993  TCP_we => '0',
994  TCP_wcount => open,
995  TCP_dout => open,
996  TCP_raddr => (others => '0'),
997  TCP_length => (others => '0'),
998  TCP_dout_valid => open,
999  TCP_rrqst => '0',
1000  TCP_rack => open,
1001  TCP_lastword => open,
1002  page_addr => ddr_pa,
1003  ipb_clk => ipb_clk,
1004  ipb_write => ipb_master_out.ipb_write ,
1005  ipb_strobe => ipb_master_out.ipb_strobe ,
1006  ipb_addr => ipb_master_out.ipb_addr ,
1007  ipb_wdata => ipb_master_out.ipb_wdata ,
1008  ipb_rdata => mem_data,
1009  ipb_ack => mem_ack,
1010  mem_stat => mem_stat,
1011  device_temp => device_temp ,
1012  ddr3_dq => ddr3_dq,
1013  ddr3_dm => ddr3_dm,
1014  ddr3_addr => ddr3_addr,
1015  ddr3_ba => ddr3_ba,
1016  ddr3_dqs_p => ddr3_dqs_p,
1017  ddr3_dqs_n => ddr3_dqs_n,
1018  ddr3_ras_n => ddr3_ras_n,
1019  ddr3_cas_n => ddr3_cas_n,
1020  ddr3_we_n => ddr3_we_n,
1021  ddr3_reset_n => ddr3_reset_n ,
1022  ddr3_cke => ddr3_cke,
1023  ddr3_odt => ddr3_odt,
1024  ddr3_ck_p => ddr3_ck_p,
1025  ddr3_ck_n => ddr3_ck_n
1026  );
1027 --mem_rst <= not sys_lock or not CLK_rdy or cmd(5) or cmd(0);
1028 mem_rst <= not sys_lock or not CLK_rdy or cmd(5);
1029 MACADDR <= x"080030f30" & '0' & not SN(8) & '0' & not SN(7 downto 6) & '1' & SN(5 downto 0);
1030 i_ipbus_if: ipbus_if PORT MAP(
1031  ipb_clk => ipb_clk,
1032  UsRclk => clk125,
1033  DRPclk => DRPclk,
1034  reset => rst_ipbus,
1035  GTX_RESET => sys_lock_n,
1036  MACADDR => MACADDR, -- new mac range 08-00-30-F3-00-00 to 08-00-30-F3-00-7F
1037  en_RARP => en_RARP,
1038  IPADDR => IPADDR,
1039  GbE_REFCLK => GbE_REFCLK,
1040  S6LINK_RXN => S6LINK_RXN,
1041  S6LINK_RXP => S6LINK_RXP,
1042  S6LINK_TXN => S6LINK_TXN,
1043  S6LINK_TXP => S6LINK_TXP,
1044  wr_AMC_en => wr_AMC_en,
1045  amc_en => AMC_en,
1046  ipb_out => ipb_master_out,
1047  ipb_in => ipb_master_in,
1048  got_SN => got_SN,
1049  SN => SN,
1050  debug_in => (others => '0'),
1051  debug_out => open
1052  );
1053 --LSC_LinkDown <= '1' when conf(1) = '0' or or_reduce(EnSFP(2 downto 0) and SFP_down) = '1' else '0';
1054 --status(0) <= LSC_LinkDown;
1055 status(0) <= or_reduce(SFP_down);
1056 status(1) <= MonBufOvfl;
1057 status(2) <= mon_evt_cnt(10);
1058 status(3) <= MonBuf_empty;
1059 status(4) <= mem_stat(0); -- monitor input FIFO overflow
1060 status(5) <= not ttc_ready;
1061 status(6) <= ttc_bcnt_err;
1062 status(7) <= ttc_serr;
1063 status(8) <= ttc_derr;
1064 status(9) <= sync_lost;
1065 status(13) <= L1Aovfl_warning;
1066 status(15) <= mem_stat(63);
1067 status(23) <= '0';
1068 run <= conf(0);
1069 EnSFP(3) <= not conf(1);
1070 mem_test <= conf(6) & conf(4);
1071 --en_brcst <= conf(5);
1072 en_brcst <= '0';
1073 i_cmd0_dl0 : SRL16E
1074  port map (
1075  Q => cmd0_dl(0), -- SRL data output
1076  A0 => '1', -- Select[0] input
1077  A1 => '1', -- Select[1] input
1078  A2 => '1', -- Select[2] input
1079  A3 => '0', -- Select[3] input
1080  CE => '1', -- Clock enable input
1081  CLK => ipb_clk, -- Clock input
1082  D => cmd(0) -- SRL data input
1083  );
1084 i_cmd0_dl1 : SRL16E
1085  port map (
1086  Q => cmd0_dl(1), -- SRL data output
1087  A0 => '1', -- Select[0] input
1088  A1 => '1', -- Select[1] input
1089  A2 => '1', -- Select[2] input
1090  A3 => '0', -- Select[3] input
1091  CE => '1', -- Clock enable input
1092  CLK => ipb_clk, -- Clock input
1093  D => cmd0_dl(0) -- SRL data input
1094  );
1095 i_cmd2_dl0 : SRL16E
1096  port map (
1097  Q => cmd2_dl(0), -- SRL data output
1098  A0 => '1', -- Select[0] input
1099  A1 => '1', -- Select[1] input
1100  A2 => '1', -- Select[2] input
1101  A3 => '0', -- Select[3] input
1102  CE => '1', -- Clock enable input
1103  CLK => ipb_clk, -- Clock input
1104  D => cmd(2) -- SRL data input
1105  );
1106 i_cmd2_dl1 : SRL16E
1107  port map (
1108  Q => cmd2_dl(1), -- SRL data output
1109  A0 => '1', -- Select[0] input
1110  A1 => '1', -- Select[1] input
1111  A2 => '1', -- Select[2] input
1112  A3 => '0', -- Select[3] input
1113  CE => '1', -- Clock enable input
1114  CLK => ipb_clk, -- Clock input
1115  D => cmd2_dl(0) -- SRL data input
1116  );
1117 process(ipb_clk)
1118 begin
1119  if(ipb_clk'event and ipb_clk = '1')then
1120  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = CSR_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1121  cmd <= ipb_master_out.ipb_wdata;
1122  else
1123  cmd <= (others => '0');
1124  end if;
1125  conf7_q <= conf(7);
1126  conf7_fall <= conf7_q and not conf(7);
1127  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = CFG_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1128  conf <= ipb_master_out.ipb_wdata(15 downto 0);
1129  end if;
1130  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = HTR_EN_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1131  Dis_pd <= ipb_master_out.ipb_wdata(15);
1132  EnSFP(2 downto 0) <= ipb_master_out.ipb_wdata(14 downto 12);
1133  AMC_en <= ipb_master_out.ipb_wdata(11 downto 0);
1134  if(AMC_en = ipb_master_out.ipb_wdata(11 downto 0))then
1135  wr_AMC_en <= '0';
1136  else
1137  wr_AMC_en <= '1';
1138  end if;
1139  if(EnSFP(2 downto 0) = ipb_master_out.ipb_wdata(14 downto 12))then
1140  wr_EnSFP <= '0';
1141  else
1142  wr_EnSFP <= '1';
1143  end if;
1144  else
1145  wr_AMC_en <= '0';
1146  wr_EnSFP <= '0';
1147  end if;
1148  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"001a" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1149  TTS_disable <= ipb_master_out.ipb_wdata(11 downto 0);
1150  end if;
1151  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = TTC_cal_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1152  en_cal_win <= ipb_master_out.ipb_wdata(31);
1153  cal_win_high(5 downto 0) <= ipb_master_out.ipb_wdata(21 downto 16);
1154  cal_win_low(5 downto 0) <= ipb_master_out.ipb_wdata(5 downto 0);
1155  end if;
1156  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1157  Source_ID(0)(11 downto 0) <= ipb_master_out.ipb_wdata(11 downto 0);
1158  end if;
1159  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id1_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1160  Source_ID(1)(11 downto 0) <= ipb_master_out.ipb_wdata(11 downto 0);
1161  end if;
1162  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id2_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1163  Source_ID(2)(11 downto 0) <= ipb_master_out.ipb_wdata(11 downto 0);
1164  end if;
1165  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"001c" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1166  LocalL1A_cfg <= ipb_master_out.ipb_wdata;
1167  end if;
1168  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SFP_CSR_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1169  LSC_ID(15 downto 2) <= ipb_master_out.ipb_wdata(31 downto 18);
1170  TxDisable_i <= ipb_master_out.ipb_wdata(15 downto 12);
1171  end if;
1172  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = TTC_bcnt_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1173  OC_OFF <= ipb_master_out.ipb_wdata(19 downto 16);
1174  BCN_OFF <= ipb_master_out.ipb_wdata(12 downto 0);
1175  end if;
1176  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = fake_length_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1177  fake_length <= ipb_master_out.ipb_wdata(19 downto 0);
1178  end if;
1179  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"0019" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1180  pattern <= ipb_master_out.ipb_wdata(11 downto 8);
1181 -- Trig_mask <= ipb_master_out.ipb_wdata(7 downto 0);
1182  end if;
1183  if(reset = '1' or (ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = MON_ctrl_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1'))then
1184  ddr_pa <= (others => '0');
1185  elsif(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = PAGE_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1186  if(run = '1')then
1187  if(MonBuf_empty = '0')then
1188  ddr_pa <= ddr_pa + 1;
1189  end if;
1190  else
1191  ddr_pa <= ipb_master_out.ipb_wdata(9 downto 0);
1192  end if;
1193  end if;
1194  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = PAGE_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1' and run = '1' and MonBuf_empty = '0')then
1195  inc_ddr_pa <= '1';
1196  else
1197  inc_ddr_pa <= '0';
1198  end if;
1199  end if;
1200 end process;
1201 ipb_master_in.ipb_ack <= ipb_master_out.ipb_strobe when ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(17) = '0' else mem_ack;
1202 process(ipb_master_out.ipb_addr)
1203 begin
1204  if(ipb_master_out.ipb_addr(27) = '1' or ipb_master_out.ipb_addr(17) = '1')then
1205  ipb_master_in.ipb_rdata <= mem_data;
1206 -- elsif(ipb_master_out.ipb_addr(20 downto 18) /= "000")then
1207 -- if(ipb_master_out.ipb_addr(0) = '0')then
1208 -- ipb_master_in.ipb_rdata <= mem_stat(31 downto 0);
1209 -- else
1210 -- ipb_master_in.ipb_rdata <= mem_stat(63 downto 32);
1211 -- end if;
1212  elsif(ipb_master_out.ipb_addr(15 downto 5) = CSR_addr(15 downto 5))then
1213  case ipb_master_out.ipb_addr(4 downto 0) is
1214  when "00000" => ipb_master_in.ipb_rdata <= not SN(7 downto 0) & not SN(8) & status(22 downto 0);
1215  when "00001" => ipb_master_in.ipb_rdata <= K7version & conf;
1216  when "00010" => ipb_master_in.ipb_rdata <= mon_ctrl;
1217  when "00011" => ipb_master_in.ipb_rdata <= '0' & SFP_down & AMC_Ready & Dis_pd & EnSFP(2 downto 0) & AMC_en;
1218  when "00100" => ipb_master_in.ipb_rdata <= LSC_ID & TxDisable_i & TxFault & (TTC_LOL or TTC_LOL) & SFP_LOS & SFP_ABS;
1219  when "00101" => ipb_master_in.ipb_rdata <= AMC_status;
1220  when "00111" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(0);
1221  when "01000" => ipb_master_in.ipb_rdata <= x"000" & OC_OFF & "000" & BCN_OFF;
1222  when "01001" => ipb_master_in.ipb_rdata <= CalibCtrl;
1223  when "01010" => ipb_master_in.ipb_rdata <= mem_stat(31 downto 0);
1224  when "01011" => ipb_master_in.ipb_rdata <= mem_stat(63 downto 32);
1225  when "01100" => ipb_master_in.ipb_rdata <= x"00000" & "00" & ddr_pa;
1226  when "01101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(15 downto 0) & '0';
1227  when "01110" => ipb_master_in.ipb_rdata <= mon_evt_cnt;
1228  when "01111" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(31 downto 16) & '0';
1229  when "10000" => ipb_master_in.ipb_rdata <= x"000" & "00" & mon_buf_avl & '1' & '0' & wport_FIFO_full & '0' & wport_rdy & x"0" & '0' & evt_data_rdy;
1230  when "10001" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(1);
1231  when "10010" => ipb_master_in.ipb_rdata <= x"000" & Source_ID(2);
1232  when "11000" => ipb_master_in.ipb_rdata <= x"000" & fake_length;
1233  when "11001" => ipb_master_in.ipb_rdata <= x"00" & "000" & TTS_coded & state & pattern & x"00";
1234  when "11010" => ipb_master_in.ipb_rdata <= ReSync_cntr & x"0" & TTS_disable;
1235  when "11100" => ipb_master_in.ipb_rdata <= LocalL1A_cfg;
1236  when "11101" => ipb_master_in.ipb_rdata <= x"0000" & "000" & mon_evt_wc(47 downto 32) & '0';
1237  when "11110" => ipb_master_in.ipb_rdata <= DNA(31 downto 0);
1238  when "11111" => ipb_master_in.ipb_rdata <= "0000000" & DNA(56 downto 32);
1239  when others => ipb_master_in.ipb_rdata <= (others => '0');
1240  end case;
1241  else
1242  ipb_master_in.ipb_rdata <= AMC_data or CounterDoB(63 downto 32) or CounterDoB(31 downto 0) or I2C_data or sysmon_data or SFP_data or ttc_data;
1243  end if;
1244 end process;
1245 rst_cntr <= cmd(1) or cmd(0);
1246 process(sysClk, rst_cntr,reset)
1247 begin
1248  if(reset = '1' or rst_cntr = '1')then
1249  TTC_serr_cntr <= (others =>'0');
1250  TTC_derr_cntr <= (others =>'0');
1251  TTC_BcntErr_cntr <= (others =>'0');
1252  L1A_cntr <= (others =>'0');
1253  L1A_OFW_cntr <= (others =>'0');
1254  L1A_BUSY_cntr <= (others =>'0');
1255  L1A_LOS_cntr <= (others =>'0');
1256  run_cntr <= (others =>'0');
1257  ready_cntr <= (others =>'0');
1258  busy_cntr <= (others =>'0');
1259  sync_cntr <= (others =>'0');
1260  ovfl_cntr <= (others =>'0');
1261  ReSync_cntr <= (others =>'0');
1262  elsif(sysClk'event and sysClk = '1')then
1263  if(inc_serr = '1')then
1264  TTC_serr_cntr <= TTC_serr_cntr + 1;
1265  end if;
1266  if(inc_derr = '1')then
1267  TTC_derr_cntr <= TTC_derr_cntr + 1;
1268  end if;
1269  if(inc_bcnterr = '1')then
1270  TTC_BcntErr_cntr <= TTC_BcntErr_cntr + 1;
1271  end if;
1272  if(inc_l1ac = '1')then
1273  L1A_cntr <= L1A_cntr + 1;
1274  if(state = x"1")then
1275  L1A_OFW_cntr <= L1A_OFW_cntr + 1;
1276  end if;
1277  if(state = x"4")then
1278  L1A_BUSY_cntr <= L1A_BUSY_cntr + 1;
1279  end if;
1280  if(state = x"2")then
1281  L1A_LOS_cntr <= L1A_LOS_cntr + 1;
1282  end if;
1283  end if;
1284  if(run = '1')then
1285  run_cntr <= run_cntr + 1;
1286  if(state(3 downto 2) = "10")then
1287  ready_cntr <= ready_cntr + 1;
1288  end if;
1289  if(state(3 downto 2) = "01")then
1290  busy_cntr <= busy_cntr + 1;
1291  end if;
1292  if(state(3) = '0' and state(1) = '1')then
1293  sync_cntr <= sync_cntr + 1;
1294  end if;
1295  if(state(3) = '0' and state(0) = '1')then
1296  ovfl_cntr <= ovfl_cntr + 1;
1297  end if;
1298  end if;
1299  if(ttc_resync = '1')then
1300  ReSync_cntr <= ReSync_cntr + 1;
1301  end if;
1302  end if;
1303 end process;
1304 ttc_resync <= ttc_soft_reset;
1305 process(sysClk,reset)
1306 begin
1307  if(reset = '1')then
1308  TTS_wait <= (others => '0');
1309  elsif(sysClk'event and sysClk = '1')then
1310  if(ttc_resync = '1')then
1311  TTS_wait <= (others => '0');
1312  elsif(TTS_wait(20) = '0' and sync_lost = '0' and AllEventBuilt = '1')then
1313  TTS_wait <= TTS_wait + 1;
1314  end if;
1315  end if;
1316 end process;
1317 process(sysClk,reset)
1318 begin
1319  if(reset = '1')then
1320  state <= "0100";
1321  elsif(sysClk'event and sysClk = '1')then
1322  if(run = '0' and conf(12) = '1')then
1323  state <= pattern;
1324  elsif(run = '0')then
1325  state <= "0100"; -- changed upon request starting version 0x3023
1326  elsif(ttc_resync = '1')then
1327  state <= "0100";
1328  else
1329  case state is
1330  when "1000" => -- Ready
1331  if(TTS_coded(4) = '1')then
1332  state <= "1111";
1333  elsif(TTS_coded(3) = '1')then
1334  state <= "1100";
1335  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1336  state <= "0010";
1337  elsif(L1Aovfl_warning = '1' or evn_fifo_full = '1' or rate_OFWp = '1' or TTS_coded(1) = '1' or TTS_coded(0) = '1')then
1338  state <= "0001";
1339  end if;
1340  when "0001" => -- OFW
1341  if(TTS_coded(4) = '1')then
1342  state <= "1111";
1343  elsif(TTS_coded(3) = '1')then
1344  state <= "1100";
1345  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1346  state <= "0010";
1347  elsif(evn_fifo_full = '1' or rate_OFWp = '1' or TTS_coded(1) = '1')then
1348  state <= "0100";
1349  elsif(L1Aovfl_warning = '0' and rate_OFWp = '0' and TTS_coded(0) = '0')then
1350  state <= "1000";
1351  end if;
1352  when "0100" => -- Busy
1353  if(TTS_wait(20) = '0')then
1354  elsif(TTS_coded(4) = '1')then
1355  state <= "1111";
1356  elsif(TTS_coded(3) = '1')then
1357  state <= "1100";
1358  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1359  state <= "0010";
1360  elsif(evn_fifo_full = '0' and rate_OFWp = '0' and TTS_coded(1) = '0')then
1361  state <= "0001";
1362  end if;
1363  when others => null; -- x"0" or x"f" disconnected, x"2" OOS, x"c" error
1364  end case;
1365  end if;
1366  end if;
1367 end process;
1368 ipb_master_in.ipb_err <= '0';
1369 i_AMC_if: AMC_if PORT MAP(
1370  sysclk => sysclk,
1371  ipb_clk => ipb_clk,
1372  clk125 => clk125,
1373  DRPclk => DRPclk,
1374  reset => AMC_reset,
1375  GTXreset => amc_GTXreset,
1376  resetCntr => rst_cntr,
1377  ReSync => ttc_resync,
1378  AllEventBuilt => AllEventBuilt ,
1379  run => run,
1380  Dis_pd => Dis_pd,
1381  enSFP => enSFP,
1382  test => conf(7),
1383  NoReSyncFake => conf(11),
1384  WaitMonBuf => conf(14),
1385  fake_length => fake_length ,
1386  en_localL1A => conf(2),
1387  T1_version => K7version(7 downto 0),
1388  Source_ID => Source_ID,
1389  AMC_en => AMC_en,
1390  TTS_disable => TTS_disable ,
1391  AMC_Ready => AMC_Ready,
1392  BC0_lock => open,
1393  TTC_lock => open,
1394  AMC_REFCLK_P => AMC_REFCLK_P ,
1395  AMC_REFCLK_N => AMC_REFCLK_N ,
1396  AMC_RXN => AMC_RXN,
1397  AMC_RXP => AMC_RXP,
1398  AMC_TXN => AMC_TXN,
1399  AMC_TXP => AMC_TXP,
1400  AMC_status => AMC_status,
1401  evt_data => EventData,
1402  evt_data_we => evt_data_we ,
1403  evt_buf_full => evt_buf_full ,
1404  evt_data_re => evt_data_re ,
1405  evt_data_rdy => evt_data_rdy ,
1406  ddr_pa => ddr_pa,
1407  MonBuf_empty => MonBuf_empty ,
1408  mon_evt_wc => mon_evt_wc,
1409  mon_ctrl => mon_ctrl,
1410  mon_buf_avl => mon_buf_avl ,
1411  TCPbuf_avl => '1',
1412  buf_rqst => EventBuf_rqst,
1413  ipb_write => ipb_master_out.ipb_write ,
1414  ipb_strobe => ipb_master_out.ipb_strobe ,
1415  ipb_addr => ipb_master_out.ipb_addr ,
1416  ipb_wdata => ipb_master_out.ipb_wdata ,
1417  ipb_rdata => AMC_data,
1418  ipb_ack => AMC_ack,
1419  TTC_clk => TTC_clk,
1420  TTC_LOS => TTC_LOS,
1421  BC0 => '0',
1422  ttc_evcnt_reset => ttc_evcnt_reset ,
1423  event_number_avl => event_number_avl ,
1424  event_number => event_number ,
1425  evn_buf_full => evn_fifo_full,
1426  ovfl_warning => L1Aovfl_warning ,
1427  TrigData => open,
1428  TTS_coded => TTS_coded
1429  );
1430 AMC_reset <= not sys_lock or cmd(0) or cmd0_dl(1);
1431 amc_GTXreset <= wr_AMC_en or conf7_fall or not sys_lock;
1432 sys_lock_n <= not sys_lock;
1433 i_DAQLSC_if: DAQLSCXG_if PORT MAP(
1434  sysclk => sysclk,
1435  clk125 => clk125,
1436  DRPclk => DRPclk,
1437  reset => AMC_reset,
1438  daq_reset => lsc_reset,
1439  gtx_reset => lsc_GTXreset,
1440  rstCntr => rst_cntr,
1441  test => '0',
1442  Dis_pd => Dis_pd,
1443  enSFP => enSFP,
1444  SFP_ABS => SFP_ABS(2 downto 0),
1445  LSC_ID => LSC_ID,
1446  SFP_down => SFP_down,
1447  inc_ddr_pa => inc_ddr_pa,
1448  evt_data_rdy => evt_data_rdy ,
1449  EventData_in => EventData,
1450  EventData_we => evt_data_we,
1451  EventData_re => evt_data_re,
1452  evt_buf_full => evt_buf_full ,
1453  buf_rqst => EventBuf_rqst,
1454  WaitMonBuf => conf(14),
1455  MonBufOverWrite => conf(13),
1456  MonBuf_avl => mon_buf_avl,
1457  MonBuf_empty => MonBuf_empty ,
1458  MonBufOvfl => MonBufOvfl,
1459  mon_evt_cnt => mon_evt_cnt ,
1460  WrtMonBlkDone => WrtMonBlkDone ,
1461  WrtMonEvtDone => WrtMonEvtDone ,
1462  wport_rdy => wport_rdy,
1463  wport_FIFO_full => wport_FIFO_full ,
1464  EventBufAddr_we => EventBufAddr_we ,
1465  EventBufAddr => EventBufAddr ,
1466  SFP0_RXN => SFP0_RXN,
1467  SFP0_RXP => SFP0_RXP,
1468  SFP1_RXN => SFP1_RXN,
1469  SFP1_RXP => SFP1_RXP,
1470  SFP2_RXN => SFP2_RXN,
1471  SFP2_RXP => SFP2_RXP,
1472  SFP0_TXN => SFP0_TXN,
1473  SFP0_TXP => SFP0_TXP,
1474  SFP1_TXN => SFP1_TXN,
1475  SFP1_TXP => SFP1_TXP,
1476  SFP2_TXN => SFP2_TXN,
1477  SFP2_TXP => SFP2_TXP,
1478  SFP_REFCLK_P => SFP_REFCLK_P ,
1479  SFP_REFCLK_N => SFP_REFCLK_N ,
1480  ipb_clk => ipb_clk,
1481  ipb_write => ipb_master_out.ipb_write ,
1482  ipb_strobe => ipb_master_out.ipb_strobe ,
1483  ipb_addr => ipb_master_out.ipb_addr ,
1484  ipb_wdata => ipb_master_out.ipb_wdata ,
1485  ipb_rdata => SFP_data,
1486  ipb_ack => SFP_ack
1487  );
1488 --lsc_reset <= not sys_lock or cmd(2) or cmd2_dl(1);
1489 --lsc_GTXreset <= wr_enSFP or not sys_lock or cmd2_dl(0);
1490 lsc_reset <= lsc_start or cmd(2) or cmd2_dl(1);
1491 lsc_GTXreset <= lsc_start or cmd2_dl(0);
1492 process(DRPclk, sys_lock)
1493 begin
1494  if(sys_lock = '0')then
1495  lsc_start <= '1';
1496  elsif(DRPclk'event and DRPclk = '1')then
1497  if(CLK_rdy = '1')then
1498  lsc_start <= '0';
1499  end if;
1500  end if;
1501 end process;
1502 i_sysmon_if: sysmon_if PORT MAP(
1503  DRPclk => DRPclk,
1504  SN => SN,
1505  VAUXN_IN => VAUXN,
1506  VAUXP_IN => VAUXP,
1507  addr => ipb_master_out.ipb_addr(15 downto 0),
1508  data => sysmon_data ,
1509  device_temp => device_temp ,
1510  ALM => ALM,
1511  OT => OT
1512  );
1513 i_counter_L : BRAM_TDP_MACRO
1514  generic map (
1515  BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
1516  DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1517  DOA_REG => 0, -- Optional port A output register (0 or 1)
1518  DOB_REG => 0, -- Optional port B output register (0 or 1)
1519  INIT_A => X"000000000", -- Initial values on A output port
1520  INIT_B => X"000000000", -- Initial values on B output port
1521  INIT_FILE => "NONE",
1522  READ_WIDTH_A => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1523  READ_WIDTH_B => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1524  SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY",
1525  -- "GENERATE_X_ONLY" or "NONE"
1526  SRVAL_A => X"000000000", -- Set/Reset value for A port output
1527  SRVAL_B => X"000000000", -- Set/Reset value for B port output
1528  WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
1529  WRITE_MODE_B => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
1530  WRITE_WIDTH_A => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1531  WRITE_WIDTH_B => 32) -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1532  port map (
1533  DOA => CounterDoA(31 downto 0), -- Output port-A data, width defined by READ_WIDTH_A parameter
1534  DOB => CounterDoB(31 downto 0), -- Output port-B data, width defined by READ_WIDTH_B parameter
1535  ADDRA => counter_wa, -- Input port-A address, width defined by Port A depth
1536  ADDRB => counter_ra_l, -- Input port-B address, width defined by Port B depth
1537  CLKA => sysclk, -- 1-bit input port-A clock
1538  CLKB => clk125, -- 1-bit input port-B clock
1539  DIA => CounterDi(31 downto 0), -- Input port-A data, width defined by WRITE_WIDTH_A parameter
1540  DIB => (others => '0'), -- Input port-B data, width defined by WRITE_WIDTH_B parameter
1541  ENA => '1', -- 1-bit input port-A enable
1542  ENB => '1', -- 1-bit input port-B enable
1543  REGCEA => '1', -- 1-bit input port-A output register enable
1544  REGCEB => '1', -- 1-bit input port-B output register enable
1545  RSTA => '0', -- 1-bit input port-A reset
1546  RSTB => '0', -- 1-bit input port-B reset
1547  WEA => counter_we, -- Input port-A write enable, width defined by Port A depth
1548  WEB => x"0" -- Input port-B write enable, width defined by Port B depth
1549  );
1550 i_counter_H : BRAM_TDP_MACRO
1551  generic map (
1552  BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
1553  DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1554  DOA_REG => 0, -- Optional port A output register (0 or 1)
1555  DOB_REG => 0, -- Optional port B output register (0 or 1)
1556  INIT_A => X"000000000", -- Initial values on A output port
1557  INIT_B => X"000000000", -- Initial values on B output port
1558  INIT_FILE => "NONE",
1559  READ_WIDTH_A => 16, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1560  READ_WIDTH_B => 16, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1561  SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY",
1562  -- "GENERATE_X_ONLY" or "NONE"
1563  SRVAL_A => X"000000000", -- Set/Reset value for A port output
1564  SRVAL_B => X"000000000", -- Set/Reset value for B port output
1565  WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
1566  WRITE_MODE_B => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
1567  WRITE_WIDTH_A => 16, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1568  WRITE_WIDTH_B => 16) -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
1569  port map (
1570  DOA => CounterDoA(47 downto 32), -- Output port-A data, width defined by READ_WIDTH_A parameter
1571  DOB => CounterDoB(47 downto 32), -- Output port-B data, width defined by READ_WIDTH_B parameter
1572  ADDRA => counter_wa, -- Input port-A address, width defined by Port A depth
1573  ADDRB => counter_ra_h, -- Input port-B address, width defined by Port B depth
1574  CLKA => sysclk, -- 1-bit input port-A clock
1575  CLKB => clk125, -- 1-bit input port-B clock
1576  DIA => CounterDi(47 downto 32), -- Input port-A data, width defined by WRITE_WIDTH_A parameter
1577  DIB => (others => '0'), -- Input port-B data, width defined by WRITE_WIDTH_B parameter
1578  ENA => '1', -- 1-bit input port-A enable
1579  ENB => '1', -- 1-bit input port-B enable
1580  REGCEA => '1', -- 1-bit input port-A output register enable
1581  REGCEB => '1', -- 1-bit input port-B output register enable
1582  RSTA => '0', -- 1-bit input port-A reset
1583  RSTB => '0', -- 1-bit input port-B reset
1584  WEA => counter_we(1 downto 0), -- Input port-A write enable, width defined by Port A depth
1585  WEB => "00" -- Input port-B write enable, width defined by Port B depth
1586  );
1587 counter_we <= x"f" when div(1 downto 0) = "11" else x"0";
1588 process(ipb_clk)
1589 begin
1590  if(ipb_clk'event and ipb_clk = '1')then
1591  newIPADDRSyncRegs <= newIPADDRSyncRegs(1 downto 0) & newIPADDR;
1592  rst_ipbus <= not newIPADDRSyncRegs(2) and newIPADDR;
1593  end if;
1594 end process;
1595 CounterDi(47 downto 8) <= (others => '0') when CntrRstCycle = '1' else
1596 CounterDoA(47 downto 8) + 1 when CounterDi(7 downto 0) < CounterDoA(7 downto 0) else CounterDoA(47 downto 8);
1597 counter_wa <= "00000" & div(6 downto 2);
1598 counter_ra_l(4 downto 0) <= ipb_master_out.ipb_addr(5 downto 1);
1599 counter_ra_h(4 downto 0) <= ipb_master_out.ipb_addr(5 downto 1);
1600 counter_ra_l(5) <= ipb_master_out.ipb_addr(0);
1601 counter_ra_h(5) <= not ipb_master_out.ipb_addr(0);
1602 counter_ra_l(9 downto 6) <= x"0" when ipb_master_out.ipb_addr(15 downto 6) = misc_cntr_addr(15 downto 6) else x"1";
1603 counter_ra_h(9 downto 6) <= x"0" when ipb_master_out.ipb_addr(15 downto 6) = misc_cntr_addr(15 downto 6) else x"1";
1604 process(sysClk)
1605 begin
1606  if(sysclk'event and sysclk = '1')then
1607  if(CntrRst = '1')then
1608  div <= (others => '0');
1609  else
1610  div <= div + 1;
1611  end if;
1612  resetCntr_SyncRegs <= resetCntr_SyncRegs(1 downto 0) & rst_cntr;
1613  CntrRst <= not resetCntr_SyncRegs(2) and resetCntr_SyncRegs(1);
1614  if(CntrRst = '1')then
1615  CntrRstCycle <= '1';
1616  elsif(and_reduce(div) = '1')then
1617  CntrRstCycle <= '0';
1618  end if;
1619  if(CntrRstCycle = '1')then
1620  CounterDi(7 downto 0) <= (others => '0');
1621  else
1622  case div(6 downto 2) is
1623  when "00000" => CounterDi(7 downto 0) <= TTC_serr_cntr;
1624  when "00001" => CounterDi(7 downto 0) <= TTC_derr_cntr;
1625  when "00010" => CounterDi(7 downto 0) <= TTC_BcntErr_cntr;
1626  when "00011" => CounterDi(7 downto 0) <= L1A_cntr;
1627  when "00100" => CounterDi(7 downto 0) <= run_cntr;
1628  when "00101" => CounterDi(7 downto 0) <= ready_cntr;
1629  when "00110" => CounterDi(7 downto 0) <= busy_cntr;
1630  when "00111" => CounterDi(7 downto 0) <= sync_cntr;
1631  when "01000" => CounterDi(7 downto 0) <= ovfl_cntr;
1632  when "01001" => CounterDi(7 downto 0) <= L1A_OFW_cntr;
1633  when "01010" => CounterDi(7 downto 0) <= L1A_BUSY_cntr;
1634  when "01011" => CounterDi(7 downto 0) <= L1A_LOS_cntr;
1635  when others => CounterDi(7 downto 0) <= (others => '0');
1636  end case;
1637  end if;
1638  end if;
1639 end process;
1640 i_DNA_PORT : DNA_PORT
1641  generic map (
1642  SIM_DNA_VALUE => X"00123456789abcd" -- Specifies a sample 57-bit DNA value for simulation
1643  )
1644  port map (
1645  DOUT => DNA_out, -- 1-bit output: DNA output data.
1646  CLK => ipb_clk, -- 1-bit input: Clock input.
1647  DIN => '0', -- 1-bit input: User data input pin.
1648  READ => load_DNA, -- 1-bit input: Active high load DNA, active low read input.
1649  SHIFT => shift_DNA(1) -- 1-bit input: Active high shift enable input.
1650  );
1651 process(ipb_clk)
1652 begin
1653  if(ipb_clk'event and ipb_clk = '1')then
1654  load_DNA <= not sys_lock;
1655  if(sys_lock = '0')then
1656  shift_DNA(0) <= '0';
1657  elsif(load_DNA = '1')then
1658  shift_DNA(0) <= '1';
1659  elsif(shift_DNA(2) = '1' and or_reduce(DNA_cntr(5 downto 1)) = '0')then
1660  shift_DNA(0) <= '0';
1661  end if;
1662  shift_DNA(2) <= shift_DNA(0);
1663  if(shift_DNA(2) = '1')then
1664  DNA_cntr <= DNA_cntr - 1;
1665  elsif(shift_DNA(0) = '1')then
1666  DNA_cntr <= "110111";
1667  end if;
1668  if(shift_DNA(2) = '1')then
1669  DNA <= DNA(55 downto 0) & DNA_OUT;
1670  end if;
1671  end if;
1672 end process;
1673 process(ipb_clk)
1674 begin
1675  if(ipb_clk'event and ipb_clk = '0')then
1676  shift_DNA(1) <= shift_DNA(0);
1677  end if;
1678 end process;
1679 end Behavioral;
1680 
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