AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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sfp2_v2_7_init.vhd
1 ------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : sfp2_v2_7_init.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 -- Description : This module instantiates the modules required for
13 -- reset and initialisation of the Transceiver
14 --
15 -- Module SFP2_v2_7_init
16 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
17 --
18 --
19 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
20 --
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64 
65 
66 library ieee;
67 use ieee.std_logic_1164.all;
68 use ieee.numeric_std.all;
69 use ieee.std_logic_unsigned.all;
70 library UNISIM;
71 use UNISIM.VCOMPONENTS.ALL;
72 
73 --***********************************Entity Declaration************************
74 
75 entity SFP2_v2_7_init is
76 generic
77 (
78  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
79  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
80  STABLE_CLOCK_PERIOD : integer := 20; --Period of the stable clock driving this state-machine, unit is [ns]
81  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
82 
83 );
84 port
85 (
86  SYSCLK_IN : in std_logic;
87  SOFT_RESET_IN : in std_logic;
88  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
89  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
90  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
91  GT0_DATA_VALID_IN : in std_logic;
92  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
93  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
94  GT1_DATA_VALID_IN : in std_logic;
95 
96  --_________________________________________________________________________
97  --GT0 (X1Y12)
98  --____________________________CHANNEL PORTS________________________________
99  ---------------------------- Channel - DRP Ports --------------------------
100  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
101  GT0_DRPCLK_IN : in std_logic;
102  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
103  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
104  GT0_DRPEN_IN : in std_logic;
105  GT0_DRPRDY_OUT : out std_logic;
106  GT0_DRPWE_IN : in std_logic;
107  ------------------------------- Loopback Ports -----------------------------
108  GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
109  ------------------------------ Power-Down Ports ----------------------------
110  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
111  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
112  --------------------- RX Initialization and Reset Ports --------------------
113  GT0_RXUSERRDY_IN : in std_logic;
114  -------------------------- RX Margin Analysis Ports ------------------------
115  GT0_EYESCANDATAERROR_OUT : out std_logic;
116  ------------------------- Receive Ports - CDR Ports ------------------------
117  GT0_RXCDRLOCK_OUT : out std_logic;
118  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
119  GT0_RXUSRCLK_IN : in std_logic;
120  GT0_RXUSRCLK2_IN : in std_logic;
121  ------------------ Receive Ports - FPGA RX interface Ports -----------------
122  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
123  ------------------- Receive Ports - Pattern Checker Ports ------------------
124  GT0_RXPRBSERR_OUT : out std_logic;
125  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
126  ------------------- Receive Ports - Pattern Checker ports ------------------
127  GT0_RXPRBSCNTRESET_IN : in std_logic;
128  --------------------------- Receive Ports - RX AFE -------------------------
129  GT0_GTXRXP_IN : in std_logic;
130  ------------------------ Receive Ports - RX AFE Ports ----------------------
131  GT0_GTXRXN_IN : in std_logic;
132  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
133  GT0_RXBUFRESET_IN : in std_logic;
134  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
135  --------------- Receive Ports - RX Fabric Output Control Ports -------------
136  GT0_RXOUTCLK_OUT : out std_logic;
137  ---------------------- Receive Ports - RX Gearbox Ports --------------------
138  GT0_RXDATAVALID_OUT : out std_logic;
139  GT0_RXHEADER_OUT : out std_logic_vector(1 downto 0);
140  GT0_RXHEADERVALID_OUT : out std_logic;
141  --------------------- Receive Ports - RX Gearbox Ports --------------------
142  GT0_RXGEARBOXSLIP_IN : in std_logic;
143  ------------- Receive Ports - RX Initialization and Reset Ports ------------
144  GT0_GTRXRESET_IN : in std_logic;
145  GT0_RXPMARESET_IN : in std_logic;
146  ------------------ Receive Ports - RX Margin Analysis ports ----------------
147  GT0_RXLPMEN_IN : in std_logic;
148  -------------- Receive Ports -RX Initialization and Reset Ports ------------
149  GT0_RXRESETDONE_OUT : out std_logic;
150  --------------------- TX Initialization and Reset Ports --------------------
151  GT0_GTTXRESET_IN : in std_logic;
152  GT0_TXUSERRDY_IN : in std_logic;
153  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
154  GT0_TXUSRCLK_IN : in std_logic;
155  GT0_TXUSRCLK2_IN : in std_logic;
156  --------------- Transmit Ports - TX Configurable Driver Ports --------------
157  GT0_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
158  GT0_TXINHIBIT_IN : in std_logic;
159  GT0_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
160  ------------------ Transmit Ports - TX Data Path interface -----------------
161  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
162  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
163  GT0_GTXTXN_OUT : out std_logic;
164  GT0_GTXTXP_OUT : out std_logic;
165  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
166  GT0_TXOUTCLK_OUT : out std_logic;
167  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
168  GT0_TXOUTCLKPCS_OUT : out std_logic;
169  --------------------- Transmit Ports - TX Gearbox Ports --------------------
170  GT0_TXHEADER_IN : in std_logic_vector(1 downto 0);
171  GT0_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
172  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
173  GT0_TXRESETDONE_OUT : out std_logic;
174  ------------------ Transmit Ports - pattern Generator Ports ----------------
175  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
176 
177  --GT1 (X1Y14)
178  --____________________________CHANNEL PORTS________________________________
179  ---------------------------- Channel - DRP Ports --------------------------
180  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
181  GT1_DRPCLK_IN : in std_logic;
182  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
183  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
184  GT1_DRPEN_IN : in std_logic;
185  GT1_DRPRDY_OUT : out std_logic;
186  GT1_DRPWE_IN : in std_logic;
187  ------------------------------- Loopback Ports -----------------------------
188  GT1_LOOPBACK_IN : in std_logic_vector(2 downto 0);
189  ------------------------------ Power-Down Ports ----------------------------
190  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
191  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
192  --------------------- RX Initialization and Reset Ports --------------------
193  GT1_RXUSERRDY_IN : in std_logic;
194  -------------------------- RX Margin Analysis Ports ------------------------
195  GT1_EYESCANDATAERROR_OUT : out std_logic;
196  ------------------------- Receive Ports - CDR Ports ------------------------
197  GT1_RXCDRLOCK_OUT : out std_logic;
198  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
199  GT1_RXUSRCLK_IN : in std_logic;
200  GT1_RXUSRCLK2_IN : in std_logic;
201  ------------------ Receive Ports - FPGA RX interface Ports -----------------
202  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
203  ------------------- Receive Ports - Pattern Checker Ports ------------------
204  GT1_RXPRBSERR_OUT : out std_logic;
205  GT1_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
206  ------------------- Receive Ports - Pattern Checker ports ------------------
207  GT1_RXPRBSCNTRESET_IN : in std_logic;
208  --------------------------- Receive Ports - RX AFE -------------------------
209  GT1_GTXRXP_IN : in std_logic;
210  ------------------------ Receive Ports - RX AFE Ports ----------------------
211  GT1_GTXRXN_IN : in std_logic;
212  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
213  GT1_RXBUFRESET_IN : in std_logic;
214  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
215  --------------- Receive Ports - RX Fabric Output Control Ports -------------
216  GT1_RXOUTCLK_OUT : out std_logic;
217  ---------------------- Receive Ports - RX Gearbox Ports --------------------
218  GT1_RXDATAVALID_OUT : out std_logic;
219  GT1_RXHEADER_OUT : out std_logic_vector(1 downto 0);
220  GT1_RXHEADERVALID_OUT : out std_logic;
221  --------------------- Receive Ports - RX Gearbox Ports --------------------
222  GT1_RXGEARBOXSLIP_IN : in std_logic;
223  ------------- Receive Ports - RX Initialization and Reset Ports ------------
224  GT1_GTRXRESET_IN : in std_logic;
225  GT1_RXPMARESET_IN : in std_logic;
226  ------------------ Receive Ports - RX Margin Analysis ports ----------------
227  GT1_RXLPMEN_IN : in std_logic;
228  -------------- Receive Ports -RX Initialization and Reset Ports ------------
229  GT1_RXRESETDONE_OUT : out std_logic;
230  --------------------- TX Initialization and Reset Ports --------------------
231  GT1_GTTXRESET_IN : in std_logic;
232  GT1_TXUSERRDY_IN : in std_logic;
233  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
234  GT1_TXUSRCLK_IN : in std_logic;
235  GT1_TXUSRCLK2_IN : in std_logic;
236  --------------- Transmit Ports - TX Configurable Driver Ports --------------
237  GT1_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
238  GT1_TXINHIBIT_IN : in std_logic;
239  GT1_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
240  ------------------ Transmit Ports - TX Data Path interface -----------------
241  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
242  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
243  GT1_GTXTXN_OUT : out std_logic;
244  GT1_GTXTXP_OUT : out std_logic;
245  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
246  GT1_TXOUTCLK_OUT : out std_logic;
247  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
248  GT1_TXOUTCLKPCS_OUT : out std_logic;
249  --------------------- Transmit Ports - TX Gearbox Ports --------------------
250  GT1_TXHEADER_IN : in std_logic_vector(1 downto 0);
251  GT1_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
252  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
253  GT1_TXRESETDONE_OUT : out std_logic;
254  ------------------ Transmit Ports - pattern Generator Ports ----------------
255  GT1_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
256 
257 
258  --____________________________COMMON PORTS________________________________
259  ---------------------- Common Block - Ref Clock Ports ---------------------
260  GT0_GTREFCLK0_COMMON_IN : in std_logic;
261  ------------------------- Common Block - QPLL Ports ------------------------
262  GT0_QPLLLOCK_OUT : out std_logic;
263  GT0_QPLLLOCKDETCLK_IN : in std_logic;
264  GT0_QPLLRESET_IN : in std_logic
265 
266 
267 );
268 
269 end SFP2_v2_7_init;
270 
271 architecture RTL of SFP2_v2_7_init is
272 
273 --**************************Component Declarations*****************************
274 
275 
276 component SFP2_v2_7
277 generic
278 (
279  -- Simulation attributes
280  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to 1 to speed up sim reset
281 
282 );
283 port
284 (
285 
286  --_________________________________________________________________________
287  --_________________________________________________________________________
288  --GT0 (X1Y12)
289  --____________________________CHANNEL PORTS________________________________
290  ---------------------------- Channel - DRP Ports --------------------------
291  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
292  GT0_DRPCLK_IN : in std_logic;
293  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
294  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
295  GT0_DRPEN_IN : in std_logic;
296  GT0_DRPRDY_OUT : out std_logic;
297  GT0_DRPWE_IN : in std_logic;
298  ------------------------------- Loopback Ports -----------------------------
299  GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
300  ------------------------------ Power-Down Ports ----------------------------
301  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
302  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
303  --------------------- RX Initialization and Reset Ports --------------------
304  GT0_RXUSERRDY_IN : in std_logic;
305  -------------------------- RX Margin Analysis Ports ------------------------
306  GT0_EYESCANDATAERROR_OUT : out std_logic;
307  ------------------------- Receive Ports - CDR Ports ------------------------
308  GT0_RXCDRLOCK_OUT : out std_logic;
309  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
310  GT0_RXUSRCLK_IN : in std_logic;
311  GT0_RXUSRCLK2_IN : in std_logic;
312  ------------------ Receive Ports - FPGA RX interface Ports -----------------
313  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
314  ------------------- Receive Ports - Pattern Checker Ports ------------------
315  GT0_RXPRBSERR_OUT : out std_logic;
316  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
317  ------------------- Receive Ports - Pattern Checker ports ------------------
318  GT0_RXPRBSCNTRESET_IN : in std_logic;
319  --------------------------- Receive Ports - RX AFE -------------------------
320  GT0_GTXRXP_IN : in std_logic;
321  ------------------------ Receive Ports - RX AFE Ports ----------------------
322  GT0_GTXRXN_IN : in std_logic;
323  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
324  GT0_RXBUFRESET_IN : in std_logic;
325  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
326  --------------------- Receive Ports - RX Equalizer Ports -------------------
327  GT0_RXDFEAGCHOLD_IN : in std_logic;
328  GT0_RXDFELFHOLD_IN : in std_logic;
329  --------------- Receive Ports - RX Fabric Output Control Ports -------------
330  GT0_RXOUTCLK_OUT : out std_logic;
331  ---------------------- Receive Ports - RX Gearbox Ports --------------------
332  GT0_RXDATAVALID_OUT : out std_logic;
333  GT0_RXHEADER_OUT : out std_logic_vector(1 downto 0);
334  GT0_RXHEADERVALID_OUT : out std_logic;
335  --------------------- Receive Ports - RX Gearbox Ports --------------------
336  GT0_RXGEARBOXSLIP_IN : in std_logic;
337  ------------- Receive Ports - RX Initialization and Reset Ports ------------
338  GT0_GTRXRESET_IN : in std_logic;
339  GT0_RXPCSRESET_IN : in std_logic;
340  GT0_RXPMARESET_IN : in std_logic;
341  ------------------ Receive Ports - RX Margin Analysis ports ----------------
342  GT0_RXLPMEN_IN : in std_logic;
343  -------------- Receive Ports -RX Initialization and Reset Ports ------------
344  GT0_RXRESETDONE_OUT : out std_logic;
345  --------------------- TX Initialization and Reset Ports --------------------
346  GT0_GTTXRESET_IN : in std_logic;
347  GT0_TXUSERRDY_IN : in std_logic;
348  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
349  GT0_TXUSRCLK_IN : in std_logic;
350  GT0_TXUSRCLK2_IN : in std_logic;
351  --------------- Transmit Ports - TX Configurable Driver Ports --------------
352  GT0_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
353  GT0_TXINHIBIT_IN : in std_logic;
354  GT0_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
355  ------------------ Transmit Ports - TX Data Path interface -----------------
356  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
357  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
358  GT0_GTXTXN_OUT : out std_logic;
359  GT0_GTXTXP_OUT : out std_logic;
360  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
361  GT0_TXOUTCLK_OUT : out std_logic;
362  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
363  GT0_TXOUTCLKPCS_OUT : out std_logic;
364  --------------------- Transmit Ports - TX Gearbox Ports --------------------
365  GT0_TXHEADER_IN : in std_logic_vector(1 downto 0);
366  GT0_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
367  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
368  GT0_TXPCSRESET_IN : in std_logic;
369  GT0_TXRESETDONE_OUT : out std_logic;
370  ------------------ Transmit Ports - pattern Generator Ports ----------------
371  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
372 
373  --_________________________________________________________________________
374  --_________________________________________________________________________
375  --GT1 (X1Y14)
376  --____________________________CHANNEL PORTS________________________________
377  ---------------------------- Channel - DRP Ports --------------------------
378  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
379  GT1_DRPCLK_IN : in std_logic;
380  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
381  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
382  GT1_DRPEN_IN : in std_logic;
383  GT1_DRPRDY_OUT : out std_logic;
384  GT1_DRPWE_IN : in std_logic;
385  ------------------------------- Loopback Ports -----------------------------
386  GT1_LOOPBACK_IN : in std_logic_vector(2 downto 0);
387  ------------------------------ Power-Down Ports ----------------------------
388  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
389  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
390  --------------------- RX Initialization and Reset Ports --------------------
391  GT1_RXUSERRDY_IN : in std_logic;
392  -------------------------- RX Margin Analysis Ports ------------------------
393  GT1_EYESCANDATAERROR_OUT : out std_logic;
394  ------------------------- Receive Ports - CDR Ports ------------------------
395  GT1_RXCDRLOCK_OUT : out std_logic;
396  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
397  GT1_RXUSRCLK_IN : in std_logic;
398  GT1_RXUSRCLK2_IN : in std_logic;
399  ------------------ Receive Ports - FPGA RX interface Ports -----------------
400  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
401  ------------------- Receive Ports - Pattern Checker Ports ------------------
402  GT1_RXPRBSERR_OUT : out std_logic;
403  GT1_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
404  ------------------- Receive Ports - Pattern Checker ports ------------------
405  GT1_RXPRBSCNTRESET_IN : in std_logic;
406  --------------------------- Receive Ports - RX AFE -------------------------
407  GT1_GTXRXP_IN : in std_logic;
408  ------------------------ Receive Ports - RX AFE Ports ----------------------
409  GT1_GTXRXN_IN : in std_logic;
410  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
411  GT1_RXBUFRESET_IN : in std_logic;
412  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
413  --------------------- Receive Ports - RX Equalizer Ports -------------------
414  GT1_RXDFEAGCHOLD_IN : in std_logic;
415  GT1_RXDFELFHOLD_IN : in std_logic;
416  --------------- Receive Ports - RX Fabric Output Control Ports -------------
417  GT1_RXOUTCLK_OUT : out std_logic;
418  ---------------------- Receive Ports - RX Gearbox Ports --------------------
419  GT1_RXDATAVALID_OUT : out std_logic;
420  GT1_RXHEADER_OUT : out std_logic_vector(1 downto 0);
421  GT1_RXHEADERVALID_OUT : out std_logic;
422  --------------------- Receive Ports - RX Gearbox Ports --------------------
423  GT1_RXGEARBOXSLIP_IN : in std_logic;
424  ------------- Receive Ports - RX Initialization and Reset Ports ------------
425  GT1_GTRXRESET_IN : in std_logic;
426  GT1_RXPCSRESET_IN : in std_logic;
427  GT1_RXPMARESET_IN : in std_logic;
428  ------------------ Receive Ports - RX Margin Analysis ports ----------------
429  GT1_RXLPMEN_IN : in std_logic;
430  -------------- Receive Ports -RX Initialization and Reset Ports ------------
431  GT1_RXRESETDONE_OUT : out std_logic;
432  --------------------- TX Initialization and Reset Ports --------------------
433  GT1_GTTXRESET_IN : in std_logic;
434  GT1_TXUSERRDY_IN : in std_logic;
435  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
436  GT1_TXUSRCLK_IN : in std_logic;
437  GT1_TXUSRCLK2_IN : in std_logic;
438  --------------- Transmit Ports - TX Configurable Driver Ports --------------
439  GT1_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
440  GT1_TXINHIBIT_IN : in std_logic;
441  GT1_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
442  ------------------ Transmit Ports - TX Data Path interface -----------------
443  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
444  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
445  GT1_GTXTXN_OUT : out std_logic;
446  GT1_GTXTXP_OUT : out std_logic;
447  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
448  GT1_TXOUTCLK_OUT : out std_logic;
449  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
450  GT1_TXOUTCLKPCS_OUT : out std_logic;
451  --------------------- Transmit Ports - TX Gearbox Ports --------------------
452  GT1_TXHEADER_IN : in std_logic_vector(1 downto 0);
453  GT1_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
454  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
455  GT1_TXPCSRESET_IN : in std_logic;
456  GT1_TXRESETDONE_OUT : out std_logic;
457  ------------------ Transmit Ports - pattern Generator Ports ----------------
458  GT1_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
459 
460 
461  --____________________________COMMON PORTS________________________________
462  ---------------------- Common Block - Ref Clock Ports ---------------------
463  GT0_GTREFCLK0_COMMON_IN : in std_logic;
464  ------------------------- Common Block - QPLL Ports ------------------------
465  GT0_QPLLLOCK_OUT : out std_logic;
466  GT0_QPLLLOCKDETCLK_IN : in std_logic;
467  GT0_QPLLREFCLKLOST_OUT : out std_logic;
468  GT0_QPLLRESET_IN : in std_logic
469 
470 
471 );
472 end component;
473 
474 component SFP2_v2_7_TX_STARTUP_FSM
475  Generic(
476  GT_TYPE : string := "GTX";
477  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
478  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
479  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
480  RX_QPLL_USED : boolean := False; -- share these two generic values
481  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
482  -- is enough. For single-lane applications the automatic alignment is
483  -- sufficient
484  );
485  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
486  --or reference-clock present at startup.
487  TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
488  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
489  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
490  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
491  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
492  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
493  TXRESETDONE : in STD_LOGIC;
494  MMCM_LOCK : in STD_LOGIC;
495  GTTXRESET : out STD_LOGIC:='0';
496  MMCM_RESET : out STD_LOGIC:='0';
497  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
498  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
499  TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
500  TXUSERRDY : out STD_LOGIC:='0';
501  RUN_PHALIGNMENT : out STD_LOGIC:='0';
502  RESET_PHALIGNMENT : out STD_LOGIC:='0';
503  PHALIGNMENT_DONE : in STD_LOGIC;
504 
505  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
506  -- Retries it took to get the transceiver up and running
507  );
508 end component;
509 
510 component SFP2_v2_7_RX_STARTUP_FSM
511  Generic(
512  EXAMPLE_SIMULATION : integer := 0;
513  EQ_MODE : string := "DFE";
514  GT_TYPE : string := "GTX";
515  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
516  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
517  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
518  RX_QPLL_USED : boolean := False; -- share these two generic values
519  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
520  -- is enough. For single-lane applications the automatic alignment is
521  -- sufficient
522  );
523  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
524  --or reference-clock present at startup.
525  RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
526  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
527  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
528  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
529  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
530  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
531  RXRESETDONE : in STD_LOGIC;
532  MMCM_LOCK : in STD_LOGIC;
533  RECCLK_STABLE : in STD_LOGIC;
534  RECCLK_MONITOR_RESTART : in STD_LOGIC;
535  DATA_VALID : in STD_LOGIC;
536  TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
537  DONT_RESET_ON_DATA_ERROR : in STD_LOGIC;
538  GTRXRESET : out STD_LOGIC:='0';
539  MMCM_RESET : out STD_LOGIC:='0';
540  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
541  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
542  RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
543  RXUSERRDY : out STD_LOGIC:='0';
544  RUN_PHALIGNMENT : out STD_LOGIC;
545  PHALIGNMENT_DONE : in STD_LOGIC;
546  RESET_PHALIGNMENT : out STD_LOGIC:='0';
547  RXDFEAGCHOLD : out STD_LOGIC;
548  RXDFELFHOLD : out STD_LOGIC;
549  RXLPMLFHOLD : out STD_LOGIC;
550  RXLPMHFHOLD : out STD_LOGIC;
551  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
552  -- Retries it took to get the transceiver up and running
553  );
554 end component;
555 
556 
557 
558 
559 
560 
561  function get_cdrlock_time(is_sim : in integer) return integer is
562  variable lock_time: integer;
563  begin
564  if (is_sim = 1) then
565  lock_time := 1000;
566  else
567  lock_time := 50000 / integer(10.3125); --Typical CDR lock time is 50,000UI as per DS183
568  end if;
569  return lock_time;
570  end function;
571 
572 
573 --***********************************Parameter Declarations********************
574 
575  constant DLY : time := 1 ns;
576  constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us
577  constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out
578 
579  -------------------------- GT Wrapper Wires ------------------------------
580  signal gt0_txresetdone_i : std_logic;
581  signal gt0_rxresetdone_i : std_logic;
582  signal gt0_gttxreset_i : std_logic;
583  signal gt0_gttxreset_t : std_logic;
584  signal gt0_gtrxreset_i : std_logic;
585  signal gt0_gtrxreset_t : std_logic;
586  signal gt0_txpcsreset_i : std_logic;
587  signal gt0_rxpcsreset_i : std_logic;
588  signal gt0_rxdfelpmreset_i : std_logic;
589  signal gt0_txuserrdy_i : std_logic;
590  signal gt0_txuserrdy_t : std_logic;
591  signal gt0_rxuserrdy_i : std_logic;
592  signal gt0_rxuserrdy_t : std_logic;
593 
594  signal gt0_rxdfeagchold_i : std_logic;
595  signal gt0_rxdfelfhold_i : std_logic;
596  signal gt0_rxlpmlfhold_i : std_logic;
597  signal gt0_rxlpmhfhold_i : std_logic;
598 
599 
600  signal gt1_txresetdone_i : std_logic;
601  signal gt1_rxresetdone_i : std_logic;
602  signal gt1_gttxreset_i : std_logic;
603  signal gt1_gttxreset_t : std_logic;
604  signal gt1_gtrxreset_i : std_logic;
605  signal gt1_gtrxreset_t : std_logic;
606  signal gt1_txpcsreset_i : std_logic;
607  signal gt1_rxpcsreset_i : std_logic;
608  signal gt1_rxdfelpmreset_i : std_logic;
609  signal gt1_txuserrdy_i : std_logic;
610  signal gt1_txuserrdy_t : std_logic;
611  signal gt1_rxuserrdy_i : std_logic;
612  signal gt1_rxuserrdy_t : std_logic;
613 
614  signal gt1_rxdfeagchold_i : std_logic;
615  signal gt1_rxdfelfhold_i : std_logic;
616  signal gt1_rxlpmlfhold_i : std_logic;
617  signal gt1_rxlpmhfhold_i : std_logic;
618 
619 
620 
621  signal gt0_qpllreset_i : std_logic;
622  signal gt0_qpllreset_t : std_logic;
623  signal gt0_qpllrefclklost_i : std_logic;
624  signal gt0_qplllock_i : std_logic;
625 
626 
627  ------------------------------- Global Signals -----------------------------
628  signal tied_to_ground_i : std_logic;
629  signal tied_to_vcc_i : std_logic;
630 
631  signal gt0_rxoutclk_i : std_logic;
632  signal gt0_recclk_stable_i : std_logic;
633 
634  signal gt1_rxoutclk_i : std_logic;
635  signal gt1_recclk_stable_i : std_logic;
636 
637 
638 
639 
640 
641 
642  signal rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
643  signal rx_cdrlocked : std_logic;
644 
645 
646 
647 
648 
649 --**************************** Main Body of Code *******************************
650 begin
651  -- Static signal Assigments
652  tied_to_ground_i <= '0';
653  tied_to_vcc_i <= '1';
654 
655  ----------------------------- The GT Wrapper -----------------------------
656 
657  -- Use the instantiation template in the example directory to add the GT wrapper to your design.
658  -- In this example, the wrapper is wired up for basic operation with a frame generator and frame
659  -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
660  -- enabled, bonding should occur after alignment.
661 
662 
663  SFP2_v2_7_i : SFP2_v2_7
664  generic map
665  (
666  WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP
667  )
668  port map
669  (
670 
671  --_____________________________________________________________________
672  --_____________________________________________________________________
673  --GT0 (X1Y12)
674 
675  ---------------------------- Channel - DRP Ports --------------------------
676  GT0_DRPADDR_IN => GT0_DRPADDR_IN,
677  GT0_DRPCLK_IN => GT0_DRPCLK_IN,
678  GT0_DRPDI_IN => GT0_DRPDI_IN ,
679  GT0_DRPDO_OUT => GT0_DRPDO_OUT,
680  GT0_DRPEN_IN => GT0_DRPEN_IN ,
681  GT0_DRPRDY_OUT => GT0_DRPRDY_OUT,
682  GT0_DRPWE_IN => GT0_DRPWE_IN ,
683  ------------------------------- Loopback Ports -----------------------------
684  GT0_LOOPBACK_IN => GT0_LOOPBACK_IN,
685  ------------------------------ Power-Down Ports ----------------------------
686  GT0_RXPD_IN => GT0_RXPD_IN ,
687  GT0_TXPD_IN => GT0_TXPD_IN ,
688  --------------------- RX Initialization and Reset Ports --------------------
689  GT0_RXUSERRDY_IN => gt0_rxuserrdy_i,
690  -------------------------- RX Margin Analysis Ports ------------------------
691  GT0_EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
692  ------------------------- Receive Ports - CDR Ports ------------------------
693  GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
694  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
695  GT0_RXUSRCLK_IN => GT0_RXUSRCLK_IN,
696  GT0_RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
697  ------------------ Receive Ports - FPGA RX interface Ports -----------------
698  GT0_RXDATA_OUT => GT0_RXDATA_OUT,
699  ------------------- Receive Ports - Pattern Checker Ports ------------------
700  GT0_RXPRBSERR_OUT => GT0_RXPRBSERR_OUT,
701  GT0_RXPRBSSEL_IN => GT0_RXPRBSSEL_IN,
702  ------------------- Receive Ports - Pattern Checker ports ------------------
703  GT0_RXPRBSCNTRESET_IN => GT0_RXPRBSCNTRESET_IN ,
704  --------------------------- Receive Ports - RX AFE -------------------------
705  GT0_GTXRXP_IN => GT0_GTXRXP_IN,
706  ------------------------ Receive Ports - RX AFE Ports ----------------------
707  GT0_GTXRXN_IN => GT0_GTXRXN_IN,
708  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
709  GT0_RXBUFRESET_IN => GT0_RXBUFRESET_IN,
710  GT0_RXBUFSTATUS_OUT => GT0_RXBUFSTATUS_OUT ,
711  --------------------- Receive Ports - RX Equalizer Ports -------------------
712  GT0_RXDFEAGCHOLD_IN => gt0_rxdfeagchold_i,
713  GT0_RXDFELFHOLD_IN => gt0_rxdfelfhold_i,
714  --------------- Receive Ports - RX Fabric Output Control Ports -------------
715  GT0_RXOUTCLK_OUT => gt0_rxoutclk_i,
716  ---------------------- Receive Ports - RX Gearbox Ports --------------------
717  GT0_RXDATAVALID_OUT => GT0_RXDATAVALID_OUT ,
718  GT0_RXHEADER_OUT => GT0_RXHEADER_OUT,
719  GT0_RXHEADERVALID_OUT => GT0_RXHEADERVALID_OUT ,
720  --------------------- Receive Ports - RX Gearbox Ports --------------------
721  GT0_RXGEARBOXSLIP_IN => GT0_RXGEARBOXSLIP_IN ,
722  ------------- Receive Ports - RX Initialization and Reset Ports ------------
723  GT0_GTRXRESET_IN => gt0_gtrxreset_i,
724  GT0_RXPCSRESET_IN => gt0_rxpcsreset_i,
725  GT0_RXPMARESET_IN => GT0_RXPMARESET_IN,
726  ------------------ Receive Ports - RX Margin Analysis ports ----------------
727  GT0_RXLPMEN_IN => GT0_RXLPMEN_IN,
728  -------------- Receive Ports -RX Initialization and Reset Ports ------------
729  GT0_RXRESETDONE_OUT => gt0_rxresetdone_i,
730  --------------------- TX Initialization and Reset Ports --------------------
731  GT0_GTTXRESET_IN => gt0_gttxreset_i,
732  GT0_TXUSERRDY_IN => gt0_txuserrdy_i,
733  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
734  GT0_TXUSRCLK_IN => GT0_TXUSRCLK_IN,
735  GT0_TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
736  --------------- Transmit Ports - TX Configurable Driver Ports --------------
737  GT0_TXDIFFCTRL_IN => GT0_TXDIFFCTRL_IN,
738  GT0_TXINHIBIT_IN => GT0_TXINHIBIT_IN,
739  GT0_TXMAINCURSOR_IN => GT0_TXMAINCURSOR_IN ,
740  ------------------ Transmit Ports - TX Data Path interface -----------------
741  GT0_TXDATA_IN => GT0_TXDATA_IN,
742  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
743  GT0_GTXTXN_OUT => GT0_GTXTXN_OUT,
744  GT0_GTXTXP_OUT => GT0_GTXTXP_OUT,
745  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
746  GT0_TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
747  GT0_TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT ,
748  GT0_TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT ,
749  --------------------- Transmit Ports - TX Gearbox Ports --------------------
750  GT0_TXHEADER_IN => GT0_TXHEADER_IN,
751  GT0_TXSEQUENCE_IN => GT0_TXSEQUENCE_IN,
752  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
753  GT0_TXPCSRESET_IN => gt0_txpcsreset_i,
754  GT0_TXRESETDONE_OUT => gt0_txresetdone_i,
755  ------------------ Transmit Ports - pattern Generator Ports ----------------
756  GT0_TXPRBSSEL_IN => GT0_TXPRBSSEL_IN,
757 
758 
759 
760  --_____________________________________________________________________
761  --_____________________________________________________________________
762  --GT1 (X1Y14)
763 
764  ---------------------------- Channel - DRP Ports --------------------------
765  GT1_DRPADDR_IN => GT1_DRPADDR_IN,
766  GT1_DRPCLK_IN => GT1_DRPCLK_IN,
767  GT1_DRPDI_IN => GT1_DRPDI_IN ,
768  GT1_DRPDO_OUT => GT1_DRPDO_OUT,
769  GT1_DRPEN_IN => GT1_DRPEN_IN ,
770  GT1_DRPRDY_OUT => GT1_DRPRDY_OUT,
771  GT1_DRPWE_IN => GT1_DRPWE_IN ,
772  ------------------------------- Loopback Ports -----------------------------
773  GT1_LOOPBACK_IN => GT1_LOOPBACK_IN,
774  ------------------------------ Power-Down Ports ----------------------------
775  GT1_RXPD_IN => GT1_RXPD_IN ,
776  GT1_TXPD_IN => GT1_TXPD_IN ,
777  --------------------- RX Initialization and Reset Ports --------------------
778  GT1_RXUSERRDY_IN => gt1_rxuserrdy_i,
779  -------------------------- RX Margin Analysis Ports ------------------------
780  GT1_EYESCANDATAERROR_OUT => GT1_EYESCANDATAERROR_OUT,
781  ------------------------- Receive Ports - CDR Ports ------------------------
782  GT1_RXCDRLOCK_OUT => GT1_RXCDRLOCK_OUT,
783  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
784  GT1_RXUSRCLK_IN => GT1_RXUSRCLK_IN,
785  GT1_RXUSRCLK2_IN => GT1_RXUSRCLK2_IN,
786  ------------------ Receive Ports - FPGA RX interface Ports -----------------
787  GT1_RXDATA_OUT => GT1_RXDATA_OUT,
788  ------------------- Receive Ports - Pattern Checker Ports ------------------
789  GT1_RXPRBSERR_OUT => GT1_RXPRBSERR_OUT,
790  GT1_RXPRBSSEL_IN => GT1_RXPRBSSEL_IN,
791  ------------------- Receive Ports - Pattern Checker ports ------------------
792  GT1_RXPRBSCNTRESET_IN => GT1_RXPRBSCNTRESET_IN ,
793  --------------------------- Receive Ports - RX AFE -------------------------
794  GT1_GTXRXP_IN => GT1_GTXRXP_IN,
795  ------------------------ Receive Ports - RX AFE Ports ----------------------
796  GT1_GTXRXN_IN => GT1_GTXRXN_IN,
797  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
798  GT1_RXBUFRESET_IN => GT1_RXBUFRESET_IN,
799  GT1_RXBUFSTATUS_OUT => GT1_RXBUFSTATUS_OUT ,
800  --------------------- Receive Ports - RX Equalizer Ports -------------------
801  GT1_RXDFEAGCHOLD_IN => gt1_rxdfeagchold_i,
802  GT1_RXDFELFHOLD_IN => gt1_rxdfelfhold_i,
803  --------------- Receive Ports - RX Fabric Output Control Ports -------------
804  GT1_RXOUTCLK_OUT => gt1_rxoutclk_i,
805  ---------------------- Receive Ports - RX Gearbox Ports --------------------
806  GT1_RXDATAVALID_OUT => GT1_RXDATAVALID_OUT ,
807  GT1_RXHEADER_OUT => GT1_RXHEADER_OUT,
808  GT1_RXHEADERVALID_OUT => GT1_RXHEADERVALID_OUT ,
809  --------------------- Receive Ports - RX Gearbox Ports --------------------
810  GT1_RXGEARBOXSLIP_IN => GT1_RXGEARBOXSLIP_IN ,
811  ------------- Receive Ports - RX Initialization and Reset Ports ------------
812  GT1_GTRXRESET_IN => gt1_gtrxreset_i,
813  GT1_RXPCSRESET_IN => gt1_rxpcsreset_i,
814  GT1_RXPMARESET_IN => GT1_RXPMARESET_IN,
815  ------------------ Receive Ports - RX Margin Analysis ports ----------------
816  GT1_RXLPMEN_IN => GT1_RXLPMEN_IN,
817  -------------- Receive Ports -RX Initialization and Reset Ports ------------
818  GT1_RXRESETDONE_OUT => gt1_rxresetdone_i,
819  --------------------- TX Initialization and Reset Ports --------------------
820  GT1_GTTXRESET_IN => gt1_gttxreset_i,
821  GT1_TXUSERRDY_IN => gt1_txuserrdy_i,
822  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
823  GT1_TXUSRCLK_IN => GT1_TXUSRCLK_IN,
824  GT1_TXUSRCLK2_IN => GT1_TXUSRCLK2_IN,
825  --------------- Transmit Ports - TX Configurable Driver Ports --------------
826  GT1_TXDIFFCTRL_IN => GT1_TXDIFFCTRL_IN,
827  GT1_TXINHIBIT_IN => GT1_TXINHIBIT_IN,
828  GT1_TXMAINCURSOR_IN => GT1_TXMAINCURSOR_IN ,
829  ------------------ Transmit Ports - TX Data Path interface -----------------
830  GT1_TXDATA_IN => GT1_TXDATA_IN,
831  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
832  GT1_GTXTXN_OUT => GT1_GTXTXN_OUT,
833  GT1_GTXTXP_OUT => GT1_GTXTXP_OUT,
834  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
835  GT1_TXOUTCLK_OUT => GT1_TXOUTCLK_OUT,
836  GT1_TXOUTCLKFABRIC_OUT => GT1_TXOUTCLKFABRIC_OUT ,
837  GT1_TXOUTCLKPCS_OUT => GT1_TXOUTCLKPCS_OUT ,
838  --------------------- Transmit Ports - TX Gearbox Ports --------------------
839  GT1_TXHEADER_IN => GT1_TXHEADER_IN,
840  GT1_TXSEQUENCE_IN => GT1_TXSEQUENCE_IN,
841  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
842  GT1_TXPCSRESET_IN => gt1_txpcsreset_i,
843  GT1_TXRESETDONE_OUT => gt1_txresetdone_i,
844  ------------------ Transmit Ports - pattern Generator Ports ----------------
845  GT1_TXPRBSSEL_IN => GT1_TXPRBSSEL_IN,
846 
847 
848 
849 
850  --____________________________COMMON PORTS________________________________
851  ---------------------- Common Block - Ref Clock Ports ---------------------
852  GT0_GTREFCLK0_COMMON_IN => GT0_GTREFCLK0_COMMON_IN ,
853  ------------------------- Common Block - QPLL Ports ------------------------
854  GT0_QPLLLOCK_OUT => gt0_qplllock_i,
855  GT0_QPLLLOCKDETCLK_IN => GT0_QPLLLOCKDETCLK_IN ,
856  GT0_QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i ,
857  GT0_QPLLRESET_IN => gt0_qpllreset_i
858 
859  );
860 
861  gt0_rxpcsreset_i <= tied_to_ground_i;
862  gt0_txpcsreset_i <= tied_to_ground_i;
863  gt1_rxpcsreset_i <= tied_to_ground_i;
864  gt1_txpcsreset_i <= tied_to_ground_i;
865 
866  gt0_rxdfelpmreset_i <= tied_to_ground_i;
867  gt1_rxdfelpmreset_i <= tied_to_ground_i;
868 
869 
870 
871 
872  GT0_TXRESETDONE_OUT <= gt0_txresetdone_i;
873  GT0_RXRESETDONE_OUT <= gt0_rxresetdone_i;
874  GT0_RXOUTCLK_OUT <= gt0_rxoutclk_i;
875  GT1_TXRESETDONE_OUT <= gt1_txresetdone_i;
876  GT1_RXRESETDONE_OUT <= gt1_rxresetdone_i;
877  GT1_RXOUTCLK_OUT <= gt1_rxoutclk_i;
878  GT0_QPLLLOCK_OUT <= gt0_qplllock_i;
879 
880 chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
881  gt0_gttxreset_i <= GT0_GTTXRESET_IN or gt0_gttxreset_t;
882  gt0_gtrxreset_i <= GT0_GTRXRESET_IN or gt0_gtrxreset_t;
883  gt0_txuserrdy_i <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t;
884  gt0_rxuserrdy_i <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t;
885  gt1_gttxreset_i <= GT1_GTTXRESET_IN or gt1_gttxreset_t;
886  gt1_gtrxreset_i <= GT1_GTRXRESET_IN or gt1_gtrxreset_t;
887  gt1_txuserrdy_i <= GT1_TXUSERRDY_IN or gt1_txuserrdy_t;
888  gt1_rxuserrdy_i <= GT1_RXUSERRDY_IN or gt1_rxuserrdy_t;
889  gt0_qpllreset_i <= GT0_QPLLRESET_IN or gt0_qpllreset_t;
890 end generate chipscope;
891 
892 no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
893  gt0_gttxreset_i <= gt0_gttxreset_t;
894  gt0_gtrxreset_i <= gt0_gtrxreset_t;
895  gt0_txuserrdy_i <= gt0_txuserrdy_t;
896  gt0_rxuserrdy_i <= gt0_rxuserrdy_t;
897  gt1_gttxreset_i <= gt1_gttxreset_t;
898  gt1_gtrxreset_i <= gt1_gtrxreset_t;
899  gt1_txuserrdy_i <= gt1_txuserrdy_t;
900  gt1_rxuserrdy_i <= gt1_rxuserrdy_t;
901  gt0_qpllreset_i <= gt0_qpllreset_t;
902 end generate no_chipscope;
903 
904 
905 gt0_txresetfsm_i: SFP2_v2_7_TX_STARTUP_FSM
906 
907  generic map(
908  GT_TYPE => "GTX", --GTX or GTH or GTP
909  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
910  RETRY_COUNTER_BITWIDTH => 8,
911  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
912  RX_QPLL_USED => TRUE, -- share these two generic values
913  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
914  -- is enough. For single-lane applications the automatic alignment is
915  -- sufficient
916  )
917  port map (
918  STABLE_CLOCK => SYSCLK_IN,
919  TXUSERCLK => GT0_TXUSRCLK_IN,
920  SOFT_RESET => SOFT_RESET_IN,
921  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
922  CPLLREFCLKLOST => tied_to_ground_i,
923  QPLLLOCK => gt0_qplllock_i,
924  CPLLLOCK => tied_to_vcc_i,
925  TXRESETDONE => gt0_txresetdone_i,
926  MMCM_LOCK => tied_to_vcc_i,
927  GTTXRESET => gt0_gttxreset_t,
928  MMCM_RESET => open,
929  QPLL_RESET => gt0_qpllreset_t,
930  CPLL_RESET => open,
931  TX_FSM_RESET_DONE => GT0_TX_FSM_RESET_DONE_OUT,
932  TXUSERRDY => gt0_txuserrdy_t,
933  RUN_PHALIGNMENT => open,
934  RESET_PHALIGNMENT => open,
935  PHALIGNMENT_DONE => tied_to_vcc_i,
936  RETRY_COUNTER => open
937  );
938 
939 
940 gt1_txresetfsm_i: SFP2_v2_7_TX_STARTUP_FSM
941 
942  generic map(
943  GT_TYPE => "GTX", --GTX or GTH or GTP
944  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
945  RETRY_COUNTER_BITWIDTH => 8,
946  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
947  RX_QPLL_USED => TRUE, -- share these two generic values
948  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
949  -- is enough. For single-lane applications the automatic alignment is
950  -- sufficient
951  )
952  port map (
953  STABLE_CLOCK => SYSCLK_IN,
954  TXUSERCLK => GT1_TXUSRCLK_IN,
955  SOFT_RESET => SOFT_RESET_IN,
956  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
957  CPLLREFCLKLOST => tied_to_ground_i,
958  QPLLLOCK => gt0_qplllock_i,
959  CPLLLOCK => tied_to_vcc_i,
960  TXRESETDONE => gt1_txresetdone_i,
961  MMCM_LOCK => tied_to_vcc_i,
962  GTTXRESET => gt1_gttxreset_t,
963  MMCM_RESET => open,
964  QPLL_RESET => open,
965  CPLL_RESET => open,
966  TX_FSM_RESET_DONE => GT1_TX_FSM_RESET_DONE_OUT,
967  TXUSERRDY => gt1_txuserrdy_t,
968  RUN_PHALIGNMENT => open,
969  RESET_PHALIGNMENT => open,
970  PHALIGNMENT_DONE => tied_to_vcc_i,
971  RETRY_COUNTER => open
972  );
973 
974 
975 
976 
977 
978 
979 gt0_rxresetfsm_i: SFP2_v2_7_RX_STARTUP_FSM
980 
981  generic map(
982  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
983  GT_TYPE => "GTX", --GTX or GTH or GTP
984  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
985  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
986  RETRY_COUNTER_BITWIDTH => 8,
987  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
988  RX_QPLL_USED => TRUE, -- share these two generic values
989  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
990  -- is enough. For single-lane applications the automatic alignment is
991  -- sufficient
992  )
993  port map (
994  STABLE_CLOCK => SYSCLK_IN,
995  RXUSERCLK => GT0_RXUSRCLK_IN,
996  SOFT_RESET => SOFT_RESET_IN,
997  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
998  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
999  CPLLREFCLKLOST => tied_to_ground_i,
1000  QPLLLOCK => gt0_qplllock_i,
1001  CPLLLOCK => tied_to_vcc_i,
1002  RXRESETDONE => gt0_rxresetdone_i,
1003  MMCM_LOCK => tied_to_vcc_i,
1004  RECCLK_STABLE => gt0_recclk_stable_i ,
1005  RECCLK_MONITOR_RESTART => tied_to_ground_i,
1006  DATA_VALID => GT0_DATA_VALID_IN,
1007  TXUSERRDY => tied_to_vcc_i,
1008  GTRXRESET => gt0_gtrxreset_t,
1009  MMCM_RESET => open,
1010  QPLL_RESET => open,
1011  CPLL_RESET => open,
1012  RX_FSM_RESET_DONE => GT0_RX_FSM_RESET_DONE_OUT,
1013  RXUSERRDY => gt0_rxuserrdy_t,
1014  RUN_PHALIGNMENT => open,
1015  RESET_PHALIGNMENT => open,
1016  PHALIGNMENT_DONE => tied_to_vcc_i,
1017  RXDFEAGCHOLD => gt0_rxdfeagchold_i,
1018  RXDFELFHOLD => gt0_rxdfelfhold_i,
1019  RXLPMLFHOLD => gt0_rxlpmlfhold_i,
1020  RXLPMHFHOLD => gt0_rxlpmhfhold_i,
1021  RETRY_COUNTER => open
1022  );
1023 
1024 gt1_rxresetfsm_i: SFP2_v2_7_RX_STARTUP_FSM
1025 
1026  generic map(
1027  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
1028  GT_TYPE => "GTX", --GTX or GTH or GTP
1029  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
1030  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
1031  RETRY_COUNTER_BITWIDTH => 8,
1032  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
1033  RX_QPLL_USED => TRUE, -- share these two generic values
1034  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
1035  -- is enough. For single-lane applications the automatic alignment is
1036  -- sufficient
1037  )
1038  port map (
1039  STABLE_CLOCK => SYSCLK_IN,
1040  RXUSERCLK => GT1_RXUSRCLK_IN,
1041  SOFT_RESET => SOFT_RESET_IN,
1042  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
1043  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
1044  CPLLREFCLKLOST => tied_to_ground_i,
1045  QPLLLOCK => gt0_qplllock_i,
1046  CPLLLOCK => tied_to_vcc_i,
1047  RXRESETDONE => gt1_rxresetdone_i,
1048  MMCM_LOCK => tied_to_vcc_i,
1049  RECCLK_STABLE => gt1_recclk_stable_i ,
1050  RECCLK_MONITOR_RESTART => tied_to_ground_i,
1051  DATA_VALID => GT1_DATA_VALID_IN,
1052  TXUSERRDY => tied_to_vcc_i,
1053  GTRXRESET => gt1_gtrxreset_t,
1054  MMCM_RESET => open,
1055  QPLL_RESET => open,
1056  CPLL_RESET => open,
1057  RX_FSM_RESET_DONE => GT1_RX_FSM_RESET_DONE_OUT,
1058  RXUSERRDY => gt1_rxuserrdy_t,
1059  RUN_PHALIGNMENT => open,
1060  RESET_PHALIGNMENT => open,
1061  PHALIGNMENT_DONE => tied_to_vcc_i,
1062  RXDFEAGCHOLD => gt1_rxdfeagchold_i,
1063  RXDFELFHOLD => gt1_rxdfelfhold_i,
1064  RXLPMLFHOLD => gt1_rxlpmlfhold_i,
1065  RXLPMHFHOLD => gt1_rxlpmhfhold_i,
1066  RETRY_COUNTER => open
1067  );
1068 
1069 
1070 
1071  cdrlock_timeout:process(SYSCLK_IN)
1072  begin
1073  if rising_edge(SYSCLK_IN) then
1074  if(gt0_gtrxreset_i = '1') then
1075  rx_cdrlocked <= '0';
1076  rx_cdrlock_counter <= 0 after DLY;
1077  elsif (rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
1078  rx_cdrlocked <= '1';
1079  rx_cdrlock_counter <= rx_cdrlock_counter after DLY;
1080  else
1081  rx_cdrlock_counter <= rx_cdrlock_counter + 1 after DLY;
1082  end if;
1083  end if;
1084  end process;
1085 
1086 gt0_recclk_stable_i <= rx_cdrlocked;
1087 gt1_recclk_stable_i <= rx_cdrlocked;
1088 
1089 
1090 
1091 
1092 
1093 
1094 
1095 end RTL;
1096 
1097 
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