June 2014 Prototype Review

• ​gm2_wfd5_140529.pdf -- PDF draft schematic of 5/29/14. See also ​Eric's Notes from initial check of backplane connections.
• ​gm2_wfd5_140603.pdf -- PDF draft schematic 6/3/14. See also ​Nate's Notes
• ​gm2_wfd5_140605.pdf -- PDF draft schematic 6/5/14. See also ​Nate's Notes
• ​gm2_wfd5_140607.pdf -- PDF draft schematic 6/7/14.

Reference Information

• ​AMC 2.0 Spec (password, DO NOT DISTRIBUTE)
• ​MTCA.0 R.10 Spec (password, DO NOT DISTRIBUTE)
• ​AMC Pinout
• ​MCH Pinout

Design Comments

• Maybe more bypass caps on DDR3 VREFs. See AMC13XG T1 schematic: ​T1.PDF (page 4) for a known working design.
• Is a resistor divider sufficiently low impedance for DDR3 VREFs? Might consider a switching regulator like the TPS51116RGER (page 7 of AMC13 schematic).
• Recommend GND on debug headers
• I notice that the MMC is not wired to the FPGA in the way we have done it (we have an SPI bus used for configuration R/W from the MMC to the FPGA). Therefore I'm assuming you have forked the MMC code and are taking care of all the pin assignments yourself.