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Updated 5 Feb 2008, esh.
This document describes the hcalOSLB.cc class used for controlling the oSLB installed on a HTR. An initial version was released in hcal ver 3.9.9 and should work, provided firmware version "c" or later is installed in the oSLB.
A significant update is planned soon (Feb-Mar 2008) to add support for the TTC-triggered link synchronization and BX histogramming features.
For more details on the oSLB operation, please see the specification document on the [http://cmsdoc.cern.ch/cms/HCAL/document/CountingHouse/HTR/HTR_Mezzanines/oSLB/ oSLB Page] of the counting house repository at CERN.
Reset the QPLL and 3 GOLs. Send idle pattern briefly, then return to sending data. Should cause deserializers in receiver to re-acquire bit level synchronization. Does not affect the data pattern being transmitted.
After a reset, any of the functions below may be called to alter the data being sent. The change will take effect immediately without disturbing the GOL, so no additional reset should be required.
Select operating mode. Several bits are defined:
|bit 0||check_ena||Send error-correcting bits on bits 31..24 of GOL data|
|bit 1||check_data_ena||Send BC0 on bit 24, BCn on bits 31..25 of GOL data|
|bit 2||test_rand_ena||Send pseudo-random data for bit error tests (test_ena must be set too)|
|bit 3||test_ena||Substitute test data for all 32 bits of GOL data|
|bit 4||send_idle||force all GOLs to send idle pattern instead of data|
|bit 5||factory_test||force all GOLs to send BU factory test pattern|
|bits 6-7||-||currently unused|
Generally, only one bit should be set at a time, except that to get pseudo-random data both test_ena and test_rand_ena must be set.
If no bits are set, 19 muon bits are sent on the low 19 bits of the GOLs according to the map selected, and the upper bits are all 0.
Select mapping of muon bits to low 19 bits of GOL output. Custom mappings require a special mapping table to be compiled in to the VHDL code.
A few fixed mappings are provided for testing:
|0x00||GOL0_data(18:0) = TP_a(18:0),GOL1_data(18:0) = TP_b(18:0),GOL2_data(18:0) = TP_a(18:0)|
|0x01||GOL0_data(18:0) = TP_b(18:0),GOL1_data(18:0) = TP_a(18:0),GOL2_data(18:0) = TP_b(18:0)|
|0x02..0xfb||Reserved for compiled-in mappings|
|0xfc||GOL0_data(17:0) = GOL1_data(17:0) = GOL2_data(17:0) = TP_a(17:0)|
|0xfd||GOL0_data(17:0) = GOL1_data(17:0) = GOL2_data(17:0) = TP_a(35:18)|
|0xfe||GOL0_data(17:0) = GOL1_data(17:0) = GOL2_data(17:0) = TP_b(17:0)|
|0xff||GOL0_data(17:0) = GOL1_data(17:0) = GOL2_data(17:0) = TP_b(35:18)|
In the table above, TP_a refers to the muon bits received from the top FPGA on the HTR (inputs 0-23), while TP_b refers to the muon bits received from the bottom FPGA on the HTR (inputs 24-47).
Sets the 32-bit test pattern sent when the bit 'test_ena' is set by
Proposed updates (not yet implemented). Require oSLB firmware version 0xe or later.
Return a detailed status work for the oSLB. The hardware registers are actually read when this function is called, so the information is up to date.
|bit 0||BC_err||Wrong number of BX between BC0|
|bit 1||QPLL ERR||QPLL reports error|
|bit 2||QPLL LOCKED||QPLL is locked|
|bit 3||GOL0 READY||GOL 0 is ready|
|bit 4||GOL1 READY||GOL 1 is ready|
|bit 5||GOL2 READY||GOL 2 is ready|
|bit 6||RX CLK STOPPED||Rx clock from HTR stopped|
|bit 7||TTC CLK STOPPED||TTC clock from HTR stopped|
|bit 8||TTC DCM LOCKED||TTC clock DCM locked|
|bit 9||TX DCM LOCKED||Tx clock DCM locked|
Read error counters from oSLB. Currently, 8 counters are defined, each with
a maximum count of 255. The values read are stored in the array
|ctr0||OSLB DCM LOCK COUNT||Any DCM (FPGA clock PLL) lost lock|
|ctr1||OSLB GOL0 NRDY COUNT||GOL 0 went not ready|
|ctr2||OSLB GOL1 NRDY COUNT||GOL 1 went not ready|
|ctr3||OSLB GOL2 NRDY COUNT||GOL 2 went not ready|
|ctr4||OSLB QPLL LOST LOCK COUNT||QPLL lost lock|
|ctr5||OSLB QPLL ERROR COUNT||QPLL reported errror|
|ctr6||OSLB BC0 ERROR COUNT||Wrong number of BX between BC0|
|ctr7||OSLB BCN MISMATCH COUNT||BCn from top/bottom of HTR disagree|
Reset all error counters and error status bits to zero.
An automatic procedure may be started on receipt of a particular TTC broadcast command. When the command is received, all 3 links will send idle words for a programmable number of BX, then a fixed test pattern, then return to sending normal data.
Enable/disable resync on TTC command.
Read a count of the number of times the resync procedure has been triggered.
Reset the counter.
Trigger the resynchronization procedure.
The oSLB can histogram the BX occupancy on 4 inputs simultaneously. A memory of 4k x 8 is provided for each histogram. BC0 must be received for histograms to fill.