bu_cms_history/TriggerRuleTests

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2008-09-12 hazen (Boston)

More new versions from Tullio. Downlaod again the above folder, with new flavors and updated file names to 'xx484'.

 HTR slot   15      16      17      18      20      21
  Spigot    10/11   9/8     7/6     5/4     3/2     1/0
  fwTOP     484    2484    4484    6484   10484    a385
  fwBOT    1484    3484    5484    8484    9385     484

Run for several hours with no errors (~1.3e9 events). Output is here .

Now some experiments with payload sizes... Set HTR to 8 TS (0 TP still). Trigger now limits to about 78.5kHz. (234 MBytes/sec!)

Set HTR to 8 TS + 8 TP. Rate now about 41kHz. Sizes vary due to HTR flavors for "8 TP":

 Starting to read file...
 FED:  27 EvN: 000001  BcN: 856  OrN: 00000001  TTS: 8/8
  0: id: 001 Size: 118 EvN: 000001 BcN: 857  OrN: 01  HDR: 8e40 LRB: 00 ntp: 24  ndd: 192 ns: 8 
  1: id: 001 Size: 170 EvN: 000001 BcN: 857  OrN: 01  HDR: 8000 LRB: 00 ntp: 128  ndd: 192 ns: 8 
  2: id: 001 Size: 202 EvN: 000001 BcN: 857  OrN: 01  HDR: 8e40 LRB: 00 ntp: 192  ndd: 192 ns: 8 
  3: id: 001 Size: 106 EvN: 000001 BcN: 857  OrN: 01  HDR: 8e40 LRB: 00 ntp: 0  ndd: 192 ns: 8 
  4: id: 001 Size: 114 EvN: 000001 BcN: 857  OrN: 01  HDR: 8e40 LRB: 00 ntp: 16  ndd: 192 ns: 8 
  5: id: 001 Size: 170 EvN: 000001 BcN: 857  OrN: 01  HDR: 8e40 LRB: 00 ntp: 128  ndd: 192 ns: 8 
  6: id: 001 Size: 170 EvN: 000001 BcN: 857  OrN: 01  HDR: 8e40 LRB: 00 ntp: 128  ndd: 192 ns: 8 
  7: id: 001 Size: 170 EvN: 000001 BcN: 857  OrN: 01  HDR: 8e40 LRB: 00 ntp: 128  ndd: 192 ns: 8 
  8: id: 001 Size: 170 EvN: 000001 BcN: 857  OrN: 01  HDR: 8e40 LRB: 00 ntp: 128  ndd: 192 ns: 8 
  9: id: 001 Size: 170 EvN: 000001 BcN: 857  OrN: 01  HDR: 8e40 LRB: 00 ntp: 128  ndd: 192 ns: 8 
 10: id: 001 Size: 118 EvN: 000001 BcN: 857  OrN: 01  HDR: 8e40 LRB: 00 ntp: 24  ndd: 192 ns: 8 
 11: id: 001 Size: 202 EvN: 000001 BcN: 857  OrN: 01  HDR: 8e40 LRB: 00 ntp: 192  ndd: 192 ns: 8 

Total 1180 (32-bit) words, or 4720 bytes = 194 MBytes/sec.

2008-09-11 hazen (Boston)

Testing Tullio's new version 484. Downloaded to ~/Firmware/HTR-484 (though files are labelled 0384). Program Flavors as follows:

  HTR slot   15      16      17      18      20      21
  Spigot    10/11   9/8     7/6     5/4     3/2     1/0
  fwTOP      484    1484    8484   10484    8385    a385
  fwBOT      484    1484    8484   10484    9385     484

First quick test with 300kHz (throttled to 133kHz) rate is OK for all 12 spigots.

2008-09-04 hazen (Boston)

Testing for HTR problem observed in pit (see eLog ).

Running some tests. Scripts used are here: http://cms1.bu.edu/~hazen/2008_LoS/run90001Output/scripts/

Raw trigger rate is 300kHz, but limited to about 120kHz by DCC backpressure. Trigger rules are "standard" ones:

 Trigger rule 1: no more than 1 triggers per 3 BX
 Trigger rule 2: no more than 2 triggers per 25 BX
 Trigger rule 3: no more than 3 triggers per 100 BX
 Trigger rule 4: no more than 4 triggers per 250 BX

HTR firmware versions are:

  HTR slot   15      16      17      18      20      21
  Spigot    10/11   9/8     7/6     5/4     3/2     1/0
  fwTOP     385    2385    4385    6385    8385    a385
  fwBOT    1385    3385    5385    7385    9385    b385

See consistent problem with spigot 6 (slot 17 bottom, FW 0x5385). Results are here:

For reference, take a run with rule 1 changed to 1 in 4 BX.

Looks AOK.

Now swap HTR firmware flavors between 18 bottom and 17 bottom. So we have:

  HTR slot   15      16      17      18      20      21
  Spigot    10/11   9/8     7/6     5/4     3/2     1/0
  fwTOP     385    2385    4385    6385    8385    a385
  fwBOT    1385    3385    7385    5385    9385    b385

Yes, now the problem has moved to spigot 4 so it seems to be Flavor 5385 which is particularly bad.

Now loading up flavors 0c..10 in slots 15, 16, 17 (top only). We'll keep the "bad" flaver 05 in 18 bottom for now.

 HTR slot   15      16      17      18      20      21
 Spigot    10/11   9/8     7/6     5/4     3/2     1/0
 fwTOP     c385    e385   10385    6385    8385    a385
 fwBOT     d385    f385    7385    5385    9385    b385

Take a run. See the same problem in spigot 4, so disable it. Now take a run with all spigots but 4 enabled, looks ok:

2007-10-19 hazen (Boston)

More trigger rules tests. Modifed DCC software a bit to support setting the synchronization control register by adding a member synchControl to hcalDCCConfigInfo class in DCC.hh. Modified DCCdiagnose.cc to add command ''dcc/sync'' to allow setting this parameter.

Modified Xilix firmware to send L1A every 64 orbits. 3/4 times, only a single L1A is sent. 1/4 times, the selected pattern is sent.

Enable SYN output on sTTS when RL HTR error bit set (write 2 to offset 0xc0c of DCC Xilinx). Also, set the DCC to skip HTR with incorrect EvN (set bit 18=0 at offset 0x18 of DCC)

Test with pattern 10 (3 L1A with 6 empty clocks between). Now we see that the first 4 triggers are OK, then the HTR sends an event with RL set, and the DCC asserts SYN. The only curious thing is that the SYN appears with the event where the HTR didn't send anything...? The TTS state is taken from the CDF trailer word... need to check with Wu when it is actually captured.

 File_EvN DCC_EvN  DCC_BCN  TTS  HTR_EvN  HTR_BCN  HTR_ERR  HTR_EvN  HTR_BCN  HTR_ERR
       1       1    1485    RDY        1     1485  0x8040         1     1485  0x8060
       2       2    1485    RDY        2     1485  0x8040         2     1485  0x8060
       3       3    1472    RDY        3     1472  0x8040         3     1472  0x8060
       4       4    1478    RDY        4     1478  0x8040         4     1478  0x8060
       5       5    1485    SYN
       6       6    1485    SYN        6     1485  0x8048         6     1485  0x8068
       7       7    1485    SYN        7     1485  0x8040         7     1485  0x8060
       8       8    1485    SYN        8     1485  0x8040         8     1485  0x8060
       9       9    1472    SYN        9     1472  0x8040         9     1472  0x8060

2007-10-18 hazen (Boston)

Testing trigger rules violations. HTR firmware is version 44 (HO flavor). DCC firmware is new version 0x2c15 (fixed bugs in SDRAM present since 0x2c11).

Test Setup

Xilinx gadget controlling orbit and L1A signals:

L1A pattern sent every 256 orbits (22ms).

Pattern selected from table below. For example, pattern 1 has two L1A with leading edges separated by 50ns (two clocks)

  Pat_No  L1A_Output
    0      1 
    1      101
    2      10101
    3      1001
    4      1001001
    5      10001
    6      100010001
    7      -none-
    8      11
    9      111
    10     100000010000001
    11-15  -none-

HTRs are left in power-up state. DCC and TTC system initialized entirely by DCCdiagnose script (very new version of DCCdiagnose.exe required).

    ttc/write 0x82 0xf000        # reset BGO fifos
    ttc/write 0x80 0xff64        # enable external orbit, disable triggers
    ttc/write 0x92 10            # inhibit 0 delay (250ns)
    ttc/write 0x94 10            # inhibit 0 duration (250ns)
    ttc/write BData0 0x00800000  # write one word (BCR, cmd=01) to fifo 0
    ttc/write 0x90 0xd           # enable BG0 channel 0
    dcc/init 0 1                 # initialize DCC spigots 0, 1
    pci/write log3_fmem 4 0x4000 # enable "stop event builder when VME full"
    dcc/start                    # set DCC to run mode
    lrb/stat 1                   # read LRB status
    ttc/cmd 2                    # send ECR
    dcc/open test.dat            # open data file
    ttc/trig 1                   # enable L1A
    sleep 1                      # delay 1 second
    ttc/trig 4                   # disable L1A
    sleep 0.1                    # wait briefly for things to finish
    dcc/dump 9999                # dump all events to file
    dcc/status                   # display final DCC status
    quit

Results

First, take data with pattern 0 (one L1A). Here the EvN and BcN all match up, all is fine.

 File_EvN DCC_EvN  DCC_BCN  HTR_EvN  HTR_BCN  HTR_ERR  HTR_EvN  HTR_BCN  HTR_ERR
       1       1    1485         1     1485  0x8040         1     1485  0x8060
       2       2    1485         2     1485  0x8040         2     1485  0x8060
       3       3    1485         3     1485  0x8040         3     1485  0x8060
       4       4    1485         4     1485  0x8040         4     1485  0x8060
       5       5    1485         5     1485  0x8040         5     1485  0x8060
       6       6    1485         6     1485  0x8040         6     1485  0x8060
       7       7    1485         7     1485  0x8040         7     1485  0x8060
       8       8    1485         8     1485  0x8040         8     1485  0x8060
       9       9    1485         9     1485  0x8040         9     1485  0x8060

Now we use pattern 1 (two L1A separated by one empty clock). The EvN are fine, but while the DCC sees BcN separated by two clocks as we expect, the HTR reports always the first BcN. Also, note that the HTR error word does not report the RL error (this would make the error word i.e. 0x8068).

I have examined the raw data, and for (i.e.) events 1 and two the data is not strictly identical. The EvN is different, and a word or two are different in the latency counter words (extra 8 words at end of HTR event).

 File_EvN DCC_EvN  DCC_BCN  HTR_EvN  HTR_BCN  HTR_ERR  HTR_EvN  HTR_BCN  HTR_ERR
       1       1    1483         1     1483  0x8040         1     1483  0x8060
       2       2    1485         2     1483  0x8040         2     1483  0x8060
       3       3    1483         3     1483  0x8040         3     1483  0x8060
       4       4    1485         4     1483  0x8040         4     1483  0x8060
       5       5    1483         5     1483  0x8040         5     1483  0x8060
       6       6    1485         6     1483  0x8040         6     1483  0x8060
       7       7    1483         7     1483  0x8040         7     1483  0x8060
       8       8    1485         8     1483  0x8040         8     1483  0x8060
       9       9    1483         9     1483  0x8040         9     1483  0x8060

Now try pattern 2 (3 L1A, with one empty clock between each). Same behavior. HTRs see 3 events with same BcN but different EvN. No RL errors reported. Again, events 1, 2, 3 from first HTR are identical except for EvN and one word in the latency counters.

 File_EvN DCC_EvN  DCC_BCN  HTR_EvN  HTR_BCN  HTR_ERR  HTR_EvN  HTR_BCN  HTR_ERR
       1       1    1481         1     1481  0x8040         1     1481  0x8060
       2       2    1483         2     1481  0x8040         2     1481  0x8060
       3       3    1485         3     1481  0x8040         3     1481  0x8060
       4       4    1481         4     1481  0x8040         4     1481  0x8060
       5       5    1483         5     1481  0x8040         5     1481  0x8060
       6       6    1485         6     1481  0x8040         6     1481  0x8060
       7       7    1481         7     1481  0x8040         7     1481  0x8060
       8       8    1483         8     1481  0x8040         8     1481  0x8060
       9       9    1485         9     1481  0x8040         9     1481  0x8060
      10      10    1481        10     1481  0x8040        10     1481  0x8060

Now try pattern 3 (2 L1A with two empty clocks between). All seems OK here.

 File_EvN DCC_EvN  DCC_BCN  HTR_EvN  HTR_BCN  HTR_ERR  HTR_EvN  HTR_BCN  HTR_ERR
       1       1    1482         1     1482  0x8040         1     1482  0x8060
       2       2    1485         2     1485  0x8040         2     1485  0x8060
       3       3    1482         3     1482  0x8040         3     1482  0x8060
       4       4    1485         4     1485  0x8040         4     1485  0x8060
       5       5    1482         5     1482  0x8040         5     1482  0x8060
       6       6    1485         6     1485  0x8040         6     1485  0x8060
       7       7    1482         7     1482  0x8040         7     1482  0x8060
       8       8    1485         8     1485  0x8040         8     1485  0x8060
       9       9    1482         9     1482  0x8040         9     1482  0x8060

Now try pattern 4 (3 L1A with two empty clocks between). ''This is interesting!'' Notice that the HTR EvN are now skipping, and correspondingly the HTR report 'RL' error bit.

 File_EvN DCC_EvN  DCC_BCN  HTR_EvN  HTR_BCN  HTR_ERR  HTR_EvN  HTR_BCN  HTR_ERR
       1       1    1479         1     1479  0x8040         1     1479  0x8060
       2       2    1482         2     1482  0x8040         2     1482  0x8060
       3       3    1485         4     1479  0x8048         4     1479  0x8068
       4       4    1479         5     1482  0x8040         5     1482  0x8060
       5       5    1482         7     1479  0x8048         7     1479  0x8068
       6       6    1485         8     1482  0x8040         8     1482  0x8060
       7       7    1479        10     1479  0x8048        10     1479  0x8068
       8       8    1482        11     1482  0x8040        11     1482  0x8060
       9       9    1485        13     1479  0x8048        13     1479  0x8068

Now pattern 10 (3 L1A with 6 empty clocks between). Essentially the same behavior.

 File_EvN DCC_EvN  DCC_BCN  HTR_EvN  HTR_BCN  HTR_ERR  HTR_EvN  HTR_BCN  HTR_ERR
       1       1    1472         1     1472  0x8040         1     1472  0x8060
       2       2    1478         2     1478  0x8040         2     1478  0x8060
       3       3    1485         4     1472  0x8048         4     1472  0x8068
       4       4    1472         5     1478  0x8040         5     1478  0x8060
       5       5    1478         7     1472  0x8048         7     1472  0x8068
       6       6    1485         8     1478  0x8040         8     1478  0x8060
       7       7    1472        10     1472  0x8048        10     1472  0x8068
       8       8    1478        11     1478  0x8040        11     1478  0x8060
       9       9    1485        13     1472  0x8048        13     1472  0x8068
      10      10    1472        14     1478  0x8040        14     1478  0x8060

Turn on DCC bit to skip HTR payload if event number skips (set bit 18=0 at offset 0x18). Now it looks better. The blanks where the HTR data is missing mean that the DCC header for those HTRs says that there is no data.

 File_EvN DCC_EvN  DCC_BCN  HTR_EvN  HTR_BCN  HTR_ERR  HTR_EvN  HTR_BCN  HTR_ERR
       1       1    1472         1     1472  0x8048         1     1472  0x8068
       2       2    1478         2     1478  0x8040         2     1478  0x8060
       3       3    1485
       4       4    1472         4     1472  0x8048         4     1472  0x8068
       5       5    1478         5     1478  0x8040         5     1478  0x8060
       6       6    1485
       7       7    1472         7     1472  0x8048         7     1472  0x8068
       8       8    1478         8     1478  0x8040         8     1478  0x8060
       9       9    1485
      10      10    1472        10     1472  0x8048        10     1472  0x8068
      11      11    1478        11     1478  0x8040        11     1478  0x8060
      12      12    1485
      13      13    1472        13     1472  0x8048        13     1472  0x8068
      14      14    1478        14     1478  0x8040        14     1478  0x8060