bu_cms_history/Testing2008

SiteMap (Historical BU CMS wiki main page)

This page describes a test procedure for a repaired DCC using (mostly) standard release HCAL software tools. The HCAL release is assumed to be at least version 6_3_2.

''Please Keep Notes Of All Work'' on DCCs. This page: DCCWorkAtCERN has the status (if known) of the DCC in the shop for repair.

Firmware Versions and Programming

Check all firmware versions with DCCdiagnose.exe as follows.

  cms1
 /tmp > DCCdiagnose.exe caen:0 13
  DCCdiagnose.exe revision 02 Jun 2008
    ...
  DCC::initialize()...
  INFO - Set up logic board at relative address 0x00240000, absolute 0x2d240000\. DCC firmware revision = 0x2c2d
  DCC::getMainAddressMap()... DCC::getMasterDevice()
  DCC revision is 2c2d
  >vers
  lc_conf    00040070 0x12 (18)
  mip1_conf  00400055 0x22 (34)
  mip2_conf  00400055 0x22 (34)
  mip3_conf  00400055 0x22 (34)
  mip4_conf  00400055 0x1b (27)
  mip5_conf  00400055 0x1b (27)
  log1_conf  00010072 0x0d (13)
  log2_conf  00020072 0x0c (12)
  log3_conf  00030072 0x15 (21)
  Xilinx              0x2c2d
  CPLD version: 2  status bits: 00
  >q
  Exit 0

Programming

All firmware files are in Wu's Directory . Download firmware files from there and use the commands below to program. Cycle power after programming all files to see new versions.

Device Utility Example command
LOG1-3 DCCprogrammer.exe DCCprogrammer.exe 11 -p LOG1 pci1vc.hex -y
Xilinx DCCprogrammer.exe DCCprogrammer.exe 11 -p XILINX dccv2c2d.mcs -y
Local Control DCCdiagnose.exe > pci/lc_prog lcl_ctrlv14.hex
LRBs DCCrepair.exe DCCrepair.exe 13 -j mip4 lrbv22.jam program -y
Logic Board CPLD DCCrepair.exe DCCrepair.exe caen:0 11 -j log3 dcc_confv2.stapl -y

Testing VME Readout

Please be sure all the cables (TTC, HTR etc) are connected. Download and unpack TestScripts17Jun08.tar.gz to a working directory.

reset_all.sh is a shell script which resets the DCC and 6 HTR modules in slots 15-20. It uses vmeio.exe to write directly to the HTR because the htr.exe utility is broken as of this writing. It will need editing if you change HTR or DCC slots.

sixhtr_dump.dcc is a script for DCCdiagnose.exe which initializes the DCC and TTC system, collects data for 1 second, and writes the binary data file test.dat.

Triggers must be coming to the TTCvi "L1A1 NIM" input. These may come from the Xilinx gadget (log on to cms2, go to ~hazen/src/TTS_ctrl and run one of the scripts such as '''./periodic_12hz''' to set the rate. If the green LEDs are not blinking on the board, press the reset button "BTN SOUTH" under the rotary knob). Or, you can use a signal generator set to a reasonable rate making NIM logic pulses into the TTCvi.

To collect data and dump it:

  ./reset_all.sh
  DCCdiagnose.exe  -x sixhtr_dump.dcc
  ~hazen/bin/dump_FED.exe -d 4 test.dat | less

S-LINK Readout Test

Install an Slink transmitter on the DCC. Connect the cable. Log on to both cms1 and cms2 (cms2 receives SLink data).

To start the receiver (on cms2):

  ~hazen/bin/my_slink -n 

To start the DCC (on cms1):

  DCCdiagnose.exe  -x sixhtr_slink.dcc

You can stop the receiver with ^C any time. Data is stored in the binary file dccv4.dat which you can display with:

  ~hazen/bin/dump_FED.exe -d 4 dccv4.dat | less

TTS Output Test

The Xilinx trigger board can capture and dump changes on the TTS signals. To perform a simple connectivity test, log on to both cms1 and cms2.

CMS1 CMS2 Notes
cd ~hazen/src/TTS_ctrl
./read_tts -z Reset the FIFO on the TTS receiver
DCCdiagnose.exe 11 -x tts_test.dcc Enable each bit individually on TTS outputs
(you can see the pattern on the LEDs)
./read_tts Read and display TTS transistions. See sample output below

Sample output for TTS test. Note that each value (1, 2, 4, 8) appears individually.

 FIFO is not Empty not Full
  0: -> f (ERR)  (           685974786 BX, dt =    17.1 sec)
  1: -> 0 (ERR)  (               33358 BX, dt = 0.000834 sec)
  2: -> 4 (OFW)  (               16842 BX, dt = 0.000421 sec)
  3: -> 0 (ERR)  (             8124106 BX, dt =   0.203 sec)
  4: -> 8 (SYN)  (                6674 BX, dt = 0.000167 sec)
  5: -> 0 (ERR)  (             8126413 BX, dt =   0.203 sec)
  6: -> 1 (BSY)  (                6318 BX, dt = 0.000158 sec)
  7: -> 0 (ERR)  (             8128218 BX, dt =   0.203 sec)
  8: -> 2 (RDY)  (                6485 BX, dt = 0.000162 sec)
  9: -> 0 (ERR)  (             8128177 BX, dt =   0.203 sec)
 10: -> 4 (OFW)  (             8143489 BX, dt =   0.204 sec)
 11: -> 0 (ERR)  (             8127897 BX, dt =   0.203 sec)
 12: -> 8 (SYN)  (                6634 BX, dt = 0.000166 sec)
 13: -> 0 (ERR)  (             8128708 BX, dt =   0.203 sec)
 14: -> 1 (BSY)  (                6712 BX, dt = 0.000168 sec)
 15: -> 0 (ERR)  (             8127970 BX, dt =   0.203 sec)
 16: -> 2 (RDY)  (                6481 BX, dt = 0.000162 sec)
 17: -> 0 (ERR)  (             8128055 BX, dt =   0.203 sec)