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LVDS Tester

This gizmo receives HTR data and performs a number of basic sanity checks. The first version will consist of a small daughterboard plugged in to a Spartan-3 Evaluation Board from Xilinx.

It is probably best to us the A2 connector on the Spartan 3 board for data input. The clock would go in to pin 35 of A2 which is an FPGA GCK (global clock) pin. The 28 data lines would go to pins 4 through 34 (any order is OK, use whatever is convenient on the layout.)

The RJ-45 connector must be one of the keyed types (hopefully there is one left over somewhere!)

Power would come from pin 3 (VCCO, 3.3V) of A2.

LVDS serial transmitter/receiver chip documentation. Reference Manual and Schematics . (see data format starting on page 3) file for old test board design.