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This page has gerber files for the new VME DCC which are ready for review. We hope to send them out for fabrication no later than 11/25/08.

The 'GD1' layer has a fabrication notes which specify the board dimensions, dielectric thicknesses, etc.

The layers are as follows:

  Silkscreen            GTO
  Solder Mask           GTS
  Solder Paste          GTP

  Layer 1               GTL     Signal
  Layer 2               GP1     GND
  Layer 3               GP2     1.2V, 3.3V area
  Layer 4               G1      Signal
  Layer 5               GP3     GND

  Layer 6               GP4     2.5V
  Layer 7               G2      Signal
  Layer 8               GP5     3.3V
  Layer 9               GP6     GND
  Layer 10              GBL     Signal

  Silkscreen            GBO
  Solder Mask           GBS
  Solder Paster         GBP

Comments on layout:

2008-11-25 (bohn)

We could add more vias in the large open areas or along the board edge to connect the ground planes together.

  All high speed signals change signal layers where there are plenty of ground vias which connect ground planes together.

Place an additional hole for a PCB front panel mount behind connector J6. Use the same padstack as the PCB ejector mounting holes.

  The gap is too small to provide enough room on the componet side for a screw or nut.
  PCB warping should not be a problem as the front panel window for RJ45 connectors should be able to correct it. 

'''There is lots of space. Please see this picture which shows that there is a circle ~ 0.360" of clear space. The hole would be 0.110; a generous screw head would be 0.250'''

2008-11-24 (bohn)

Vias to GND Planes do not have thermal reliefs. Same for connector P3, all pins to ground do not have thermal reliefs (press fit?).

  Vias to power planes have thermal relief where needed. 
 (under FPGA and through hole components need soldering)

Adjust Reference Designators (overlapping holes or unclear placement): R27, R20, C158, C159, C17, C196, C193, R72, C33, C188, C41, C206, C38, C21, C309, C303, C297, C116, C328, C333, C78 (move + symbol), C92, C93, U18, C271, R115, R120

  Silkscreen are mainly for debugging purpose only, assembling house should use pick and 
  place file for component placement. 

Include the following on the silk screen: DCC v1.0, Boston University Electronics Design Facility, http://edf.bu.edu, Design by Shouxiang Wu, November 2008

  modified in the new slikscreen file 

2008-11-24 (hazen)

Silkscreen text tool width should be smaller, maybe 7 or 8 mils.

Capacitor orientation is not clear. Need some drawing with package outlines to ensure assembly is done correctly.

'''The problem is with non-polarized parts which might be installed 90 degrees from the correct orientation. This is not important for the PCB fabrication in any case'''

It might be a good idea to run through the design calculations for regulator U31, which produces 1.2V for the FPGA cores. (on power schematic). See TPS54010 data sheet .

  Went through it again without finding anything wrong.