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This page has ''very'' gory details on DCC hardware initialization. This is not for the faint of heart! It describes the standard DCC initialization software. Note that the U2 chip on the motherboard is very flexible, and can be initialized in different ways to support other applications.

Please refer to:

DCC Hardware Reference Manual]

A Tundra Universe 2 chip (hereafter "U2") provides a bridge between the VME bus (on the crate backplane) and the PCI busses on each motherboard. On the motherboard, there are 3 PCI busses, interconnected (see DCC manual) with two PCI2031 bridges. A table of PCI devices which can be installed on the motherboard is shown at the end of this page.

At power-up, the U2 chip does not provide access to any PCI busses. It must be configured by writing to it's control registers, which appear in VME A24 space at the power-up address:

  0x100000 + (slot-2) * 0x80000

This address is fixed in hardware, and uses the VME64x geographical address pins. After initialization by the standard DCC software, the address is changed to

  (slot-2) * 0x1000

(still in VME A24) by writing to the VRAI_BS register on the U2. The U2 provides up to 7 "windows" called VMEbus Slave Images which map regions of VME address space to PCI bus address space. The DCC software uses only images 0, 1, 2 and 4 as follows:

  VSI0   VME A32, no prefetch   PCI configuration space
  VSI1   VME A32, no prefetch   PCI memory normal space ("mem")
  VSI2   VME A32, prefetch      PCI fast memory space ("fmem")
  VSI4   VME A32, no prefetch   PCI I/O space

Each VSI has 4 control registers. See U2 document for details, but briefly:

  VSIn_CTL  controls the VME space (A24/A32) and PCI space (mem/conf/io) etc
  VSIn_BS   is the base address in VME space for the VSI
  VSIn_BD   is the top address in VME space for the VSI
  VSIn_TO   is a offset added to VSIn_BS to get the PCI address

For example, on a particular board, the VSI0_BS is 0x2c000000 and the VSI0_TO is 0xd4000000. Ignoring carry, 0x2c000000 + 0xd4000000 = 0x00000000. So, the PCI base address for VSI0 (which maps PCI configuration space) is 0.

The standard configuration software sets the base address of VSI0 to the following slot-based A32 address:

  0x20000000 + slot * 0x01000000

So, for example, a configured DCC in slot 12 has a base address of 0x2c000000.

Very well. We (in principle) understand how to open windows from VME space to PCI space. Now, some details about PCI devices.

Each PCI device responds to 256 configuration addresses by default. These address describe the device and it's capabilities (see PCI spec PDF file page 210 for details). To access a PCI device configuration space, use the following formula to determine the PCI bus address:

  (bus << 16) + (dev << 11) + (fun << 8) + conf_adr

Where bus is the bus number (0..2), dev is the device number (0..4) and fun is a function select number (not used on DCC, always 0) and conf_adr is the address within configuration space on the device. For example, to address LRB#1 configuration space offset 00, use offset 0x21800.

In addition to the configuration space, each PCI device can also supply up to 6 additional areas of memory or I/O space, controlled by 6 registers called BAR0..BAR5 (BAR = Base Address Register). The configuration software must interrogate all 6 BARs on each PCI device to determine how much memory and I/O space is required. Since the selection of devices installed on a motherboard may change, this results in a very important observation:

''The memory map of a DCC is not fixed, and can change if the complement of install daughterboards is changed, or even in response to firmware updates''.

Each BAR register has a well-defined format (see PCI spec PDF starting page 221). By following the procedure defined there, the software determines whether each BAR represents I/O space, normal memory space, or fast (prefetchable) memory space. and the size of the space.

PCI Device Sites on Motherboard

Physical Bus No Bus Name Device No Alias Description
0 PCI 3 0 br3 Bus 0/1 Bridge
0 1 log3 DCC logic board PCI 3 target
0 2 u2 Universe 2 PCI configuration
0 3 bc Unised PMC site (future Ethernet?)
0 4 lc Motherboard local control PCI target
1 PCI 2 0 br2 Bus 1/2 Bridge
1 1 log2 DCC logic board PCI 2 target
1 2 mip3 LRB#3 on DCC
1 3 mip4 LRB#4 on DCC
1 4 mip5 LRB#5 on DCC
2 PCI 1 0 not used
2 1 log1 DCC logic board PCI 1 target
2 2 mip0 not used (LRB site under Slink)
2 3 mip1 LRB#1 on DCC
2 4 mip2 LRB#2 on DCC