bu_cms_history/DCC_CfgScripts

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This page documents the configuration script options for the HCAL DCC.

Maintained by E. Hazen. Updated 2009-06-05.

In principle the "official" documentation is here .

NOTE: These parameters are the same for DCC1 and DCC2 unless otherwise noted.

Main Parameters

The main context for DCC parameters is DCC. Parameters defined in this context will apply to all DCCs in a crate. A variable NUMBER may take on values 0 or 1 for the two possible DCCs in a crate. Values (such as slot) which are specific to a DCC should be inside a conditional which tests NUMBER.

Name Type Default Description
present bool false DCC installed
slot int 0 VME slot 2-21
enableSLINK bool false Enable Slink-64 output
monitorEventScaler int 1 Prescale for VME spy events (1-65535) and error capture control '''1 '''
spigotActive bool15 false Enable HTR input 0-15
sourceId int 0xfff Source ID sent in CDF header (12 bits)
addrTablePath string /home/daqowner/dist/hal Directory containing DCC HAL tables
lrbAddrTableFile string none HAL address table for LRBs
log12AddrTableFile string none HAL address table for LOG1, LOG2 interfaces
log123ConfAddrTableFile string none HAL address table for PCI configuration spaces
logicBoardAddrTableFile string none HAL address table for Xilinx on logic board '''2 '''
firmwareRevXilinx int -1 (any) Firmware revision to load into Xilinx chip
firmwareRevLOG1 int -1 (any) Firmware revision to load into PCI LOG1 interface
firmwareRevLOG2 int -1 (any) Firmware revision to load into PCI LOG2 interface
firmwareRevLOG3 int -1 (any) Firmware revision to load into PCI LOG3 interface
BcNOffset int 0 BcN offset (0..3563). (limited to -15..+15 for older firmware) '''3 '''
OrNOffset int 0 OrN at TTS OC reset (0...15)
TTS_VME bool false Stop event builder when VME buffers full
TTC_CMD bool false Enable DCC response to TTC broadcast commands
synchControl int 0x001c9090 Value to write to synchronization control register '''4 '''
enableRule5 bool false Enable trigger rule "No more than 30 L1As every 12000 BXs" (added
in release 6.1.0)
GapCalibEnable bool true Enable orbit gap calibration trigger features
GapL1A_LowLimit int 3485 Lower BcN limit for calibration trigger in gap (not included) minimum setting 3456
GapL1A_HiLimit int 3494 Upper BcN limit for calibration trigger in gap (included) maximum setting 3519

DCC2 Specific Settings

Name Type Default Description
dcc2XilinxAddrTableFile string none HAL table file for XIlinx chip
dcc2VmeAddrTableFile string none HAL table file for VME chip
firmwareRevDCC2DSP int -1 (any) Firmware revision to load into Xilinx/Event Builder chip
firmwareRevDCC2LRB int -1 (any) Firmware revision to load into LRB chips
firmwareRevDCC2VME int -1 (any) Firmware revision to load into VME chip
majorVersion int 1 DCC version: 1 (or missing) for DCC1, 2 for DCC2

Notes:

the capture of specific types of errors in the VME buffer as follows:

  bit 23          If set to '1', catches events when LRB event length greater than 512 and truncated
                  For DCC2 version 0x3010 and later, this bit captures S-LINK CRC error events instead
  bit 22          If set to '1', catches events when CRC error happened
  bit 21          If set to '1', catches events when oc/bcn mismatch happened
  bit 20          If set to '1', catches events when evn mismatch happened
  bit 19          If set to '1', catches events when HTR_CK set
  bit 18          If set to '1', catches events when HTR_EE set
  bit 17          If set to '1', catches events when HTR_BZ set
  bit 16          If set to '1', catches events when HTR_OW set

  synchControl = 0x001c9090      # the default setting used until now
  synchControl = 0x00000000      # enable all reSync features

sTTS Control

Beginning with firmware revision 0x2c00, the following additional parameters are required, which define the behavior of the TTS outputs under various error conditions. Each parameter is an ordered pair (thr,state) with two elements.

transition. occurs once.

TTS states defined in the DAQ Interfacing Guide .

The threshold is applied to a 4-bit up/down counter which counts up when an event is seen with the condition present, and down when an event is seen with the condition absent. The default for all is currently "15,RDY".

   0,xxx    means go to state xxx if condition occurs once
   1,xxx    means go to state xxx if condition occurs twice
   2,xxx    means go to state xxx if condition occurs three times...
  14,xxx    means go to state xxx if condition occurs 15 times
  15,xxx    means never change state based on this condition.

In the "15" case it does not matter what xxx is but the convention is to use "RDY".

"RDY" is the normal state. It never makes sense to code a transition to this state, so again, by convention, any threshold except 15 should have xxx not equal "RDY".

Examples:

Parameter Description
err_ctrl_HTR_error Array of 15 elements, one per error bit in the HTR header. See
HTR documentation (pages 3, 4) for details of each bit ||
err_ctrl_L1_EvN_mismatch DCC event number did not match HTR event number (L1A)
err_ctrl_L1_BcN_mismatch DCC bunch number did not match HTR bunch number (L1A)
err_ctrl_CT_EvN_mismatch DCC event number did not match HTR event number (calibration trigger)
err_ctrl_CT_BcN_mismatch DCC bunch number did not match HTR bunch number (calibration trigger)
err_ctrl_bcnt_mismatch Number of clocks between BC0 was not correct