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Yet another HTR/DCC protocol: NewProtoNoHamming.pdf . Re-compile on drew4.umd.edu, download first file HTR_00378.mcs and program into slots 15, 17. These are currently connected to spigots 6-9 on the DCC. Program LRB 3, 4 with v26 (LRBv26.txt ).
Strange results... see http://cms1.bu.edu/~hazen/2008_LoS/2008-08-05_a/
Now testing v78/v25 on spigots 0-3. Very wierd... same problem.
http://cms1.bu.edu/~hazen/2008_LoS/2008-08-05_a/ and http://cms1.bu.edu/~hazen/2008_LoS/2008-08-05_c/ (low rate, few events).
Check HTR L1A count (0x228) and it agrees with DCC count. Time for long shots. My HTR_xxx78.mcs files are from July 24th, while the ones at CERN are from Jul 25th and the md5sums are different. Download a new HTR_00078.mcs to /tmp and program into HTR slot 20 both top/bottom. No improvement.
OK, going back to HTR_0005A in slot 16, cable to spigots 12, 13. Program LRB 5 with v0x22. Results here: http://cms1.bu.edu/~hazen/2008_LoS/2008-08-05_c
This triggers a HTR bug which is present at least in 5A, 78 and 378, which causes it to send a completely mangled stream with 2 blocks per L1A. Setting to i.e. 0102 is fine.
Trying again. Optimistically programming 378 into all HTR, cable to spigots 0-11 in order from slot 21 left. Start with LRB1 only at v0x26. Seems OK, so program LRB 2-4.
Long run with 6 HTR running HTR_00378. No errors seen in 400M events.
Install HTR_08176 in slot 20. This is Tullio's version with 20MHz clock and 90 degree phase shift between top and bottom Xilinx. One can see the pickup on the clock still from the top channel-link data lines.
Install HTR_01277 in slot 20 (spigots 0, 1) to test Drew's CRC implementation. Test first with 2c2d DCC firmware. Doesn't work... many CRC errors still. Now try 2c2e on the DCC so we can see what is going on.
Reset clock phase to 0800(1,270). Try again. Save results:
Install HTR_00177.mcs on slot 20 only. Capture
HTR Phase settings for reference:
0 = 0000 = 180, 1 = 0800 = 270 2 = 0800 = 0 3 = 1800 = 90.
Installed first 12 "flavors" of v77 to 6 HTRs. Took a short run at 15kHz fixed triggers. Results are here: 2008-07-22_a/ . Spigot 8 went LoS, and spigot 10 has 1 each UERR/CERR.
In the dump at EvN 0x057042, spigot 10 recorded an event with one correct word followed by 510 zeros.
Note that the script reset_new.sh was used to configure the HTRs, and the script sixhtr.dcc was used to configure the DCCs for this run.
The cabling as as follows:
spigot 00 - HTR 21 BOT spigot 01 - HTR 21 TOP spigot 02 - HTR 20 BOT spigot 03 - HTR 20 TOP spigot 04 - HTR 18 BOT spigot 05 - HTR 18 TOP spigot 06 - HTR 17 BOT spigot 07 - HTR 17 TOP spigot 08 - HTR 16 BOT spigot 09 - HTR 16 TOP spigot 10 - HTR 15 BOT spigot 11 - HTR 15 TOP
HTR in slot 14 is currently not connected due to lack of cables :(
Increase trigger rate to 60kHz (more or less the maximum, given that
the payload size is 710 words). Take
Captured the first EvN error in spigot 8 at EvN=0xf96631. The HTR EvN is 0xf97631.
There seems to be a consistent problem with spigot 8
(bottom of HTR in slot 16, with 5077 firmware.
Test at ~ 50kHz fixed trigger rate with ntp=nds=2.
Mux = 0 About 12k events with CERR on spigot 7 only (bottom of HTR in slot 17) Mux = 1 No UERR/CERR in 10M events Mux = 2 Lots of UERR/CERR on all spigots Mux = 3 Few UERR, lots of CERR on most spigots
Comments from Drew:
Eric, the information below is not accurate enough. What *570 does is use 4ma slow skew LVCMOS25 for the channel link data, and 8ma fast skew for the clock. Sorry about that. But note that the clock IS a DDR2 output, and the data are from DFFs on the IOB.
Note also that I've changed the SLB outputs as well from the LVDVI_DIV2_25 to LVCMOS25 8ma slow skew as well. I spoke to Jose about this and he said he did not think that that will cause problems with the SLB data on the SLB mezzanine cards but it will have to be tested.
Here are details of two protocol changes suggested by Drew:
Data bits 5, 13 grounded and 30 ohm impedance on outputs. There are ''no link errors'' in 0x26af0 events.
Loading new version 00470 to all HTR. See Drew's Email for details.
First attempt looks very bad. All bottom spigots have many errors. Tried mux settings 0,1 - results are the same.
This version had lots of CERR, UERR.
This version is an "old" reference version with 30 ohm impedance and bits 5, 13 working as usual.
Looking at errors. HTR FW 906D on HTRs in slots 15, 16, 17, 18 connected to DCC spigots 0,1, 3,4, 6,7, 9,10. Special LRB firmware v01. NDS=NTP=02. Capture 1000 events using script ham.dcc.
Processed 0x3e8 (1000) events Total elapsed BX: 2297 Average spacing = 2.297 Average rate = 1.7414e+07 Hz FED 27 HTR 0 Word 5 Errors: 8 Bits: 00100000 FED 27 HTR 0 Word 112 Errors: 21 Bits: 00100000 FED 27 HTR 9 Word 5 Errors: 115 Bits: 00100000 FED 27 HTR 9 Word 112 Errors: 140 Bits: 00100000
Now try firmware B06D.
Processed 0x3e8 (1000) events Total elapsed BX: 607 Average spacing = 0.607 Average rate = 6.58979e+07 Hz FED 27 HTR 0 Word 96 Errors: 12 Bits: 00100000 FED 27 HTR 9 Word 96 Errors: 74 Bits: 00100000
Measuring HTR CL clock jitter. HTR firmware version 08370. Default (power-up) register settings. LeCroy HFP1000 1GHz active probe, connected to vias near CL Tx with ~ 3cm wire on signal and GND. One probe on top CLK, one probe on top TxIN0.
Firmware version 08370. No L1A (CL idle) jitter is ~ 150ps pk/pk. WIth L1A, trigger on rising edge of TxIN0, jitter is ~ 250ps pk/pk.