to D0STT Page.
Maintained by E. Hazen. Updated 5/24/2002.
This page provides documenation for the Silicon Trigger Card (STC).
See also
Meenakshi's page.
of STC notes.
Danger! Most of the things on this page refer only to the now completely obsolete "Rev A" board! You'll have to ask someone else about the production boards. The sole exception is that correct PCB documentation is below (as far as I know):
| Prototype Rev 1 PCB documentation page |
| Prototype Rev 2 PCB documentation page |
| Prototype Rev 3 PCB documentation page |
| Downloaded Parameters Used by the Control Logic | W. Earle | 3/19/01 | params.pdf | |
| Specifications for One Channel... | W. Earle | 11/10/00 | channel_10Nov00.pdf | |
| Detailed Memory Map for Channel Logic | R. Perry et al | Detailed_memory_map_for_BU.doc.pdf | ||
| Specifications for the STC Control Logic | W. Earle | 11/10/00 | control_10Nov00.pdf | |
| Readout Procedure for Hits, Centroids and L3 Data | W. Earle | 11/10/00 | readout_10Nov00.pdf | |
| PCI Interfaces on STC | E. Hazen | 2/8/01 | stc_pci.pdf |
| Rumors about Power Supply Sequencing... Not! | E. Hazen | 4/17/01 | Altera Datasheet Excerpts |
| Road LUT block diagram for prototype | E. Hazen | 12/7/00 | road_LUT.pdf |
| Road LUT interface timing for prototype | E. Hazen | 12/14/00 | LUT_timing.pdf |
| Proposed SRAM for Prototype | Cypress Semi | 10/18/99 | cy7c1019v33.pdf |