Address3130292827262524232221201918171615141312111009080706050403020100NameDescription
 3130292827262524232221201918171615141312111009080706050403020100  
0x0100 ACTION.DTTRIG.SAMPLE_BUFFER_ENABLETrigger time alignment sample buffer when 1
 3130292827262524232221201918171615141312111009080706050403020100  
0x0000 ACTION.RECONFIGURE.BOTHStart both V6 and S6 Configuration
 3130292827262524232221201918171615141312111009080706050403020100  
0x0000 ACTION.RESETS.GENERALbit 0 - general reset
0x0000 ACTION.RESETS.TTC_COMMAND_HISTORYclear TTC command history
0x0000 ACTION.RESETS.TTC_FILTER_LISTclear TTC command filter list
 3130292827262524232221201918171615141312111009080706050403020100  
0x0104 CONF.DTTRIG.AMC_DELAY_dSet delay in 1/8 BX steps for AMC input
0x0101 CONF.DTTRIG.ENABLEEnable DT LUT trigger
0x0200 CONF.DTTRIG.LUTLook-up table for trigger inputs (512 words)
 3130292827262524232221201918171615141312111009080706050403020100  
0x0001 CONF.FLASH.CMDSends data from Flash WBUF (clocks/8 – 1) to be sent
 3130292827262524232221201918171615141312111009080706050403020100  
0x0030 CONF.TTC.OCR_CMDTTC OrN reset command
0x0030 CONF.TTC.OCR_MASKTTC OrN reset mask
0x000d CONF.TTC.OVERRIDE_MASKBitmask of additional locations to send TTC clock/data
 3130292827262524232221201918171615141312111009080706050403020100  
0x000d CONF.TTC_HISTORY.ENABLETTC history enable
0x0020 CONF.TTC_HISTORY.ENA_dTTC history filter enable
0x0020 CONF.TTC_HISTORY.EXCL_CMD_dTTC history command to exclude
0x000d CONF.TTC_HISTORY.FILTERTTC history filter enable
0x0020 CONF.TTC_HISTORY.FILTER_LISTTTC history list base address
0x0020 CONF.TTC_HISTORY.MASK_CMD__dTTC history command mask (1 to ignore bit)
 3130292827262524232221201918171615141312111009080706050403020100  
0x1080 FLASH_RBUFFlash read buffer (buffer is R/W)
0x1000 FLASH_WBUFFlash write buffer (buffer is R/W)
0x0000 IDRead IPBus version / address 0 alias
 3130292827262524232221201918171615141312111009080706050403020100  
0x0002 STATUS.AMC.ENABLE_MASKReads back what was written to Virtex 0x3
 3130292827262524232221201918171615141312111009080706050403020100  
0x0400 STATUS.DTTRIG.SAMPLE_BUFFERSample buffer for DT trigger input alignment
 3130292827262524232221201918171615141312111009080706050403020100  
0x0000 STATUS.FIRMWARE_VERST2 Firmware Version Number
 3130292827262524232221201918171615141312111009080706050403020100  
0x0001 STATUS.FLASH.BUSYbit 0 - flash I/O busy
 3130292827262524232221201918171615141312111009080706050403020100  
0x000f STATUS.FPGA.DNA_HIBits 32-56 of FPGA DNA
0x000e STATUS.FPGA.DNA_LOBits 0-31 of FPGA DNA
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0x0003 STATUS.RECONFIGURE.CRCconfiguration data CRC
 3130292827262524232221201918171615141312111009080706050403020100  
0x0000 STATUS.SERIAL_NOT2 Serial Number
 3130292827262524232221201918171615141312111009080706050403020100  
0x000b STATUS.TTC.BCNTBunch count (always running)
0x0007 STATUS.TTC.BCNT_ERRORTTC Bunch count error counter (8 bits only)
0x000c STATUS.TTC.CLK_FREQTTC clock freq divided by 50
0x0005 STATUS.TTC.LAST_BCNTTC bunch count of last received L1A
0x0004 STATUS.TTC.LAST_EVNTTC event number of last received L1A
0x0006 STATUS.TTC.LAST_ORNTTC orbit number of last received L1A
0x0009 STATUS.TTC.MBIT_ERRORTTC multi bit error count (8 bits only)
0x0008 STATUS.TTC.SBIT_ERRORTTC single bit error count (8 bits only)
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0x0800 STATUS.TTC_HISTORY.BUFFER.BASETTC history buffer base address
0x0802 STATUS.TTC_HISTORY.BUFFER.BCN_dTTC bunch number from history
0x0800 STATUS.TTC_HISTORY.BUFFER.CMD_dTTC command from history
0x0803 STATUS.TTC_HISTORY.BUFFER.EVN_dTTC EvN from history
0x0801 STATUS.TTC_HISTORY.BUFFER.ORN_dTTC orbit number from history
0x000d STATUS.TTC_HISTORY.COUNTNumber of entries or oldest entry in TTC history
0x0011 STATUS.TTC_HISTORY.COUNT_CMD_dTTC command counter
0x0010 STATUS.TTC_HISTORY.ECR_COUNTTTC reset event number command counter
0x000d STATUS.TTC_HISTORY.FULLTTC history has at least 512 entries