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Address | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | Name | Description
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.LOCAL_TRIG.CONTINUOUS | set continuous local L1A (setup with register 0x1c)
|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.LOCAL_TRIG.SEND_BURST | Send burst (possibly single) local L1A
|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.LOCAL_TRIG.SEND_ECR | sends event number reset thru TTC when in local L1A mode
|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.LOCAL_TRIG.SEND_OCR | sends orbit number reset thru TTC when in local L1A mode
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x00001021 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.LTRIG.CATCH_BC0 | HCAL Trigger test mode catch BC0
|
0x00001021 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.LTRIG.SAMPLE_IN | HCAL Trigger test mode sample input
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x0000000c |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.MONITOR_BUFFER.NEXT_PAGE | SDRAM increment page number by 1 in run mode
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.RESETS.COUNTER | counter reset
|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.RESETS.DAQ | DAQLSC reset
|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.RESETS.EVN | reset event number
|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.RESETS.GENERAL | general reset (ddr3 memory controller not included)
|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.RESETS.ORN | reset orbit number
|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.RESETS.SDRAM | reset ddr3 memory controller
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTION.TTC.SINGLE_COMMAND | Send single command if enabled by bit 30 in reg 0x24-0x27
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000003 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.AMC.ENABLE_MASK | 1 enables AMC1..12
|
0x00000018 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.AMC.FAKE_DATA_SIZE | scale factor( = contents + 1). Note: if bit 18 is set to '1', these bits are ignored.
|
0x0000001a |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.AMC.TTS_DISABLE_MASK | Disable corresponding AMCs TTS input signal
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000008 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.BCN_OFFSET | BcN offset
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000009 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.CAL_ENABLE | Enable calibration events in orbit gap (HCAL), default '1'
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000009 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.CAL_WINDOW_LOWER | read only entire lower window limit
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000009 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.CAL_WINDOW_LOWER_FIXED | fixed as 110110
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000009 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.CAL_WINDOW_LOWER_PROG | settable part of calibration window lower limit,3456 minimum(not included), default to '011101'
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000009 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.CAL_WINDOW_UPPER | read only entire upper window limit
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000009 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.CAL_WINDOW_UPPER_FIXED | fixed as 110110
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000009 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.CAL_WINDOW_UPPER_PROG | settable part of calibration window upper limit,3519 maximum(included), default to '100110'
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000001 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.DIAG.DISABLE_EVB | if '1', pauses event building. For debugging only
|
0x00000001 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.DIAG.ENABLE_MEMTEST | 1 enables memory self test
|
0x00000001 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.DIAG.FAKE_TTC_ENABLE | if '1', TTS output is 80MHz clock which can be looped back to TTC input
|
0x00000001 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.DIAG.MEMTEST_COUNTER | if '0', memory test uses 64bit PRBS. If '1', uses 32 bit sequencial numbers.
|
0x00000001 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.DIAG.TTS_TEST_ENABLE | if '1', TTS test mode (outputs from TTS_TEST_PATTERN)
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000001 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.EVB.ENABLE_DAQLSC | 1 enables DAQLSC
|
0x00000002 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.EVB.ENABLE_MASKED_EVN | If set to '1', bit 22-19 determine which events will be saved
|
0x00000001 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.EVB.MON_FULL_OVERWRITE | If '1', overwrite old events in monitor buffer when full
|
0x00000001 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.EVB.MON_FULL_STOP_EVB | if '1', monitor buffer full will stop event builder
|
0x00000002 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.EVB.SELECT_MASKED_EVN | Value n=0..15, save events with EvN low (20-n) bits '0'
|
0x00000002 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.EVB.SET_MON_PRESCALE | scale factor( = contents + 1). Note: if bit 18 is set to '1', these bits are ignored.
|
0x00000002 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.EVB.STOP_ON_CRC_ERR | If '1', stop monitor buffer write on AMC CRC error
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000007 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.ID.EVT_STAT | CMS evt_stat for output data
|
0x00000007 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.ID.EVT_TY | CMS evt_ty for output data
|
0x00000004 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.ID.FED_ID | SLINK ID(bits 15-14 always 0)
|
0x00000007 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.ID.SOURCE_ID | CMS Source ID for output data
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000001 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.LOCAL_TRIG.FAKE_DATA_ENABLE | if '1', generate fake event upon receiving L1A
|
0x00000028 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.LOCAL_TRIG.GAP_BEGIN | Beginning of orbit gap; triggers excluded
|
0x00000029 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.LOCAL_TRIG.GAP_END | End of orbit gap; triggers excluded
|
0x0000001c |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.LOCAL_TRIG.NUM_TRIG | Local L1A burst length (N+1) so =0 means 1 L1A
|
0x0000001c |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.LOCAL_TRIG.RATE | Local L1A rate. L1A every N+1 orbits@BcN=0x1f4, N+1 BX or 2*N's random
|
0x0000001c |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.LOCAL_TRIG.RULES | Local L1A trig rules: 0=all, 1=all but rule 4, 2=rules 1+2, 3=only rule 1
|
0x0000001c |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.LOCAL_TRIG.TYPE | Local L1A type: 0=per orbit 2=per BX 3=random
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000019 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.LTRIG.AMC.TRIGGER_MASK | AMC Trigger Mask Register
|
0x00001020 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.LTRIG.PRBS_SEL | HCAL Trigger test mode PRB select
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000008 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.ORN_OFFSET | OrN offset
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000001 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.RUN | run mode
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000004 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.SFP.DISABLE_TTS | 1 disables TTS transmitter
|
0x00000004 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.SFP.DISABLE_TX_MASK | 1 disables SFP0..2 transmitter
|
0x00000003 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.SFP.ENABLE_MASK | 1 enables SFP0..2
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000001 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.TTC.ENABLE_BGO | 1 enables locally generated BGO commands
|
0x0000002a |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.TTC.OCR_COMMAND | Orbit count reset TTC command
|
0x0000002a |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.TTC.OCR_MASK | Ignore 1 bits when comparing orbit count reset TTC command
|
0x0000002b |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.TTC.RESYNC.COMMAND | Resync TTC command
|
0x0000002b |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.TTC.RESYNC.MASK | Ignore 1 bits when comparing resync TTC command
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000019 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF.TTS_TEST_PATTERN | TTS output test pattern
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x08000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FULL_MEMORY | full memory read/write access. (write disabled in run mode) thru 0xfffffff
|
0x00020000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MONITOR_BUFFER_RAM | memory read window
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000e0f |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.AMC.AMC_CRC_ERR | AMC even CRC error detected
|
0x00000005 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.AMC.LINK_VERS_WRONG_MASK | 1 AMC1..12 link version wrong
|
0x00000005 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.AMC.LOSS_OF_SYNC_MASK | 0 AMC1..12 loss of sync
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000003 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.AMC_LINK_READY_MASK | 1 indicates AMC1..12 Link Ready
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000e0d |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.AMC_TTC.TTC_LOCKED_MASK | 1 if corresponding AMC enabled and TTC locked
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000019 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.AMC_TTS_STATE | encoded TTS from enabled AMCs
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
---|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.DIAG.DDR_RESET_DONE | if 0, DDR memory reset done
|
0x0000000b |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.DIAG.DDR_STATUS_HI | memory status register upper word (debug only, read only), bits 0-10 SDRAM write page address (?)
|
0x0000000a |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.DIAG.DDR_STATUS_LO | memory status register lower word (debug only, read only)
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000010 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.EVB.DATA_READY_MASK | event data ready in event buffer of event builders
|
0x00000010 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.EVB.EVENT_SIZE_MASK | event size in event buffer of event builders
|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.EVB.OVERFLOW_WARNING | L1A overflow warning
|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.EVB.SYNC_LOST | TTC sync lost (L1A buffer overflow)
|
0x00000010 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.EVB.TCP_BUFFER_AVAILABLE | TCP buffer available
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000001 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.FIRMWARE_VERS | read only Virtex firmware version
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000030 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.FPGA.DIE_TEMP | V6 die temperature in unit of 0.1 degree Celsius
|
0x0000001f |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.FPGA.DNA_HI |
|
0x0000001e |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.FPGA.DNA_LO | Kintex FPGA DNA
|
0x00000038 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.FPGA.MV_12V0 | 12V power voltage in millivolt
|
0x00000031 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.FPGA.MV_1V0 | 1.0V analog power voltage in millivolt
|
0x00000032 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.FPGA.MV_1V2 | 1.2V analog power voltage in millivolt
|
0x00000034 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.FPGA.MV_1V5 | 1.5V power voltage in millivolt
|
0x0000003a |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.FPGA.MV_2V0 | 2.0V VccAuxIO power voltage in millivolt
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0x00000035 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.FPGA.MV_2V5 | 2.5V power voltage in millivolt
|
0x00000036 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.FPGA.MV_3V3 | 3.3V power voltage in millivolt
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x0000004d |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.GENERAL.BUSY_TIME_HI |
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0x0000004c |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.GENERAL.BUSY_TIME_LO | busy time counter
|
0x00000051 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.GENERAL.OF_WARN_TIME_HI |
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0x00000050 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.GENERAL.OF_WARN_TIME_LO | L1A overflow warning time counter
|
0x0000004b |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.GENERAL.READY_TIME_HI |
|
0x0000004a |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.GENERAL.READY_TIME_LO | ready time counter
|
0x00000049 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.GENERAL.RUN_TIME_HI |
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0x00000048 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.GENERAL.RUN_TIME_LO | run time counter
|
0x0000004f |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.GENERAL.SYNC_LOST_TIME_HI |
|
0x0000004e |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.GENERAL.SYNC_LOST_TIME_LO | L1A sync lost time counter
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.LOCAL_TRIG.CONTINUOUS_ON | continous local L1A on (setup with register 0x1c)
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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0x00001021 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.LTRIG.PRBS_ERRORS | HCAL Trigger test mode PRBS error count
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000010 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.MONITOR_BUFFER.AVAILABLE | monitor buffer available
|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.MONITOR_BUFFER.EMPTY | monitor buffer empty
|
0x0000000d |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.MONITOR_BUFFER.EOI_TYPE | all 0 if not in catch mode, otherwise gives the type of error of the bad event
|
0x0000000d |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.MONITOR_BUFFER.EVENTS_AFTER_EOI | all 0 if not in catch mode, otherwise gives the number of events stored after the bad event
|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.MONITOR_BUFFER.FULL | monitor buffer full
|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.MONITOR_BUFFER.OVERFLOW | monitor buffer overflow
|
0x0000000c |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.MONITOR_BUFFER.PAGE_NO | SDRAM page number (r/w only when not in run mode)
|
0x0000000e |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.MONITOR_BUFFER.UNREAD_EVENTS | number of unread events captured by monitor
|
0x0000000d |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.MONITOR_BUFFER.WORDS_SFP0 | SFP 0 monitored event size in 32-bit word. 0 if no data available
|
0x0000000f |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.MONITOR_BUFFER.WORDS_SFP1 | SFP 1 monitored event size in 32-bit word. 0 if no data available
|
0x0000001d |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.MONITOR_BUFFER.WORDS_SFP2 | SFP 2 monitored event size in 32-bit word. 0 if no data available
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.SERIAL_HI | Serial Number High one bit
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.SERIAL_LO | Serial Number Low eight bits
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.SERIAL_NO | T1 board SN
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.SFP.ANY_DOWN | reads 1 when any of the enabled SFP ports is down
|
0x00000004 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.SFP.RX_SIG_LOST_MASK | 1 indicates SFP0..2 Receiver signal lost
|
0x00000004 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.SFP.SFP_ABSENT_MASK | 1 indicates SFP0..2 absent
|
0x00000004 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.SFP.TTS_LOS_LOL | 1 indicates TTC_LOS or TTC_LOL
|
0x00000004 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.SFP.TTS_SFP_ABSENT | 1 indicates TTC/TTS SFP absent
|
0x00000004 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.SFP.TTS_TX_FAULT | 1 indicates TTS TxFault
|
0x00000004 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.SFP.TX_FAULT_MASK | 1 indicates SFP0..2 TxFault
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000003 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.SFP_LSC_DOWN_MASK | 1 when DAQLSC of SFP0..2 is down
|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
|
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0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.BCNT_ERROR | TTC bcnt error
|
0x00000045 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.BCNT_ERRORS_HI |
|
0x00000044 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.BCNT_ERRORS_LO | TTC BC0 error counter
|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.MULT_BIT_ERROR | TTC multi-bit error
|
0x00000043 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.MULT_BIT_ERRORS_HI |
|
0x00000042 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.MULT_BIT_ERRORS_LO | TTC multi-bit error counter
|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.NOT_READY | TTC not ready
|
0x0000001a |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.RESYNC_COUNT | Count of TTC resync commands received
|
0x00000160 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.ROM | TTC/TTS SFP ROM data(first 128 bytes, little endian)
|
0x00000000 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.SGL_BIT_ERROR | TTC single bit error
|
0x00000041 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.SGL_BIT_ERRORS_HI |
|
0x00000040 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATUS.TTC.SGL_BIT_ERRORS_LO | TTC single bit error counter
|